1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVMe admin command implementation. 4 * Copyright (c) 2015-2016 HGST, a Western Digital Company. 5 */ 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 #include <linux/module.h> 8 #include <linux/rculist.h> 9 #include <linux/part_stat.h> 10 11 #include <generated/utsrelease.h> 12 #include <linux/unaligned.h> 13 #include "nvmet.h" 14 15 static void nvmet_execute_delete_sq(struct nvmet_req *req) 16 { 17 struct nvmet_ctrl *ctrl = req->sq->ctrl; 18 u16 sqid = le16_to_cpu(req->cmd->delete_queue.qid); 19 u16 status; 20 21 if (!nvmet_is_pci_ctrl(ctrl)) { 22 status = nvmet_report_invalid_opcode(req); 23 goto complete; 24 } 25 26 if (!sqid) { 27 status = NVME_SC_QID_INVALID | NVME_STATUS_DNR; 28 goto complete; 29 } 30 31 status = nvmet_check_sqid(ctrl, sqid, false); 32 if (status != NVME_SC_SUCCESS) 33 goto complete; 34 35 status = ctrl->ops->delete_sq(ctrl, sqid); 36 37 complete: 38 nvmet_req_complete(req, status); 39 } 40 41 static void nvmet_execute_create_sq(struct nvmet_req *req) 42 { 43 struct nvmet_ctrl *ctrl = req->sq->ctrl; 44 struct nvme_command *cmd = req->cmd; 45 u16 sqid = le16_to_cpu(cmd->create_sq.sqid); 46 u16 cqid = le16_to_cpu(cmd->create_sq.cqid); 47 u16 sq_flags = le16_to_cpu(cmd->create_sq.sq_flags); 48 u16 qsize = le16_to_cpu(cmd->create_sq.qsize); 49 u64 prp1 = le64_to_cpu(cmd->create_sq.prp1); 50 u16 status; 51 52 if (!nvmet_is_pci_ctrl(ctrl)) { 53 status = nvmet_report_invalid_opcode(req); 54 goto complete; 55 } 56 57 if (!sqid) { 58 status = NVME_SC_QID_INVALID | NVME_STATUS_DNR; 59 goto complete; 60 } 61 62 status = nvmet_check_sqid(ctrl, sqid, true); 63 if (status != NVME_SC_SUCCESS) 64 goto complete; 65 66 status = nvmet_check_io_cqid(ctrl, cqid, false); 67 if (status != NVME_SC_SUCCESS) { 68 pr_err("SQ %u: Invalid CQID %u\n", sqid, cqid); 69 goto complete; 70 } 71 72 if (!qsize || qsize > NVME_CAP_MQES(ctrl->cap)) { 73 status = NVME_SC_QUEUE_SIZE | NVME_STATUS_DNR; 74 goto complete; 75 } 76 77 status = ctrl->ops->create_sq(ctrl, sqid, cqid, sq_flags, qsize, prp1); 78 79 complete: 80 nvmet_req_complete(req, status); 81 } 82 83 static void nvmet_execute_delete_cq(struct nvmet_req *req) 84 { 85 struct nvmet_ctrl *ctrl = req->sq->ctrl; 86 u16 cqid = le16_to_cpu(req->cmd->delete_queue.qid); 87 u16 status; 88 89 if (!nvmet_is_pci_ctrl(ctrl)) { 90 status = nvmet_report_invalid_opcode(req); 91 goto complete; 92 } 93 94 status = nvmet_check_io_cqid(ctrl, cqid, false); 95 if (status != NVME_SC_SUCCESS) 96 goto complete; 97 98 if (!ctrl->cqs[cqid] || nvmet_cq_in_use(ctrl->cqs[cqid])) { 99 /* Some SQs are still using this CQ */ 100 status = NVME_SC_QID_INVALID | NVME_STATUS_DNR; 101 goto complete; 102 } 103 104 status = ctrl->ops->delete_cq(ctrl, cqid); 105 106 complete: 107 nvmet_req_complete(req, status); 108 } 109 110 static void nvmet_execute_create_cq(struct nvmet_req *req) 111 { 112 struct nvmet_ctrl *ctrl = req->sq->ctrl; 113 struct nvme_command *cmd = req->cmd; 114 u16 cqid = le16_to_cpu(cmd->create_cq.cqid); 115 u16 cq_flags = le16_to_cpu(cmd->create_cq.cq_flags); 116 u16 qsize = le16_to_cpu(cmd->create_cq.qsize); 117 u16 irq_vector = le16_to_cpu(cmd->create_cq.irq_vector); 118 u64 prp1 = le64_to_cpu(cmd->create_cq.prp1); 119 u16 status; 120 121 if (!nvmet_is_pci_ctrl(ctrl)) { 122 status = nvmet_report_invalid_opcode(req); 123 goto complete; 124 } 125 126 status = nvmet_check_io_cqid(ctrl, cqid, true); 127 if (status != NVME_SC_SUCCESS) 128 goto complete; 129 130 if (!qsize || qsize > NVME_CAP_MQES(ctrl->cap)) { 131 status = NVME_SC_QUEUE_SIZE | NVME_STATUS_DNR; 132 goto complete; 133 } 134 135 status = ctrl->ops->create_cq(ctrl, cqid, cq_flags, qsize, 136 prp1, irq_vector); 137 138 complete: 139 nvmet_req_complete(req, status); 140 } 141 142 u32 nvmet_get_log_page_len(struct nvme_command *cmd) 143 { 144 u32 len = le16_to_cpu(cmd->get_log_page.numdu); 145 146 len <<= 16; 147 len += le16_to_cpu(cmd->get_log_page.numdl); 148 /* NUMD is a 0's based value */ 149 len += 1; 150 len *= sizeof(u32); 151 152 return len; 153 } 154 155 static u32 nvmet_feat_data_len(struct nvmet_req *req, u32 cdw10) 156 { 157 switch (cdw10 & 0xff) { 158 case NVME_FEAT_HOST_ID: 159 return sizeof(req->sq->ctrl->hostid); 160 default: 161 return 0; 162 } 163 } 164 165 u64 nvmet_get_log_page_offset(struct nvme_command *cmd) 166 { 167 return le64_to_cpu(cmd->get_log_page.lpo); 168 } 169 170 static void nvmet_execute_get_log_page_noop(struct nvmet_req *req) 171 { 172 nvmet_req_complete(req, nvmet_zero_sgl(req, 0, req->transfer_len)); 173 } 174 175 static void nvmet_execute_get_log_page_error(struct nvmet_req *req) 176 { 177 struct nvmet_ctrl *ctrl = req->sq->ctrl; 178 unsigned long flags; 179 off_t offset = 0; 180 u64 slot; 181 u64 i; 182 183 spin_lock_irqsave(&ctrl->error_lock, flags); 184 slot = ctrl->err_counter % NVMET_ERROR_LOG_SLOTS; 185 186 for (i = 0; i < NVMET_ERROR_LOG_SLOTS; i++) { 187 if (nvmet_copy_to_sgl(req, offset, &ctrl->slots[slot], 188 sizeof(struct nvme_error_slot))) 189 break; 190 191 if (slot == 0) 192 slot = NVMET_ERROR_LOG_SLOTS - 1; 193 else 194 slot--; 195 offset += sizeof(struct nvme_error_slot); 196 } 197 spin_unlock_irqrestore(&ctrl->error_lock, flags); 198 nvmet_req_complete(req, 0); 199 } 200 201 static void nvmet_execute_get_supported_log_pages(struct nvmet_req *req) 202 { 203 struct nvme_supported_log *logs; 204 u16 status; 205 206 logs = kzalloc_obj(*logs); 207 if (!logs) { 208 status = NVME_SC_INTERNAL; 209 goto out; 210 } 211 212 logs->lids[NVME_LOG_SUPPORTED] = cpu_to_le32(NVME_LIDS_LSUPP); 213 logs->lids[NVME_LOG_ERROR] = cpu_to_le32(NVME_LIDS_LSUPP); 214 logs->lids[NVME_LOG_SMART] = cpu_to_le32(NVME_LIDS_LSUPP); 215 logs->lids[NVME_LOG_FW_SLOT] = cpu_to_le32(NVME_LIDS_LSUPP); 216 logs->lids[NVME_LOG_CHANGED_NS] = cpu_to_le32(NVME_LIDS_LSUPP); 217 logs->lids[NVME_LOG_CMD_EFFECTS] = cpu_to_le32(NVME_LIDS_LSUPP); 218 logs->lids[NVME_LOG_ENDURANCE_GROUP] = cpu_to_le32(NVME_LIDS_LSUPP); 219 logs->lids[NVME_LOG_ANA] = cpu_to_le32(NVME_LIDS_LSUPP); 220 logs->lids[NVME_LOG_FEATURES] = cpu_to_le32(NVME_LIDS_LSUPP); 221 logs->lids[NVME_LOG_RMI] = cpu_to_le32(NVME_LIDS_LSUPP); 222 logs->lids[NVME_LOG_RESERVATION] = cpu_to_le32(NVME_LIDS_LSUPP); 223 224 status = nvmet_copy_to_sgl(req, 0, logs, sizeof(*logs)); 225 kfree(logs); 226 out: 227 nvmet_req_complete(req, status); 228 } 229 230 static u16 nvmet_get_smart_log_nsid(struct nvmet_req *req, 231 struct nvme_smart_log *slog) 232 { 233 u64 host_reads, host_writes, data_units_read, data_units_written; 234 u16 status; 235 236 status = nvmet_req_find_ns(req); 237 if (status) 238 return status; 239 240 /* we don't have the right data for file backed ns */ 241 if (!req->ns->bdev) 242 return NVME_SC_SUCCESS; 243 244 host_reads = part_stat_read(req->ns->bdev, ios[READ]); 245 data_units_read = 246 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[READ]), 1000); 247 host_writes = part_stat_read(req->ns->bdev, ios[WRITE]); 248 data_units_written = 249 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[WRITE]), 1000); 250 251 put_unaligned_le64(host_reads, &slog->host_reads[0]); 252 put_unaligned_le64(data_units_read, &slog->data_units_read[0]); 253 put_unaligned_le64(host_writes, &slog->host_writes[0]); 254 put_unaligned_le64(data_units_written, &slog->data_units_written[0]); 255 256 return NVME_SC_SUCCESS; 257 } 258 259 static u16 nvmet_get_smart_log_all(struct nvmet_req *req, 260 struct nvme_smart_log *slog) 261 { 262 u64 host_reads = 0, host_writes = 0; 263 u64 data_units_read = 0, data_units_written = 0; 264 struct nvmet_ns *ns; 265 struct nvmet_ctrl *ctrl; 266 unsigned long idx; 267 268 ctrl = req->sq->ctrl; 269 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) { 270 /* we don't have the right data for file backed ns */ 271 if (!ns->bdev) 272 continue; 273 host_reads += part_stat_read(ns->bdev, ios[READ]); 274 data_units_read += DIV_ROUND_UP( 275 part_stat_read(ns->bdev, sectors[READ]), 1000); 276 host_writes += part_stat_read(ns->bdev, ios[WRITE]); 277 data_units_written += DIV_ROUND_UP( 278 part_stat_read(ns->bdev, sectors[WRITE]), 1000); 279 } 280 281 put_unaligned_le64(host_reads, &slog->host_reads[0]); 282 put_unaligned_le64(data_units_read, &slog->data_units_read[0]); 283 put_unaligned_le64(host_writes, &slog->host_writes[0]); 284 put_unaligned_le64(data_units_written, &slog->data_units_written[0]); 285 286 return NVME_SC_SUCCESS; 287 } 288 289 static void nvmet_execute_get_log_page_rmi(struct nvmet_req *req) 290 { 291 struct nvme_rotational_media_log *log; 292 struct gendisk *disk; 293 u16 status; 294 295 req->cmd->common.nsid = cpu_to_le32(le16_to_cpu( 296 req->cmd->get_log_page.lsi)); 297 status = nvmet_req_find_ns(req); 298 if (status) 299 goto out; 300 301 if (!req->ns->bdev || !bdev_rot(req->ns->bdev)) { 302 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 303 goto out; 304 } 305 306 if (req->transfer_len != sizeof(*log)) { 307 status = NVME_SC_SGL_INVALID_DATA | NVME_STATUS_DNR; 308 goto out; 309 } 310 311 log = kzalloc_obj(*log); 312 if (!log) { 313 status = NVME_SC_INTERNAL; 314 goto out; 315 } 316 317 log->endgid = req->cmd->get_log_page.lsi; 318 disk = req->ns->bdev->bd_disk; 319 if (disk && disk->ia_ranges) 320 log->numa = cpu_to_le16(disk->ia_ranges->nr_ia_ranges); 321 else 322 log->numa = cpu_to_le16(1); 323 324 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log)); 325 kfree(log); 326 out: 327 nvmet_req_complete(req, status); 328 } 329 330 static void nvmet_execute_get_log_page_smart(struct nvmet_req *req) 331 { 332 struct nvme_smart_log *log; 333 u16 status = NVME_SC_INTERNAL; 334 unsigned long flags; 335 336 if (req->transfer_len != sizeof(*log)) 337 goto out; 338 339 log = kzalloc_obj(*log); 340 if (!log) 341 goto out; 342 343 if (req->cmd->get_log_page.nsid == cpu_to_le32(NVME_NSID_ALL)) 344 status = nvmet_get_smart_log_all(req, log); 345 else 346 status = nvmet_get_smart_log_nsid(req, log); 347 if (status) 348 goto out_free_log; 349 350 spin_lock_irqsave(&req->sq->ctrl->error_lock, flags); 351 put_unaligned_le64(req->sq->ctrl->err_counter, 352 &log->num_err_log_entries); 353 spin_unlock_irqrestore(&req->sq->ctrl->error_lock, flags); 354 355 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log)); 356 out_free_log: 357 kfree(log); 358 out: 359 nvmet_req_complete(req, status); 360 } 361 362 static void nvmet_get_cmd_effects_admin(struct nvmet_ctrl *ctrl, 363 struct nvme_effects_log *log) 364 { 365 /* For a PCI target controller, advertize support for the . */ 366 if (nvmet_is_pci_ctrl(ctrl)) { 367 log->acs[nvme_admin_delete_sq] = 368 log->acs[nvme_admin_create_sq] = 369 log->acs[nvme_admin_delete_cq] = 370 log->acs[nvme_admin_create_cq] = 371 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP); 372 } 373 374 log->acs[nvme_admin_get_log_page] = 375 log->acs[nvme_admin_identify] = 376 log->acs[nvme_admin_abort_cmd] = 377 log->acs[nvme_admin_set_features] = 378 log->acs[nvme_admin_get_features] = 379 log->acs[nvme_admin_async_event] = 380 log->acs[nvme_admin_keep_alive] = 381 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP); 382 } 383 384 static void nvmet_get_cmd_effects_nvm(struct nvme_effects_log *log) 385 { 386 log->iocs[nvme_cmd_read] = 387 log->iocs[nvme_cmd_flush] = 388 log->iocs[nvme_cmd_dsm] = 389 log->iocs[nvme_cmd_resv_acquire] = 390 log->iocs[nvme_cmd_resv_register] = 391 log->iocs[nvme_cmd_resv_release] = 392 log->iocs[nvme_cmd_resv_report] = 393 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP); 394 log->iocs[nvme_cmd_write] = 395 log->iocs[nvme_cmd_write_zeroes] = 396 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC); 397 } 398 399 static void nvmet_get_cmd_effects_zns(struct nvme_effects_log *log) 400 { 401 log->iocs[nvme_cmd_zone_append] = 402 log->iocs[nvme_cmd_zone_mgmt_send] = 403 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC); 404 log->iocs[nvme_cmd_zone_mgmt_recv] = 405 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP); 406 } 407 408 static void nvmet_execute_get_log_cmd_effects_ns(struct nvmet_req *req) 409 { 410 struct nvmet_ctrl *ctrl = req->sq->ctrl; 411 struct nvme_effects_log *log; 412 u16 status = NVME_SC_SUCCESS; 413 414 log = kzalloc_obj(*log); 415 if (!log) { 416 status = NVME_SC_INTERNAL; 417 goto out; 418 } 419 420 switch (req->cmd->get_log_page.csi) { 421 case NVME_CSI_NVM: 422 nvmet_get_cmd_effects_admin(ctrl, log); 423 nvmet_get_cmd_effects_nvm(log); 424 break; 425 case NVME_CSI_ZNS: 426 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) { 427 status = NVME_SC_INVALID_IO_CMD_SET; 428 goto free; 429 } 430 nvmet_get_cmd_effects_admin(ctrl, log); 431 nvmet_get_cmd_effects_nvm(log); 432 nvmet_get_cmd_effects_zns(log); 433 break; 434 default: 435 status = NVME_SC_INVALID_LOG_PAGE; 436 goto free; 437 } 438 439 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log)); 440 free: 441 kfree(log); 442 out: 443 nvmet_req_complete(req, status); 444 } 445 446 static void nvmet_execute_get_log_changed_ns(struct nvmet_req *req) 447 { 448 struct nvmet_ctrl *ctrl = req->sq->ctrl; 449 u16 status = NVME_SC_INTERNAL; 450 size_t len; 451 452 if (req->transfer_len != NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32)) 453 goto out; 454 455 mutex_lock(&ctrl->lock); 456 if (ctrl->nr_changed_ns == U32_MAX) 457 len = sizeof(__le32); 458 else 459 len = ctrl->nr_changed_ns * sizeof(__le32); 460 status = nvmet_copy_to_sgl(req, 0, ctrl->changed_ns_list, len); 461 if (!status) 462 status = nvmet_zero_sgl(req, len, req->transfer_len - len); 463 ctrl->nr_changed_ns = 0; 464 nvmet_clear_aen_bit(req, NVME_AEN_BIT_NS_ATTR); 465 mutex_unlock(&ctrl->lock); 466 out: 467 nvmet_req_complete(req, status); 468 } 469 470 static u32 nvmet_format_ana_group(struct nvmet_req *req, u32 grpid, 471 struct nvme_ana_group_desc *desc) 472 { 473 struct nvmet_ctrl *ctrl = req->sq->ctrl; 474 struct nvmet_ns *ns; 475 unsigned long idx; 476 u32 count = 0; 477 478 if (!(req->cmd->get_log_page.lsp & NVME_ANA_LOG_RGO)) { 479 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) { 480 if (ns->anagrpid == grpid) 481 desc->nsids[count++] = cpu_to_le32(ns->nsid); 482 } 483 } 484 485 desc->grpid = cpu_to_le32(grpid); 486 desc->nnsids = cpu_to_le32(count); 487 desc->chgcnt = cpu_to_le64(nvmet_ana_chgcnt); 488 desc->state = req->port->ana_state[grpid]; 489 memset(desc->rsvd17, 0, sizeof(desc->rsvd17)); 490 return struct_size(desc, nsids, count); 491 } 492 493 static void nvmet_execute_get_log_page_endgrp(struct nvmet_req *req) 494 { 495 u64 host_reads, host_writes, data_units_read, data_units_written; 496 struct nvme_endurance_group_log *log; 497 u16 status; 498 499 /* 500 * The target driver emulates each endurance group as its own 501 * namespace, reusing the nsid as the endurance group identifier. 502 */ 503 req->cmd->common.nsid = cpu_to_le32(le16_to_cpu( 504 req->cmd->get_log_page.lsi)); 505 status = nvmet_req_find_ns(req); 506 if (status) 507 goto out; 508 509 log = kzalloc_obj(*log); 510 if (!log) { 511 status = NVME_SC_INTERNAL; 512 goto out; 513 } 514 515 if (!req->ns->bdev) 516 goto copy; 517 518 host_reads = part_stat_read(req->ns->bdev, ios[READ]); 519 data_units_read = 520 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[READ]), 1000); 521 host_writes = part_stat_read(req->ns->bdev, ios[WRITE]); 522 data_units_written = 523 DIV_ROUND_UP(part_stat_read(req->ns->bdev, sectors[WRITE]), 1000); 524 525 put_unaligned_le64(host_reads, &log->hrc[0]); 526 put_unaligned_le64(data_units_read, &log->dur[0]); 527 put_unaligned_le64(host_writes, &log->hwc[0]); 528 put_unaligned_le64(data_units_written, &log->duw[0]); 529 copy: 530 status = nvmet_copy_to_sgl(req, 0, log, sizeof(*log)); 531 kfree(log); 532 out: 533 nvmet_req_complete(req, status); 534 } 535 536 static void nvmet_execute_get_log_page_ana(struct nvmet_req *req) 537 { 538 struct nvme_ana_rsp_hdr hdr = { 0, }; 539 struct nvme_ana_group_desc *desc; 540 size_t offset = sizeof(struct nvme_ana_rsp_hdr); /* start beyond hdr */ 541 size_t len; 542 u32 grpid; 543 u16 ngrps = 0; 544 u16 status; 545 546 status = NVME_SC_INTERNAL; 547 desc = kmalloc_flex(*desc, nsids, NVMET_MAX_NAMESPACES); 548 if (!desc) 549 goto out; 550 551 down_read(&nvmet_ana_sem); 552 for (grpid = 1; grpid <= NVMET_MAX_ANAGRPS; grpid++) { 553 if (!nvmet_ana_group_enabled[grpid]) 554 continue; 555 len = nvmet_format_ana_group(req, grpid, desc); 556 status = nvmet_copy_to_sgl(req, offset, desc, len); 557 if (status) 558 break; 559 offset += len; 560 ngrps++; 561 } 562 for ( ; grpid <= NVMET_MAX_ANAGRPS; grpid++) { 563 if (nvmet_ana_group_enabled[grpid]) 564 ngrps++; 565 } 566 567 hdr.chgcnt = cpu_to_le64(nvmet_ana_chgcnt); 568 hdr.ngrps = cpu_to_le16(ngrps); 569 nvmet_clear_aen_bit(req, NVME_AEN_BIT_ANA_CHANGE); 570 up_read(&nvmet_ana_sem); 571 572 kfree(desc); 573 574 /* copy the header last once we know the number of groups */ 575 status = nvmet_copy_to_sgl(req, 0, &hdr, sizeof(hdr)); 576 out: 577 nvmet_req_complete(req, status); 578 } 579 580 static void nvmet_execute_get_log_page_features(struct nvmet_req *req) 581 { 582 struct nvme_supported_features_log *features; 583 u16 status; 584 585 features = kzalloc_obj(*features); 586 if (!features) { 587 status = NVME_SC_INTERNAL; 588 goto out; 589 } 590 591 features->fis[NVME_FEAT_NUM_QUEUES] = 592 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE); 593 features->fis[NVME_FEAT_KATO] = 594 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE); 595 features->fis[NVME_FEAT_ASYNC_EVENT] = 596 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE); 597 features->fis[NVME_FEAT_HOST_ID] = 598 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_CSCPE); 599 features->fis[NVME_FEAT_WRITE_PROTECT] = 600 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_NSCPE); 601 features->fis[NVME_FEAT_RESV_MASK] = 602 cpu_to_le32(NVME_FIS_FSUPP | NVME_FIS_NSCPE); 603 604 status = nvmet_copy_to_sgl(req, 0, features, sizeof(*features)); 605 kfree(features); 606 out: 607 nvmet_req_complete(req, status); 608 } 609 610 static void nvmet_execute_get_log_page(struct nvmet_req *req) 611 { 612 if (!nvmet_check_transfer_len(req, nvmet_get_log_page_len(req->cmd))) 613 return; 614 615 switch (req->cmd->get_log_page.lid) { 616 case NVME_LOG_SUPPORTED: 617 return nvmet_execute_get_supported_log_pages(req); 618 case NVME_LOG_ERROR: 619 return nvmet_execute_get_log_page_error(req); 620 case NVME_LOG_SMART: 621 return nvmet_execute_get_log_page_smart(req); 622 case NVME_LOG_FW_SLOT: 623 /* 624 * We only support a single firmware slot which always is 625 * active, so we can zero out the whole firmware slot log and 626 * still claim to fully implement this mandatory log page. 627 */ 628 return nvmet_execute_get_log_page_noop(req); 629 case NVME_LOG_CHANGED_NS: 630 return nvmet_execute_get_log_changed_ns(req); 631 case NVME_LOG_CMD_EFFECTS: 632 return nvmet_execute_get_log_cmd_effects_ns(req); 633 case NVME_LOG_ENDURANCE_GROUP: 634 return nvmet_execute_get_log_page_endgrp(req); 635 case NVME_LOG_ANA: 636 return nvmet_execute_get_log_page_ana(req); 637 case NVME_LOG_FEATURES: 638 return nvmet_execute_get_log_page_features(req); 639 case NVME_LOG_RMI: 640 return nvmet_execute_get_log_page_rmi(req); 641 case NVME_LOG_RESERVATION: 642 return nvmet_execute_get_log_page_resv(req); 643 } 644 pr_debug("unhandled lid %d on qid %d\n", 645 req->cmd->get_log_page.lid, req->sq->qid); 646 req->error_loc = offsetof(struct nvme_get_log_page_command, lid); 647 nvmet_req_complete(req, NVME_SC_INVALID_FIELD | NVME_STATUS_DNR); 648 } 649 650 static void nvmet_execute_identify_ctrl(struct nvmet_req *req) 651 { 652 struct nvmet_ctrl *ctrl = req->sq->ctrl; 653 struct nvmet_subsys *subsys = ctrl->subsys; 654 struct nvme_id_ctrl *id; 655 u32 cmd_capsule_size, ctratt; 656 u16 status = 0; 657 658 if (!subsys->subsys_discovered) { 659 mutex_lock(&subsys->lock); 660 subsys->subsys_discovered = true; 661 mutex_unlock(&subsys->lock); 662 } 663 664 id = kzalloc_obj(*id); 665 if (!id) { 666 status = NVME_SC_INTERNAL; 667 goto out; 668 } 669 670 id->vid = cpu_to_le16(subsys->vendor_id); 671 id->ssvid = cpu_to_le16(subsys->subsys_vendor_id); 672 673 memcpy(id->sn, ctrl->subsys->serial, NVMET_SN_MAX_SIZE); 674 memcpy_and_pad(id->mn, sizeof(id->mn), subsys->model_number, 675 strlen(subsys->model_number), ' '); 676 memcpy_and_pad(id->fr, sizeof(id->fr), 677 subsys->firmware_rev, strlen(subsys->firmware_rev), ' '); 678 679 put_unaligned_le24(subsys->ieee_oui, id->ieee); 680 681 id->rab = 6; 682 683 if (nvmet_is_disc_subsys(ctrl->subsys)) 684 id->cntrltype = NVME_CTRL_DISC; 685 else 686 id->cntrltype = NVME_CTRL_IO; 687 688 /* we support multiple ports, multiples hosts and ANA: */ 689 id->cmic = NVME_CTRL_CMIC_MULTI_PORT | NVME_CTRL_CMIC_MULTI_CTRL | 690 NVME_CTRL_CMIC_ANA; 691 692 /* Limit MDTS according to port config or transport capability */ 693 id->mdts = nvmet_ctrl_mdts(req); 694 id->cntlid = cpu_to_le16(ctrl->cntlid); 695 id->ver = cpu_to_le32(ctrl->subsys->ver); 696 697 /* XXX: figure out what to do about RTD3R/RTD3 */ 698 id->oaes = cpu_to_le32(NVMET_AEN_CFG_OPTIONAL); 699 ctratt = NVME_CTRL_ATTR_HID_128_BIT | NVME_CTRL_ATTR_TBKAS; 700 if (nvmet_is_pci_ctrl(ctrl)) 701 ctratt |= NVME_CTRL_ATTR_RHII; 702 id->ctratt = cpu_to_le32(ctratt); 703 704 id->oacs = 0; 705 706 /* 707 * We don't really have a practical limit on the number of abort 708 * commands. But we don't do anything useful for abort either, so 709 * no point in allowing more abort commands than the spec requires. 710 */ 711 id->acl = 3; 712 713 id->aerl = NVMET_ASYNC_EVENTS - 1; 714 715 /* first slot is read-only, only one slot supported */ 716 id->frmw = (1 << 0) | (1 << 1); 717 id->lpa = (1 << 0) | (1 << 1) | (1 << 2); 718 id->elpe = NVMET_ERROR_LOG_SLOTS - 1; 719 id->npss = 0; 720 721 /* We support keep-alive timeout in granularity of seconds */ 722 id->kas = cpu_to_le16(NVMET_KAS); 723 724 id->sqes = (0x6 << 4) | 0x6; 725 id->cqes = (0x4 << 4) | 0x4; 726 727 /* no enforcement soft-limit for maxcmd - pick arbitrary high value */ 728 id->maxcmd = cpu_to_le16(NVMET_MAX_CMD(ctrl)); 729 730 id->nn = cpu_to_le32(NVMET_MAX_NAMESPACES); 731 id->mnan = cpu_to_le32(NVMET_MAX_NAMESPACES); 732 id->oncs = cpu_to_le16(NVME_CTRL_ONCS_DSM | 733 NVME_CTRL_ONCS_WRITE_ZEROES | 734 NVME_CTRL_ONCS_RESERVATIONS); 735 736 /* XXX: don't report vwc if the underlying device is write through */ 737 id->vwc = NVME_CTRL_VWC_PRESENT; 738 739 /* 740 * We can't support atomic writes bigger than a LBA without support 741 * from the backend device. 742 */ 743 id->awun = 0; 744 id->awupf = 0; 745 746 /* we always support SGLs */ 747 id->sgls = cpu_to_le32(NVME_CTRL_SGLS_BYTE_ALIGNED); 748 if (ctrl->ops->flags & NVMF_KEYED_SGLS) 749 id->sgls |= cpu_to_le32(NVME_CTRL_SGLS_KSDBDS); 750 if (req->port->inline_data_size) 751 id->sgls |= cpu_to_le32(NVME_CTRL_SGLS_SAOS); 752 753 strscpy(id->subnqn, ctrl->subsys->subsysnqn, sizeof(id->subnqn)); 754 755 /* 756 * Max command capsule size is sqe + in-capsule data size. 757 * Disable in-capsule data for Metadata capable controllers. 758 */ 759 cmd_capsule_size = sizeof(struct nvme_command); 760 if (!ctrl->pi_support) 761 cmd_capsule_size += req->port->inline_data_size; 762 id->ioccsz = cpu_to_le32(cmd_capsule_size / 16); 763 764 /* Max response capsule size is cqe */ 765 id->iorcsz = cpu_to_le32(sizeof(struct nvme_completion) / 16); 766 767 id->msdbd = ctrl->ops->msdbd; 768 769 /* 770 * Endurance group identifier is 16 bits, so we can't let namespaces 771 * overflow that since we reuse the nsid 772 */ 773 BUILD_BUG_ON(NVMET_MAX_NAMESPACES > USHRT_MAX); 774 id->endgidmax = cpu_to_le16(NVMET_MAX_NAMESPACES); 775 776 id->anacap = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4); 777 id->anatt = 10; /* random value */ 778 id->anagrpmax = cpu_to_le32(NVMET_MAX_ANAGRPS); 779 id->nanagrpid = cpu_to_le32(NVMET_MAX_ANAGRPS); 780 781 /* 782 * Meh, we don't really support any power state. Fake up the same 783 * values that qemu does. 784 */ 785 id->psd[0].max_power = cpu_to_le16(0x9c4); 786 id->psd[0].entry_lat = cpu_to_le32(0x10); 787 id->psd[0].exit_lat = cpu_to_le32(0x4); 788 789 id->nwpc = 1 << 0; /* write protect and no write protect */ 790 791 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id)); 792 793 kfree(id); 794 out: 795 nvmet_req_complete(req, status); 796 } 797 798 static void nvmet_execute_identify_ns(struct nvmet_req *req) 799 { 800 struct nvme_id_ns *id; 801 u16 status; 802 803 if (le32_to_cpu(req->cmd->identify.nsid) == NVME_NSID_ALL) { 804 req->error_loc = offsetof(struct nvme_identify, nsid); 805 status = NVME_SC_INVALID_NS | NVME_STATUS_DNR; 806 goto out; 807 } 808 809 id = kzalloc_obj(*id); 810 if (!id) { 811 status = NVME_SC_INTERNAL; 812 goto out; 813 } 814 815 /* return an all zeroed buffer if we can't find an active namespace */ 816 status = nvmet_req_find_ns(req); 817 if (status) { 818 status = 0; 819 goto done; 820 } 821 822 if (nvmet_ns_revalidate(req->ns)) { 823 mutex_lock(&req->ns->subsys->lock); 824 nvmet_ns_changed(req->ns->subsys, req->ns->nsid); 825 mutex_unlock(&req->ns->subsys->lock); 826 } 827 828 /* 829 * nuse = ncap = nsze isn't always true, but we have no way to find 830 * that out from the underlying device. 831 */ 832 id->ncap = id->nsze = 833 cpu_to_le64(req->ns->size >> req->ns->blksize_shift); 834 switch (req->port->ana_state[req->ns->anagrpid]) { 835 case NVME_ANA_INACCESSIBLE: 836 case NVME_ANA_PERSISTENT_LOSS: 837 break; 838 default: 839 id->nuse = id->nsze; 840 break; 841 } 842 843 if (req->ns->bdev) 844 nvmet_bdev_set_limits(req->ns->bdev, id); 845 846 /* 847 * We just provide a single LBA format that matches what the 848 * underlying device reports. 849 */ 850 id->nlbaf = 0; 851 id->flbas = 0; 852 853 /* 854 * Our namespace might always be shared. Not just with other 855 * controllers, but also with any other user of the block device. 856 */ 857 id->nmic = NVME_NS_NMIC_SHARED; 858 id->anagrpid = cpu_to_le32(req->ns->anagrpid); 859 860 if (req->ns->pr.enable) 861 id->rescap = NVME_PR_SUPPORT_WRITE_EXCLUSIVE | 862 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS | 863 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY | 864 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY | 865 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS | 866 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS | 867 NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF; 868 869 /* 870 * Since we don't know any better, every namespace is its own endurance 871 * group. 872 */ 873 id->endgid = cpu_to_le16(req->ns->nsid); 874 875 memcpy(&id->nguid, &req->ns->nguid, sizeof(id->nguid)); 876 877 id->lbaf[0].ds = req->ns->blksize_shift; 878 879 if (req->sq->ctrl->pi_support && nvmet_ns_has_pi(req->ns)) { 880 id->dpc = NVME_NS_DPC_PI_FIRST | NVME_NS_DPC_PI_LAST | 881 NVME_NS_DPC_PI_TYPE1 | NVME_NS_DPC_PI_TYPE2 | 882 NVME_NS_DPC_PI_TYPE3; 883 id->mc = NVME_MC_EXTENDED_LBA; 884 id->dps = req->ns->pi_type; 885 id->flbas = NVME_NS_FLBAS_META_EXT; 886 id->lbaf[0].ms = cpu_to_le16(req->ns->metadata_size); 887 } 888 889 if (req->ns->readonly) 890 id->nsattr |= NVME_NS_ATTR_RO; 891 done: 892 if (!status) 893 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id)); 894 895 kfree(id); 896 out: 897 nvmet_req_complete(req, status); 898 } 899 900 static void nvmet_execute_identify_endgrp_list(struct nvmet_req *req) 901 { 902 u16 min_endgid = le16_to_cpu(req->cmd->identify.cnssid); 903 static const int buf_size = NVME_IDENTIFY_DATA_SIZE; 904 struct nvmet_ctrl *ctrl = req->sq->ctrl; 905 struct nvmet_ns *ns; 906 unsigned long idx; 907 __le16 *list; 908 u16 status; 909 int i = 1; 910 911 list = kzalloc(buf_size, GFP_KERNEL); 912 if (!list) { 913 status = NVME_SC_INTERNAL; 914 goto out; 915 } 916 917 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) { 918 if (ns->nsid <= min_endgid) 919 continue; 920 921 list[i++] = cpu_to_le16(ns->nsid); 922 if (i == buf_size / sizeof(__le16)) 923 break; 924 } 925 926 list[0] = cpu_to_le16(i - 1); 927 status = nvmet_copy_to_sgl(req, 0, list, buf_size); 928 kfree(list); 929 out: 930 nvmet_req_complete(req, status); 931 } 932 933 static void nvmet_execute_identify_nslist(struct nvmet_req *req, bool match_css) 934 { 935 static const int buf_size = NVME_IDENTIFY_DATA_SIZE; 936 struct nvmet_ctrl *ctrl = req->sq->ctrl; 937 struct nvmet_ns *ns; 938 unsigned long idx; 939 u32 min_nsid = le32_to_cpu(req->cmd->identify.nsid); 940 __le32 *list; 941 u16 status = 0; 942 int i = 0; 943 944 /* 945 * NSID values 0xFFFFFFFE and NVME_NSID_ALL are invalid 946 * See NVMe Base Specification, Active Namespace ID list (CNS 02h). 947 */ 948 if (min_nsid == 0xFFFFFFFE || min_nsid == NVME_NSID_ALL) { 949 req->error_loc = offsetof(struct nvme_identify, nsid); 950 status = NVME_SC_INVALID_NS | NVME_STATUS_DNR; 951 goto out; 952 } 953 954 list = kzalloc(buf_size, GFP_KERNEL); 955 if (!list) { 956 status = NVME_SC_INTERNAL; 957 goto out; 958 } 959 960 nvmet_for_each_enabled_ns(&ctrl->subsys->namespaces, idx, ns) { 961 if (ns->nsid <= min_nsid) 962 continue; 963 if (match_css && ns->csi != req->cmd->identify.csi) 964 continue; 965 list[i++] = cpu_to_le32(ns->nsid); 966 if (i == buf_size / sizeof(__le32)) 967 break; 968 } 969 970 status = nvmet_copy_to_sgl(req, 0, list, buf_size); 971 972 kfree(list); 973 out: 974 nvmet_req_complete(req, status); 975 } 976 977 static u16 nvmet_copy_ns_identifier(struct nvmet_req *req, u8 type, u8 len, 978 void *id, off_t *off) 979 { 980 struct nvme_ns_id_desc desc = { 981 .nidt = type, 982 .nidl = len, 983 }; 984 u16 status; 985 986 status = nvmet_copy_to_sgl(req, *off, &desc, sizeof(desc)); 987 if (status) 988 return status; 989 *off += sizeof(desc); 990 991 status = nvmet_copy_to_sgl(req, *off, id, len); 992 if (status) 993 return status; 994 *off += len; 995 996 return 0; 997 } 998 999 static void nvmet_execute_identify_desclist(struct nvmet_req *req) 1000 { 1001 off_t off = 0; 1002 u16 status; 1003 1004 status = nvmet_req_find_ns(req); 1005 if (status) 1006 goto out; 1007 1008 if (memchr_inv(&req->ns->uuid, 0, sizeof(req->ns->uuid))) { 1009 status = nvmet_copy_ns_identifier(req, NVME_NIDT_UUID, 1010 NVME_NIDT_UUID_LEN, 1011 &req->ns->uuid, &off); 1012 if (status) 1013 goto out; 1014 } 1015 if (memchr_inv(req->ns->nguid, 0, sizeof(req->ns->nguid))) { 1016 status = nvmet_copy_ns_identifier(req, NVME_NIDT_NGUID, 1017 NVME_NIDT_NGUID_LEN, 1018 &req->ns->nguid, &off); 1019 if (status) 1020 goto out; 1021 } 1022 1023 status = nvmet_copy_ns_identifier(req, NVME_NIDT_CSI, 1024 NVME_NIDT_CSI_LEN, 1025 &req->ns->csi, &off); 1026 if (status) 1027 goto out; 1028 1029 if (sg_zero_buffer(req->sg, req->sg_cnt, NVME_IDENTIFY_DATA_SIZE - off, 1030 off) != NVME_IDENTIFY_DATA_SIZE - off) 1031 status = NVME_SC_INTERNAL | NVME_STATUS_DNR; 1032 1033 out: 1034 nvmet_req_complete(req, status); 1035 } 1036 1037 static void nvmet_execute_identify_ctrl_nvm(struct nvmet_req *req) 1038 { 1039 /* Not supported: return zeroes */ 1040 nvmet_req_complete(req, 1041 nvmet_zero_sgl(req, 0, sizeof(struct nvme_id_ctrl_nvm))); 1042 } 1043 1044 static void nvme_execute_identify_ns_nvm(struct nvmet_req *req) 1045 { 1046 u16 status; 1047 struct nvme_id_ns_nvm *id; 1048 1049 status = nvmet_req_find_ns(req); 1050 if (status) 1051 goto out; 1052 1053 id = kzalloc_obj(*id); 1054 if (!id) { 1055 status = NVME_SC_INTERNAL; 1056 goto out; 1057 } 1058 if (req->ns->bdev) 1059 nvmet_bdev_set_nvm_limits(req->ns->bdev, id); 1060 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id)); 1061 kfree(id); 1062 out: 1063 nvmet_req_complete(req, status); 1064 } 1065 1066 static void nvmet_execute_id_cs_indep(struct nvmet_req *req) 1067 { 1068 struct nvme_id_ns_cs_indep *id; 1069 u16 status; 1070 1071 status = nvmet_req_find_ns(req); 1072 if (status) 1073 goto out; 1074 1075 id = kzalloc_obj(*id); 1076 if (!id) { 1077 status = NVME_SC_INTERNAL; 1078 goto out; 1079 } 1080 1081 id->nstat = NVME_NSTAT_NRDY; 1082 id->anagrpid = cpu_to_le32(req->ns->anagrpid); 1083 id->nmic = NVME_NS_NMIC_SHARED; 1084 if (req->ns->readonly) 1085 id->nsattr |= NVME_NS_ATTR_RO; 1086 if (req->ns->bdev && bdev_rot(req->ns->bdev)) 1087 id->nsfeat |= NVME_NS_ROTATIONAL; 1088 /* 1089 * We need flush command to flush the file's metadata, 1090 * so report supporting vwc if backend is file, even 1091 * though buffered_io is disable. 1092 */ 1093 if (req->ns->bdev && !bdev_write_cache(req->ns->bdev)) 1094 id->nsfeat |= NVME_NS_VWC_NOT_PRESENT; 1095 1096 status = nvmet_copy_to_sgl(req, 0, id, sizeof(*id)); 1097 kfree(id); 1098 out: 1099 nvmet_req_complete(req, status); 1100 } 1101 1102 static void nvmet_execute_identify(struct nvmet_req *req) 1103 { 1104 if (!nvmet_check_transfer_len(req, NVME_IDENTIFY_DATA_SIZE)) 1105 return; 1106 1107 switch (req->cmd->identify.cns) { 1108 case NVME_ID_CNS_NS: 1109 nvmet_execute_identify_ns(req); 1110 return; 1111 case NVME_ID_CNS_CTRL: 1112 nvmet_execute_identify_ctrl(req); 1113 return; 1114 case NVME_ID_CNS_NS_ACTIVE_LIST: 1115 nvmet_execute_identify_nslist(req, false); 1116 return; 1117 case NVME_ID_CNS_NS_DESC_LIST: 1118 nvmet_execute_identify_desclist(req); 1119 return; 1120 case NVME_ID_CNS_CS_NS: 1121 switch (req->cmd->identify.csi) { 1122 case NVME_CSI_NVM: 1123 nvme_execute_identify_ns_nvm(req); 1124 return; 1125 case NVME_CSI_ZNS: 1126 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED)) { 1127 nvmet_execute_identify_ns_zns(req); 1128 return; 1129 } 1130 break; 1131 } 1132 break; 1133 case NVME_ID_CNS_CS_CTRL: 1134 switch (req->cmd->identify.csi) { 1135 case NVME_CSI_NVM: 1136 nvmet_execute_identify_ctrl_nvm(req); 1137 return; 1138 case NVME_CSI_ZNS: 1139 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED)) { 1140 nvmet_execute_identify_ctrl_zns(req); 1141 return; 1142 } 1143 break; 1144 } 1145 break; 1146 case NVME_ID_CNS_NS_ACTIVE_LIST_CS: 1147 nvmet_execute_identify_nslist(req, true); 1148 return; 1149 case NVME_ID_CNS_NS_CS_INDEP: 1150 nvmet_execute_id_cs_indep(req); 1151 return; 1152 case NVME_ID_CNS_ENDGRP_LIST: 1153 nvmet_execute_identify_endgrp_list(req); 1154 return; 1155 } 1156 1157 pr_debug("unhandled identify cns %d on qid %d\n", 1158 req->cmd->identify.cns, req->sq->qid); 1159 req->error_loc = offsetof(struct nvme_identify, cns); 1160 nvmet_req_complete(req, NVME_SC_INVALID_FIELD | NVME_STATUS_DNR); 1161 } 1162 1163 /* 1164 * A "minimum viable" abort implementation: the command is mandatory in the 1165 * spec, but we are not required to do any useful work. We couldn't really 1166 * do a useful abort, so don't bother even with waiting for the command 1167 * to be executed and return immediately telling the command to abort 1168 * wasn't found. 1169 */ 1170 static void nvmet_execute_abort(struct nvmet_req *req) 1171 { 1172 if (!nvmet_check_transfer_len(req, 0)) 1173 return; 1174 nvmet_set_result(req, 1); 1175 nvmet_req_complete(req, 0); 1176 } 1177 1178 static u16 nvmet_write_protect_flush_sync(struct nvmet_req *req) 1179 { 1180 u16 status; 1181 1182 if (req->ns->file) 1183 status = nvmet_file_flush(req); 1184 else 1185 status = nvmet_bdev_flush(req); 1186 1187 if (status) 1188 pr_err("write protect flush failed nsid: %u\n", req->ns->nsid); 1189 return status; 1190 } 1191 1192 static u16 nvmet_set_feat_write_protect(struct nvmet_req *req) 1193 { 1194 u32 write_protect = le32_to_cpu(req->cmd->common.cdw11); 1195 struct nvmet_subsys *subsys = nvmet_req_subsys(req); 1196 u16 status; 1197 1198 status = nvmet_req_find_ns(req); 1199 if (status) 1200 return status; 1201 1202 mutex_lock(&subsys->lock); 1203 switch (write_protect) { 1204 case NVME_NS_WRITE_PROTECT: 1205 req->ns->readonly = true; 1206 status = nvmet_write_protect_flush_sync(req); 1207 if (status) 1208 req->ns->readonly = false; 1209 break; 1210 case NVME_NS_NO_WRITE_PROTECT: 1211 req->ns->readonly = false; 1212 status = 0; 1213 break; 1214 default: 1215 break; 1216 } 1217 1218 if (!status) 1219 nvmet_ns_changed(subsys, req->ns->nsid); 1220 mutex_unlock(&subsys->lock); 1221 return status; 1222 } 1223 1224 u16 nvmet_set_feat_kato(struct nvmet_req *req) 1225 { 1226 u32 val32 = le32_to_cpu(req->cmd->common.cdw11); 1227 1228 nvmet_stop_keep_alive_timer(req->sq->ctrl); 1229 req->sq->ctrl->kato = DIV_ROUND_UP(val32, 1000); 1230 nvmet_start_keep_alive_timer(req->sq->ctrl); 1231 1232 nvmet_set_result(req, req->sq->ctrl->kato); 1233 1234 return 0; 1235 } 1236 1237 u16 nvmet_set_feat_async_event(struct nvmet_req *req, u32 mask) 1238 { 1239 u32 val32 = le32_to_cpu(req->cmd->common.cdw11); 1240 1241 if (val32 & ~mask) { 1242 req->error_loc = offsetof(struct nvme_common_command, cdw11); 1243 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1244 } 1245 1246 WRITE_ONCE(req->sq->ctrl->aen_enabled, val32); 1247 nvmet_set_result(req, val32); 1248 1249 return 0; 1250 } 1251 1252 static u16 nvmet_set_feat_host_id(struct nvmet_req *req) 1253 { 1254 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1255 1256 if (!nvmet_is_pci_ctrl(ctrl)) 1257 return NVME_SC_CMD_SEQ_ERROR | NVME_STATUS_DNR; 1258 1259 /* 1260 * The NVMe base specifications v2.1 recommends supporting 128-bits host 1261 * IDs (section 5.1.25.1.28.1). However, that same section also says 1262 * that "The controller may support a 64-bit Host Identifier and/or an 1263 * extended 128-bit Host Identifier". So simplify this support and do 1264 * not support 64-bits host IDs to avoid needing to check that all 1265 * controllers associated with the same subsystem all use the same host 1266 * ID size. 1267 */ 1268 if (!(req->cmd->common.cdw11 & cpu_to_le32(1 << 0))) { 1269 req->error_loc = offsetof(struct nvme_common_command, cdw11); 1270 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1271 } 1272 1273 return nvmet_copy_from_sgl(req, 0, &req->sq->ctrl->hostid, 1274 sizeof(req->sq->ctrl->hostid)); 1275 } 1276 1277 static u16 nvmet_set_feat_irq_coalesce(struct nvmet_req *req) 1278 { 1279 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1280 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11); 1281 struct nvmet_feat_irq_coalesce irqc = { 1282 .time = (cdw11 >> 8) & 0xff, 1283 .thr = cdw11 & 0xff, 1284 }; 1285 1286 /* 1287 * This feature is not supported for fabrics controllers and mandatory 1288 * for PCI controllers. 1289 */ 1290 if (!nvmet_is_pci_ctrl(ctrl)) { 1291 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1292 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1293 } 1294 1295 return ctrl->ops->set_feature(ctrl, NVME_FEAT_IRQ_COALESCE, &irqc); 1296 } 1297 1298 static u16 nvmet_set_feat_irq_config(struct nvmet_req *req) 1299 { 1300 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1301 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11); 1302 struct nvmet_feat_irq_config irqcfg = { 1303 .iv = cdw11 & 0xffff, 1304 .cd = (cdw11 >> 16) & 0x1, 1305 }; 1306 1307 /* 1308 * This feature is not supported for fabrics controllers and mandatory 1309 * for PCI controllers. 1310 */ 1311 if (!nvmet_is_pci_ctrl(ctrl)) { 1312 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1313 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1314 } 1315 1316 return ctrl->ops->set_feature(ctrl, NVME_FEAT_IRQ_CONFIG, &irqcfg); 1317 } 1318 1319 static u16 nvmet_set_feat_arbitration(struct nvmet_req *req) 1320 { 1321 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1322 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11); 1323 struct nvmet_feat_arbitration arb = { 1324 .hpw = (cdw11 >> 24) & 0xff, 1325 .mpw = (cdw11 >> 16) & 0xff, 1326 .lpw = (cdw11 >> 8) & 0xff, 1327 .ab = cdw11 & 0x3, 1328 }; 1329 1330 if (!ctrl->ops->set_feature) { 1331 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1332 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1333 } 1334 1335 return ctrl->ops->set_feature(ctrl, NVME_FEAT_ARBITRATION, &arb); 1336 } 1337 1338 void nvmet_execute_set_features(struct nvmet_req *req) 1339 { 1340 struct nvmet_ctrl *ctrl = nvmet_req_ctrl(req); 1341 u32 cdw10 = le32_to_cpu(req->cmd->common.cdw10); 1342 u32 cdw11 = le32_to_cpu(req->cmd->common.cdw11); 1343 u16 status = 0; 1344 u16 nsqr; 1345 u16 ncqr; 1346 1347 if (!nvmet_check_data_len_lte(req, 0)) 1348 return; 1349 1350 switch (cdw10 & 0xff) { 1351 case NVME_FEAT_ARBITRATION: 1352 status = nvmet_set_feat_arbitration(req); 1353 break; 1354 case NVME_FEAT_NUM_QUEUES: 1355 ncqr = (cdw11 >> 16) & 0xffff; 1356 nsqr = cdw11 & 0xffff; 1357 if (ncqr == 0xffff || nsqr == 0xffff) { 1358 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1359 break; 1360 } 1361 nvmet_set_result(req, 1362 (ctrl->max_qid - 1) | ((ctrl->max_qid - 1) << 16)); 1363 break; 1364 case NVME_FEAT_IRQ_COALESCE: 1365 status = nvmet_set_feat_irq_coalesce(req); 1366 break; 1367 case NVME_FEAT_IRQ_CONFIG: 1368 status = nvmet_set_feat_irq_config(req); 1369 break; 1370 case NVME_FEAT_KATO: 1371 status = nvmet_set_feat_kato(req); 1372 break; 1373 case NVME_FEAT_ASYNC_EVENT: 1374 status = nvmet_set_feat_async_event(req, NVMET_AEN_CFG_ALL); 1375 break; 1376 case NVME_FEAT_HOST_ID: 1377 status = nvmet_set_feat_host_id(req); 1378 break; 1379 case NVME_FEAT_WRITE_PROTECT: 1380 status = nvmet_set_feat_write_protect(req); 1381 break; 1382 case NVME_FEAT_RESV_MASK: 1383 status = nvmet_set_feat_resv_notif_mask(req, cdw11); 1384 break; 1385 default: 1386 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1387 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1388 break; 1389 } 1390 1391 nvmet_req_complete(req, status); 1392 } 1393 1394 static u16 nvmet_get_feat_write_protect(struct nvmet_req *req) 1395 { 1396 struct nvmet_subsys *subsys = nvmet_req_subsys(req); 1397 u32 result; 1398 1399 result = nvmet_req_find_ns(req); 1400 if (result) 1401 return result; 1402 1403 mutex_lock(&subsys->lock); 1404 if (req->ns->readonly == true) 1405 result = NVME_NS_WRITE_PROTECT; 1406 else 1407 result = NVME_NS_NO_WRITE_PROTECT; 1408 nvmet_set_result(req, result); 1409 mutex_unlock(&subsys->lock); 1410 1411 return 0; 1412 } 1413 1414 static u16 nvmet_get_feat_irq_coalesce(struct nvmet_req *req) 1415 { 1416 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1417 struct nvmet_feat_irq_coalesce irqc = { }; 1418 u16 status; 1419 1420 /* 1421 * This feature is not supported for fabrics controllers and mandatory 1422 * for PCI controllers. 1423 */ 1424 if (!nvmet_is_pci_ctrl(ctrl)) { 1425 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1426 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1427 } 1428 1429 status = ctrl->ops->get_feature(ctrl, NVME_FEAT_IRQ_COALESCE, &irqc); 1430 if (status != NVME_SC_SUCCESS) 1431 return status; 1432 1433 nvmet_set_result(req, ((u32)irqc.time << 8) | (u32)irqc.thr); 1434 1435 return NVME_SC_SUCCESS; 1436 } 1437 1438 static u16 nvmet_get_feat_irq_config(struct nvmet_req *req) 1439 { 1440 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1441 u32 iv = le32_to_cpu(req->cmd->common.cdw11) & 0xffff; 1442 struct nvmet_feat_irq_config irqcfg = { .iv = iv }; 1443 u16 status; 1444 1445 /* 1446 * This feature is not supported for fabrics controllers and mandatory 1447 * for PCI controllers. 1448 */ 1449 if (!nvmet_is_pci_ctrl(ctrl)) { 1450 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1451 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1452 } 1453 1454 status = ctrl->ops->get_feature(ctrl, NVME_FEAT_IRQ_CONFIG, &irqcfg); 1455 if (status != NVME_SC_SUCCESS) 1456 return status; 1457 1458 nvmet_set_result(req, ((u32)irqcfg.cd << 16) | iv); 1459 1460 return NVME_SC_SUCCESS; 1461 } 1462 1463 static u16 nvmet_get_feat_arbitration(struct nvmet_req *req) 1464 { 1465 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1466 struct nvmet_feat_arbitration arb = { }; 1467 u16 status; 1468 1469 if (!ctrl->ops->get_feature) { 1470 req->error_loc = offsetof(struct nvme_common_command, cdw10); 1471 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1472 } 1473 1474 status = ctrl->ops->get_feature(ctrl, NVME_FEAT_ARBITRATION, &arb); 1475 if (status != NVME_SC_SUCCESS) 1476 return status; 1477 1478 nvmet_set_result(req, 1479 ((u32)arb.hpw << 24) | 1480 ((u32)arb.mpw << 16) | 1481 ((u32)arb.lpw << 8) | 1482 (arb.ab & 0x3)); 1483 1484 return NVME_SC_SUCCESS; 1485 } 1486 1487 void nvmet_get_feat_kato(struct nvmet_req *req) 1488 { 1489 nvmet_set_result(req, req->sq->ctrl->kato * 1000); 1490 } 1491 1492 void nvmet_get_feat_async_event(struct nvmet_req *req) 1493 { 1494 nvmet_set_result(req, READ_ONCE(req->sq->ctrl->aen_enabled)); 1495 } 1496 1497 void nvmet_execute_get_features(struct nvmet_req *req) 1498 { 1499 struct nvmet_ctrl *ctrl = nvmet_req_ctrl(req); 1500 u32 cdw10 = le32_to_cpu(req->cmd->common.cdw10); 1501 u16 status = 0; 1502 1503 if (!nvmet_check_transfer_len(req, nvmet_feat_data_len(req, cdw10))) 1504 return; 1505 1506 switch (cdw10 & 0xff) { 1507 /* 1508 * These features are mandatory in the spec, but we don't 1509 * have a useful way to implement them. We'll eventually 1510 * need to come up with some fake values for these. 1511 */ 1512 #if 0 1513 case NVME_FEAT_POWER_MGMT: 1514 break; 1515 case NVME_FEAT_TEMP_THRESH: 1516 break; 1517 case NVME_FEAT_ERR_RECOVERY: 1518 break; 1519 case NVME_FEAT_WRITE_ATOMIC: 1520 break; 1521 #endif 1522 case NVME_FEAT_ARBITRATION: 1523 status = nvmet_get_feat_arbitration(req); 1524 break; 1525 case NVME_FEAT_IRQ_COALESCE: 1526 status = nvmet_get_feat_irq_coalesce(req); 1527 break; 1528 case NVME_FEAT_IRQ_CONFIG: 1529 status = nvmet_get_feat_irq_config(req); 1530 break; 1531 case NVME_FEAT_ASYNC_EVENT: 1532 nvmet_get_feat_async_event(req); 1533 break; 1534 case NVME_FEAT_VOLATILE_WC: 1535 nvmet_set_result(req, 1); 1536 break; 1537 case NVME_FEAT_NUM_QUEUES: 1538 nvmet_set_result(req, 1539 (ctrl->max_qid-1) | ((ctrl->max_qid-1) << 16)); 1540 break; 1541 case NVME_FEAT_KATO: 1542 nvmet_get_feat_kato(req); 1543 break; 1544 case NVME_FEAT_HOST_ID: 1545 /* need 128-bit host identifier flag */ 1546 if (!(req->cmd->common.cdw11 & cpu_to_le32(1 << 0))) { 1547 req->error_loc = 1548 offsetof(struct nvme_common_command, cdw11); 1549 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1550 break; 1551 } 1552 1553 status = nvmet_copy_to_sgl(req, 0, &req->sq->ctrl->hostid, 1554 sizeof(req->sq->ctrl->hostid)); 1555 break; 1556 case NVME_FEAT_WRITE_PROTECT: 1557 status = nvmet_get_feat_write_protect(req); 1558 break; 1559 case NVME_FEAT_RESV_MASK: 1560 status = nvmet_get_feat_resv_notif_mask(req); 1561 break; 1562 default: 1563 req->error_loc = 1564 offsetof(struct nvme_common_command, cdw10); 1565 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1566 break; 1567 } 1568 1569 nvmet_req_complete(req, status); 1570 } 1571 1572 void nvmet_execute_async_event(struct nvmet_req *req) 1573 { 1574 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1575 1576 if (!nvmet_check_transfer_len(req, 0)) 1577 return; 1578 1579 mutex_lock(&ctrl->lock); 1580 if (ctrl->nr_async_event_cmds >= NVMET_ASYNC_EVENTS) { 1581 mutex_unlock(&ctrl->lock); 1582 nvmet_req_complete(req, NVME_SC_ASYNC_LIMIT | NVME_STATUS_DNR); 1583 return; 1584 } 1585 ctrl->async_event_cmds[ctrl->nr_async_event_cmds++] = req; 1586 mutex_unlock(&ctrl->lock); 1587 1588 queue_work(nvmet_aen_wq, &ctrl->async_event_work); 1589 } 1590 1591 void nvmet_execute_keep_alive(struct nvmet_req *req) 1592 { 1593 struct nvmet_ctrl *ctrl = req->sq->ctrl; 1594 u16 status = 0; 1595 1596 if (!nvmet_check_transfer_len(req, 0)) 1597 return; 1598 1599 if (!ctrl->kato) { 1600 status = NVME_SC_KA_TIMEOUT_INVALID; 1601 goto out; 1602 } 1603 1604 pr_debug("ctrl %d update keep-alive timer for %d secs\n", 1605 ctrl->cntlid, ctrl->kato); 1606 mod_delayed_work(system_percpu_wq, &ctrl->ka_work, ctrl->kato * HZ); 1607 out: 1608 nvmet_req_complete(req, status); 1609 } 1610 1611 u32 nvmet_admin_cmd_data_len(struct nvmet_req *req) 1612 { 1613 struct nvme_command *cmd = req->cmd; 1614 1615 if (nvme_is_fabrics(cmd)) 1616 return nvmet_fabrics_admin_cmd_data_len(req); 1617 if (nvmet_is_disc_subsys(nvmet_req_subsys(req))) 1618 return nvmet_discovery_cmd_data_len(req); 1619 1620 switch (cmd->common.opcode) { 1621 case nvme_admin_get_log_page: 1622 return nvmet_get_log_page_len(cmd); 1623 case nvme_admin_identify: 1624 return NVME_IDENTIFY_DATA_SIZE; 1625 case nvme_admin_get_features: 1626 return nvmet_feat_data_len(req, le32_to_cpu(cmd->common.cdw10)); 1627 default: 1628 return 0; 1629 } 1630 } 1631 1632 u16 nvmet_parse_admin_cmd(struct nvmet_req *req) 1633 { 1634 struct nvme_command *cmd = req->cmd; 1635 u16 ret; 1636 1637 if (nvme_is_fabrics(cmd)) 1638 return nvmet_parse_fabrics_admin_cmd(req); 1639 if (nvmet_is_disc_subsys(nvmet_req_subsys(req))) 1640 return nvmet_parse_discovery_cmd(req); 1641 1642 ret = nvmet_check_ctrl_status(req); 1643 if (unlikely(ret)) 1644 return ret; 1645 1646 /* For PCI controllers, admin commands shall not use SGL. */ 1647 if (nvmet_is_pci_ctrl(req->sq->ctrl) && !req->sq->qid && 1648 cmd->common.flags & NVME_CMD_SGL_ALL) 1649 return NVME_SC_INVALID_FIELD | NVME_STATUS_DNR; 1650 1651 if (nvmet_is_passthru_req(req)) 1652 return nvmet_parse_passthru_admin_cmd(req); 1653 1654 switch (cmd->common.opcode) { 1655 case nvme_admin_delete_sq: 1656 req->execute = nvmet_execute_delete_sq; 1657 return 0; 1658 case nvme_admin_create_sq: 1659 req->execute = nvmet_execute_create_sq; 1660 return 0; 1661 case nvme_admin_get_log_page: 1662 req->execute = nvmet_execute_get_log_page; 1663 return 0; 1664 case nvme_admin_delete_cq: 1665 req->execute = nvmet_execute_delete_cq; 1666 return 0; 1667 case nvme_admin_create_cq: 1668 req->execute = nvmet_execute_create_cq; 1669 return 0; 1670 case nvme_admin_identify: 1671 req->execute = nvmet_execute_identify; 1672 return 0; 1673 case nvme_admin_abort_cmd: 1674 req->execute = nvmet_execute_abort; 1675 return 0; 1676 case nvme_admin_set_features: 1677 req->execute = nvmet_execute_set_features; 1678 return 0; 1679 case nvme_admin_get_features: 1680 req->execute = nvmet_execute_get_features; 1681 return 0; 1682 case nvme_admin_async_event: 1683 req->execute = nvmet_execute_async_event; 1684 return 0; 1685 case nvme_admin_keep_alive: 1686 req->execute = nvmet_execute_keep_alive; 1687 return 0; 1688 default: 1689 return nvmet_report_invalid_opcode(req); 1690 } 1691 } 1692