1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static unsigned int write_queues; 72 module_param(write_queues, uint, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static unsigned int poll_queues; 78 module_param(poll_queues, uint, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 int io_sqes; 104 u32 db_stride; 105 void __iomem *bar; 106 unsigned long bar_mapped_size; 107 struct work_struct remove_work; 108 struct mutex shutdown_lock; 109 bool subsystem; 110 u64 cmb_size; 111 bool cmb_use_sqes; 112 u32 cmbsz; 113 u32 cmbloc; 114 struct nvme_ctrl ctrl; 115 u32 last_ps; 116 117 mempool_t *iod_mempool; 118 119 /* shadow doorbell buffer support: */ 120 u32 *dbbuf_dbs; 121 dma_addr_t dbbuf_dbs_dma_addr; 122 u32 *dbbuf_eis; 123 dma_addr_t dbbuf_eis_dma_addr; 124 125 /* host memory buffer support: */ 126 u64 host_mem_size; 127 u32 nr_host_mem_descs; 128 dma_addr_t host_mem_descs_dma; 129 struct nvme_host_mem_buf_desc *host_mem_descs; 130 void **host_mem_desc_bufs; 131 }; 132 133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134 { 135 int n = 0, ret; 136 137 ret = kstrtoint(val, 10, &n); 138 if (ret != 0 || n < 2) 139 return -EINVAL; 140 141 return param_set_int(val, kp); 142 } 143 144 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145 { 146 return qid * 2 * stride; 147 } 148 149 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150 { 151 return (qid * 2 + 1) * stride; 152 } 153 154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 155 { 156 return container_of(ctrl, struct nvme_dev, ctrl); 157 } 158 159 /* 160 * An NVM Express queue. Each device has at least two (one for admin 161 * commands and one for I/O commands). 162 */ 163 struct nvme_queue { 164 struct nvme_dev *dev; 165 spinlock_t sq_lock; 166 void *sq_cmds; 167 /* only used for poll queues: */ 168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 169 volatile struct nvme_completion *cqes; 170 dma_addr_t sq_dma_addr; 171 dma_addr_t cq_dma_addr; 172 u32 __iomem *q_db; 173 u16 q_depth; 174 u16 cq_vector; 175 u16 sq_tail; 176 u16 last_sq_tail; 177 u16 cq_head; 178 u16 qid; 179 u8 cq_phase; 180 u8 sqes; 181 unsigned long flags; 182 #define NVMEQ_ENABLED 0 183 #define NVMEQ_SQ_CMB 1 184 #define NVMEQ_DELETE_ERROR 2 185 #define NVMEQ_POLLED 3 186 u32 *dbbuf_sq_db; 187 u32 *dbbuf_cq_db; 188 u32 *dbbuf_sq_ei; 189 u32 *dbbuf_cq_ei; 190 struct completion delete_done; 191 }; 192 193 /* 194 * The nvme_iod describes the data in an I/O. 195 * 196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 197 * to the actual struct scatterlist. 198 */ 199 struct nvme_iod { 200 struct nvme_request req; 201 struct nvme_queue *nvmeq; 202 bool use_sgl; 203 int aborted; 204 int npages; /* In the PRP list. 0 means small pool in use */ 205 int nents; /* Used in scatterlist */ 206 dma_addr_t first_dma; 207 unsigned int dma_len; /* length of single DMA segment mapping */ 208 dma_addr_t meta_dma; 209 struct scatterlist *sg; 210 }; 211 212 static unsigned int max_io_queues(void) 213 { 214 return num_possible_cpus() + write_queues + poll_queues; 215 } 216 217 static unsigned int max_queue_count(void) 218 { 219 /* IO queues + admin queue */ 220 return 1 + max_io_queues(); 221 } 222 223 static inline unsigned int nvme_dbbuf_size(u32 stride) 224 { 225 return (max_queue_count() * 8 * stride); 226 } 227 228 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229 { 230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231 232 if (dev->dbbuf_dbs) 233 return 0; 234 235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236 &dev->dbbuf_dbs_dma_addr, 237 GFP_KERNEL); 238 if (!dev->dbbuf_dbs) 239 return -ENOMEM; 240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241 &dev->dbbuf_eis_dma_addr, 242 GFP_KERNEL); 243 if (!dev->dbbuf_eis) { 244 dma_free_coherent(dev->dev, mem_size, 245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246 dev->dbbuf_dbs = NULL; 247 return -ENOMEM; 248 } 249 250 return 0; 251 } 252 253 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254 { 255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256 257 if (dev->dbbuf_dbs) { 258 dma_free_coherent(dev->dev, mem_size, 259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260 dev->dbbuf_dbs = NULL; 261 } 262 if (dev->dbbuf_eis) { 263 dma_free_coherent(dev->dev, mem_size, 264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265 dev->dbbuf_eis = NULL; 266 } 267 } 268 269 static void nvme_dbbuf_init(struct nvme_dev *dev, 270 struct nvme_queue *nvmeq, int qid) 271 { 272 if (!dev->dbbuf_dbs || !qid) 273 return; 274 275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279 } 280 281 static void nvme_dbbuf_set(struct nvme_dev *dev) 282 { 283 struct nvme_command c; 284 285 if (!dev->dbbuf_dbs) 286 return; 287 288 memset(&c, 0, sizeof(c)); 289 c.dbbuf.opcode = nvme_admin_dbbuf; 290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292 293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295 /* Free memory and continue on */ 296 nvme_dbbuf_dma_free(dev); 297 } 298 } 299 300 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301 { 302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303 } 304 305 /* Update dbbuf and return true if an MMIO is required */ 306 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307 volatile u32 *dbbuf_ei) 308 { 309 if (dbbuf_db) { 310 u16 old_value; 311 312 /* 313 * Ensure that the queue is written before updating 314 * the doorbell in memory 315 */ 316 wmb(); 317 318 old_value = *dbbuf_db; 319 *dbbuf_db = value; 320 321 /* 322 * Ensure that the doorbell is updated before reading the event 323 * index from memory. The controller needs to provide similar 324 * ordering to ensure the envent index is updated before reading 325 * the doorbell. 326 */ 327 mb(); 328 329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330 return false; 331 } 332 333 return true; 334 } 335 336 /* 337 * Will slightly overestimate the number of pages needed. This is OK 338 * as it only leads to a small amount of wasted memory for the lifetime of 339 * the I/O. 340 */ 341 static int nvme_npages(unsigned size, struct nvme_dev *dev) 342 { 343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 344 dev->ctrl.page_size); 345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 346 } 347 348 /* 349 * Calculates the number of pages needed for the SGL segments. For example a 4k 350 * page can accommodate 256 SGL descriptors. 351 */ 352 static int nvme_pci_npages_sgl(unsigned int num_seg) 353 { 354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355 } 356 357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358 unsigned int size, unsigned int nseg, bool use_sgl) 359 { 360 size_t alloc_size; 361 362 if (use_sgl) 363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364 else 365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366 367 return alloc_size + sizeof(struct scatterlist) * nseg; 368 } 369 370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 371 unsigned int hctx_idx) 372 { 373 struct nvme_dev *dev = data; 374 struct nvme_queue *nvmeq = &dev->queues[0]; 375 376 WARN_ON(hctx_idx != 0); 377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 378 379 hctx->driver_data = nvmeq; 380 return 0; 381 } 382 383 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 384 unsigned int hctx_idx) 385 { 386 struct nvme_dev *dev = data; 387 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 388 389 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 390 hctx->driver_data = nvmeq; 391 return 0; 392 } 393 394 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 395 unsigned int hctx_idx, unsigned int numa_node) 396 { 397 struct nvme_dev *dev = set->driver_data; 398 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 399 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 400 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 401 402 BUG_ON(!nvmeq); 403 iod->nvmeq = nvmeq; 404 405 nvme_req(req)->ctrl = &dev->ctrl; 406 return 0; 407 } 408 409 static int queue_irq_offset(struct nvme_dev *dev) 410 { 411 /* if we have more than 1 vec, admin queue offsets us by 1 */ 412 if (dev->num_vecs > 1) 413 return 1; 414 415 return 0; 416 } 417 418 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 419 { 420 struct nvme_dev *dev = set->driver_data; 421 int i, qoff, offset; 422 423 offset = queue_irq_offset(dev); 424 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 425 struct blk_mq_queue_map *map = &set->map[i]; 426 427 map->nr_queues = dev->io_queues[i]; 428 if (!map->nr_queues) { 429 BUG_ON(i == HCTX_TYPE_DEFAULT); 430 continue; 431 } 432 433 /* 434 * The poll queue(s) doesn't have an IRQ (and hence IRQ 435 * affinity), so use the regular blk-mq cpu mapping 436 */ 437 map->queue_offset = qoff; 438 if (i != HCTX_TYPE_POLL && offset) 439 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 440 else 441 blk_mq_map_queues(map); 442 qoff += map->nr_queues; 443 offset += map->nr_queues; 444 } 445 446 return 0; 447 } 448 449 /* 450 * Write sq tail if we are asked to, or if the next command would wrap. 451 */ 452 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 453 { 454 if (!write_sq) { 455 u16 next_tail = nvmeq->sq_tail + 1; 456 457 if (next_tail == nvmeq->q_depth) 458 next_tail = 0; 459 if (next_tail != nvmeq->last_sq_tail) 460 return; 461 } 462 463 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 464 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 465 writel(nvmeq->sq_tail, nvmeq->q_db); 466 nvmeq->last_sq_tail = nvmeq->sq_tail; 467 } 468 469 /** 470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 471 * @nvmeq: The queue to use 472 * @cmd: The command to send 473 * @write_sq: whether to write to the SQ doorbell 474 */ 475 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 476 bool write_sq) 477 { 478 spin_lock(&nvmeq->sq_lock); 479 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 480 cmd, sizeof(*cmd)); 481 if (++nvmeq->sq_tail == nvmeq->q_depth) 482 nvmeq->sq_tail = 0; 483 nvme_write_sq_db(nvmeq, write_sq); 484 spin_unlock(&nvmeq->sq_lock); 485 } 486 487 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 488 { 489 struct nvme_queue *nvmeq = hctx->driver_data; 490 491 spin_lock(&nvmeq->sq_lock); 492 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 493 nvme_write_sq_db(nvmeq, true); 494 spin_unlock(&nvmeq->sq_lock); 495 } 496 497 static void **nvme_pci_iod_list(struct request *req) 498 { 499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 500 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 501 } 502 503 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 504 { 505 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 506 int nseg = blk_rq_nr_phys_segments(req); 507 unsigned int avg_seg_size; 508 509 if (nseg == 0) 510 return false; 511 512 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 513 514 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 515 return false; 516 if (!iod->nvmeq->qid) 517 return false; 518 if (!sgl_threshold || avg_seg_size < sgl_threshold) 519 return false; 520 return true; 521 } 522 523 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 524 { 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 527 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 528 int i; 529 530 if (iod->dma_len) { 531 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 532 rq_dma_dir(req)); 533 return; 534 } 535 536 WARN_ON_ONCE(!iod->nents); 537 538 if (is_pci_p2pdma_page(sg_page(iod->sg))) 539 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 540 rq_dma_dir(req)); 541 else 542 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 543 544 545 if (iod->npages == 0) 546 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 547 dma_addr); 548 549 for (i = 0; i < iod->npages; i++) { 550 void *addr = nvme_pci_iod_list(req)[i]; 551 552 if (iod->use_sgl) { 553 struct nvme_sgl_desc *sg_list = addr; 554 555 next_dma_addr = 556 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 557 } else { 558 __le64 *prp_list = addr; 559 560 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 561 } 562 563 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 564 dma_addr = next_dma_addr; 565 } 566 567 mempool_free(iod->sg, dev->iod_mempool); 568 } 569 570 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 571 { 572 int i; 573 struct scatterlist *sg; 574 575 for_each_sg(sgl, sg, nents, i) { 576 dma_addr_t phys = sg_phys(sg); 577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 578 "dma_address:%pad dma_length:%d\n", 579 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 580 sg_dma_len(sg)); 581 } 582 } 583 584 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 585 struct request *req, struct nvme_rw_command *cmnd) 586 { 587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 588 struct dma_pool *pool; 589 int length = blk_rq_payload_bytes(req); 590 struct scatterlist *sg = iod->sg; 591 int dma_len = sg_dma_len(sg); 592 u64 dma_addr = sg_dma_address(sg); 593 u32 page_size = dev->ctrl.page_size; 594 int offset = dma_addr & (page_size - 1); 595 __le64 *prp_list; 596 void **list = nvme_pci_iod_list(req); 597 dma_addr_t prp_dma; 598 int nprps, i; 599 600 length -= (page_size - offset); 601 if (length <= 0) { 602 iod->first_dma = 0; 603 goto done; 604 } 605 606 dma_len -= (page_size - offset); 607 if (dma_len) { 608 dma_addr += (page_size - offset); 609 } else { 610 sg = sg_next(sg); 611 dma_addr = sg_dma_address(sg); 612 dma_len = sg_dma_len(sg); 613 } 614 615 if (length <= page_size) { 616 iod->first_dma = dma_addr; 617 goto done; 618 } 619 620 nprps = DIV_ROUND_UP(length, page_size); 621 if (nprps <= (256 / 8)) { 622 pool = dev->prp_small_pool; 623 iod->npages = 0; 624 } else { 625 pool = dev->prp_page_pool; 626 iod->npages = 1; 627 } 628 629 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 630 if (!prp_list) { 631 iod->first_dma = dma_addr; 632 iod->npages = -1; 633 return BLK_STS_RESOURCE; 634 } 635 list[0] = prp_list; 636 iod->first_dma = prp_dma; 637 i = 0; 638 for (;;) { 639 if (i == page_size >> 3) { 640 __le64 *old_prp_list = prp_list; 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 642 if (!prp_list) 643 return BLK_STS_RESOURCE; 644 list[iod->npages++] = prp_list; 645 prp_list[0] = old_prp_list[i - 1]; 646 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 647 i = 1; 648 } 649 prp_list[i++] = cpu_to_le64(dma_addr); 650 dma_len -= page_size; 651 dma_addr += page_size; 652 length -= page_size; 653 if (length <= 0) 654 break; 655 if (dma_len > 0) 656 continue; 657 if (unlikely(dma_len < 0)) 658 goto bad_sgl; 659 sg = sg_next(sg); 660 dma_addr = sg_dma_address(sg); 661 dma_len = sg_dma_len(sg); 662 } 663 664 done: 665 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 666 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 667 668 return BLK_STS_OK; 669 670 bad_sgl: 671 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 672 "Invalid SGL for payload:%d nents:%d\n", 673 blk_rq_payload_bytes(req), iod->nents); 674 return BLK_STS_IOERR; 675 } 676 677 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 678 struct scatterlist *sg) 679 { 680 sge->addr = cpu_to_le64(sg_dma_address(sg)); 681 sge->length = cpu_to_le32(sg_dma_len(sg)); 682 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 683 } 684 685 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 686 dma_addr_t dma_addr, int entries) 687 { 688 sge->addr = cpu_to_le64(dma_addr); 689 if (entries < SGES_PER_PAGE) { 690 sge->length = cpu_to_le32(entries * sizeof(*sge)); 691 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 692 } else { 693 sge->length = cpu_to_le32(PAGE_SIZE); 694 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 695 } 696 } 697 698 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 699 struct request *req, struct nvme_rw_command *cmd, int entries) 700 { 701 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 702 struct dma_pool *pool; 703 struct nvme_sgl_desc *sg_list; 704 struct scatterlist *sg = iod->sg; 705 dma_addr_t sgl_dma; 706 int i = 0; 707 708 /* setting the transfer type as SGL */ 709 cmd->flags = NVME_CMD_SGL_METABUF; 710 711 if (entries == 1) { 712 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 713 return BLK_STS_OK; 714 } 715 716 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 717 pool = dev->prp_small_pool; 718 iod->npages = 0; 719 } else { 720 pool = dev->prp_page_pool; 721 iod->npages = 1; 722 } 723 724 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 725 if (!sg_list) { 726 iod->npages = -1; 727 return BLK_STS_RESOURCE; 728 } 729 730 nvme_pci_iod_list(req)[0] = sg_list; 731 iod->first_dma = sgl_dma; 732 733 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 734 735 do { 736 if (i == SGES_PER_PAGE) { 737 struct nvme_sgl_desc *old_sg_desc = sg_list; 738 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 739 740 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 741 if (!sg_list) 742 return BLK_STS_RESOURCE; 743 744 i = 0; 745 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 746 sg_list[i++] = *link; 747 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 748 } 749 750 nvme_pci_sgl_set_data(&sg_list[i++], sg); 751 sg = sg_next(sg); 752 } while (--entries > 0); 753 754 return BLK_STS_OK; 755 } 756 757 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 758 struct request *req, struct nvme_rw_command *cmnd, 759 struct bio_vec *bv) 760 { 761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 762 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 763 unsigned int first_prp_len = dev->ctrl.page_size - offset; 764 765 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 766 if (dma_mapping_error(dev->dev, iod->first_dma)) 767 return BLK_STS_RESOURCE; 768 iod->dma_len = bv->bv_len; 769 770 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 771 if (bv->bv_len > first_prp_len) 772 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 773 return 0; 774 } 775 776 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 777 struct request *req, struct nvme_rw_command *cmnd, 778 struct bio_vec *bv) 779 { 780 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 781 782 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 783 if (dma_mapping_error(dev->dev, iod->first_dma)) 784 return BLK_STS_RESOURCE; 785 iod->dma_len = bv->bv_len; 786 787 cmnd->flags = NVME_CMD_SGL_METABUF; 788 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 789 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 790 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 791 return 0; 792 } 793 794 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 795 struct nvme_command *cmnd) 796 { 797 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 798 blk_status_t ret = BLK_STS_RESOURCE; 799 int nr_mapped; 800 801 if (blk_rq_nr_phys_segments(req) == 1) { 802 struct bio_vec bv = req_bvec(req); 803 804 if (!is_pci_p2pdma_page(bv.bv_page)) { 805 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 806 return nvme_setup_prp_simple(dev, req, 807 &cmnd->rw, &bv); 808 809 if (iod->nvmeq->qid && 810 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 811 return nvme_setup_sgl_simple(dev, req, 812 &cmnd->rw, &bv); 813 } 814 } 815 816 iod->dma_len = 0; 817 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 818 if (!iod->sg) 819 return BLK_STS_RESOURCE; 820 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 821 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 822 if (!iod->nents) 823 goto out; 824 825 if (is_pci_p2pdma_page(sg_page(iod->sg))) 826 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 827 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 828 else 829 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 830 rq_dma_dir(req), DMA_ATTR_NO_WARN); 831 if (!nr_mapped) 832 goto out; 833 834 iod->use_sgl = nvme_pci_use_sgls(dev, req); 835 if (iod->use_sgl) 836 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 837 else 838 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 839 out: 840 if (ret != BLK_STS_OK) 841 nvme_unmap_data(dev, req); 842 return ret; 843 } 844 845 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 846 struct nvme_command *cmnd) 847 { 848 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 849 850 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 851 rq_dma_dir(req), 0); 852 if (dma_mapping_error(dev->dev, iod->meta_dma)) 853 return BLK_STS_IOERR; 854 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 855 return 0; 856 } 857 858 /* 859 * NOTE: ns is NULL when called on the admin queue. 860 */ 861 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 862 const struct blk_mq_queue_data *bd) 863 { 864 struct nvme_ns *ns = hctx->queue->queuedata; 865 struct nvme_queue *nvmeq = hctx->driver_data; 866 struct nvme_dev *dev = nvmeq->dev; 867 struct request *req = bd->rq; 868 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 869 struct nvme_command cmnd; 870 blk_status_t ret; 871 872 iod->aborted = 0; 873 iod->npages = -1; 874 iod->nents = 0; 875 876 /* 877 * We should not need to do this, but we're still using this to 878 * ensure we can drain requests on a dying queue. 879 */ 880 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 881 return BLK_STS_IOERR; 882 883 ret = nvme_setup_cmd(ns, req, &cmnd); 884 if (ret) 885 return ret; 886 887 if (blk_rq_nr_phys_segments(req)) { 888 ret = nvme_map_data(dev, req, &cmnd); 889 if (ret) 890 goto out_free_cmd; 891 } 892 893 if (blk_integrity_rq(req)) { 894 ret = nvme_map_metadata(dev, req, &cmnd); 895 if (ret) 896 goto out_unmap_data; 897 } 898 899 blk_mq_start_request(req); 900 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 901 return BLK_STS_OK; 902 out_unmap_data: 903 nvme_unmap_data(dev, req); 904 out_free_cmd: 905 nvme_cleanup_cmd(req); 906 return ret; 907 } 908 909 static void nvme_pci_complete_rq(struct request *req) 910 { 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 912 struct nvme_dev *dev = iod->nvmeq->dev; 913 914 if (blk_integrity_rq(req)) 915 dma_unmap_page(dev->dev, iod->meta_dma, 916 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 917 if (blk_rq_nr_phys_segments(req)) 918 nvme_unmap_data(dev, req); 919 nvme_complete_rq(req); 920 } 921 922 /* We read the CQE phase first to check if the rest of the entry is valid */ 923 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 924 { 925 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 926 nvmeq->cq_phase; 927 } 928 929 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 930 { 931 u16 head = nvmeq->cq_head; 932 933 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 934 nvmeq->dbbuf_cq_ei)) 935 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 936 } 937 938 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 939 { 940 if (!nvmeq->qid) 941 return nvmeq->dev->admin_tagset.tags[0]; 942 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 943 } 944 945 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 946 { 947 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 948 struct request *req; 949 950 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 951 dev_warn(nvmeq->dev->ctrl.device, 952 "invalid id %d completed on queue %d\n", 953 cqe->command_id, le16_to_cpu(cqe->sq_id)); 954 return; 955 } 956 957 /* 958 * AEN requests are special as they don't time out and can 959 * survive any kind of queue freeze and often don't respond to 960 * aborts. We don't even bother to allocate a struct request 961 * for them but rather special case them here. 962 */ 963 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 964 nvme_complete_async_event(&nvmeq->dev->ctrl, 965 cqe->status, &cqe->result); 966 return; 967 } 968 969 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 970 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 971 nvme_end_request(req, cqe->status, cqe->result); 972 } 973 974 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 975 { 976 if (++nvmeq->cq_head == nvmeq->q_depth) { 977 nvmeq->cq_head = 0; 978 nvmeq->cq_phase ^= 1; 979 } 980 } 981 982 static inline int nvme_process_cq(struct nvme_queue *nvmeq) 983 { 984 int found = 0; 985 986 while (nvme_cqe_pending(nvmeq)) { 987 found++; 988 nvme_handle_cqe(nvmeq, nvmeq->cq_head); 989 nvme_update_cq_head(nvmeq); 990 } 991 992 if (found) 993 nvme_ring_cq_doorbell(nvmeq); 994 return found; 995 } 996 997 static irqreturn_t nvme_irq(int irq, void *data) 998 { 999 struct nvme_queue *nvmeq = data; 1000 irqreturn_t ret = IRQ_NONE; 1001 1002 /* 1003 * The rmb/wmb pair ensures we see all updates from a previous run of 1004 * the irq handler, even if that was on another CPU. 1005 */ 1006 rmb(); 1007 if (nvme_process_cq(nvmeq)) 1008 ret = IRQ_HANDLED; 1009 wmb(); 1010 1011 return ret; 1012 } 1013 1014 static irqreturn_t nvme_irq_check(int irq, void *data) 1015 { 1016 struct nvme_queue *nvmeq = data; 1017 if (nvme_cqe_pending(nvmeq)) 1018 return IRQ_WAKE_THREAD; 1019 return IRQ_NONE; 1020 } 1021 1022 /* 1023 * Poll for completions for any interrupt driven queue 1024 * Can be called from any context. 1025 */ 1026 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1027 { 1028 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1029 1030 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1031 1032 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1033 nvme_process_cq(nvmeq); 1034 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1035 } 1036 1037 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1038 { 1039 struct nvme_queue *nvmeq = hctx->driver_data; 1040 bool found; 1041 1042 if (!nvme_cqe_pending(nvmeq)) 1043 return 0; 1044 1045 spin_lock(&nvmeq->cq_poll_lock); 1046 found = nvme_process_cq(nvmeq); 1047 spin_unlock(&nvmeq->cq_poll_lock); 1048 1049 return found; 1050 } 1051 1052 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1053 { 1054 struct nvme_dev *dev = to_nvme_dev(ctrl); 1055 struct nvme_queue *nvmeq = &dev->queues[0]; 1056 struct nvme_command c; 1057 1058 memset(&c, 0, sizeof(c)); 1059 c.common.opcode = nvme_admin_async_event; 1060 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1061 nvme_submit_cmd(nvmeq, &c, true); 1062 } 1063 1064 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1065 { 1066 struct nvme_command c; 1067 1068 memset(&c, 0, sizeof(c)); 1069 c.delete_queue.opcode = opcode; 1070 c.delete_queue.qid = cpu_to_le16(id); 1071 1072 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1073 } 1074 1075 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1076 struct nvme_queue *nvmeq, s16 vector) 1077 { 1078 struct nvme_command c; 1079 int flags = NVME_QUEUE_PHYS_CONTIG; 1080 1081 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1082 flags |= NVME_CQ_IRQ_ENABLED; 1083 1084 /* 1085 * Note: we (ab)use the fact that the prp fields survive if no data 1086 * is attached to the request. 1087 */ 1088 memset(&c, 0, sizeof(c)); 1089 c.create_cq.opcode = nvme_admin_create_cq; 1090 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1091 c.create_cq.cqid = cpu_to_le16(qid); 1092 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1093 c.create_cq.cq_flags = cpu_to_le16(flags); 1094 c.create_cq.irq_vector = cpu_to_le16(vector); 1095 1096 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1097 } 1098 1099 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1100 struct nvme_queue *nvmeq) 1101 { 1102 struct nvme_ctrl *ctrl = &dev->ctrl; 1103 struct nvme_command c; 1104 int flags = NVME_QUEUE_PHYS_CONTIG; 1105 1106 /* 1107 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1108 * set. Since URGENT priority is zeroes, it makes all queues 1109 * URGENT. 1110 */ 1111 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1112 flags |= NVME_SQ_PRIO_MEDIUM; 1113 1114 /* 1115 * Note: we (ab)use the fact that the prp fields survive if no data 1116 * is attached to the request. 1117 */ 1118 memset(&c, 0, sizeof(c)); 1119 c.create_sq.opcode = nvme_admin_create_sq; 1120 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1121 c.create_sq.sqid = cpu_to_le16(qid); 1122 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1123 c.create_sq.sq_flags = cpu_to_le16(flags); 1124 c.create_sq.cqid = cpu_to_le16(qid); 1125 1126 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1127 } 1128 1129 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1130 { 1131 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1132 } 1133 1134 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1135 { 1136 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1137 } 1138 1139 static void abort_endio(struct request *req, blk_status_t error) 1140 { 1141 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1142 struct nvme_queue *nvmeq = iod->nvmeq; 1143 1144 dev_warn(nvmeq->dev->ctrl.device, 1145 "Abort status: 0x%x", nvme_req(req)->status); 1146 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1147 blk_mq_free_request(req); 1148 } 1149 1150 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1151 { 1152 1153 /* If true, indicates loss of adapter communication, possibly by a 1154 * NVMe Subsystem reset. 1155 */ 1156 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1157 1158 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1159 switch (dev->ctrl.state) { 1160 case NVME_CTRL_RESETTING: 1161 case NVME_CTRL_CONNECTING: 1162 return false; 1163 default: 1164 break; 1165 } 1166 1167 /* We shouldn't reset unless the controller is on fatal error state 1168 * _or_ if we lost the communication with it. 1169 */ 1170 if (!(csts & NVME_CSTS_CFS) && !nssro) 1171 return false; 1172 1173 return true; 1174 } 1175 1176 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1177 { 1178 /* Read a config register to help see what died. */ 1179 u16 pci_status; 1180 int result; 1181 1182 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1183 &pci_status); 1184 if (result == PCIBIOS_SUCCESSFUL) 1185 dev_warn(dev->ctrl.device, 1186 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1187 csts, pci_status); 1188 else 1189 dev_warn(dev->ctrl.device, 1190 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1191 csts, result); 1192 } 1193 1194 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1195 { 1196 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1197 struct nvme_queue *nvmeq = iod->nvmeq; 1198 struct nvme_dev *dev = nvmeq->dev; 1199 struct request *abort_req; 1200 struct nvme_command cmd; 1201 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1202 1203 /* If PCI error recovery process is happening, we cannot reset or 1204 * the recovery mechanism will surely fail. 1205 */ 1206 mb(); 1207 if (pci_channel_offline(to_pci_dev(dev->dev))) 1208 return BLK_EH_RESET_TIMER; 1209 1210 /* 1211 * Reset immediately if the controller is failed 1212 */ 1213 if (nvme_should_reset(dev, csts)) { 1214 nvme_warn_reset(dev, csts); 1215 nvme_dev_disable(dev, false); 1216 nvme_reset_ctrl(&dev->ctrl); 1217 return BLK_EH_DONE; 1218 } 1219 1220 /* 1221 * Did we miss an interrupt? 1222 */ 1223 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1224 nvme_poll(req->mq_hctx); 1225 else 1226 nvme_poll_irqdisable(nvmeq); 1227 1228 if (blk_mq_request_completed(req)) { 1229 dev_warn(dev->ctrl.device, 1230 "I/O %d QID %d timeout, completion polled\n", 1231 req->tag, nvmeq->qid); 1232 return BLK_EH_DONE; 1233 } 1234 1235 /* 1236 * Shutdown immediately if controller times out while starting. The 1237 * reset work will see the pci device disabled when it gets the forced 1238 * cancellation error. All outstanding requests are completed on 1239 * shutdown, so we return BLK_EH_DONE. 1240 */ 1241 switch (dev->ctrl.state) { 1242 case NVME_CTRL_CONNECTING: 1243 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1244 /* fall through */ 1245 case NVME_CTRL_DELETING: 1246 dev_warn_ratelimited(dev->ctrl.device, 1247 "I/O %d QID %d timeout, disable controller\n", 1248 req->tag, nvmeq->qid); 1249 nvme_dev_disable(dev, true); 1250 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1251 return BLK_EH_DONE; 1252 case NVME_CTRL_RESETTING: 1253 return BLK_EH_RESET_TIMER; 1254 default: 1255 break; 1256 } 1257 1258 /* 1259 * Shutdown the controller immediately and schedule a reset if the 1260 * command was already aborted once before and still hasn't been 1261 * returned to the driver, or if this is the admin queue. 1262 */ 1263 if (!nvmeq->qid || iod->aborted) { 1264 dev_warn(dev->ctrl.device, 1265 "I/O %d QID %d timeout, reset controller\n", 1266 req->tag, nvmeq->qid); 1267 nvme_dev_disable(dev, false); 1268 nvme_reset_ctrl(&dev->ctrl); 1269 1270 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1271 return BLK_EH_DONE; 1272 } 1273 1274 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1275 atomic_inc(&dev->ctrl.abort_limit); 1276 return BLK_EH_RESET_TIMER; 1277 } 1278 iod->aborted = 1; 1279 1280 memset(&cmd, 0, sizeof(cmd)); 1281 cmd.abort.opcode = nvme_admin_abort_cmd; 1282 cmd.abort.cid = req->tag; 1283 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1284 1285 dev_warn(nvmeq->dev->ctrl.device, 1286 "I/O %d QID %d timeout, aborting\n", 1287 req->tag, nvmeq->qid); 1288 1289 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1290 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1291 if (IS_ERR(abort_req)) { 1292 atomic_inc(&dev->ctrl.abort_limit); 1293 return BLK_EH_RESET_TIMER; 1294 } 1295 1296 abort_req->timeout = ADMIN_TIMEOUT; 1297 abort_req->end_io_data = NULL; 1298 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1299 1300 /* 1301 * The aborted req will be completed on receiving the abort req. 1302 * We enable the timer again. If hit twice, it'll cause a device reset, 1303 * as the device then is in a faulty state. 1304 */ 1305 return BLK_EH_RESET_TIMER; 1306 } 1307 1308 static void nvme_free_queue(struct nvme_queue *nvmeq) 1309 { 1310 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1311 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1312 if (!nvmeq->sq_cmds) 1313 return; 1314 1315 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1316 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1317 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1318 } else { 1319 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1320 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1321 } 1322 } 1323 1324 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1325 { 1326 int i; 1327 1328 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1329 dev->ctrl.queue_count--; 1330 nvme_free_queue(&dev->queues[i]); 1331 } 1332 } 1333 1334 /** 1335 * nvme_suspend_queue - put queue into suspended state 1336 * @nvmeq: queue to suspend 1337 */ 1338 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1339 { 1340 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1341 return 1; 1342 1343 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1344 mb(); 1345 1346 nvmeq->dev->online_queues--; 1347 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1348 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1349 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1350 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1351 return 0; 1352 } 1353 1354 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1355 { 1356 int i; 1357 1358 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1359 nvme_suspend_queue(&dev->queues[i]); 1360 } 1361 1362 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1363 { 1364 struct nvme_queue *nvmeq = &dev->queues[0]; 1365 1366 if (shutdown) 1367 nvme_shutdown_ctrl(&dev->ctrl); 1368 else 1369 nvme_disable_ctrl(&dev->ctrl); 1370 1371 nvme_poll_irqdisable(nvmeq); 1372 } 1373 1374 /* 1375 * Called only on a device that has been disabled and after all other threads 1376 * that can check this device's completion queues have synced. This is the 1377 * last chance for the driver to see a natural completion before 1378 * nvme_cancel_request() terminates all incomplete requests. 1379 */ 1380 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1381 { 1382 int i; 1383 1384 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1385 nvme_process_cq(&dev->queues[i]); 1386 } 1387 1388 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1389 int entry_size) 1390 { 1391 int q_depth = dev->q_depth; 1392 unsigned q_size_aligned = roundup(q_depth * entry_size, 1393 dev->ctrl.page_size); 1394 1395 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1396 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1397 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1398 q_depth = div_u64(mem_per_q, entry_size); 1399 1400 /* 1401 * Ensure the reduced q_depth is above some threshold where it 1402 * would be better to map queues in system memory with the 1403 * original depth 1404 */ 1405 if (q_depth < 64) 1406 return -ENOMEM; 1407 } 1408 1409 return q_depth; 1410 } 1411 1412 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1413 int qid) 1414 { 1415 struct pci_dev *pdev = to_pci_dev(dev->dev); 1416 1417 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1418 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1419 if (nvmeq->sq_cmds) { 1420 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1421 nvmeq->sq_cmds); 1422 if (nvmeq->sq_dma_addr) { 1423 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1424 return 0; 1425 } 1426 1427 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1428 } 1429 } 1430 1431 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1432 &nvmeq->sq_dma_addr, GFP_KERNEL); 1433 if (!nvmeq->sq_cmds) 1434 return -ENOMEM; 1435 return 0; 1436 } 1437 1438 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1439 { 1440 struct nvme_queue *nvmeq = &dev->queues[qid]; 1441 1442 if (dev->ctrl.queue_count > qid) 1443 return 0; 1444 1445 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1446 nvmeq->q_depth = depth; 1447 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1448 &nvmeq->cq_dma_addr, GFP_KERNEL); 1449 if (!nvmeq->cqes) 1450 goto free_nvmeq; 1451 1452 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1453 goto free_cqdma; 1454 1455 nvmeq->dev = dev; 1456 spin_lock_init(&nvmeq->sq_lock); 1457 spin_lock_init(&nvmeq->cq_poll_lock); 1458 nvmeq->cq_head = 0; 1459 nvmeq->cq_phase = 1; 1460 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1461 nvmeq->qid = qid; 1462 dev->ctrl.queue_count++; 1463 1464 return 0; 1465 1466 free_cqdma: 1467 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1468 nvmeq->cq_dma_addr); 1469 free_nvmeq: 1470 return -ENOMEM; 1471 } 1472 1473 static int queue_request_irq(struct nvme_queue *nvmeq) 1474 { 1475 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1476 int nr = nvmeq->dev->ctrl.instance; 1477 1478 if (use_threaded_interrupts) { 1479 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1480 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1481 } else { 1482 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1483 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1484 } 1485 } 1486 1487 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1488 { 1489 struct nvme_dev *dev = nvmeq->dev; 1490 1491 nvmeq->sq_tail = 0; 1492 nvmeq->last_sq_tail = 0; 1493 nvmeq->cq_head = 0; 1494 nvmeq->cq_phase = 1; 1495 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1496 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1497 nvme_dbbuf_init(dev, nvmeq, qid); 1498 dev->online_queues++; 1499 wmb(); /* ensure the first interrupt sees the initialization */ 1500 } 1501 1502 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1503 { 1504 struct nvme_dev *dev = nvmeq->dev; 1505 int result; 1506 u16 vector = 0; 1507 1508 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1509 1510 /* 1511 * A queue's vector matches the queue identifier unless the controller 1512 * has only one vector available. 1513 */ 1514 if (!polled) 1515 vector = dev->num_vecs == 1 ? 0 : qid; 1516 else 1517 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1518 1519 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1520 if (result) 1521 return result; 1522 1523 result = adapter_alloc_sq(dev, qid, nvmeq); 1524 if (result < 0) 1525 return result; 1526 if (result) 1527 goto release_cq; 1528 1529 nvmeq->cq_vector = vector; 1530 nvme_init_queue(nvmeq, qid); 1531 1532 if (!polled) { 1533 result = queue_request_irq(nvmeq); 1534 if (result < 0) 1535 goto release_sq; 1536 } 1537 1538 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1539 return result; 1540 1541 release_sq: 1542 dev->online_queues--; 1543 adapter_delete_sq(dev, qid); 1544 release_cq: 1545 adapter_delete_cq(dev, qid); 1546 return result; 1547 } 1548 1549 static const struct blk_mq_ops nvme_mq_admin_ops = { 1550 .queue_rq = nvme_queue_rq, 1551 .complete = nvme_pci_complete_rq, 1552 .init_hctx = nvme_admin_init_hctx, 1553 .init_request = nvme_init_request, 1554 .timeout = nvme_timeout, 1555 }; 1556 1557 static const struct blk_mq_ops nvme_mq_ops = { 1558 .queue_rq = nvme_queue_rq, 1559 .complete = nvme_pci_complete_rq, 1560 .commit_rqs = nvme_commit_rqs, 1561 .init_hctx = nvme_init_hctx, 1562 .init_request = nvme_init_request, 1563 .map_queues = nvme_pci_map_queues, 1564 .timeout = nvme_timeout, 1565 .poll = nvme_poll, 1566 }; 1567 1568 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1569 { 1570 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1571 /* 1572 * If the controller was reset during removal, it's possible 1573 * user requests may be waiting on a stopped queue. Start the 1574 * queue to flush these to completion. 1575 */ 1576 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1577 blk_cleanup_queue(dev->ctrl.admin_q); 1578 blk_mq_free_tag_set(&dev->admin_tagset); 1579 } 1580 } 1581 1582 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1583 { 1584 if (!dev->ctrl.admin_q) { 1585 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1586 dev->admin_tagset.nr_hw_queues = 1; 1587 1588 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1589 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1590 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1591 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1592 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1593 dev->admin_tagset.driver_data = dev; 1594 1595 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1596 return -ENOMEM; 1597 dev->ctrl.admin_tagset = &dev->admin_tagset; 1598 1599 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1600 if (IS_ERR(dev->ctrl.admin_q)) { 1601 blk_mq_free_tag_set(&dev->admin_tagset); 1602 return -ENOMEM; 1603 } 1604 if (!blk_get_queue(dev->ctrl.admin_q)) { 1605 nvme_dev_remove_admin(dev); 1606 dev->ctrl.admin_q = NULL; 1607 return -ENODEV; 1608 } 1609 } else 1610 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1611 1612 return 0; 1613 } 1614 1615 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1616 { 1617 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1618 } 1619 1620 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1621 { 1622 struct pci_dev *pdev = to_pci_dev(dev->dev); 1623 1624 if (size <= dev->bar_mapped_size) 1625 return 0; 1626 if (size > pci_resource_len(pdev, 0)) 1627 return -ENOMEM; 1628 if (dev->bar) 1629 iounmap(dev->bar); 1630 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1631 if (!dev->bar) { 1632 dev->bar_mapped_size = 0; 1633 return -ENOMEM; 1634 } 1635 dev->bar_mapped_size = size; 1636 dev->dbs = dev->bar + NVME_REG_DBS; 1637 1638 return 0; 1639 } 1640 1641 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1642 { 1643 int result; 1644 u32 aqa; 1645 struct nvme_queue *nvmeq; 1646 1647 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1648 if (result < 0) 1649 return result; 1650 1651 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1652 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1653 1654 if (dev->subsystem && 1655 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1656 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1657 1658 result = nvme_disable_ctrl(&dev->ctrl); 1659 if (result < 0) 1660 return result; 1661 1662 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1663 if (result) 1664 return result; 1665 1666 nvmeq = &dev->queues[0]; 1667 aqa = nvmeq->q_depth - 1; 1668 aqa |= aqa << 16; 1669 1670 writel(aqa, dev->bar + NVME_REG_AQA); 1671 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1672 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1673 1674 result = nvme_enable_ctrl(&dev->ctrl); 1675 if (result) 1676 return result; 1677 1678 nvmeq->cq_vector = 0; 1679 nvme_init_queue(nvmeq, 0); 1680 result = queue_request_irq(nvmeq); 1681 if (result) { 1682 dev->online_queues--; 1683 return result; 1684 } 1685 1686 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1687 return result; 1688 } 1689 1690 static int nvme_create_io_queues(struct nvme_dev *dev) 1691 { 1692 unsigned i, max, rw_queues; 1693 int ret = 0; 1694 1695 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1696 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1697 ret = -ENOMEM; 1698 break; 1699 } 1700 } 1701 1702 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1703 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1704 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1705 dev->io_queues[HCTX_TYPE_READ]; 1706 } else { 1707 rw_queues = max; 1708 } 1709 1710 for (i = dev->online_queues; i <= max; i++) { 1711 bool polled = i > rw_queues; 1712 1713 ret = nvme_create_queue(&dev->queues[i], i, polled); 1714 if (ret) 1715 break; 1716 } 1717 1718 /* 1719 * Ignore failing Create SQ/CQ commands, we can continue with less 1720 * than the desired amount of queues, and even a controller without 1721 * I/O queues can still be used to issue admin commands. This might 1722 * be useful to upgrade a buggy firmware for example. 1723 */ 1724 return ret >= 0 ? 0 : ret; 1725 } 1726 1727 static ssize_t nvme_cmb_show(struct device *dev, 1728 struct device_attribute *attr, 1729 char *buf) 1730 { 1731 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1732 1733 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1734 ndev->cmbloc, ndev->cmbsz); 1735 } 1736 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1737 1738 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1739 { 1740 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1741 1742 return 1ULL << (12 + 4 * szu); 1743 } 1744 1745 static u32 nvme_cmb_size(struct nvme_dev *dev) 1746 { 1747 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1748 } 1749 1750 static void nvme_map_cmb(struct nvme_dev *dev) 1751 { 1752 u64 size, offset; 1753 resource_size_t bar_size; 1754 struct pci_dev *pdev = to_pci_dev(dev->dev); 1755 int bar; 1756 1757 if (dev->cmb_size) 1758 return; 1759 1760 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1761 if (!dev->cmbsz) 1762 return; 1763 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1764 1765 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1766 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1767 bar = NVME_CMB_BIR(dev->cmbloc); 1768 bar_size = pci_resource_len(pdev, bar); 1769 1770 if (offset > bar_size) 1771 return; 1772 1773 /* 1774 * Controllers may support a CMB size larger than their BAR, 1775 * for example, due to being behind a bridge. Reduce the CMB to 1776 * the reported size of the BAR 1777 */ 1778 if (size > bar_size - offset) 1779 size = bar_size - offset; 1780 1781 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1782 dev_warn(dev->ctrl.device, 1783 "failed to register the CMB\n"); 1784 return; 1785 } 1786 1787 dev->cmb_size = size; 1788 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1789 1790 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1791 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1792 pci_p2pmem_publish(pdev, true); 1793 1794 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1795 &dev_attr_cmb.attr, NULL)) 1796 dev_warn(dev->ctrl.device, 1797 "failed to add sysfs attribute for CMB\n"); 1798 } 1799 1800 static inline void nvme_release_cmb(struct nvme_dev *dev) 1801 { 1802 if (dev->cmb_size) { 1803 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1804 &dev_attr_cmb.attr, NULL); 1805 dev->cmb_size = 0; 1806 } 1807 } 1808 1809 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1810 { 1811 u64 dma_addr = dev->host_mem_descs_dma; 1812 struct nvme_command c; 1813 int ret; 1814 1815 memset(&c, 0, sizeof(c)); 1816 c.features.opcode = nvme_admin_set_features; 1817 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1818 c.features.dword11 = cpu_to_le32(bits); 1819 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1820 ilog2(dev->ctrl.page_size)); 1821 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1822 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1823 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1824 1825 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1826 if (ret) { 1827 dev_warn(dev->ctrl.device, 1828 "failed to set host mem (err %d, flags %#x).\n", 1829 ret, bits); 1830 } 1831 return ret; 1832 } 1833 1834 static void nvme_free_host_mem(struct nvme_dev *dev) 1835 { 1836 int i; 1837 1838 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1839 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1840 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1841 1842 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1843 le64_to_cpu(desc->addr), 1844 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1845 } 1846 1847 kfree(dev->host_mem_desc_bufs); 1848 dev->host_mem_desc_bufs = NULL; 1849 dma_free_coherent(dev->dev, 1850 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1851 dev->host_mem_descs, dev->host_mem_descs_dma); 1852 dev->host_mem_descs = NULL; 1853 dev->nr_host_mem_descs = 0; 1854 } 1855 1856 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1857 u32 chunk_size) 1858 { 1859 struct nvme_host_mem_buf_desc *descs; 1860 u32 max_entries, len; 1861 dma_addr_t descs_dma; 1862 int i = 0; 1863 void **bufs; 1864 u64 size, tmp; 1865 1866 tmp = (preferred + chunk_size - 1); 1867 do_div(tmp, chunk_size); 1868 max_entries = tmp; 1869 1870 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1871 max_entries = dev->ctrl.hmmaxd; 1872 1873 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1874 &descs_dma, GFP_KERNEL); 1875 if (!descs) 1876 goto out; 1877 1878 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1879 if (!bufs) 1880 goto out_free_descs; 1881 1882 for (size = 0; size < preferred && i < max_entries; size += len) { 1883 dma_addr_t dma_addr; 1884 1885 len = min_t(u64, chunk_size, preferred - size); 1886 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1887 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1888 if (!bufs[i]) 1889 break; 1890 1891 descs[i].addr = cpu_to_le64(dma_addr); 1892 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1893 i++; 1894 } 1895 1896 if (!size) 1897 goto out_free_bufs; 1898 1899 dev->nr_host_mem_descs = i; 1900 dev->host_mem_size = size; 1901 dev->host_mem_descs = descs; 1902 dev->host_mem_descs_dma = descs_dma; 1903 dev->host_mem_desc_bufs = bufs; 1904 return 0; 1905 1906 out_free_bufs: 1907 while (--i >= 0) { 1908 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1909 1910 dma_free_attrs(dev->dev, size, bufs[i], 1911 le64_to_cpu(descs[i].addr), 1912 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1913 } 1914 1915 kfree(bufs); 1916 out_free_descs: 1917 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1918 descs_dma); 1919 out: 1920 dev->host_mem_descs = NULL; 1921 return -ENOMEM; 1922 } 1923 1924 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1925 { 1926 u32 chunk_size; 1927 1928 /* start big and work our way down */ 1929 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1930 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1931 chunk_size /= 2) { 1932 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1933 if (!min || dev->host_mem_size >= min) 1934 return 0; 1935 nvme_free_host_mem(dev); 1936 } 1937 } 1938 1939 return -ENOMEM; 1940 } 1941 1942 static int nvme_setup_host_mem(struct nvme_dev *dev) 1943 { 1944 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1945 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1946 u64 min = (u64)dev->ctrl.hmmin * 4096; 1947 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1948 int ret; 1949 1950 preferred = min(preferred, max); 1951 if (min > max) { 1952 dev_warn(dev->ctrl.device, 1953 "min host memory (%lld MiB) above limit (%d MiB).\n", 1954 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1955 nvme_free_host_mem(dev); 1956 return 0; 1957 } 1958 1959 /* 1960 * If we already have a buffer allocated check if we can reuse it. 1961 */ 1962 if (dev->host_mem_descs) { 1963 if (dev->host_mem_size >= min) 1964 enable_bits |= NVME_HOST_MEM_RETURN; 1965 else 1966 nvme_free_host_mem(dev); 1967 } 1968 1969 if (!dev->host_mem_descs) { 1970 if (nvme_alloc_host_mem(dev, min, preferred)) { 1971 dev_warn(dev->ctrl.device, 1972 "failed to allocate host memory buffer.\n"); 1973 return 0; /* controller must work without HMB */ 1974 } 1975 1976 dev_info(dev->ctrl.device, 1977 "allocated %lld MiB host memory buffer.\n", 1978 dev->host_mem_size >> ilog2(SZ_1M)); 1979 } 1980 1981 ret = nvme_set_host_mem(dev, enable_bits); 1982 if (ret) 1983 nvme_free_host_mem(dev); 1984 return ret; 1985 } 1986 1987 /* 1988 * nirqs is the number of interrupts available for write and read 1989 * queues. The core already reserved an interrupt for the admin queue. 1990 */ 1991 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 1992 { 1993 struct nvme_dev *dev = affd->priv; 1994 unsigned int nr_read_queues; 1995 1996 /* 1997 * If there is no interupt available for queues, ensure that 1998 * the default queue is set to 1. The affinity set size is 1999 * also set to one, but the irq core ignores it for this case. 2000 * 2001 * If only one interrupt is available or 'write_queue' == 0, combine 2002 * write and read queues. 2003 * 2004 * If 'write_queues' > 0, ensure it leaves room for at least one read 2005 * queue. 2006 */ 2007 if (!nrirqs) { 2008 nrirqs = 1; 2009 nr_read_queues = 0; 2010 } else if (nrirqs == 1 || !write_queues) { 2011 nr_read_queues = 0; 2012 } else if (write_queues >= nrirqs) { 2013 nr_read_queues = 1; 2014 } else { 2015 nr_read_queues = nrirqs - write_queues; 2016 } 2017 2018 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2019 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2020 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2021 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2022 affd->nr_sets = nr_read_queues ? 2 : 1; 2023 } 2024 2025 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2026 { 2027 struct pci_dev *pdev = to_pci_dev(dev->dev); 2028 struct irq_affinity affd = { 2029 .pre_vectors = 1, 2030 .calc_sets = nvme_calc_irq_sets, 2031 .priv = dev, 2032 }; 2033 unsigned int irq_queues, this_p_queues; 2034 2035 /* 2036 * Poll queues don't need interrupts, but we need at least one IO 2037 * queue left over for non-polled IO. 2038 */ 2039 this_p_queues = poll_queues; 2040 if (this_p_queues >= nr_io_queues) { 2041 this_p_queues = nr_io_queues - 1; 2042 irq_queues = 1; 2043 } else { 2044 irq_queues = nr_io_queues - this_p_queues + 1; 2045 } 2046 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2047 2048 /* Initialize for the single interrupt case */ 2049 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2050 dev->io_queues[HCTX_TYPE_READ] = 0; 2051 2052 /* 2053 * Some Apple controllers require all queues to use the 2054 * first vector. 2055 */ 2056 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2057 irq_queues = 1; 2058 2059 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2060 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2061 } 2062 2063 static void nvme_disable_io_queues(struct nvme_dev *dev) 2064 { 2065 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2066 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2067 } 2068 2069 static int nvme_setup_io_queues(struct nvme_dev *dev) 2070 { 2071 struct nvme_queue *adminq = &dev->queues[0]; 2072 struct pci_dev *pdev = to_pci_dev(dev->dev); 2073 int result, nr_io_queues; 2074 unsigned long size; 2075 2076 nr_io_queues = max_io_queues(); 2077 2078 /* 2079 * If tags are shared with admin queue (Apple bug), then 2080 * make sure we only use one IO queue. 2081 */ 2082 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2083 nr_io_queues = 1; 2084 2085 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2086 if (result < 0) 2087 return result; 2088 2089 if (nr_io_queues == 0) 2090 return 0; 2091 2092 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2093 2094 if (dev->cmb_use_sqes) { 2095 result = nvme_cmb_qdepth(dev, nr_io_queues, 2096 sizeof(struct nvme_command)); 2097 if (result > 0) 2098 dev->q_depth = result; 2099 else 2100 dev->cmb_use_sqes = false; 2101 } 2102 2103 do { 2104 size = db_bar_size(dev, nr_io_queues); 2105 result = nvme_remap_bar(dev, size); 2106 if (!result) 2107 break; 2108 if (!--nr_io_queues) 2109 return -ENOMEM; 2110 } while (1); 2111 adminq->q_db = dev->dbs; 2112 2113 retry: 2114 /* Deregister the admin queue's interrupt */ 2115 pci_free_irq(pdev, 0, adminq); 2116 2117 /* 2118 * If we enable msix early due to not intx, disable it again before 2119 * setting up the full range we need. 2120 */ 2121 pci_free_irq_vectors(pdev); 2122 2123 result = nvme_setup_irqs(dev, nr_io_queues); 2124 if (result <= 0) 2125 return -EIO; 2126 2127 dev->num_vecs = result; 2128 result = max(result - 1, 1); 2129 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2130 2131 /* 2132 * Should investigate if there's a performance win from allocating 2133 * more queues than interrupt vectors; it might allow the submission 2134 * path to scale better, even if the receive path is limited by the 2135 * number of interrupts. 2136 */ 2137 result = queue_request_irq(adminq); 2138 if (result) 2139 return result; 2140 set_bit(NVMEQ_ENABLED, &adminq->flags); 2141 2142 result = nvme_create_io_queues(dev); 2143 if (result || dev->online_queues < 2) 2144 return result; 2145 2146 if (dev->online_queues - 1 < dev->max_qid) { 2147 nr_io_queues = dev->online_queues - 1; 2148 nvme_disable_io_queues(dev); 2149 nvme_suspend_io_queues(dev); 2150 goto retry; 2151 } 2152 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2153 dev->io_queues[HCTX_TYPE_DEFAULT], 2154 dev->io_queues[HCTX_TYPE_READ], 2155 dev->io_queues[HCTX_TYPE_POLL]); 2156 return 0; 2157 } 2158 2159 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2160 { 2161 struct nvme_queue *nvmeq = req->end_io_data; 2162 2163 blk_mq_free_request(req); 2164 complete(&nvmeq->delete_done); 2165 } 2166 2167 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2168 { 2169 struct nvme_queue *nvmeq = req->end_io_data; 2170 2171 if (error) 2172 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2173 2174 nvme_del_queue_end(req, error); 2175 } 2176 2177 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2178 { 2179 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2180 struct request *req; 2181 struct nvme_command cmd; 2182 2183 memset(&cmd, 0, sizeof(cmd)); 2184 cmd.delete_queue.opcode = opcode; 2185 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2186 2187 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2188 if (IS_ERR(req)) 2189 return PTR_ERR(req); 2190 2191 req->timeout = ADMIN_TIMEOUT; 2192 req->end_io_data = nvmeq; 2193 2194 init_completion(&nvmeq->delete_done); 2195 blk_execute_rq_nowait(q, NULL, req, false, 2196 opcode == nvme_admin_delete_cq ? 2197 nvme_del_cq_end : nvme_del_queue_end); 2198 return 0; 2199 } 2200 2201 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2202 { 2203 int nr_queues = dev->online_queues - 1, sent = 0; 2204 unsigned long timeout; 2205 2206 retry: 2207 timeout = ADMIN_TIMEOUT; 2208 while (nr_queues > 0) { 2209 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2210 break; 2211 nr_queues--; 2212 sent++; 2213 } 2214 while (sent) { 2215 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2216 2217 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2218 timeout); 2219 if (timeout == 0) 2220 return false; 2221 2222 sent--; 2223 if (nr_queues) 2224 goto retry; 2225 } 2226 return true; 2227 } 2228 2229 static void nvme_dev_add(struct nvme_dev *dev) 2230 { 2231 int ret; 2232 2233 if (!dev->ctrl.tagset) { 2234 dev->tagset.ops = &nvme_mq_ops; 2235 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2236 dev->tagset.nr_maps = 2; /* default + read */ 2237 if (dev->io_queues[HCTX_TYPE_POLL]) 2238 dev->tagset.nr_maps++; 2239 dev->tagset.timeout = NVME_IO_TIMEOUT; 2240 dev->tagset.numa_node = dev_to_node(dev->dev); 2241 dev->tagset.queue_depth = 2242 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2243 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2244 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2245 dev->tagset.driver_data = dev; 2246 2247 /* 2248 * Some Apple controllers requires tags to be unique 2249 * across admin and IO queue, so reserve the first 32 2250 * tags of the IO queue. 2251 */ 2252 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2253 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2254 2255 ret = blk_mq_alloc_tag_set(&dev->tagset); 2256 if (ret) { 2257 dev_warn(dev->ctrl.device, 2258 "IO queues tagset allocation failed %d\n", ret); 2259 return; 2260 } 2261 dev->ctrl.tagset = &dev->tagset; 2262 } else { 2263 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2264 2265 /* Free previously allocated queues that are no longer usable */ 2266 nvme_free_queues(dev, dev->online_queues); 2267 } 2268 2269 nvme_dbbuf_set(dev); 2270 } 2271 2272 static int nvme_pci_enable(struct nvme_dev *dev) 2273 { 2274 int result = -ENOMEM; 2275 struct pci_dev *pdev = to_pci_dev(dev->dev); 2276 2277 if (pci_enable_device_mem(pdev)) 2278 return result; 2279 2280 pci_set_master(pdev); 2281 2282 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2283 goto disable; 2284 2285 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2286 result = -ENODEV; 2287 goto disable; 2288 } 2289 2290 /* 2291 * Some devices and/or platforms don't advertise or work with INTx 2292 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2293 * adjust this later. 2294 */ 2295 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2296 if (result < 0) 2297 return result; 2298 2299 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2300 2301 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2302 io_queue_depth); 2303 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2304 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2305 dev->dbs = dev->bar + 4096; 2306 2307 /* 2308 * Some Apple controllers require a non-standard SQE size. 2309 * Interestingly they also seem to ignore the CC:IOSQES register 2310 * so we don't bother updating it here. 2311 */ 2312 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2313 dev->io_sqes = 7; 2314 else 2315 dev->io_sqes = NVME_NVM_IOSQES; 2316 2317 /* 2318 * Temporary fix for the Apple controller found in the MacBook8,1 and 2319 * some MacBook7,1 to avoid controller resets and data loss. 2320 */ 2321 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2322 dev->q_depth = 2; 2323 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2324 "set queue depth=%u to work around controller resets\n", 2325 dev->q_depth); 2326 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2327 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2328 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2329 dev->q_depth = 64; 2330 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2331 "set queue depth=%u\n", dev->q_depth); 2332 } 2333 2334 /* 2335 * Controllers with the shared tags quirk need the IO queue to be 2336 * big enough so that we get 32 tags for the admin queue 2337 */ 2338 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2339 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2340 dev->q_depth = NVME_AQ_DEPTH + 2; 2341 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2342 dev->q_depth); 2343 } 2344 2345 2346 nvme_map_cmb(dev); 2347 2348 pci_enable_pcie_error_reporting(pdev); 2349 pci_save_state(pdev); 2350 return 0; 2351 2352 disable: 2353 pci_disable_device(pdev); 2354 return result; 2355 } 2356 2357 static void nvme_dev_unmap(struct nvme_dev *dev) 2358 { 2359 if (dev->bar) 2360 iounmap(dev->bar); 2361 pci_release_mem_regions(to_pci_dev(dev->dev)); 2362 } 2363 2364 static void nvme_pci_disable(struct nvme_dev *dev) 2365 { 2366 struct pci_dev *pdev = to_pci_dev(dev->dev); 2367 2368 pci_free_irq_vectors(pdev); 2369 2370 if (pci_is_enabled(pdev)) { 2371 pci_disable_pcie_error_reporting(pdev); 2372 pci_disable_device(pdev); 2373 } 2374 } 2375 2376 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2377 { 2378 bool dead = true, freeze = false; 2379 struct pci_dev *pdev = to_pci_dev(dev->dev); 2380 2381 mutex_lock(&dev->shutdown_lock); 2382 if (pci_is_enabled(pdev)) { 2383 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2384 2385 if (dev->ctrl.state == NVME_CTRL_LIVE || 2386 dev->ctrl.state == NVME_CTRL_RESETTING) { 2387 freeze = true; 2388 nvme_start_freeze(&dev->ctrl); 2389 } 2390 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2391 pdev->error_state != pci_channel_io_normal); 2392 } 2393 2394 /* 2395 * Give the controller a chance to complete all entered requests if 2396 * doing a safe shutdown. 2397 */ 2398 if (!dead && shutdown && freeze) 2399 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2400 2401 nvme_stop_queues(&dev->ctrl); 2402 2403 if (!dead && dev->ctrl.queue_count > 0) { 2404 nvme_disable_io_queues(dev); 2405 nvme_disable_admin_queue(dev, shutdown); 2406 } 2407 nvme_suspend_io_queues(dev); 2408 nvme_suspend_queue(&dev->queues[0]); 2409 nvme_pci_disable(dev); 2410 nvme_reap_pending_cqes(dev); 2411 2412 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2413 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2414 blk_mq_tagset_wait_completed_request(&dev->tagset); 2415 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2416 2417 /* 2418 * The driver will not be starting up queues again if shutting down so 2419 * must flush all entered requests to their failed completion to avoid 2420 * deadlocking blk-mq hot-cpu notifier. 2421 */ 2422 if (shutdown) { 2423 nvme_start_queues(&dev->ctrl); 2424 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2425 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2426 } 2427 mutex_unlock(&dev->shutdown_lock); 2428 } 2429 2430 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2431 { 2432 if (!nvme_wait_reset(&dev->ctrl)) 2433 return -EBUSY; 2434 nvme_dev_disable(dev, shutdown); 2435 return 0; 2436 } 2437 2438 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2439 { 2440 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2441 PAGE_SIZE, PAGE_SIZE, 0); 2442 if (!dev->prp_page_pool) 2443 return -ENOMEM; 2444 2445 /* Optimisation for I/Os between 4k and 128k */ 2446 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2447 256, 256, 0); 2448 if (!dev->prp_small_pool) { 2449 dma_pool_destroy(dev->prp_page_pool); 2450 return -ENOMEM; 2451 } 2452 return 0; 2453 } 2454 2455 static void nvme_release_prp_pools(struct nvme_dev *dev) 2456 { 2457 dma_pool_destroy(dev->prp_page_pool); 2458 dma_pool_destroy(dev->prp_small_pool); 2459 } 2460 2461 static void nvme_free_tagset(struct nvme_dev *dev) 2462 { 2463 if (dev->tagset.tags) 2464 blk_mq_free_tag_set(&dev->tagset); 2465 dev->ctrl.tagset = NULL; 2466 } 2467 2468 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2469 { 2470 struct nvme_dev *dev = to_nvme_dev(ctrl); 2471 2472 nvme_dbbuf_dma_free(dev); 2473 nvme_free_tagset(dev); 2474 if (dev->ctrl.admin_q) 2475 blk_put_queue(dev->ctrl.admin_q); 2476 free_opal_dev(dev->ctrl.opal_dev); 2477 mempool_destroy(dev->iod_mempool); 2478 put_device(dev->dev); 2479 kfree(dev->queues); 2480 kfree(dev); 2481 } 2482 2483 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2484 { 2485 /* 2486 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2487 * may be holding this pci_dev's device lock. 2488 */ 2489 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2490 nvme_get_ctrl(&dev->ctrl); 2491 nvme_dev_disable(dev, false); 2492 nvme_kill_queues(&dev->ctrl); 2493 if (!queue_work(nvme_wq, &dev->remove_work)) 2494 nvme_put_ctrl(&dev->ctrl); 2495 } 2496 2497 static void nvme_reset_work(struct work_struct *work) 2498 { 2499 struct nvme_dev *dev = 2500 container_of(work, struct nvme_dev, ctrl.reset_work); 2501 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2502 int result; 2503 2504 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2505 result = -ENODEV; 2506 goto out; 2507 } 2508 2509 /* 2510 * If we're called to reset a live controller first shut it down before 2511 * moving on. 2512 */ 2513 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2514 nvme_dev_disable(dev, false); 2515 nvme_sync_queues(&dev->ctrl); 2516 2517 mutex_lock(&dev->shutdown_lock); 2518 result = nvme_pci_enable(dev); 2519 if (result) 2520 goto out_unlock; 2521 2522 result = nvme_pci_configure_admin_queue(dev); 2523 if (result) 2524 goto out_unlock; 2525 2526 result = nvme_alloc_admin_tags(dev); 2527 if (result) 2528 goto out_unlock; 2529 2530 /* 2531 * Limit the max command size to prevent iod->sg allocations going 2532 * over a single page. 2533 */ 2534 dev->ctrl.max_hw_sectors = min_t(u32, 2535 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2536 dev->ctrl.max_segments = NVME_MAX_SEGS; 2537 2538 /* 2539 * Don't limit the IOMMU merged segment size. 2540 */ 2541 dma_set_max_seg_size(dev->dev, 0xffffffff); 2542 2543 mutex_unlock(&dev->shutdown_lock); 2544 2545 /* 2546 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2547 * initializing procedure here. 2548 */ 2549 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2550 dev_warn(dev->ctrl.device, 2551 "failed to mark controller CONNECTING\n"); 2552 result = -EBUSY; 2553 goto out; 2554 } 2555 2556 result = nvme_init_identify(&dev->ctrl); 2557 if (result) 2558 goto out; 2559 2560 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2561 if (!dev->ctrl.opal_dev) 2562 dev->ctrl.opal_dev = 2563 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2564 else if (was_suspend) 2565 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2566 } else { 2567 free_opal_dev(dev->ctrl.opal_dev); 2568 dev->ctrl.opal_dev = NULL; 2569 } 2570 2571 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2572 result = nvme_dbbuf_dma_alloc(dev); 2573 if (result) 2574 dev_warn(dev->dev, 2575 "unable to allocate dma for dbbuf\n"); 2576 } 2577 2578 if (dev->ctrl.hmpre) { 2579 result = nvme_setup_host_mem(dev); 2580 if (result < 0) 2581 goto out; 2582 } 2583 2584 result = nvme_setup_io_queues(dev); 2585 if (result) 2586 goto out; 2587 2588 /* 2589 * Keep the controller around but remove all namespaces if we don't have 2590 * any working I/O queue. 2591 */ 2592 if (dev->online_queues < 2) { 2593 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2594 nvme_kill_queues(&dev->ctrl); 2595 nvme_remove_namespaces(&dev->ctrl); 2596 nvme_free_tagset(dev); 2597 } else { 2598 nvme_start_queues(&dev->ctrl); 2599 nvme_wait_freeze(&dev->ctrl); 2600 nvme_dev_add(dev); 2601 nvme_unfreeze(&dev->ctrl); 2602 } 2603 2604 /* 2605 * If only admin queue live, keep it to do further investigation or 2606 * recovery. 2607 */ 2608 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2609 dev_warn(dev->ctrl.device, 2610 "failed to mark controller live state\n"); 2611 result = -ENODEV; 2612 goto out; 2613 } 2614 2615 nvme_start_ctrl(&dev->ctrl); 2616 return; 2617 2618 out_unlock: 2619 mutex_unlock(&dev->shutdown_lock); 2620 out: 2621 if (result) 2622 dev_warn(dev->ctrl.device, 2623 "Removing after probe failure status: %d\n", result); 2624 nvme_remove_dead_ctrl(dev); 2625 } 2626 2627 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2628 { 2629 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2630 struct pci_dev *pdev = to_pci_dev(dev->dev); 2631 2632 if (pci_get_drvdata(pdev)) 2633 device_release_driver(&pdev->dev); 2634 nvme_put_ctrl(&dev->ctrl); 2635 } 2636 2637 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2638 { 2639 *val = readl(to_nvme_dev(ctrl)->bar + off); 2640 return 0; 2641 } 2642 2643 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2644 { 2645 writel(val, to_nvme_dev(ctrl)->bar + off); 2646 return 0; 2647 } 2648 2649 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2650 { 2651 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2652 return 0; 2653 } 2654 2655 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2656 { 2657 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2658 2659 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2660 } 2661 2662 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2663 .name = "pcie", 2664 .module = THIS_MODULE, 2665 .flags = NVME_F_METADATA_SUPPORTED | 2666 NVME_F_PCI_P2PDMA, 2667 .reg_read32 = nvme_pci_reg_read32, 2668 .reg_write32 = nvme_pci_reg_write32, 2669 .reg_read64 = nvme_pci_reg_read64, 2670 .free_ctrl = nvme_pci_free_ctrl, 2671 .submit_async_event = nvme_pci_submit_async_event, 2672 .get_address = nvme_pci_get_address, 2673 }; 2674 2675 static int nvme_dev_map(struct nvme_dev *dev) 2676 { 2677 struct pci_dev *pdev = to_pci_dev(dev->dev); 2678 2679 if (pci_request_mem_regions(pdev, "nvme")) 2680 return -ENODEV; 2681 2682 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2683 goto release; 2684 2685 return 0; 2686 release: 2687 pci_release_mem_regions(pdev); 2688 return -ENODEV; 2689 } 2690 2691 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2692 { 2693 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2694 /* 2695 * Several Samsung devices seem to drop off the PCIe bus 2696 * randomly when APST is on and uses the deepest sleep state. 2697 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2698 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2699 * 950 PRO 256GB", but it seems to be restricted to two Dell 2700 * laptops. 2701 */ 2702 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2703 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2704 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2705 return NVME_QUIRK_NO_DEEPEST_PS; 2706 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2707 /* 2708 * Samsung SSD 960 EVO drops off the PCIe bus after system 2709 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2710 * within few minutes after bootup on a Coffee Lake board - 2711 * ASUS PRIME Z370-A 2712 */ 2713 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2714 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2715 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2716 return NVME_QUIRK_NO_APST; 2717 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2718 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2719 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2720 /* 2721 * Forcing to use host managed nvme power settings for 2722 * lowest idle power with quick resume latency on 2723 * Samsung and Toshiba SSDs based on suspend behavior 2724 * on Coffee Lake board for LENOVO C640 2725 */ 2726 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2727 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2728 return NVME_QUIRK_SIMPLE_SUSPEND; 2729 } 2730 2731 return 0; 2732 } 2733 2734 static void nvme_async_probe(void *data, async_cookie_t cookie) 2735 { 2736 struct nvme_dev *dev = data; 2737 2738 flush_work(&dev->ctrl.reset_work); 2739 flush_work(&dev->ctrl.scan_work); 2740 nvme_put_ctrl(&dev->ctrl); 2741 } 2742 2743 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2744 { 2745 int node, result = -ENOMEM; 2746 struct nvme_dev *dev; 2747 unsigned long quirks = id->driver_data; 2748 size_t alloc_size; 2749 2750 node = dev_to_node(&pdev->dev); 2751 if (node == NUMA_NO_NODE) 2752 set_dev_node(&pdev->dev, first_memory_node); 2753 2754 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2755 if (!dev) 2756 return -ENOMEM; 2757 2758 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2759 GFP_KERNEL, node); 2760 if (!dev->queues) 2761 goto free; 2762 2763 dev->dev = get_device(&pdev->dev); 2764 pci_set_drvdata(pdev, dev); 2765 2766 result = nvme_dev_map(dev); 2767 if (result) 2768 goto put_pci; 2769 2770 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2771 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2772 mutex_init(&dev->shutdown_lock); 2773 2774 result = nvme_setup_prp_pools(dev); 2775 if (result) 2776 goto unmap; 2777 2778 quirks |= check_vendor_combination_bug(pdev); 2779 2780 /* 2781 * Double check that our mempool alloc size will cover the biggest 2782 * command we support. 2783 */ 2784 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2785 NVME_MAX_SEGS, true); 2786 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2787 2788 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2789 mempool_kfree, 2790 (void *) alloc_size, 2791 GFP_KERNEL, node); 2792 if (!dev->iod_mempool) { 2793 result = -ENOMEM; 2794 goto release_pools; 2795 } 2796 2797 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2798 quirks); 2799 if (result) 2800 goto release_mempool; 2801 2802 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2803 2804 nvme_reset_ctrl(&dev->ctrl); 2805 async_schedule(nvme_async_probe, dev); 2806 2807 return 0; 2808 2809 release_mempool: 2810 mempool_destroy(dev->iod_mempool); 2811 release_pools: 2812 nvme_release_prp_pools(dev); 2813 unmap: 2814 nvme_dev_unmap(dev); 2815 put_pci: 2816 put_device(dev->dev); 2817 free: 2818 kfree(dev->queues); 2819 kfree(dev); 2820 return result; 2821 } 2822 2823 static void nvme_reset_prepare(struct pci_dev *pdev) 2824 { 2825 struct nvme_dev *dev = pci_get_drvdata(pdev); 2826 2827 /* 2828 * We don't need to check the return value from waiting for the reset 2829 * state as pci_dev device lock is held, making it impossible to race 2830 * with ->remove(). 2831 */ 2832 nvme_disable_prepare_reset(dev, false); 2833 nvme_sync_queues(&dev->ctrl); 2834 } 2835 2836 static void nvme_reset_done(struct pci_dev *pdev) 2837 { 2838 struct nvme_dev *dev = pci_get_drvdata(pdev); 2839 2840 if (!nvme_try_sched_reset(&dev->ctrl)) 2841 flush_work(&dev->ctrl.reset_work); 2842 } 2843 2844 static void nvme_shutdown(struct pci_dev *pdev) 2845 { 2846 struct nvme_dev *dev = pci_get_drvdata(pdev); 2847 nvme_disable_prepare_reset(dev, true); 2848 } 2849 2850 /* 2851 * The driver's remove may be called on a device in a partially initialized 2852 * state. This function must not have any dependencies on the device state in 2853 * order to proceed. 2854 */ 2855 static void nvme_remove(struct pci_dev *pdev) 2856 { 2857 struct nvme_dev *dev = pci_get_drvdata(pdev); 2858 2859 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2860 pci_set_drvdata(pdev, NULL); 2861 2862 if (!pci_device_is_present(pdev)) { 2863 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2864 nvme_dev_disable(dev, true); 2865 nvme_dev_remove_admin(dev); 2866 } 2867 2868 flush_work(&dev->ctrl.reset_work); 2869 nvme_stop_ctrl(&dev->ctrl); 2870 nvme_remove_namespaces(&dev->ctrl); 2871 nvme_dev_disable(dev, true); 2872 nvme_release_cmb(dev); 2873 nvme_free_host_mem(dev); 2874 nvme_dev_remove_admin(dev); 2875 nvme_free_queues(dev, 0); 2876 nvme_release_prp_pools(dev); 2877 nvme_dev_unmap(dev); 2878 nvme_uninit_ctrl(&dev->ctrl); 2879 } 2880 2881 #ifdef CONFIG_PM_SLEEP 2882 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2883 { 2884 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2885 } 2886 2887 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2888 { 2889 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2890 } 2891 2892 static int nvme_resume(struct device *dev) 2893 { 2894 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2895 struct nvme_ctrl *ctrl = &ndev->ctrl; 2896 2897 if (ndev->last_ps == U32_MAX || 2898 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2899 return nvme_try_sched_reset(&ndev->ctrl); 2900 return 0; 2901 } 2902 2903 static int nvme_suspend(struct device *dev) 2904 { 2905 struct pci_dev *pdev = to_pci_dev(dev); 2906 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2907 struct nvme_ctrl *ctrl = &ndev->ctrl; 2908 int ret = -EBUSY; 2909 2910 ndev->last_ps = U32_MAX; 2911 2912 /* 2913 * The platform does not remove power for a kernel managed suspend so 2914 * use host managed nvme power settings for lowest idle power if 2915 * possible. This should have quicker resume latency than a full device 2916 * shutdown. But if the firmware is involved after the suspend or the 2917 * device does not support any non-default power states, shut down the 2918 * device fully. 2919 * 2920 * If ASPM is not enabled for the device, shut down the device and allow 2921 * the PCI bus layer to put it into D3 in order to take the PCIe link 2922 * down, so as to allow the platform to achieve its minimum low-power 2923 * state (which may not be possible if the link is up). 2924 */ 2925 if (pm_suspend_via_firmware() || !ctrl->npss || 2926 !pcie_aspm_enabled(pdev) || 2927 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2928 return nvme_disable_prepare_reset(ndev, true); 2929 2930 nvme_start_freeze(ctrl); 2931 nvme_wait_freeze(ctrl); 2932 nvme_sync_queues(ctrl); 2933 2934 if (ctrl->state != NVME_CTRL_LIVE) 2935 goto unfreeze; 2936 2937 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2938 if (ret < 0) 2939 goto unfreeze; 2940 2941 /* 2942 * A saved state prevents pci pm from generically controlling the 2943 * device's power. If we're using protocol specific settings, we don't 2944 * want pci interfering. 2945 */ 2946 pci_save_state(pdev); 2947 2948 ret = nvme_set_power_state(ctrl, ctrl->npss); 2949 if (ret < 0) 2950 goto unfreeze; 2951 2952 if (ret) { 2953 /* discard the saved state */ 2954 pci_load_saved_state(pdev, NULL); 2955 2956 /* 2957 * Clearing npss forces a controller reset on resume. The 2958 * correct value will be rediscovered then. 2959 */ 2960 ret = nvme_disable_prepare_reset(ndev, true); 2961 ctrl->npss = 0; 2962 } 2963 unfreeze: 2964 nvme_unfreeze(ctrl); 2965 return ret; 2966 } 2967 2968 static int nvme_simple_suspend(struct device *dev) 2969 { 2970 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2971 return nvme_disable_prepare_reset(ndev, true); 2972 } 2973 2974 static int nvme_simple_resume(struct device *dev) 2975 { 2976 struct pci_dev *pdev = to_pci_dev(dev); 2977 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2978 2979 return nvme_try_sched_reset(&ndev->ctrl); 2980 } 2981 2982 static const struct dev_pm_ops nvme_dev_pm_ops = { 2983 .suspend = nvme_suspend, 2984 .resume = nvme_resume, 2985 .freeze = nvme_simple_suspend, 2986 .thaw = nvme_simple_resume, 2987 .poweroff = nvme_simple_suspend, 2988 .restore = nvme_simple_resume, 2989 }; 2990 #endif /* CONFIG_PM_SLEEP */ 2991 2992 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2993 pci_channel_state_t state) 2994 { 2995 struct nvme_dev *dev = pci_get_drvdata(pdev); 2996 2997 /* 2998 * A frozen channel requires a reset. When detected, this method will 2999 * shutdown the controller to quiesce. The controller will be restarted 3000 * after the slot reset through driver's slot_reset callback. 3001 */ 3002 switch (state) { 3003 case pci_channel_io_normal: 3004 return PCI_ERS_RESULT_CAN_RECOVER; 3005 case pci_channel_io_frozen: 3006 dev_warn(dev->ctrl.device, 3007 "frozen state error detected, reset controller\n"); 3008 nvme_dev_disable(dev, false); 3009 return PCI_ERS_RESULT_NEED_RESET; 3010 case pci_channel_io_perm_failure: 3011 dev_warn(dev->ctrl.device, 3012 "failure state error detected, request disconnect\n"); 3013 return PCI_ERS_RESULT_DISCONNECT; 3014 } 3015 return PCI_ERS_RESULT_NEED_RESET; 3016 } 3017 3018 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3019 { 3020 struct nvme_dev *dev = pci_get_drvdata(pdev); 3021 3022 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3023 pci_restore_state(pdev); 3024 nvme_reset_ctrl(&dev->ctrl); 3025 return PCI_ERS_RESULT_RECOVERED; 3026 } 3027 3028 static void nvme_error_resume(struct pci_dev *pdev) 3029 { 3030 struct nvme_dev *dev = pci_get_drvdata(pdev); 3031 3032 flush_work(&dev->ctrl.reset_work); 3033 } 3034 3035 static const struct pci_error_handlers nvme_err_handler = { 3036 .error_detected = nvme_error_detected, 3037 .slot_reset = nvme_slot_reset, 3038 .resume = nvme_error_resume, 3039 .reset_prepare = nvme_reset_prepare, 3040 .reset_done = nvme_reset_done, 3041 }; 3042 3043 static const struct pci_device_id nvme_id_table[] = { 3044 { PCI_VDEVICE(INTEL, 0x0953), 3045 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3046 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3047 { PCI_VDEVICE(INTEL, 0x0a53), 3048 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3049 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3050 { PCI_VDEVICE(INTEL, 0x0a54), 3051 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3052 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3053 { PCI_VDEVICE(INTEL, 0x0a55), 3054 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3055 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3056 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3057 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3058 NVME_QUIRK_MEDIUM_PRIO_SQ | 3059 NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 3060 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3061 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3062 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3063 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3064 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3065 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3066 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3067 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3068 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3069 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3070 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3071 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3072 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3073 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3074 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3075 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3076 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3077 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3078 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3079 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3080 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3081 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3082 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3083 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3084 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3085 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3086 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3087 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3088 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3089 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3090 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3091 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3092 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3093 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3094 NVME_QUIRK_128_BYTES_SQES | 3095 NVME_QUIRK_SHARED_TAGS }, 3096 { 0, } 3097 }; 3098 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3099 3100 static struct pci_driver nvme_driver = { 3101 .name = "nvme", 3102 .id_table = nvme_id_table, 3103 .probe = nvme_probe, 3104 .remove = nvme_remove, 3105 .shutdown = nvme_shutdown, 3106 #ifdef CONFIG_PM_SLEEP 3107 .driver = { 3108 .pm = &nvme_dev_pm_ops, 3109 }, 3110 #endif 3111 .sriov_configure = pci_sriov_configure_simple, 3112 .err_handler = &nvme_err_handler, 3113 }; 3114 3115 static int __init nvme_init(void) 3116 { 3117 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3118 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3119 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3120 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3121 3122 write_queues = min(write_queues, num_possible_cpus()); 3123 poll_queues = min(poll_queues, num_possible_cpus()); 3124 return pci_register_driver(&nvme_driver); 3125 } 3126 3127 static void __exit nvme_exit(void) 3128 { 3129 pci_unregister_driver(&nvme_driver); 3130 flush_workqueue(nvme_wq); 3131 } 3132 3133 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3134 MODULE_LICENSE("GPL"); 3135 MODULE_VERSION("1.0"); 3136 module_init(nvme_init); 3137 module_exit(nvme_exit); 3138