1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/blk-integrity.h> 13 #include <linux/dmi.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kstrtox.h> 18 #include <linux/memremap.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/once.h> 23 #include <linux/pci.h> 24 #include <linux/suspend.h> 25 #include <linux/t10-pi.h> 26 #include <linux/types.h> 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #include <linux/io-64-nonatomic-hi-lo.h> 29 #include <linux/sed-opal.h> 30 #include <linux/pci-p2pdma.h> 31 32 #include "trace.h" 33 #include "nvme.h" 34 35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 37 38 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39 40 /* 41 * These can be higher, but we need to ensure that any command doesn't 42 * require an sg allocation that needs more than a page of data. 43 */ 44 #define NVME_MAX_KB_SZ 8192 45 #define NVME_MAX_SEGS 128 46 #define NVME_MAX_NR_ALLOCATIONS 5 47 48 static int use_threaded_interrupts; 49 module_param(use_threaded_interrupts, int, 0444); 50 51 static bool use_cmb_sqes = true; 52 module_param(use_cmb_sqes, bool, 0444); 53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 54 55 static unsigned int max_host_mem_size_mb = 128; 56 module_param(max_host_mem_size_mb, uint, 0444); 57 MODULE_PARM_DESC(max_host_mem_size_mb, 58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 59 60 static unsigned int sgl_threshold = SZ_32K; 61 module_param(sgl_threshold, uint, 0644); 62 MODULE_PARM_DESC(sgl_threshold, 63 "Use SGLs when average request segment size is larger or equal to " 64 "this size. Use 0 to disable SGLs."); 65 66 #define NVME_PCI_MIN_QUEUE_SIZE 2 67 #define NVME_PCI_MAX_QUEUE_SIZE 4095 68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69 static const struct kernel_param_ops io_queue_depth_ops = { 70 .set = io_queue_depth_set, 71 .get = param_get_uint, 72 }; 73 74 static unsigned int io_queue_depth = 1024; 75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 77 78 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 79 { 80 unsigned int n; 81 int ret; 82 83 ret = kstrtouint(val, 10, &n); 84 if (ret != 0 || n > num_possible_cpus()) 85 return -EINVAL; 86 return param_set_uint(val, kp); 87 } 88 89 static const struct kernel_param_ops io_queue_count_ops = { 90 .set = io_queue_count_set, 91 .get = param_get_uint, 92 }; 93 94 static unsigned int write_queues; 95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 96 MODULE_PARM_DESC(write_queues, 97 "Number of queues to use for writes. If not set, reads and writes " 98 "will share a queue set."); 99 100 static unsigned int poll_queues; 101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 103 104 static bool noacpi; 105 module_param(noacpi, bool, 0444); 106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 107 108 struct nvme_dev; 109 struct nvme_queue; 110 111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 112 static void nvme_delete_io_queues(struct nvme_dev *dev); 113 static void nvme_update_attrs(struct nvme_dev *dev); 114 115 /* 116 * Represents an NVM Express device. Each nvme_dev is a PCI function. 117 */ 118 struct nvme_dev { 119 struct nvme_queue *queues; 120 struct blk_mq_tag_set tagset; 121 struct blk_mq_tag_set admin_tagset; 122 u32 __iomem *dbs; 123 struct device *dev; 124 struct dma_pool *prp_page_pool; 125 struct dma_pool *prp_small_pool; 126 unsigned online_queues; 127 unsigned max_qid; 128 unsigned io_queues[HCTX_MAX_TYPES]; 129 unsigned int num_vecs; 130 u32 q_depth; 131 int io_sqes; 132 u32 db_stride; 133 void __iomem *bar; 134 unsigned long bar_mapped_size; 135 struct mutex shutdown_lock; 136 bool subsystem; 137 u64 cmb_size; 138 bool cmb_use_sqes; 139 u32 cmbsz; 140 u32 cmbloc; 141 struct nvme_ctrl ctrl; 142 u32 last_ps; 143 bool hmb; 144 145 mempool_t *iod_mempool; 146 147 /* shadow doorbell buffer support: */ 148 __le32 *dbbuf_dbs; 149 dma_addr_t dbbuf_dbs_dma_addr; 150 __le32 *dbbuf_eis; 151 dma_addr_t dbbuf_eis_dma_addr; 152 153 /* host memory buffer support: */ 154 u64 host_mem_size; 155 u32 nr_host_mem_descs; 156 dma_addr_t host_mem_descs_dma; 157 struct nvme_host_mem_buf_desc *host_mem_descs; 158 void **host_mem_desc_bufs; 159 unsigned int nr_allocated_queues; 160 unsigned int nr_write_queues; 161 unsigned int nr_poll_queues; 162 }; 163 164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 165 { 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 167 NVME_PCI_MAX_QUEUE_SIZE); 168 } 169 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171 { 172 return qid * 2 * stride; 173 } 174 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176 { 177 return (qid * 2 + 1) * stride; 178 } 179 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 181 { 182 return container_of(ctrl, struct nvme_dev, ctrl); 183 } 184 185 /* 186 * An NVM Express queue. Each device has at least two (one for admin 187 * commands and one for I/O commands). 188 */ 189 struct nvme_queue { 190 struct nvme_dev *dev; 191 spinlock_t sq_lock; 192 void *sq_cmds; 193 /* only used for poll queues: */ 194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 195 struct nvme_completion *cqes; 196 dma_addr_t sq_dma_addr; 197 dma_addr_t cq_dma_addr; 198 u32 __iomem *q_db; 199 u32 q_depth; 200 u16 cq_vector; 201 u16 sq_tail; 202 u16 last_sq_tail; 203 u16 cq_head; 204 u16 qid; 205 u8 cq_phase; 206 u8 sqes; 207 unsigned long flags; 208 #define NVMEQ_ENABLED 0 209 #define NVMEQ_SQ_CMB 1 210 #define NVMEQ_DELETE_ERROR 2 211 #define NVMEQ_POLLED 3 212 __le32 *dbbuf_sq_db; 213 __le32 *dbbuf_cq_db; 214 __le32 *dbbuf_sq_ei; 215 __le32 *dbbuf_cq_ei; 216 struct completion delete_done; 217 }; 218 219 union nvme_descriptor { 220 struct nvme_sgl_desc *sg_list; 221 __le64 *prp_list; 222 }; 223 224 /* 225 * The nvme_iod describes the data in an I/O. 226 * 227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 228 * to the actual struct scatterlist. 229 */ 230 struct nvme_iod { 231 struct nvme_request req; 232 struct nvme_command cmd; 233 bool aborted; 234 s8 nr_allocations; /* PRP list pool allocations. 0 means small 235 pool in use */ 236 unsigned int dma_len; /* length of single DMA segment mapping */ 237 dma_addr_t first_dma; 238 dma_addr_t meta_dma; 239 struct sg_table sgt; 240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS]; 241 }; 242 243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 244 { 245 return dev->nr_allocated_queues * 8 * dev->db_stride; 246 } 247 248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 249 { 250 unsigned int mem_size = nvme_dbbuf_size(dev); 251 252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 253 return; 254 255 if (dev->dbbuf_dbs) { 256 /* 257 * Clear the dbbuf memory so the driver doesn't observe stale 258 * values from the previous instantiation. 259 */ 260 memset(dev->dbbuf_dbs, 0, mem_size); 261 memset(dev->dbbuf_eis, 0, mem_size); 262 return; 263 } 264 265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 266 &dev->dbbuf_dbs_dma_addr, 267 GFP_KERNEL); 268 if (!dev->dbbuf_dbs) 269 goto fail; 270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 271 &dev->dbbuf_eis_dma_addr, 272 GFP_KERNEL); 273 if (!dev->dbbuf_eis) 274 goto fail_free_dbbuf_dbs; 275 return; 276 277 fail_free_dbbuf_dbs: 278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 279 dev->dbbuf_dbs_dma_addr); 280 dev->dbbuf_dbs = NULL; 281 fail: 282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 283 } 284 285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 286 { 287 unsigned int mem_size = nvme_dbbuf_size(dev); 288 289 if (dev->dbbuf_dbs) { 290 dma_free_coherent(dev->dev, mem_size, 291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 292 dev->dbbuf_dbs = NULL; 293 } 294 if (dev->dbbuf_eis) { 295 dma_free_coherent(dev->dev, mem_size, 296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 297 dev->dbbuf_eis = NULL; 298 } 299 } 300 301 static void nvme_dbbuf_init(struct nvme_dev *dev, 302 struct nvme_queue *nvmeq, int qid) 303 { 304 if (!dev->dbbuf_dbs || !qid) 305 return; 306 307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 311 } 312 313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 314 { 315 if (!nvmeq->qid) 316 return; 317 318 nvmeq->dbbuf_sq_db = NULL; 319 nvmeq->dbbuf_cq_db = NULL; 320 nvmeq->dbbuf_sq_ei = NULL; 321 nvmeq->dbbuf_cq_ei = NULL; 322 } 323 324 static void nvme_dbbuf_set(struct nvme_dev *dev) 325 { 326 struct nvme_command c = { }; 327 unsigned int i; 328 329 if (!dev->dbbuf_dbs) 330 return; 331 332 c.dbbuf.opcode = nvme_admin_dbbuf; 333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 335 336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 338 /* Free memory and continue on */ 339 nvme_dbbuf_dma_free(dev); 340 341 for (i = 1; i <= dev->online_queues; i++) 342 nvme_dbbuf_free(&dev->queues[i]); 343 } 344 } 345 346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 347 { 348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 349 } 350 351 /* Update dbbuf and return true if an MMIO is required */ 352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db, 353 volatile __le32 *dbbuf_ei) 354 { 355 if (dbbuf_db) { 356 u16 old_value, event_idx; 357 358 /* 359 * Ensure that the queue is written before updating 360 * the doorbell in memory 361 */ 362 wmb(); 363 364 old_value = le32_to_cpu(*dbbuf_db); 365 *dbbuf_db = cpu_to_le32(value); 366 367 /* 368 * Ensure that the doorbell is updated before reading the event 369 * index from memory. The controller needs to provide similar 370 * ordering to ensure the envent index is updated before reading 371 * the doorbell. 372 */ 373 mb(); 374 375 event_idx = le32_to_cpu(*dbbuf_ei); 376 if (!nvme_dbbuf_need_event(event_idx, value, old_value)) 377 return false; 378 } 379 380 return true; 381 } 382 383 /* 384 * Will slightly overestimate the number of pages needed. This is OK 385 * as it only leads to a small amount of wasted memory for the lifetime of 386 * the I/O. 387 */ 388 static int nvme_pci_npages_prp(void) 389 { 390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; 391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); 392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); 393 } 394 395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 396 unsigned int hctx_idx) 397 { 398 struct nvme_dev *dev = to_nvme_dev(data); 399 struct nvme_queue *nvmeq = &dev->queues[0]; 400 401 WARN_ON(hctx_idx != 0); 402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 403 404 hctx->driver_data = nvmeq; 405 return 0; 406 } 407 408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 409 unsigned int hctx_idx) 410 { 411 struct nvme_dev *dev = to_nvme_dev(data); 412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 413 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 415 hctx->driver_data = nvmeq; 416 return 0; 417 } 418 419 static int nvme_pci_init_request(struct blk_mq_tag_set *set, 420 struct request *req, unsigned int hctx_idx, 421 unsigned int numa_node) 422 { 423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 424 425 nvme_req(req)->ctrl = set->driver_data; 426 nvme_req(req)->cmd = &iod->cmd; 427 return 0; 428 } 429 430 static int queue_irq_offset(struct nvme_dev *dev) 431 { 432 /* if we have more than 1 vec, admin queue offsets us by 1 */ 433 if (dev->num_vecs > 1) 434 return 1; 435 436 return 0; 437 } 438 439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 440 { 441 struct nvme_dev *dev = to_nvme_dev(set->driver_data); 442 int i, qoff, offset; 443 444 offset = queue_irq_offset(dev); 445 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 446 struct blk_mq_queue_map *map = &set->map[i]; 447 448 map->nr_queues = dev->io_queues[i]; 449 if (!map->nr_queues) { 450 BUG_ON(i == HCTX_TYPE_DEFAULT); 451 continue; 452 } 453 454 /* 455 * The poll queue(s) doesn't have an IRQ (and hence IRQ 456 * affinity), so use the regular blk-mq cpu mapping 457 */ 458 map->queue_offset = qoff; 459 if (i != HCTX_TYPE_POLL && offset) 460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 461 else 462 blk_mq_map_queues(map); 463 qoff += map->nr_queues; 464 offset += map->nr_queues; 465 } 466 } 467 468 /* 469 * Write sq tail if we are asked to, or if the next command would wrap. 470 */ 471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 472 { 473 if (!write_sq) { 474 u16 next_tail = nvmeq->sq_tail + 1; 475 476 if (next_tail == nvmeq->q_depth) 477 next_tail = 0; 478 if (next_tail != nvmeq->last_sq_tail) 479 return; 480 } 481 482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 484 writel(nvmeq->sq_tail, nvmeq->q_db); 485 nvmeq->last_sq_tail = nvmeq->sq_tail; 486 } 487 488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 489 struct nvme_command *cmd) 490 { 491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 492 absolute_pointer(cmd), sizeof(*cmd)); 493 if (++nvmeq->sq_tail == nvmeq->q_depth) 494 nvmeq->sq_tail = 0; 495 } 496 497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 498 { 499 struct nvme_queue *nvmeq = hctx->driver_data; 500 501 spin_lock(&nvmeq->sq_lock); 502 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 503 nvme_write_sq_db(nvmeq, true); 504 spin_unlock(&nvmeq->sq_lock); 505 } 506 507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req, 508 int nseg) 509 { 510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 511 unsigned int avg_seg_size; 512 513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 514 515 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 516 return false; 517 if (!nvmeq->qid) 518 return false; 519 if (!sgl_threshold || avg_seg_size < sgl_threshold) 520 return false; 521 return true; 522 } 523 524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 525 { 526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 528 dma_addr_t dma_addr = iod->first_dma; 529 int i; 530 531 for (i = 0; i < iod->nr_allocations; i++) { 532 __le64 *prp_list = iod->list[i].prp_list; 533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 534 535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 536 dma_addr = next_dma_addr; 537 } 538 } 539 540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 541 { 542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 543 544 if (iod->dma_len) { 545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 546 rq_dma_dir(req)); 547 return; 548 } 549 550 WARN_ON_ONCE(!iod->sgt.nents); 551 552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 553 554 if (iod->nr_allocations == 0) 555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, 556 iod->first_dma); 557 else if (iod->nr_allocations == 1) 558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, 559 iod->first_dma); 560 else 561 nvme_free_prps(dev, req); 562 mempool_free(iod->sgt.sgl, dev->iod_mempool); 563 } 564 565 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 566 { 567 int i; 568 struct scatterlist *sg; 569 570 for_each_sg(sgl, sg, nents, i) { 571 dma_addr_t phys = sg_phys(sg); 572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 573 "dma_address:%pad dma_length:%d\n", 574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 575 sg_dma_len(sg)); 576 } 577 } 578 579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 580 struct request *req, struct nvme_rw_command *cmnd) 581 { 582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 583 struct dma_pool *pool; 584 int length = blk_rq_payload_bytes(req); 585 struct scatterlist *sg = iod->sgt.sgl; 586 int dma_len = sg_dma_len(sg); 587 u64 dma_addr = sg_dma_address(sg); 588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 589 __le64 *prp_list; 590 dma_addr_t prp_dma; 591 int nprps, i; 592 593 length -= (NVME_CTRL_PAGE_SIZE - offset); 594 if (length <= 0) { 595 iod->first_dma = 0; 596 goto done; 597 } 598 599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 600 if (dma_len) { 601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 602 } else { 603 sg = sg_next(sg); 604 dma_addr = sg_dma_address(sg); 605 dma_len = sg_dma_len(sg); 606 } 607 608 if (length <= NVME_CTRL_PAGE_SIZE) { 609 iod->first_dma = dma_addr; 610 goto done; 611 } 612 613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 614 if (nprps <= (256 / 8)) { 615 pool = dev->prp_small_pool; 616 iod->nr_allocations = 0; 617 } else { 618 pool = dev->prp_page_pool; 619 iod->nr_allocations = 1; 620 } 621 622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 623 if (!prp_list) { 624 iod->nr_allocations = -1; 625 return BLK_STS_RESOURCE; 626 } 627 iod->list[0].prp_list = prp_list; 628 iod->first_dma = prp_dma; 629 i = 0; 630 for (;;) { 631 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 632 __le64 *old_prp_list = prp_list; 633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 634 if (!prp_list) 635 goto free_prps; 636 iod->list[iod->nr_allocations++].prp_list = prp_list; 637 prp_list[0] = old_prp_list[i - 1]; 638 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 639 i = 1; 640 } 641 prp_list[i++] = cpu_to_le64(dma_addr); 642 dma_len -= NVME_CTRL_PAGE_SIZE; 643 dma_addr += NVME_CTRL_PAGE_SIZE; 644 length -= NVME_CTRL_PAGE_SIZE; 645 if (length <= 0) 646 break; 647 if (dma_len > 0) 648 continue; 649 if (unlikely(dma_len < 0)) 650 goto bad_sgl; 651 sg = sg_next(sg); 652 dma_addr = sg_dma_address(sg); 653 dma_len = sg_dma_len(sg); 654 } 655 done: 656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 658 return BLK_STS_OK; 659 free_prps: 660 nvme_free_prps(dev, req); 661 return BLK_STS_RESOURCE; 662 bad_sgl: 663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 664 "Invalid SGL for payload:%d nents:%d\n", 665 blk_rq_payload_bytes(req), iod->sgt.nents); 666 return BLK_STS_IOERR; 667 } 668 669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 670 struct scatterlist *sg) 671 { 672 sge->addr = cpu_to_le64(sg_dma_address(sg)); 673 sge->length = cpu_to_le32(sg_dma_len(sg)); 674 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 675 } 676 677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 678 dma_addr_t dma_addr, int entries) 679 { 680 sge->addr = cpu_to_le64(dma_addr); 681 sge->length = cpu_to_le32(entries * sizeof(*sge)); 682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 683 } 684 685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 686 struct request *req, struct nvme_rw_command *cmd) 687 { 688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 689 struct dma_pool *pool; 690 struct nvme_sgl_desc *sg_list; 691 struct scatterlist *sg = iod->sgt.sgl; 692 unsigned int entries = iod->sgt.nents; 693 dma_addr_t sgl_dma; 694 int i = 0; 695 696 /* setting the transfer type as SGL */ 697 cmd->flags = NVME_CMD_SGL_METABUF; 698 699 if (entries == 1) { 700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 701 return BLK_STS_OK; 702 } 703 704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 705 pool = dev->prp_small_pool; 706 iod->nr_allocations = 0; 707 } else { 708 pool = dev->prp_page_pool; 709 iod->nr_allocations = 1; 710 } 711 712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 713 if (!sg_list) { 714 iod->nr_allocations = -1; 715 return BLK_STS_RESOURCE; 716 } 717 718 iod->list[0].sg_list = sg_list; 719 iod->first_dma = sgl_dma; 720 721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 722 do { 723 nvme_pci_sgl_set_data(&sg_list[i++], sg); 724 sg = sg_next(sg); 725 } while (--entries > 0); 726 727 return BLK_STS_OK; 728 } 729 730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 731 struct request *req, struct nvme_rw_command *cmnd, 732 struct bio_vec *bv) 733 { 734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 737 738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 739 if (dma_mapping_error(dev->dev, iod->first_dma)) 740 return BLK_STS_RESOURCE; 741 iod->dma_len = bv->bv_len; 742 743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 744 if (bv->bv_len > first_prp_len) 745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 746 else 747 cmnd->dptr.prp2 = 0; 748 return BLK_STS_OK; 749 } 750 751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 752 struct request *req, struct nvme_rw_command *cmnd, 753 struct bio_vec *bv) 754 { 755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 756 757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 758 if (dma_mapping_error(dev->dev, iod->first_dma)) 759 return BLK_STS_RESOURCE; 760 iod->dma_len = bv->bv_len; 761 762 cmnd->flags = NVME_CMD_SGL_METABUF; 763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 766 return BLK_STS_OK; 767 } 768 769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 770 struct nvme_command *cmnd) 771 { 772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 773 blk_status_t ret = BLK_STS_RESOURCE; 774 int rc; 775 776 if (blk_rq_nr_phys_segments(req) == 1) { 777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 778 struct bio_vec bv = req_bvec(req); 779 780 if (!is_pci_p2pdma_page(bv.bv_page)) { 781 if ((bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) + 782 bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 783 return nvme_setup_prp_simple(dev, req, 784 &cmnd->rw, &bv); 785 786 if (nvmeq->qid && sgl_threshold && 787 nvme_ctrl_sgl_supported(&dev->ctrl)) 788 return nvme_setup_sgl_simple(dev, req, 789 &cmnd->rw, &bv); 790 } 791 } 792 793 iod->dma_len = 0; 794 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 795 if (!iod->sgt.sgl) 796 return BLK_STS_RESOURCE; 797 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 798 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 799 if (!iod->sgt.orig_nents) 800 goto out_free_sg; 801 802 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 803 DMA_ATTR_NO_WARN); 804 if (rc) { 805 if (rc == -EREMOTEIO) 806 ret = BLK_STS_TARGET; 807 goto out_free_sg; 808 } 809 810 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents)) 811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 812 else 813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 814 if (ret != BLK_STS_OK) 815 goto out_unmap_sg; 816 return BLK_STS_OK; 817 818 out_unmap_sg: 819 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 820 out_free_sg: 821 mempool_free(iod->sgt.sgl, dev->iod_mempool); 822 return ret; 823 } 824 825 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 826 struct nvme_command *cmnd) 827 { 828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 829 struct bio_vec bv = rq_integrity_vec(req); 830 831 iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0); 832 if (dma_mapping_error(dev->dev, iod->meta_dma)) 833 return BLK_STS_IOERR; 834 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 835 return BLK_STS_OK; 836 } 837 838 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 839 { 840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 841 blk_status_t ret; 842 843 iod->aborted = false; 844 iod->nr_allocations = -1; 845 iod->sgt.nents = 0; 846 847 ret = nvme_setup_cmd(req->q->queuedata, req); 848 if (ret) 849 return ret; 850 851 if (blk_rq_nr_phys_segments(req)) { 852 ret = nvme_map_data(dev, req, &iod->cmd); 853 if (ret) 854 goto out_free_cmd; 855 } 856 857 if (blk_integrity_rq(req)) { 858 ret = nvme_map_metadata(dev, req, &iod->cmd); 859 if (ret) 860 goto out_unmap_data; 861 } 862 863 nvme_start_request(req); 864 return BLK_STS_OK; 865 out_unmap_data: 866 nvme_unmap_data(dev, req); 867 out_free_cmd: 868 nvme_cleanup_cmd(req); 869 return ret; 870 } 871 872 /* 873 * NOTE: ns is NULL when called on the admin queue. 874 */ 875 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 876 const struct blk_mq_queue_data *bd) 877 { 878 struct nvme_queue *nvmeq = hctx->driver_data; 879 struct nvme_dev *dev = nvmeq->dev; 880 struct request *req = bd->rq; 881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 882 blk_status_t ret; 883 884 /* 885 * We should not need to do this, but we're still using this to 886 * ensure we can drain requests on a dying queue. 887 */ 888 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 889 return BLK_STS_IOERR; 890 891 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 892 return nvme_fail_nonready_command(&dev->ctrl, req); 893 894 ret = nvme_prep_rq(dev, req); 895 if (unlikely(ret)) 896 return ret; 897 spin_lock(&nvmeq->sq_lock); 898 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 899 nvme_write_sq_db(nvmeq, bd->last); 900 spin_unlock(&nvmeq->sq_lock); 901 return BLK_STS_OK; 902 } 903 904 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 905 { 906 spin_lock(&nvmeq->sq_lock); 907 while (!rq_list_empty(*rqlist)) { 908 struct request *req = rq_list_pop(rqlist); 909 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 910 911 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 912 } 913 nvme_write_sq_db(nvmeq, true); 914 spin_unlock(&nvmeq->sq_lock); 915 } 916 917 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 918 { 919 /* 920 * We should not need to do this, but we're still using this to 921 * ensure we can drain requests on a dying queue. 922 */ 923 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 924 return false; 925 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 926 return false; 927 928 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 929 } 930 931 static void nvme_queue_rqs(struct request **rqlist) 932 { 933 struct request *req, *next, *prev = NULL; 934 struct request *requeue_list = NULL; 935 936 rq_list_for_each_safe(rqlist, req, next) { 937 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 938 939 if (!nvme_prep_rq_batch(nvmeq, req)) { 940 /* detach 'req' and add to remainder list */ 941 rq_list_move(rqlist, &requeue_list, req, prev); 942 943 req = prev; 944 if (!req) 945 continue; 946 } 947 948 if (!next || req->mq_hctx != next->mq_hctx) { 949 /* detach rest of list, and submit */ 950 req->rq_next = NULL; 951 nvme_submit_cmds(nvmeq, rqlist); 952 *rqlist = next; 953 prev = NULL; 954 } else 955 prev = req; 956 } 957 958 *rqlist = requeue_list; 959 } 960 961 static __always_inline void nvme_pci_unmap_rq(struct request *req) 962 { 963 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 964 struct nvme_dev *dev = nvmeq->dev; 965 966 if (blk_integrity_rq(req)) { 967 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 968 969 dma_unmap_page(dev->dev, iod->meta_dma, 970 rq_integrity_vec(req).bv_len, rq_dma_dir(req)); 971 } 972 973 if (blk_rq_nr_phys_segments(req)) 974 nvme_unmap_data(dev, req); 975 } 976 977 static void nvme_pci_complete_rq(struct request *req) 978 { 979 nvme_pci_unmap_rq(req); 980 nvme_complete_rq(req); 981 } 982 983 static void nvme_pci_complete_batch(struct io_comp_batch *iob) 984 { 985 nvme_complete_batch(iob, nvme_pci_unmap_rq); 986 } 987 988 /* We read the CQE phase first to check if the rest of the entry is valid */ 989 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 990 { 991 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 992 993 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 994 } 995 996 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 997 { 998 u16 head = nvmeq->cq_head; 999 1000 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1001 nvmeq->dbbuf_cq_ei)) 1002 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1003 } 1004 1005 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1006 { 1007 if (!nvmeq->qid) 1008 return nvmeq->dev->admin_tagset.tags[0]; 1009 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1010 } 1011 1012 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1013 struct io_comp_batch *iob, u16 idx) 1014 { 1015 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1016 __u16 command_id = READ_ONCE(cqe->command_id); 1017 struct request *req; 1018 1019 /* 1020 * AEN requests are special as they don't time out and can 1021 * survive any kind of queue freeze and often don't respond to 1022 * aborts. We don't even bother to allocate a struct request 1023 * for them but rather special case them here. 1024 */ 1025 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1026 nvme_complete_async_event(&nvmeq->dev->ctrl, 1027 cqe->status, &cqe->result); 1028 return; 1029 } 1030 1031 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1032 if (unlikely(!req)) { 1033 dev_warn(nvmeq->dev->ctrl.device, 1034 "invalid id %d completed on queue %d\n", 1035 command_id, le16_to_cpu(cqe->sq_id)); 1036 return; 1037 } 1038 1039 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1040 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1041 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1042 nvme_pci_complete_batch)) 1043 nvme_pci_complete_rq(req); 1044 } 1045 1046 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1047 { 1048 u32 tmp = nvmeq->cq_head + 1; 1049 1050 if (tmp == nvmeq->q_depth) { 1051 nvmeq->cq_head = 0; 1052 nvmeq->cq_phase ^= 1; 1053 } else { 1054 nvmeq->cq_head = tmp; 1055 } 1056 } 1057 1058 static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1059 struct io_comp_batch *iob) 1060 { 1061 int found = 0; 1062 1063 while (nvme_cqe_pending(nvmeq)) { 1064 found++; 1065 /* 1066 * load-load control dependency between phase and the rest of 1067 * the cqe requires a full read memory barrier 1068 */ 1069 dma_rmb(); 1070 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 1071 nvme_update_cq_head(nvmeq); 1072 } 1073 1074 if (found) 1075 nvme_ring_cq_doorbell(nvmeq); 1076 return found; 1077 } 1078 1079 static irqreturn_t nvme_irq(int irq, void *data) 1080 { 1081 struct nvme_queue *nvmeq = data; 1082 DEFINE_IO_COMP_BATCH(iob); 1083 1084 if (nvme_poll_cq(nvmeq, &iob)) { 1085 if (!rq_list_empty(iob.req_list)) 1086 nvme_pci_complete_batch(&iob); 1087 return IRQ_HANDLED; 1088 } 1089 return IRQ_NONE; 1090 } 1091 1092 static irqreturn_t nvme_irq_check(int irq, void *data) 1093 { 1094 struct nvme_queue *nvmeq = data; 1095 1096 if (nvme_cqe_pending(nvmeq)) 1097 return IRQ_WAKE_THREAD; 1098 return IRQ_NONE; 1099 } 1100 1101 /* 1102 * Poll for completions for any interrupt driven queue 1103 * Can be called from any context. 1104 */ 1105 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1106 { 1107 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1108 1109 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1110 1111 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1112 nvme_poll_cq(nvmeq, NULL); 1113 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1114 } 1115 1116 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 1117 { 1118 struct nvme_queue *nvmeq = hctx->driver_data; 1119 bool found; 1120 1121 if (!nvme_cqe_pending(nvmeq)) 1122 return 0; 1123 1124 spin_lock(&nvmeq->cq_poll_lock); 1125 found = nvme_poll_cq(nvmeq, iob); 1126 spin_unlock(&nvmeq->cq_poll_lock); 1127 1128 return found; 1129 } 1130 1131 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1132 { 1133 struct nvme_dev *dev = to_nvme_dev(ctrl); 1134 struct nvme_queue *nvmeq = &dev->queues[0]; 1135 struct nvme_command c = { }; 1136 1137 c.common.opcode = nvme_admin_async_event; 1138 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1139 1140 spin_lock(&nvmeq->sq_lock); 1141 nvme_sq_copy_cmd(nvmeq, &c); 1142 nvme_write_sq_db(nvmeq, true); 1143 spin_unlock(&nvmeq->sq_lock); 1144 } 1145 1146 static int nvme_pci_subsystem_reset(struct nvme_ctrl *ctrl) 1147 { 1148 struct nvme_dev *dev = to_nvme_dev(ctrl); 1149 int ret = 0; 1150 1151 /* 1152 * Taking the shutdown_lock ensures the BAR mapping is not being 1153 * altered by reset_work. Holding this lock before the RESETTING state 1154 * change, if successful, also ensures nvme_remove won't be able to 1155 * proceed to iounmap until we're done. 1156 */ 1157 mutex_lock(&dev->shutdown_lock); 1158 if (!dev->bar_mapped_size) { 1159 ret = -ENODEV; 1160 goto unlock; 1161 } 1162 1163 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) { 1164 ret = -EBUSY; 1165 goto unlock; 1166 } 1167 1168 writel(NVME_SUBSYS_RESET, dev->bar + NVME_REG_NSSR); 1169 nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE); 1170 1171 /* 1172 * Read controller status to flush the previous write and trigger a 1173 * pcie read error. 1174 */ 1175 readl(dev->bar + NVME_REG_CSTS); 1176 unlock: 1177 mutex_unlock(&dev->shutdown_lock); 1178 return ret; 1179 } 1180 1181 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1182 { 1183 struct nvme_command c = { }; 1184 1185 c.delete_queue.opcode = opcode; 1186 c.delete_queue.qid = cpu_to_le16(id); 1187 1188 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1189 } 1190 1191 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1192 struct nvme_queue *nvmeq, s16 vector) 1193 { 1194 struct nvme_command c = { }; 1195 int flags = NVME_QUEUE_PHYS_CONTIG; 1196 1197 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1198 flags |= NVME_CQ_IRQ_ENABLED; 1199 1200 /* 1201 * Note: we (ab)use the fact that the prp fields survive if no data 1202 * is attached to the request. 1203 */ 1204 c.create_cq.opcode = nvme_admin_create_cq; 1205 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1206 c.create_cq.cqid = cpu_to_le16(qid); 1207 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1208 c.create_cq.cq_flags = cpu_to_le16(flags); 1209 c.create_cq.irq_vector = cpu_to_le16(vector); 1210 1211 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1212 } 1213 1214 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1215 struct nvme_queue *nvmeq) 1216 { 1217 struct nvme_ctrl *ctrl = &dev->ctrl; 1218 struct nvme_command c = { }; 1219 int flags = NVME_QUEUE_PHYS_CONTIG; 1220 1221 /* 1222 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1223 * set. Since URGENT priority is zeroes, it makes all queues 1224 * URGENT. 1225 */ 1226 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1227 flags |= NVME_SQ_PRIO_MEDIUM; 1228 1229 /* 1230 * Note: we (ab)use the fact that the prp fields survive if no data 1231 * is attached to the request. 1232 */ 1233 c.create_sq.opcode = nvme_admin_create_sq; 1234 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1235 c.create_sq.sqid = cpu_to_le16(qid); 1236 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1237 c.create_sq.sq_flags = cpu_to_le16(flags); 1238 c.create_sq.cqid = cpu_to_le16(qid); 1239 1240 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1241 } 1242 1243 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1244 { 1245 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1246 } 1247 1248 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1249 { 1250 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1251 } 1252 1253 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 1254 { 1255 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1256 1257 dev_warn(nvmeq->dev->ctrl.device, 1258 "Abort status: 0x%x", nvme_req(req)->status); 1259 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1260 blk_mq_free_request(req); 1261 return RQ_END_IO_NONE; 1262 } 1263 1264 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1265 { 1266 /* If true, indicates loss of adapter communication, possibly by a 1267 * NVMe Subsystem reset. 1268 */ 1269 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1270 1271 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1272 switch (nvme_ctrl_state(&dev->ctrl)) { 1273 case NVME_CTRL_RESETTING: 1274 case NVME_CTRL_CONNECTING: 1275 return false; 1276 default: 1277 break; 1278 } 1279 1280 /* We shouldn't reset unless the controller is on fatal error state 1281 * _or_ if we lost the communication with it. 1282 */ 1283 if (!(csts & NVME_CSTS_CFS) && !nssro) 1284 return false; 1285 1286 return true; 1287 } 1288 1289 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1290 { 1291 /* Read a config register to help see what died. */ 1292 u16 pci_status; 1293 int result; 1294 1295 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1296 &pci_status); 1297 if (result == PCIBIOS_SUCCESSFUL) 1298 dev_warn(dev->ctrl.device, 1299 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1300 csts, pci_status); 1301 else 1302 dev_warn(dev->ctrl.device, 1303 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1304 csts, result); 1305 1306 if (csts != ~0) 1307 return; 1308 1309 dev_warn(dev->ctrl.device, 1310 "Does your device have a faulty power saving mode enabled?\n"); 1311 dev_warn(dev->ctrl.device, 1312 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1313 } 1314 1315 static enum blk_eh_timer_return nvme_timeout(struct request *req) 1316 { 1317 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1318 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1319 struct nvme_dev *dev = nvmeq->dev; 1320 struct request *abort_req; 1321 struct nvme_command cmd = { }; 1322 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1323 u8 opcode; 1324 1325 if (nvme_state_terminal(&dev->ctrl)) 1326 goto disable; 1327 1328 /* If PCI error recovery process is happening, we cannot reset or 1329 * the recovery mechanism will surely fail. 1330 */ 1331 mb(); 1332 if (pci_channel_offline(to_pci_dev(dev->dev))) 1333 return BLK_EH_RESET_TIMER; 1334 1335 /* 1336 * Reset immediately if the controller is failed 1337 */ 1338 if (nvme_should_reset(dev, csts)) { 1339 nvme_warn_reset(dev, csts); 1340 goto disable; 1341 } 1342 1343 /* 1344 * Did we miss an interrupt? 1345 */ 1346 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1347 nvme_poll(req->mq_hctx, NULL); 1348 else 1349 nvme_poll_irqdisable(nvmeq); 1350 1351 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { 1352 dev_warn(dev->ctrl.device, 1353 "I/O tag %d (%04x) QID %d timeout, completion polled\n", 1354 req->tag, nvme_cid(req), nvmeq->qid); 1355 return BLK_EH_DONE; 1356 } 1357 1358 /* 1359 * Shutdown immediately if controller times out while starting. The 1360 * reset work will see the pci device disabled when it gets the forced 1361 * cancellation error. All outstanding requests are completed on 1362 * shutdown, so we return BLK_EH_DONE. 1363 */ 1364 switch (nvme_ctrl_state(&dev->ctrl)) { 1365 case NVME_CTRL_CONNECTING: 1366 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1367 fallthrough; 1368 case NVME_CTRL_DELETING: 1369 dev_warn_ratelimited(dev->ctrl.device, 1370 "I/O tag %d (%04x) QID %d timeout, disable controller\n", 1371 req->tag, nvme_cid(req), nvmeq->qid); 1372 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1373 nvme_dev_disable(dev, true); 1374 return BLK_EH_DONE; 1375 case NVME_CTRL_RESETTING: 1376 return BLK_EH_RESET_TIMER; 1377 default: 1378 break; 1379 } 1380 1381 /* 1382 * Shutdown the controller immediately and schedule a reset if the 1383 * command was already aborted once before and still hasn't been 1384 * returned to the driver, or if this is the admin queue. 1385 */ 1386 opcode = nvme_req(req)->cmd->common.opcode; 1387 if (!nvmeq->qid || iod->aborted) { 1388 dev_warn(dev->ctrl.device, 1389 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n", 1390 req->tag, nvme_cid(req), opcode, 1391 nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid); 1392 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1393 goto disable; 1394 } 1395 1396 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1397 atomic_inc(&dev->ctrl.abort_limit); 1398 return BLK_EH_RESET_TIMER; 1399 } 1400 iod->aborted = true; 1401 1402 cmd.abort.opcode = nvme_admin_abort_cmd; 1403 cmd.abort.cid = nvme_cid(req); 1404 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1405 1406 dev_warn(nvmeq->dev->ctrl.device, 1407 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n", 1408 req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode), 1409 nvmeq->qid, blk_op_str(req_op(req)), req_op(req), 1410 blk_rq_bytes(req)); 1411 1412 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 1413 BLK_MQ_REQ_NOWAIT); 1414 if (IS_ERR(abort_req)) { 1415 atomic_inc(&dev->ctrl.abort_limit); 1416 return BLK_EH_RESET_TIMER; 1417 } 1418 nvme_init_request(abort_req, &cmd); 1419 1420 abort_req->end_io = abort_endio; 1421 abort_req->end_io_data = NULL; 1422 blk_execute_rq_nowait(abort_req, false); 1423 1424 /* 1425 * The aborted req will be completed on receiving the abort req. 1426 * We enable the timer again. If hit twice, it'll cause a device reset, 1427 * as the device then is in a faulty state. 1428 */ 1429 return BLK_EH_RESET_TIMER; 1430 1431 disable: 1432 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { 1433 if (nvme_state_terminal(&dev->ctrl)) 1434 nvme_dev_disable(dev, true); 1435 return BLK_EH_DONE; 1436 } 1437 1438 nvme_dev_disable(dev, false); 1439 if (nvme_try_sched_reset(&dev->ctrl)) 1440 nvme_unquiesce_io_queues(&dev->ctrl); 1441 return BLK_EH_DONE; 1442 } 1443 1444 static void nvme_free_queue(struct nvme_queue *nvmeq) 1445 { 1446 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1447 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1448 if (!nvmeq->sq_cmds) 1449 return; 1450 1451 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1452 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1453 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1454 } else { 1455 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1456 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1457 } 1458 } 1459 1460 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1461 { 1462 int i; 1463 1464 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1465 dev->ctrl.queue_count--; 1466 nvme_free_queue(&dev->queues[i]); 1467 } 1468 } 1469 1470 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid) 1471 { 1472 struct nvme_queue *nvmeq = &dev->queues[qid]; 1473 1474 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1475 return; 1476 1477 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1478 mb(); 1479 1480 nvmeq->dev->online_queues--; 1481 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1482 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 1483 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1484 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); 1485 } 1486 1487 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1488 { 1489 int i; 1490 1491 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1492 nvme_suspend_queue(dev, i); 1493 } 1494 1495 /* 1496 * Called only on a device that has been disabled and after all other threads 1497 * that can check this device's completion queues have synced, except 1498 * nvme_poll(). This is the last chance for the driver to see a natural 1499 * completion before nvme_cancel_request() terminates all incomplete requests. 1500 */ 1501 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1502 { 1503 int i; 1504 1505 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1506 spin_lock(&dev->queues[i].cq_poll_lock); 1507 nvme_poll_cq(&dev->queues[i], NULL); 1508 spin_unlock(&dev->queues[i].cq_poll_lock); 1509 } 1510 } 1511 1512 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1513 int entry_size) 1514 { 1515 int q_depth = dev->q_depth; 1516 unsigned q_size_aligned = roundup(q_depth * entry_size, 1517 NVME_CTRL_PAGE_SIZE); 1518 1519 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1520 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1521 1522 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1523 q_depth = div_u64(mem_per_q, entry_size); 1524 1525 /* 1526 * Ensure the reduced q_depth is above some threshold where it 1527 * would be better to map queues in system memory with the 1528 * original depth 1529 */ 1530 if (q_depth < 64) 1531 return -ENOMEM; 1532 } 1533 1534 return q_depth; 1535 } 1536 1537 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1538 int qid) 1539 { 1540 struct pci_dev *pdev = to_pci_dev(dev->dev); 1541 1542 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1543 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1544 if (nvmeq->sq_cmds) { 1545 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1546 nvmeq->sq_cmds); 1547 if (nvmeq->sq_dma_addr) { 1548 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1549 return 0; 1550 } 1551 1552 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1553 } 1554 } 1555 1556 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1557 &nvmeq->sq_dma_addr, GFP_KERNEL); 1558 if (!nvmeq->sq_cmds) 1559 return -ENOMEM; 1560 return 0; 1561 } 1562 1563 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1564 { 1565 struct nvme_queue *nvmeq = &dev->queues[qid]; 1566 1567 if (dev->ctrl.queue_count > qid) 1568 return 0; 1569 1570 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1571 nvmeq->q_depth = depth; 1572 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1573 &nvmeq->cq_dma_addr, GFP_KERNEL); 1574 if (!nvmeq->cqes) 1575 goto free_nvmeq; 1576 1577 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1578 goto free_cqdma; 1579 1580 nvmeq->dev = dev; 1581 spin_lock_init(&nvmeq->sq_lock); 1582 spin_lock_init(&nvmeq->cq_poll_lock); 1583 nvmeq->cq_head = 0; 1584 nvmeq->cq_phase = 1; 1585 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1586 nvmeq->qid = qid; 1587 dev->ctrl.queue_count++; 1588 1589 return 0; 1590 1591 free_cqdma: 1592 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1593 nvmeq->cq_dma_addr); 1594 free_nvmeq: 1595 return -ENOMEM; 1596 } 1597 1598 static int queue_request_irq(struct nvme_queue *nvmeq) 1599 { 1600 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1601 int nr = nvmeq->dev->ctrl.instance; 1602 1603 if (use_threaded_interrupts) { 1604 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1605 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1606 } else { 1607 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1608 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1609 } 1610 } 1611 1612 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1613 { 1614 struct nvme_dev *dev = nvmeq->dev; 1615 1616 nvmeq->sq_tail = 0; 1617 nvmeq->last_sq_tail = 0; 1618 nvmeq->cq_head = 0; 1619 nvmeq->cq_phase = 1; 1620 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1621 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1622 nvme_dbbuf_init(dev, nvmeq, qid); 1623 dev->online_queues++; 1624 wmb(); /* ensure the first interrupt sees the initialization */ 1625 } 1626 1627 /* 1628 * Try getting shutdown_lock while setting up IO queues. 1629 */ 1630 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1631 { 1632 /* 1633 * Give up if the lock is being held by nvme_dev_disable. 1634 */ 1635 if (!mutex_trylock(&dev->shutdown_lock)) 1636 return -ENODEV; 1637 1638 /* 1639 * Controller is in wrong state, fail early. 1640 */ 1641 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) { 1642 mutex_unlock(&dev->shutdown_lock); 1643 return -ENODEV; 1644 } 1645 1646 return 0; 1647 } 1648 1649 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1650 { 1651 struct nvme_dev *dev = nvmeq->dev; 1652 int result; 1653 u16 vector = 0; 1654 1655 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1656 1657 /* 1658 * A queue's vector matches the queue identifier unless the controller 1659 * has only one vector available. 1660 */ 1661 if (!polled) 1662 vector = dev->num_vecs == 1 ? 0 : qid; 1663 else 1664 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1665 1666 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1667 if (result) 1668 return result; 1669 1670 result = adapter_alloc_sq(dev, qid, nvmeq); 1671 if (result < 0) 1672 return result; 1673 if (result) 1674 goto release_cq; 1675 1676 nvmeq->cq_vector = vector; 1677 1678 result = nvme_setup_io_queues_trylock(dev); 1679 if (result) 1680 return result; 1681 nvme_init_queue(nvmeq, qid); 1682 if (!polled) { 1683 result = queue_request_irq(nvmeq); 1684 if (result < 0) 1685 goto release_sq; 1686 } 1687 1688 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1689 mutex_unlock(&dev->shutdown_lock); 1690 return result; 1691 1692 release_sq: 1693 dev->online_queues--; 1694 mutex_unlock(&dev->shutdown_lock); 1695 adapter_delete_sq(dev, qid); 1696 release_cq: 1697 adapter_delete_cq(dev, qid); 1698 return result; 1699 } 1700 1701 static const struct blk_mq_ops nvme_mq_admin_ops = { 1702 .queue_rq = nvme_queue_rq, 1703 .complete = nvme_pci_complete_rq, 1704 .init_hctx = nvme_admin_init_hctx, 1705 .init_request = nvme_pci_init_request, 1706 .timeout = nvme_timeout, 1707 }; 1708 1709 static const struct blk_mq_ops nvme_mq_ops = { 1710 .queue_rq = nvme_queue_rq, 1711 .queue_rqs = nvme_queue_rqs, 1712 .complete = nvme_pci_complete_rq, 1713 .commit_rqs = nvme_commit_rqs, 1714 .init_hctx = nvme_init_hctx, 1715 .init_request = nvme_pci_init_request, 1716 .map_queues = nvme_pci_map_queues, 1717 .timeout = nvme_timeout, 1718 .poll = nvme_poll, 1719 }; 1720 1721 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1722 { 1723 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1724 /* 1725 * If the controller was reset during removal, it's possible 1726 * user requests may be waiting on a stopped queue. Start the 1727 * queue to flush these to completion. 1728 */ 1729 nvme_unquiesce_admin_queue(&dev->ctrl); 1730 nvme_remove_admin_tag_set(&dev->ctrl); 1731 } 1732 } 1733 1734 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1735 { 1736 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1737 } 1738 1739 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1740 { 1741 struct pci_dev *pdev = to_pci_dev(dev->dev); 1742 1743 if (size <= dev->bar_mapped_size) 1744 return 0; 1745 if (size > pci_resource_len(pdev, 0)) 1746 return -ENOMEM; 1747 if (dev->bar) 1748 iounmap(dev->bar); 1749 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1750 if (!dev->bar) { 1751 dev->bar_mapped_size = 0; 1752 return -ENOMEM; 1753 } 1754 dev->bar_mapped_size = size; 1755 dev->dbs = dev->bar + NVME_REG_DBS; 1756 1757 return 0; 1758 } 1759 1760 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1761 { 1762 int result; 1763 u32 aqa; 1764 struct nvme_queue *nvmeq; 1765 1766 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1767 if (result < 0) 1768 return result; 1769 1770 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1771 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1772 1773 if (dev->subsystem && 1774 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1775 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1776 1777 /* 1778 * If the device has been passed off to us in an enabled state, just 1779 * clear the enabled bit. The spec says we should set the 'shutdown 1780 * notification bits', but doing so may cause the device to complete 1781 * commands to the admin queue ... and we don't know what memory that 1782 * might be pointing at! 1783 */ 1784 result = nvme_disable_ctrl(&dev->ctrl, false); 1785 if (result < 0) 1786 return result; 1787 1788 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1789 if (result) 1790 return result; 1791 1792 dev->ctrl.numa_node = dev_to_node(dev->dev); 1793 1794 nvmeq = &dev->queues[0]; 1795 aqa = nvmeq->q_depth - 1; 1796 aqa |= aqa << 16; 1797 1798 writel(aqa, dev->bar + NVME_REG_AQA); 1799 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1800 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1801 1802 result = nvme_enable_ctrl(&dev->ctrl); 1803 if (result) 1804 return result; 1805 1806 nvmeq->cq_vector = 0; 1807 nvme_init_queue(nvmeq, 0); 1808 result = queue_request_irq(nvmeq); 1809 if (result) { 1810 dev->online_queues--; 1811 return result; 1812 } 1813 1814 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1815 return result; 1816 } 1817 1818 static int nvme_create_io_queues(struct nvme_dev *dev) 1819 { 1820 unsigned i, max, rw_queues; 1821 int ret = 0; 1822 1823 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1824 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1825 ret = -ENOMEM; 1826 break; 1827 } 1828 } 1829 1830 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1831 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1832 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1833 dev->io_queues[HCTX_TYPE_READ]; 1834 } else { 1835 rw_queues = max; 1836 } 1837 1838 for (i = dev->online_queues; i <= max; i++) { 1839 bool polled = i > rw_queues; 1840 1841 ret = nvme_create_queue(&dev->queues[i], i, polled); 1842 if (ret) 1843 break; 1844 } 1845 1846 /* 1847 * Ignore failing Create SQ/CQ commands, we can continue with less 1848 * than the desired amount of queues, and even a controller without 1849 * I/O queues can still be used to issue admin commands. This might 1850 * be useful to upgrade a buggy firmware for example. 1851 */ 1852 return ret >= 0 ? 0 : ret; 1853 } 1854 1855 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1856 { 1857 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1858 1859 return 1ULL << (12 + 4 * szu); 1860 } 1861 1862 static u32 nvme_cmb_size(struct nvme_dev *dev) 1863 { 1864 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1865 } 1866 1867 static void nvme_map_cmb(struct nvme_dev *dev) 1868 { 1869 u64 size, offset; 1870 resource_size_t bar_size; 1871 struct pci_dev *pdev = to_pci_dev(dev->dev); 1872 int bar; 1873 1874 if (dev->cmb_size) 1875 return; 1876 1877 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1878 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1879 1880 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1881 if (!dev->cmbsz) 1882 return; 1883 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1884 1885 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1886 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1887 bar = NVME_CMB_BIR(dev->cmbloc); 1888 bar_size = pci_resource_len(pdev, bar); 1889 1890 if (offset > bar_size) 1891 return; 1892 1893 /* 1894 * Tell the controller about the host side address mapping the CMB, 1895 * and enable CMB decoding for the NVMe 1.4+ scheme: 1896 */ 1897 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1898 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1899 (pci_bus_address(pdev, bar) + offset), 1900 dev->bar + NVME_REG_CMBMSC); 1901 } 1902 1903 /* 1904 * Controllers may support a CMB size larger than their BAR, 1905 * for example, due to being behind a bridge. Reduce the CMB to 1906 * the reported size of the BAR 1907 */ 1908 if (size > bar_size - offset) 1909 size = bar_size - offset; 1910 1911 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1912 dev_warn(dev->ctrl.device, 1913 "failed to register the CMB\n"); 1914 return; 1915 } 1916 1917 dev->cmb_size = size; 1918 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1919 1920 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1921 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1922 pci_p2pmem_publish(pdev, true); 1923 1924 nvme_update_attrs(dev); 1925 } 1926 1927 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1928 { 1929 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1930 u64 dma_addr = dev->host_mem_descs_dma; 1931 struct nvme_command c = { }; 1932 int ret; 1933 1934 c.features.opcode = nvme_admin_set_features; 1935 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1936 c.features.dword11 = cpu_to_le32(bits); 1937 c.features.dword12 = cpu_to_le32(host_mem_size); 1938 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1939 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1940 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1941 1942 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1943 if (ret) { 1944 dev_warn(dev->ctrl.device, 1945 "failed to set host mem (err %d, flags %#x).\n", 1946 ret, bits); 1947 } else 1948 dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1949 1950 return ret; 1951 } 1952 1953 static void nvme_free_host_mem(struct nvme_dev *dev) 1954 { 1955 int i; 1956 1957 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1958 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1959 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 1960 1961 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1962 le64_to_cpu(desc->addr), 1963 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1964 } 1965 1966 kfree(dev->host_mem_desc_bufs); 1967 dev->host_mem_desc_bufs = NULL; 1968 dma_free_coherent(dev->dev, 1969 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1970 dev->host_mem_descs, dev->host_mem_descs_dma); 1971 dev->host_mem_descs = NULL; 1972 dev->nr_host_mem_descs = 0; 1973 } 1974 1975 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1976 u32 chunk_size) 1977 { 1978 struct nvme_host_mem_buf_desc *descs; 1979 u32 max_entries, len; 1980 dma_addr_t descs_dma; 1981 int i = 0; 1982 void **bufs; 1983 u64 size, tmp; 1984 1985 tmp = (preferred + chunk_size - 1); 1986 do_div(tmp, chunk_size); 1987 max_entries = tmp; 1988 1989 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1990 max_entries = dev->ctrl.hmmaxd; 1991 1992 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1993 &descs_dma, GFP_KERNEL); 1994 if (!descs) 1995 goto out; 1996 1997 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1998 if (!bufs) 1999 goto out_free_descs; 2000 2001 for (size = 0; size < preferred && i < max_entries; size += len) { 2002 dma_addr_t dma_addr; 2003 2004 len = min_t(u64, chunk_size, preferred - size); 2005 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 2006 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2007 if (!bufs[i]) 2008 break; 2009 2010 descs[i].addr = cpu_to_le64(dma_addr); 2011 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 2012 i++; 2013 } 2014 2015 if (!size) 2016 goto out_free_bufs; 2017 2018 dev->nr_host_mem_descs = i; 2019 dev->host_mem_size = size; 2020 dev->host_mem_descs = descs; 2021 dev->host_mem_descs_dma = descs_dma; 2022 dev->host_mem_desc_bufs = bufs; 2023 return 0; 2024 2025 out_free_bufs: 2026 while (--i >= 0) { 2027 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 2028 2029 dma_free_attrs(dev->dev, size, bufs[i], 2030 le64_to_cpu(descs[i].addr), 2031 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2032 } 2033 2034 kfree(bufs); 2035 out_free_descs: 2036 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 2037 descs_dma); 2038 out: 2039 dev->host_mem_descs = NULL; 2040 return -ENOMEM; 2041 } 2042 2043 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 2044 { 2045 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 2046 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 2047 u64 chunk_size; 2048 2049 /* start big and work our way down */ 2050 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2051 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2052 if (!min || dev->host_mem_size >= min) 2053 return 0; 2054 nvme_free_host_mem(dev); 2055 } 2056 } 2057 2058 return -ENOMEM; 2059 } 2060 2061 static int nvme_setup_host_mem(struct nvme_dev *dev) 2062 { 2063 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2064 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2065 u64 min = (u64)dev->ctrl.hmmin * 4096; 2066 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2067 int ret; 2068 2069 if (!dev->ctrl.hmpre) 2070 return 0; 2071 2072 preferred = min(preferred, max); 2073 if (min > max) { 2074 dev_warn(dev->ctrl.device, 2075 "min host memory (%lld MiB) above limit (%d MiB).\n", 2076 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2077 nvme_free_host_mem(dev); 2078 return 0; 2079 } 2080 2081 /* 2082 * If we already have a buffer allocated check if we can reuse it. 2083 */ 2084 if (dev->host_mem_descs) { 2085 if (dev->host_mem_size >= min) 2086 enable_bits |= NVME_HOST_MEM_RETURN; 2087 else 2088 nvme_free_host_mem(dev); 2089 } 2090 2091 if (!dev->host_mem_descs) { 2092 if (nvme_alloc_host_mem(dev, min, preferred)) { 2093 dev_warn(dev->ctrl.device, 2094 "failed to allocate host memory buffer.\n"); 2095 return 0; /* controller must work without HMB */ 2096 } 2097 2098 dev_info(dev->ctrl.device, 2099 "allocated %lld MiB host memory buffer.\n", 2100 dev->host_mem_size >> ilog2(SZ_1M)); 2101 } 2102 2103 ret = nvme_set_host_mem(dev, enable_bits); 2104 if (ret) 2105 nvme_free_host_mem(dev); 2106 return ret; 2107 } 2108 2109 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 2110 char *buf) 2111 { 2112 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2113 2114 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 2115 ndev->cmbloc, ndev->cmbsz); 2116 } 2117 static DEVICE_ATTR_RO(cmb); 2118 2119 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 2120 char *buf) 2121 { 2122 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2123 2124 return sysfs_emit(buf, "%u\n", ndev->cmbloc); 2125 } 2126 static DEVICE_ATTR_RO(cmbloc); 2127 2128 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 2129 char *buf) 2130 { 2131 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2132 2133 return sysfs_emit(buf, "%u\n", ndev->cmbsz); 2134 } 2135 static DEVICE_ATTR_RO(cmbsz); 2136 2137 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2138 char *buf) 2139 { 2140 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2141 2142 return sysfs_emit(buf, "%d\n", ndev->hmb); 2143 } 2144 2145 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2146 const char *buf, size_t count) 2147 { 2148 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2149 bool new; 2150 int ret; 2151 2152 if (kstrtobool(buf, &new) < 0) 2153 return -EINVAL; 2154 2155 if (new == ndev->hmb) 2156 return count; 2157 2158 if (new) { 2159 ret = nvme_setup_host_mem(ndev); 2160 } else { 2161 ret = nvme_set_host_mem(ndev, 0); 2162 if (!ret) 2163 nvme_free_host_mem(ndev); 2164 } 2165 2166 if (ret < 0) 2167 return ret; 2168 2169 return count; 2170 } 2171 static DEVICE_ATTR_RW(hmb); 2172 2173 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 2174 struct attribute *a, int n) 2175 { 2176 struct nvme_ctrl *ctrl = 2177 dev_get_drvdata(container_of(kobj, struct device, kobj)); 2178 struct nvme_dev *dev = to_nvme_dev(ctrl); 2179 2180 if (a == &dev_attr_cmb.attr || 2181 a == &dev_attr_cmbloc.attr || 2182 a == &dev_attr_cmbsz.attr) { 2183 if (!dev->cmbsz) 2184 return 0; 2185 } 2186 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2187 return 0; 2188 2189 return a->mode; 2190 } 2191 2192 static struct attribute *nvme_pci_attrs[] = { 2193 &dev_attr_cmb.attr, 2194 &dev_attr_cmbloc.attr, 2195 &dev_attr_cmbsz.attr, 2196 &dev_attr_hmb.attr, 2197 NULL, 2198 }; 2199 2200 static const struct attribute_group nvme_pci_dev_attrs_group = { 2201 .attrs = nvme_pci_attrs, 2202 .is_visible = nvme_pci_attrs_are_visible, 2203 }; 2204 2205 static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 2206 &nvme_dev_attrs_group, 2207 &nvme_pci_dev_attrs_group, 2208 NULL, 2209 }; 2210 2211 static void nvme_update_attrs(struct nvme_dev *dev) 2212 { 2213 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group); 2214 } 2215 2216 /* 2217 * nirqs is the number of interrupts available for write and read 2218 * queues. The core already reserved an interrupt for the admin queue. 2219 */ 2220 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2221 { 2222 struct nvme_dev *dev = affd->priv; 2223 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2224 2225 /* 2226 * If there is no interrupt available for queues, ensure that 2227 * the default queue is set to 1. The affinity set size is 2228 * also set to one, but the irq core ignores it for this case. 2229 * 2230 * If only one interrupt is available or 'write_queue' == 0, combine 2231 * write and read queues. 2232 * 2233 * If 'write_queues' > 0, ensure it leaves room for at least one read 2234 * queue. 2235 */ 2236 if (!nrirqs) { 2237 nrirqs = 1; 2238 nr_read_queues = 0; 2239 } else if (nrirqs == 1 || !nr_write_queues) { 2240 nr_read_queues = 0; 2241 } else if (nr_write_queues >= nrirqs) { 2242 nr_read_queues = 1; 2243 } else { 2244 nr_read_queues = nrirqs - nr_write_queues; 2245 } 2246 2247 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2248 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2249 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2250 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2251 affd->nr_sets = nr_read_queues ? 2 : 1; 2252 } 2253 2254 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2255 { 2256 struct pci_dev *pdev = to_pci_dev(dev->dev); 2257 struct irq_affinity affd = { 2258 .pre_vectors = 1, 2259 .calc_sets = nvme_calc_irq_sets, 2260 .priv = dev, 2261 }; 2262 unsigned int irq_queues, poll_queues; 2263 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY; 2264 2265 /* 2266 * Poll queues don't need interrupts, but we need at least one I/O queue 2267 * left over for non-polled I/O. 2268 */ 2269 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2270 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2271 2272 /* 2273 * Initialize for the single interrupt case, will be updated in 2274 * nvme_calc_irq_sets(). 2275 */ 2276 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2277 dev->io_queues[HCTX_TYPE_READ] = 0; 2278 2279 /* 2280 * We need interrupts for the admin queue and each non-polled I/O queue, 2281 * but some Apple controllers require all queues to use the first 2282 * vector. 2283 */ 2284 irq_queues = 1; 2285 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2286 irq_queues += (nr_io_queues - poll_queues); 2287 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) 2288 flags &= ~PCI_IRQ_MSI; 2289 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags, 2290 &affd); 2291 } 2292 2293 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2294 { 2295 /* 2296 * If tags are shared with admin queue (Apple bug), then 2297 * make sure we only use one IO queue. 2298 */ 2299 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2300 return 1; 2301 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2302 } 2303 2304 static int nvme_setup_io_queues(struct nvme_dev *dev) 2305 { 2306 struct nvme_queue *adminq = &dev->queues[0]; 2307 struct pci_dev *pdev = to_pci_dev(dev->dev); 2308 unsigned int nr_io_queues; 2309 unsigned long size; 2310 int result; 2311 2312 /* 2313 * Sample the module parameters once at reset time so that we have 2314 * stable values to work with. 2315 */ 2316 dev->nr_write_queues = write_queues; 2317 dev->nr_poll_queues = poll_queues; 2318 2319 nr_io_queues = dev->nr_allocated_queues - 1; 2320 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2321 if (result < 0) 2322 return result; 2323 2324 if (nr_io_queues == 0) 2325 return 0; 2326 2327 /* 2328 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2329 * from set to unset. If there is a window to it is truely freed, 2330 * pci_free_irq_vectors() jumping into this window will crash. 2331 * And take lock to avoid racing with pci_free_irq_vectors() in 2332 * nvme_dev_disable() path. 2333 */ 2334 result = nvme_setup_io_queues_trylock(dev); 2335 if (result) 2336 return result; 2337 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2338 pci_free_irq(pdev, 0, adminq); 2339 2340 if (dev->cmb_use_sqes) { 2341 result = nvme_cmb_qdepth(dev, nr_io_queues, 2342 sizeof(struct nvme_command)); 2343 if (result > 0) { 2344 dev->q_depth = result; 2345 dev->ctrl.sqsize = result - 1; 2346 } else { 2347 dev->cmb_use_sqes = false; 2348 } 2349 } 2350 2351 do { 2352 size = db_bar_size(dev, nr_io_queues); 2353 result = nvme_remap_bar(dev, size); 2354 if (!result) 2355 break; 2356 if (!--nr_io_queues) { 2357 result = -ENOMEM; 2358 goto out_unlock; 2359 } 2360 } while (1); 2361 adminq->q_db = dev->dbs; 2362 2363 retry: 2364 /* Deregister the admin queue's interrupt */ 2365 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2366 pci_free_irq(pdev, 0, adminq); 2367 2368 /* 2369 * If we enable msix early due to not intx, disable it again before 2370 * setting up the full range we need. 2371 */ 2372 pci_free_irq_vectors(pdev); 2373 2374 result = nvme_setup_irqs(dev, nr_io_queues); 2375 if (result <= 0) { 2376 result = -EIO; 2377 goto out_unlock; 2378 } 2379 2380 dev->num_vecs = result; 2381 result = max(result - 1, 1); 2382 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2383 2384 /* 2385 * Should investigate if there's a performance win from allocating 2386 * more queues than interrupt vectors; it might allow the submission 2387 * path to scale better, even if the receive path is limited by the 2388 * number of interrupts. 2389 */ 2390 result = queue_request_irq(adminq); 2391 if (result) 2392 goto out_unlock; 2393 set_bit(NVMEQ_ENABLED, &adminq->flags); 2394 mutex_unlock(&dev->shutdown_lock); 2395 2396 result = nvme_create_io_queues(dev); 2397 if (result || dev->online_queues < 2) 2398 return result; 2399 2400 if (dev->online_queues - 1 < dev->max_qid) { 2401 nr_io_queues = dev->online_queues - 1; 2402 nvme_delete_io_queues(dev); 2403 result = nvme_setup_io_queues_trylock(dev); 2404 if (result) 2405 return result; 2406 nvme_suspend_io_queues(dev); 2407 goto retry; 2408 } 2409 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2410 dev->io_queues[HCTX_TYPE_DEFAULT], 2411 dev->io_queues[HCTX_TYPE_READ], 2412 dev->io_queues[HCTX_TYPE_POLL]); 2413 return 0; 2414 out_unlock: 2415 mutex_unlock(&dev->shutdown_lock); 2416 return result; 2417 } 2418 2419 static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2420 blk_status_t error) 2421 { 2422 struct nvme_queue *nvmeq = req->end_io_data; 2423 2424 blk_mq_free_request(req); 2425 complete(&nvmeq->delete_done); 2426 return RQ_END_IO_NONE; 2427 } 2428 2429 static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2430 blk_status_t error) 2431 { 2432 struct nvme_queue *nvmeq = req->end_io_data; 2433 2434 if (error) 2435 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2436 2437 return nvme_del_queue_end(req, error); 2438 } 2439 2440 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2441 { 2442 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2443 struct request *req; 2444 struct nvme_command cmd = { }; 2445 2446 cmd.delete_queue.opcode = opcode; 2447 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2448 2449 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2450 if (IS_ERR(req)) 2451 return PTR_ERR(req); 2452 nvme_init_request(req, &cmd); 2453 2454 if (opcode == nvme_admin_delete_cq) 2455 req->end_io = nvme_del_cq_end; 2456 else 2457 req->end_io = nvme_del_queue_end; 2458 req->end_io_data = nvmeq; 2459 2460 init_completion(&nvmeq->delete_done); 2461 blk_execute_rq_nowait(req, false); 2462 return 0; 2463 } 2464 2465 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode) 2466 { 2467 int nr_queues = dev->online_queues - 1, sent = 0; 2468 unsigned long timeout; 2469 2470 retry: 2471 timeout = NVME_ADMIN_TIMEOUT; 2472 while (nr_queues > 0) { 2473 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2474 break; 2475 nr_queues--; 2476 sent++; 2477 } 2478 while (sent) { 2479 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2480 2481 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2482 timeout); 2483 if (timeout == 0) 2484 return false; 2485 2486 sent--; 2487 if (nr_queues) 2488 goto retry; 2489 } 2490 return true; 2491 } 2492 2493 static void nvme_delete_io_queues(struct nvme_dev *dev) 2494 { 2495 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq)) 2496 __nvme_delete_io_queues(dev, nvme_admin_delete_cq); 2497 } 2498 2499 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev) 2500 { 2501 if (dev->io_queues[HCTX_TYPE_POLL]) 2502 return 3; 2503 if (dev->io_queues[HCTX_TYPE_READ]) 2504 return 2; 2505 return 1; 2506 } 2507 2508 static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 2509 { 2510 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2511 /* free previously allocated queues that are no longer usable */ 2512 nvme_free_queues(dev, dev->online_queues); 2513 } 2514 2515 static int nvme_pci_enable(struct nvme_dev *dev) 2516 { 2517 int result = -ENOMEM; 2518 struct pci_dev *pdev = to_pci_dev(dev->dev); 2519 unsigned int flags = PCI_IRQ_ALL_TYPES; 2520 2521 if (pci_enable_device_mem(pdev)) 2522 return result; 2523 2524 pci_set_master(pdev); 2525 2526 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2527 result = -ENODEV; 2528 goto disable; 2529 } 2530 2531 /* 2532 * Some devices and/or platforms don't advertise or work with INTx 2533 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2534 * adjust this later. 2535 */ 2536 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) 2537 flags &= ~PCI_IRQ_MSI; 2538 result = pci_alloc_irq_vectors(pdev, 1, 1, flags); 2539 if (result < 0) 2540 goto disable; 2541 2542 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2543 2544 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2545 io_queue_depth); 2546 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2547 dev->dbs = dev->bar + 4096; 2548 2549 /* 2550 * Some Apple controllers require a non-standard SQE size. 2551 * Interestingly they also seem to ignore the CC:IOSQES register 2552 * so we don't bother updating it here. 2553 */ 2554 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2555 dev->io_sqes = 7; 2556 else 2557 dev->io_sqes = NVME_NVM_IOSQES; 2558 2559 /* 2560 * Temporary fix for the Apple controller found in the MacBook8,1 and 2561 * some MacBook7,1 to avoid controller resets and data loss. 2562 */ 2563 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2564 dev->q_depth = 2; 2565 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2566 "set queue depth=%u to work around controller resets\n", 2567 dev->q_depth); 2568 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2569 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2570 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2571 dev->q_depth = 64; 2572 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2573 "set queue depth=%u\n", dev->q_depth); 2574 } 2575 2576 /* 2577 * Controllers with the shared tags quirk need the IO queue to be 2578 * big enough so that we get 32 tags for the admin queue 2579 */ 2580 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2581 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2582 dev->q_depth = NVME_AQ_DEPTH + 2; 2583 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2584 dev->q_depth); 2585 } 2586 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2587 2588 nvme_map_cmb(dev); 2589 2590 pci_save_state(pdev); 2591 2592 result = nvme_pci_configure_admin_queue(dev); 2593 if (result) 2594 goto free_irq; 2595 return result; 2596 2597 free_irq: 2598 pci_free_irq_vectors(pdev); 2599 disable: 2600 pci_disable_device(pdev); 2601 return result; 2602 } 2603 2604 static void nvme_dev_unmap(struct nvme_dev *dev) 2605 { 2606 if (dev->bar) 2607 iounmap(dev->bar); 2608 pci_release_mem_regions(to_pci_dev(dev->dev)); 2609 } 2610 2611 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev) 2612 { 2613 struct pci_dev *pdev = to_pci_dev(dev->dev); 2614 u32 csts; 2615 2616 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev)) 2617 return true; 2618 if (pdev->error_state != pci_channel_io_normal) 2619 return true; 2620 2621 csts = readl(dev->bar + NVME_REG_CSTS); 2622 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY); 2623 } 2624 2625 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2626 { 2627 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl); 2628 struct pci_dev *pdev = to_pci_dev(dev->dev); 2629 bool dead; 2630 2631 mutex_lock(&dev->shutdown_lock); 2632 dead = nvme_pci_ctrl_is_dead(dev); 2633 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) { 2634 if (pci_is_enabled(pdev)) 2635 nvme_start_freeze(&dev->ctrl); 2636 /* 2637 * Give the controller a chance to complete all entered requests 2638 * if doing a safe shutdown. 2639 */ 2640 if (!dead && shutdown) 2641 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2642 } 2643 2644 nvme_quiesce_io_queues(&dev->ctrl); 2645 2646 if (!dead && dev->ctrl.queue_count > 0) { 2647 nvme_delete_io_queues(dev); 2648 nvme_disable_ctrl(&dev->ctrl, shutdown); 2649 nvme_poll_irqdisable(&dev->queues[0]); 2650 } 2651 nvme_suspend_io_queues(dev); 2652 nvme_suspend_queue(dev, 0); 2653 pci_free_irq_vectors(pdev); 2654 if (pci_is_enabled(pdev)) 2655 pci_disable_device(pdev); 2656 nvme_reap_pending_cqes(dev); 2657 2658 nvme_cancel_tagset(&dev->ctrl); 2659 nvme_cancel_admin_tagset(&dev->ctrl); 2660 2661 /* 2662 * The driver will not be starting up queues again if shutting down so 2663 * must flush all entered requests to their failed completion to avoid 2664 * deadlocking blk-mq hot-cpu notifier. 2665 */ 2666 if (shutdown) { 2667 nvme_unquiesce_io_queues(&dev->ctrl); 2668 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2669 nvme_unquiesce_admin_queue(&dev->ctrl); 2670 } 2671 mutex_unlock(&dev->shutdown_lock); 2672 } 2673 2674 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2675 { 2676 if (!nvme_wait_reset(&dev->ctrl)) 2677 return -EBUSY; 2678 nvme_dev_disable(dev, shutdown); 2679 return 0; 2680 } 2681 2682 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2683 { 2684 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2685 NVME_CTRL_PAGE_SIZE, 2686 NVME_CTRL_PAGE_SIZE, 0); 2687 if (!dev->prp_page_pool) 2688 return -ENOMEM; 2689 2690 /* Optimisation for I/Os between 4k and 128k */ 2691 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2692 256, 256, 0); 2693 if (!dev->prp_small_pool) { 2694 dma_pool_destroy(dev->prp_page_pool); 2695 return -ENOMEM; 2696 } 2697 return 0; 2698 } 2699 2700 static void nvme_release_prp_pools(struct nvme_dev *dev) 2701 { 2702 dma_pool_destroy(dev->prp_page_pool); 2703 dma_pool_destroy(dev->prp_small_pool); 2704 } 2705 2706 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2707 { 2708 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS; 2709 2710 dev->iod_mempool = mempool_create_node(1, 2711 mempool_kmalloc, mempool_kfree, 2712 (void *)alloc_size, GFP_KERNEL, 2713 dev_to_node(dev->dev)); 2714 if (!dev->iod_mempool) 2715 return -ENOMEM; 2716 return 0; 2717 } 2718 2719 static void nvme_free_tagset(struct nvme_dev *dev) 2720 { 2721 if (dev->tagset.tags) 2722 nvme_remove_io_tag_set(&dev->ctrl); 2723 dev->ctrl.tagset = NULL; 2724 } 2725 2726 /* pairs with nvme_pci_alloc_dev */ 2727 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2728 { 2729 struct nvme_dev *dev = to_nvme_dev(ctrl); 2730 2731 nvme_free_tagset(dev); 2732 put_device(dev->dev); 2733 kfree(dev->queues); 2734 kfree(dev); 2735 } 2736 2737 static void nvme_reset_work(struct work_struct *work) 2738 { 2739 struct nvme_dev *dev = 2740 container_of(work, struct nvme_dev, ctrl.reset_work); 2741 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2742 int result; 2743 2744 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) { 2745 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2746 dev->ctrl.state); 2747 result = -ENODEV; 2748 goto out; 2749 } 2750 2751 /* 2752 * If we're called to reset a live controller first shut it down before 2753 * moving on. 2754 */ 2755 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2756 nvme_dev_disable(dev, false); 2757 nvme_sync_queues(&dev->ctrl); 2758 2759 mutex_lock(&dev->shutdown_lock); 2760 result = nvme_pci_enable(dev); 2761 if (result) 2762 goto out_unlock; 2763 nvme_unquiesce_admin_queue(&dev->ctrl); 2764 mutex_unlock(&dev->shutdown_lock); 2765 2766 /* 2767 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2768 * initializing procedure here. 2769 */ 2770 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2771 dev_warn(dev->ctrl.device, 2772 "failed to mark controller CONNECTING\n"); 2773 result = -EBUSY; 2774 goto out; 2775 } 2776 2777 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2778 if (result) 2779 goto out; 2780 2781 nvme_dbbuf_dma_alloc(dev); 2782 2783 result = nvme_setup_host_mem(dev); 2784 if (result < 0) 2785 goto out; 2786 2787 result = nvme_setup_io_queues(dev); 2788 if (result) 2789 goto out; 2790 2791 /* 2792 * Freeze and update the number of I/O queues as thos might have 2793 * changed. If there are no I/O queues left after this reset, keep the 2794 * controller around but remove all namespaces. 2795 */ 2796 if (dev->online_queues > 1) { 2797 nvme_dbbuf_set(dev); 2798 nvme_unquiesce_io_queues(&dev->ctrl); 2799 nvme_wait_freeze(&dev->ctrl); 2800 nvme_pci_update_nr_queues(dev); 2801 nvme_unfreeze(&dev->ctrl); 2802 } else { 2803 dev_warn(dev->ctrl.device, "IO queues lost\n"); 2804 nvme_mark_namespaces_dead(&dev->ctrl); 2805 nvme_unquiesce_io_queues(&dev->ctrl); 2806 nvme_remove_namespaces(&dev->ctrl); 2807 nvme_free_tagset(dev); 2808 } 2809 2810 /* 2811 * If only admin queue live, keep it to do further investigation or 2812 * recovery. 2813 */ 2814 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2815 dev_warn(dev->ctrl.device, 2816 "failed to mark controller live state\n"); 2817 result = -ENODEV; 2818 goto out; 2819 } 2820 2821 nvme_start_ctrl(&dev->ctrl); 2822 return; 2823 2824 out_unlock: 2825 mutex_unlock(&dev->shutdown_lock); 2826 out: 2827 /* 2828 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2829 * may be holding this pci_dev's device lock. 2830 */ 2831 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2832 result); 2833 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2834 nvme_dev_disable(dev, true); 2835 nvme_sync_queues(&dev->ctrl); 2836 nvme_mark_namespaces_dead(&dev->ctrl); 2837 nvme_unquiesce_io_queues(&dev->ctrl); 2838 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2839 } 2840 2841 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2842 { 2843 *val = readl(to_nvme_dev(ctrl)->bar + off); 2844 return 0; 2845 } 2846 2847 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2848 { 2849 writel(val, to_nvme_dev(ctrl)->bar + off); 2850 return 0; 2851 } 2852 2853 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2854 { 2855 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2856 return 0; 2857 } 2858 2859 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2860 { 2861 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2862 2863 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2864 } 2865 2866 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 2867 { 2868 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2869 struct nvme_subsystem *subsys = ctrl->subsys; 2870 2871 dev_err(ctrl->device, 2872 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 2873 pdev->vendor, pdev->device, 2874 nvme_strlen(subsys->model, sizeof(subsys->model)), 2875 subsys->model, nvme_strlen(subsys->firmware_rev, 2876 sizeof(subsys->firmware_rev)), 2877 subsys->firmware_rev); 2878 } 2879 2880 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 2881 { 2882 struct nvme_dev *dev = to_nvme_dev(ctrl); 2883 2884 return dma_pci_p2pdma_supported(dev->dev); 2885 } 2886 2887 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2888 .name = "pcie", 2889 .module = THIS_MODULE, 2890 .flags = NVME_F_METADATA_SUPPORTED, 2891 .dev_attr_groups = nvme_pci_dev_attr_groups, 2892 .reg_read32 = nvme_pci_reg_read32, 2893 .reg_write32 = nvme_pci_reg_write32, 2894 .reg_read64 = nvme_pci_reg_read64, 2895 .free_ctrl = nvme_pci_free_ctrl, 2896 .submit_async_event = nvme_pci_submit_async_event, 2897 .subsystem_reset = nvme_pci_subsystem_reset, 2898 .get_address = nvme_pci_get_address, 2899 .print_device_info = nvme_pci_print_device_info, 2900 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 2901 }; 2902 2903 static int nvme_dev_map(struct nvme_dev *dev) 2904 { 2905 struct pci_dev *pdev = to_pci_dev(dev->dev); 2906 2907 if (pci_request_mem_regions(pdev, "nvme")) 2908 return -ENODEV; 2909 2910 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2911 goto release; 2912 2913 return 0; 2914 release: 2915 pci_release_mem_regions(pdev); 2916 return -ENODEV; 2917 } 2918 2919 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2920 { 2921 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2922 /* 2923 * Several Samsung devices seem to drop off the PCIe bus 2924 * randomly when APST is on and uses the deepest sleep state. 2925 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2926 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2927 * 950 PRO 256GB", but it seems to be restricted to two Dell 2928 * laptops. 2929 */ 2930 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2931 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2932 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2933 return NVME_QUIRK_NO_DEEPEST_PS; 2934 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2935 /* 2936 * Samsung SSD 960 EVO drops off the PCIe bus after system 2937 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2938 * within few minutes after bootup on a Coffee Lake board - 2939 * ASUS PRIME Z370-A 2940 */ 2941 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2942 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2943 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2944 return NVME_QUIRK_NO_APST; 2945 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2946 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2947 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2948 /* 2949 * Forcing to use host managed nvme power settings for 2950 * lowest idle power with quick resume latency on 2951 * Samsung and Toshiba SSDs based on suspend behavior 2952 * on Coffee Lake board for LENOVO C640 2953 */ 2954 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2955 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2956 return NVME_QUIRK_SIMPLE_SUSPEND; 2957 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 || 2958 pdev->device == 0x500f)) { 2959 /* 2960 * Exclude some Kingston NV1 and A2000 devices from 2961 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a 2962 * lot fo energy with s2idle sleep on some TUXEDO platforms. 2963 */ 2964 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") || 2965 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") || 2966 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") || 2967 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1")) 2968 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND; 2969 } 2970 2971 return 0; 2972 } 2973 2974 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 2975 const struct pci_device_id *id) 2976 { 2977 unsigned long quirks = id->driver_data; 2978 int node = dev_to_node(&pdev->dev); 2979 struct nvme_dev *dev; 2980 int ret = -ENOMEM; 2981 2982 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2983 if (!dev) 2984 return ERR_PTR(-ENOMEM); 2985 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2986 mutex_init(&dev->shutdown_lock); 2987 2988 dev->nr_write_queues = write_queues; 2989 dev->nr_poll_queues = poll_queues; 2990 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 2991 dev->queues = kcalloc_node(dev->nr_allocated_queues, 2992 sizeof(struct nvme_queue), GFP_KERNEL, node); 2993 if (!dev->queues) 2994 goto out_free_dev; 2995 2996 dev->dev = get_device(&pdev->dev); 2997 2998 quirks |= check_vendor_combination_bug(pdev); 2999 if (!noacpi && 3000 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) && 3001 acpi_storage_d3(&pdev->dev)) { 3002 /* 3003 * Some systems use a bios work around to ask for D3 on 3004 * platforms that support kernel managed suspend. 3005 */ 3006 dev_info(&pdev->dev, 3007 "platform quirk: setting simple suspend\n"); 3008 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3009 } 3010 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3011 quirks); 3012 if (ret) 3013 goto out_put_device; 3014 3015 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 3016 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)); 3017 else 3018 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3019 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 3020 dma_set_max_seg_size(&pdev->dev, 0xffffffff); 3021 3022 /* 3023 * Limit the max command size to prevent iod->sg allocations going 3024 * over a single page. 3025 */ 3026 dev->ctrl.max_hw_sectors = min_t(u32, 3027 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9); 3028 dev->ctrl.max_segments = NVME_MAX_SEGS; 3029 3030 /* 3031 * There is no support for SGLs for metadata (yet), so we are limited to 3032 * a single integrity segment for the separate metadata pointer. 3033 */ 3034 dev->ctrl.max_integrity_segments = 1; 3035 return dev; 3036 3037 out_put_device: 3038 put_device(dev->dev); 3039 kfree(dev->queues); 3040 out_free_dev: 3041 kfree(dev); 3042 return ERR_PTR(ret); 3043 } 3044 3045 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3046 { 3047 struct nvme_dev *dev; 3048 int result = -ENOMEM; 3049 3050 dev = nvme_pci_alloc_dev(pdev, id); 3051 if (IS_ERR(dev)) 3052 return PTR_ERR(dev); 3053 3054 result = nvme_add_ctrl(&dev->ctrl); 3055 if (result) 3056 goto out_put_ctrl; 3057 3058 result = nvme_dev_map(dev); 3059 if (result) 3060 goto out_uninit_ctrl; 3061 3062 result = nvme_setup_prp_pools(dev); 3063 if (result) 3064 goto out_dev_unmap; 3065 3066 result = nvme_pci_alloc_iod_mempool(dev); 3067 if (result) 3068 goto out_release_prp_pools; 3069 3070 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3071 3072 result = nvme_pci_enable(dev); 3073 if (result) 3074 goto out_release_iod_mempool; 3075 3076 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset, 3077 &nvme_mq_admin_ops, sizeof(struct nvme_iod)); 3078 if (result) 3079 goto out_disable; 3080 3081 /* 3082 * Mark the controller as connecting before sending admin commands to 3083 * allow the timeout handler to do the right thing. 3084 */ 3085 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3086 dev_warn(dev->ctrl.device, 3087 "failed to mark controller CONNECTING\n"); 3088 result = -EBUSY; 3089 goto out_disable; 3090 } 3091 3092 result = nvme_init_ctrl_finish(&dev->ctrl, false); 3093 if (result) 3094 goto out_disable; 3095 3096 nvme_dbbuf_dma_alloc(dev); 3097 3098 result = nvme_setup_host_mem(dev); 3099 if (result < 0) 3100 goto out_disable; 3101 3102 result = nvme_setup_io_queues(dev); 3103 if (result) 3104 goto out_disable; 3105 3106 if (dev->online_queues > 1) { 3107 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, 3108 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod)); 3109 nvme_dbbuf_set(dev); 3110 } 3111 3112 if (!dev->ctrl.tagset) 3113 dev_warn(dev->ctrl.device, "IO queues not created\n"); 3114 3115 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3116 dev_warn(dev->ctrl.device, 3117 "failed to mark controller live state\n"); 3118 result = -ENODEV; 3119 goto out_disable; 3120 } 3121 3122 pci_set_drvdata(pdev, dev); 3123 3124 nvme_start_ctrl(&dev->ctrl); 3125 nvme_put_ctrl(&dev->ctrl); 3126 flush_work(&dev->ctrl.scan_work); 3127 return 0; 3128 3129 out_disable: 3130 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3131 nvme_dev_disable(dev, true); 3132 nvme_free_host_mem(dev); 3133 nvme_dev_remove_admin(dev); 3134 nvme_dbbuf_dma_free(dev); 3135 nvme_free_queues(dev, 0); 3136 out_release_iod_mempool: 3137 mempool_destroy(dev->iod_mempool); 3138 out_release_prp_pools: 3139 nvme_release_prp_pools(dev); 3140 out_dev_unmap: 3141 nvme_dev_unmap(dev); 3142 out_uninit_ctrl: 3143 nvme_uninit_ctrl(&dev->ctrl); 3144 out_put_ctrl: 3145 nvme_put_ctrl(&dev->ctrl); 3146 return result; 3147 } 3148 3149 static void nvme_reset_prepare(struct pci_dev *pdev) 3150 { 3151 struct nvme_dev *dev = pci_get_drvdata(pdev); 3152 3153 /* 3154 * We don't need to check the return value from waiting for the reset 3155 * state as pci_dev device lock is held, making it impossible to race 3156 * with ->remove(). 3157 */ 3158 nvme_disable_prepare_reset(dev, false); 3159 nvme_sync_queues(&dev->ctrl); 3160 } 3161 3162 static void nvme_reset_done(struct pci_dev *pdev) 3163 { 3164 struct nvme_dev *dev = pci_get_drvdata(pdev); 3165 3166 if (!nvme_try_sched_reset(&dev->ctrl)) 3167 flush_work(&dev->ctrl.reset_work); 3168 } 3169 3170 static void nvme_shutdown(struct pci_dev *pdev) 3171 { 3172 struct nvme_dev *dev = pci_get_drvdata(pdev); 3173 3174 nvme_disable_prepare_reset(dev, true); 3175 } 3176 3177 /* 3178 * The driver's remove may be called on a device in a partially initialized 3179 * state. This function must not have any dependencies on the device state in 3180 * order to proceed. 3181 */ 3182 static void nvme_remove(struct pci_dev *pdev) 3183 { 3184 struct nvme_dev *dev = pci_get_drvdata(pdev); 3185 3186 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3187 pci_set_drvdata(pdev, NULL); 3188 3189 if (!pci_device_is_present(pdev)) { 3190 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 3191 nvme_dev_disable(dev, true); 3192 } 3193 3194 flush_work(&dev->ctrl.reset_work); 3195 nvme_stop_ctrl(&dev->ctrl); 3196 nvme_remove_namespaces(&dev->ctrl); 3197 nvme_dev_disable(dev, true); 3198 nvme_free_host_mem(dev); 3199 nvme_dev_remove_admin(dev); 3200 nvme_dbbuf_dma_free(dev); 3201 nvme_free_queues(dev, 0); 3202 mempool_destroy(dev->iod_mempool); 3203 nvme_release_prp_pools(dev); 3204 nvme_dev_unmap(dev); 3205 nvme_uninit_ctrl(&dev->ctrl); 3206 } 3207 3208 #ifdef CONFIG_PM_SLEEP 3209 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3210 { 3211 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3212 } 3213 3214 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3215 { 3216 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3217 } 3218 3219 static int nvme_resume(struct device *dev) 3220 { 3221 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3222 struct nvme_ctrl *ctrl = &ndev->ctrl; 3223 3224 if (ndev->last_ps == U32_MAX || 3225 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3226 goto reset; 3227 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3228 goto reset; 3229 3230 return 0; 3231 reset: 3232 return nvme_try_sched_reset(ctrl); 3233 } 3234 3235 static int nvme_suspend(struct device *dev) 3236 { 3237 struct pci_dev *pdev = to_pci_dev(dev); 3238 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3239 struct nvme_ctrl *ctrl = &ndev->ctrl; 3240 int ret = -EBUSY; 3241 3242 ndev->last_ps = U32_MAX; 3243 3244 /* 3245 * The platform does not remove power for a kernel managed suspend so 3246 * use host managed nvme power settings for lowest idle power if 3247 * possible. This should have quicker resume latency than a full device 3248 * shutdown. But if the firmware is involved after the suspend or the 3249 * device does not support any non-default power states, shut down the 3250 * device fully. 3251 * 3252 * If ASPM is not enabled for the device, shut down the device and allow 3253 * the PCI bus layer to put it into D3 in order to take the PCIe link 3254 * down, so as to allow the platform to achieve its minimum low-power 3255 * state (which may not be possible if the link is up). 3256 */ 3257 if (pm_suspend_via_firmware() || !ctrl->npss || 3258 !pcie_aspm_enabled(pdev) || 3259 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3260 return nvme_disable_prepare_reset(ndev, true); 3261 3262 nvme_start_freeze(ctrl); 3263 nvme_wait_freeze(ctrl); 3264 nvme_sync_queues(ctrl); 3265 3266 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE) 3267 goto unfreeze; 3268 3269 /* 3270 * Host memory access may not be successful in a system suspend state, 3271 * but the specification allows the controller to access memory in a 3272 * non-operational power state. 3273 */ 3274 if (ndev->hmb) { 3275 ret = nvme_set_host_mem(ndev, 0); 3276 if (ret < 0) 3277 goto unfreeze; 3278 } 3279 3280 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3281 if (ret < 0) 3282 goto unfreeze; 3283 3284 /* 3285 * A saved state prevents pci pm from generically controlling the 3286 * device's power. If we're using protocol specific settings, we don't 3287 * want pci interfering. 3288 */ 3289 pci_save_state(pdev); 3290 3291 ret = nvme_set_power_state(ctrl, ctrl->npss); 3292 if (ret < 0) 3293 goto unfreeze; 3294 3295 if (ret) { 3296 /* discard the saved state */ 3297 pci_load_saved_state(pdev, NULL); 3298 3299 /* 3300 * Clearing npss forces a controller reset on resume. The 3301 * correct value will be rediscovered then. 3302 */ 3303 ret = nvme_disable_prepare_reset(ndev, true); 3304 ctrl->npss = 0; 3305 } 3306 unfreeze: 3307 nvme_unfreeze(ctrl); 3308 return ret; 3309 } 3310 3311 static int nvme_simple_suspend(struct device *dev) 3312 { 3313 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3314 3315 return nvme_disable_prepare_reset(ndev, true); 3316 } 3317 3318 static int nvme_simple_resume(struct device *dev) 3319 { 3320 struct pci_dev *pdev = to_pci_dev(dev); 3321 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3322 3323 return nvme_try_sched_reset(&ndev->ctrl); 3324 } 3325 3326 static const struct dev_pm_ops nvme_dev_pm_ops = { 3327 .suspend = nvme_suspend, 3328 .resume = nvme_resume, 3329 .freeze = nvme_simple_suspend, 3330 .thaw = nvme_simple_resume, 3331 .poweroff = nvme_simple_suspend, 3332 .restore = nvme_simple_resume, 3333 }; 3334 #endif /* CONFIG_PM_SLEEP */ 3335 3336 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3337 pci_channel_state_t state) 3338 { 3339 struct nvme_dev *dev = pci_get_drvdata(pdev); 3340 3341 /* 3342 * A frozen channel requires a reset. When detected, this method will 3343 * shutdown the controller to quiesce. The controller will be restarted 3344 * after the slot reset through driver's slot_reset callback. 3345 */ 3346 switch (state) { 3347 case pci_channel_io_normal: 3348 return PCI_ERS_RESULT_CAN_RECOVER; 3349 case pci_channel_io_frozen: 3350 dev_warn(dev->ctrl.device, 3351 "frozen state error detected, reset controller\n"); 3352 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { 3353 nvme_dev_disable(dev, true); 3354 return PCI_ERS_RESULT_DISCONNECT; 3355 } 3356 nvme_dev_disable(dev, false); 3357 return PCI_ERS_RESULT_NEED_RESET; 3358 case pci_channel_io_perm_failure: 3359 dev_warn(dev->ctrl.device, 3360 "failure state error detected, request disconnect\n"); 3361 return PCI_ERS_RESULT_DISCONNECT; 3362 } 3363 return PCI_ERS_RESULT_NEED_RESET; 3364 } 3365 3366 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3367 { 3368 struct nvme_dev *dev = pci_get_drvdata(pdev); 3369 3370 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3371 pci_restore_state(pdev); 3372 if (!nvme_try_sched_reset(&dev->ctrl)) 3373 nvme_unquiesce_io_queues(&dev->ctrl); 3374 return PCI_ERS_RESULT_RECOVERED; 3375 } 3376 3377 static void nvme_error_resume(struct pci_dev *pdev) 3378 { 3379 struct nvme_dev *dev = pci_get_drvdata(pdev); 3380 3381 flush_work(&dev->ctrl.reset_work); 3382 } 3383 3384 static const struct pci_error_handlers nvme_err_handler = { 3385 .error_detected = nvme_error_detected, 3386 .slot_reset = nvme_slot_reset, 3387 .resume = nvme_error_resume, 3388 .reset_prepare = nvme_reset_prepare, 3389 .reset_done = nvme_reset_done, 3390 }; 3391 3392 static const struct pci_device_id nvme_id_table[] = { 3393 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3394 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3395 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3396 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3397 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3398 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3399 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3400 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3401 NVME_QUIRK_DEALLOCATE_ZEROES | 3402 NVME_QUIRK_IGNORE_DEV_SUBNQN | 3403 NVME_QUIRK_BOGUS_NID, }, 3404 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3405 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3406 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3407 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3408 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3409 NVME_QUIRK_MEDIUM_PRIO_SQ | 3410 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3411 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3412 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3413 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3414 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3415 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3416 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3417 NVME_QUIRK_BOGUS_NID, }, 3418 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3419 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3420 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */ 3421 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3422 NVME_QUIRK_BOGUS_NID, }, 3423 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3424 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3425 NVME_QUIRK_BOGUS_NID, }, 3426 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3427 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3428 NVME_QUIRK_NO_NS_DESC_LIST, }, 3429 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3430 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3431 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3432 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3433 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3434 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3435 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3436 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3437 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3438 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3439 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3440 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3441 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */ 3442 .driver_data = NVME_QUIRK_BROKEN_MSI }, 3443 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 3444 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3445 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3446 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3447 NVME_QUIRK_BOGUS_NID, }, 3448 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3449 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3450 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3451 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3452 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3453 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3454 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3455 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3456 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3457 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3458 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3459 NVME_QUIRK_BOGUS_NID, }, 3460 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */ 3461 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3462 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3463 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3464 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3465 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3466 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3467 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3468 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3469 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3470 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3471 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3472 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3473 { PCI_DEVICE(0x1c5c, 0x1D59), /* SK Hynix BC901 */ 3474 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3475 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3476 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3477 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3478 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3479 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 3480 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES | 3481 NVME_QUIRK_BOGUS_NID, }, 3482 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 3483 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3484 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */ 3485 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3486 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 3487 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3488 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 3489 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3490 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3491 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3492 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3493 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3494 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */ 3495 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, }, 3496 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3498 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3499 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3500 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3501 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3502 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3504 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3505 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3506 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */ 3507 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3508 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */ 3509 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3510 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3511 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3512 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3513 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3514 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3515 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3516 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */ 3517 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3518 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 3519 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3520 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3521 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3522 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3523 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3524 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 3525 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3526 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3527 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3528 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3529 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3530 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */ 3531 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3532 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 3533 .driver_data = NVME_QUIRK_BOGUS_NID | 3534 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3535 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */ 3536 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3537 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */ 3538 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3539 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */ 3540 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3541 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3542 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3543 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3544 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3545 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3546 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3547 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3548 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3549 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3550 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3551 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3552 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3553 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3554 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3555 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3556 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3557 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3558 NVME_QUIRK_128_BYTES_SQES | 3559 NVME_QUIRK_SHARED_TAGS | 3560 NVME_QUIRK_SKIP_CID_GEN | 3561 NVME_QUIRK_IDENTIFY_CNS }, 3562 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3563 { 0, } 3564 }; 3565 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3566 3567 static struct pci_driver nvme_driver = { 3568 .name = "nvme", 3569 .id_table = nvme_id_table, 3570 .probe = nvme_probe, 3571 .remove = nvme_remove, 3572 .shutdown = nvme_shutdown, 3573 .driver = { 3574 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3575 #ifdef CONFIG_PM_SLEEP 3576 .pm = &nvme_dev_pm_ops, 3577 #endif 3578 }, 3579 .sriov_configure = pci_sriov_configure_simple, 3580 .err_handler = &nvme_err_handler, 3581 }; 3582 3583 static int __init nvme_init(void) 3584 { 3585 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3586 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3587 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3588 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3589 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE); 3590 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE); 3591 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS); 3592 3593 return pci_register_driver(&nvme_driver); 3594 } 3595 3596 static void __exit nvme_exit(void) 3597 { 3598 pci_unregister_driver(&nvme_driver); 3599 flush_workqueue(nvme_wq); 3600 } 3601 3602 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3603 MODULE_LICENSE("GPL"); 3604 MODULE_VERSION("1.0"); 3605 MODULE_DESCRIPTION("NVMe host PCIe transport driver"); 3606 module_init(nvme_init); 3607 module_exit(nvme_exit); 3608