1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/t10-pi.h> 22 #include <linux/types.h> 23 #include <linux/io-64-nonatomic-lo-hi.h> 24 #include <linux/sed-opal.h> 25 #include <linux/pci-p2pdma.h> 26 27 #include "trace.h" 28 #include "nvme.h" 29 30 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 31 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 32 33 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 34 35 /* 36 * These can be higher, but we need to ensure that any command doesn't 37 * require an sg allocation that needs more than a page of data. 38 */ 39 #define NVME_MAX_KB_SZ 4096 40 #define NVME_MAX_SEGS 127 41 42 static int use_threaded_interrupts; 43 module_param(use_threaded_interrupts, int, 0); 44 45 static bool use_cmb_sqes = true; 46 module_param(use_cmb_sqes, bool, 0444); 47 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 48 49 static unsigned int max_host_mem_size_mb = 128; 50 module_param(max_host_mem_size_mb, uint, 0444); 51 MODULE_PARM_DESC(max_host_mem_size_mb, 52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 53 54 static unsigned int sgl_threshold = SZ_32K; 55 module_param(sgl_threshold, uint, 0644); 56 MODULE_PARM_DESC(sgl_threshold, 57 "Use SGLs when average request segment size is larger or equal to " 58 "this size. Use 0 to disable SGLs."); 59 60 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 61 static const struct kernel_param_ops io_queue_depth_ops = { 62 .set = io_queue_depth_set, 63 .get = param_get_int, 64 }; 65 66 static int io_queue_depth = 1024; 67 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 68 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 69 70 static int queue_count_set(const char *val, const struct kernel_param *kp); 71 static const struct kernel_param_ops queue_count_ops = { 72 .set = queue_count_set, 73 .get = param_get_int, 74 }; 75 76 static int write_queues; 77 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 78 MODULE_PARM_DESC(write_queues, 79 "Number of queues to use for writes. If not set, reads and writes " 80 "will share a queue set."); 81 82 static int poll_queues = 0; 83 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 84 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 85 86 struct nvme_dev; 87 struct nvme_queue; 88 89 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 90 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 91 92 /* 93 * Represents an NVM Express device. Each nvme_dev is a PCI function. 94 */ 95 struct nvme_dev { 96 struct nvme_queue *queues; 97 struct blk_mq_tag_set tagset; 98 struct blk_mq_tag_set admin_tagset; 99 u32 __iomem *dbs; 100 struct device *dev; 101 struct dma_pool *prp_page_pool; 102 struct dma_pool *prp_small_pool; 103 unsigned online_queues; 104 unsigned max_qid; 105 unsigned io_queues[HCTX_MAX_TYPES]; 106 unsigned int num_vecs; 107 int q_depth; 108 u32 db_stride; 109 void __iomem *bar; 110 unsigned long bar_mapped_size; 111 struct work_struct remove_work; 112 struct mutex shutdown_lock; 113 bool subsystem; 114 u64 cmb_size; 115 bool cmb_use_sqes; 116 u32 cmbsz; 117 u32 cmbloc; 118 struct nvme_ctrl ctrl; 119 120 mempool_t *iod_mempool; 121 122 /* shadow doorbell buffer support: */ 123 u32 *dbbuf_dbs; 124 dma_addr_t dbbuf_dbs_dma_addr; 125 u32 *dbbuf_eis; 126 dma_addr_t dbbuf_eis_dma_addr; 127 128 /* host memory buffer support: */ 129 u64 host_mem_size; 130 u32 nr_host_mem_descs; 131 dma_addr_t host_mem_descs_dma; 132 struct nvme_host_mem_buf_desc *host_mem_descs; 133 void **host_mem_desc_bufs; 134 }; 135 136 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 137 { 138 int n = 0, ret; 139 140 ret = kstrtoint(val, 10, &n); 141 if (ret != 0 || n < 2) 142 return -EINVAL; 143 144 return param_set_int(val, kp); 145 } 146 147 static int queue_count_set(const char *val, const struct kernel_param *kp) 148 { 149 int n, ret; 150 151 ret = kstrtoint(val, 10, &n); 152 if (ret) 153 return ret; 154 if (n > num_possible_cpus()) 155 n = num_possible_cpus(); 156 157 return param_set_int(val, kp); 158 } 159 160 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 161 { 162 return qid * 2 * stride; 163 } 164 165 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 166 { 167 return (qid * 2 + 1) * stride; 168 } 169 170 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 171 { 172 return container_of(ctrl, struct nvme_dev, ctrl); 173 } 174 175 /* 176 * An NVM Express queue. Each device has at least two (one for admin 177 * commands and one for I/O commands). 178 */ 179 struct nvme_queue { 180 struct nvme_dev *dev; 181 spinlock_t sq_lock; 182 struct nvme_command *sq_cmds; 183 /* only used for poll queues: */ 184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 185 volatile struct nvme_completion *cqes; 186 struct blk_mq_tags **tags; 187 dma_addr_t sq_dma_addr; 188 dma_addr_t cq_dma_addr; 189 u32 __iomem *q_db; 190 u16 q_depth; 191 u16 cq_vector; 192 u16 sq_tail; 193 u16 last_sq_tail; 194 u16 cq_head; 195 u16 last_cq_head; 196 u16 qid; 197 u8 cq_phase; 198 unsigned long flags; 199 #define NVMEQ_ENABLED 0 200 #define NVMEQ_SQ_CMB 1 201 #define NVMEQ_DELETE_ERROR 2 202 #define NVMEQ_POLLED 3 203 u32 *dbbuf_sq_db; 204 u32 *dbbuf_cq_db; 205 u32 *dbbuf_sq_ei; 206 u32 *dbbuf_cq_ei; 207 struct completion delete_done; 208 }; 209 210 /* 211 * The nvme_iod describes the data in an I/O. 212 * 213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 214 * to the actual struct scatterlist. 215 */ 216 struct nvme_iod { 217 struct nvme_request req; 218 struct nvme_queue *nvmeq; 219 bool use_sgl; 220 int aborted; 221 int npages; /* In the PRP list. 0 means small pool in use */ 222 int nents; /* Used in scatterlist */ 223 dma_addr_t first_dma; 224 unsigned int dma_len; /* length of single DMA segment mapping */ 225 dma_addr_t meta_dma; 226 struct scatterlist *sg; 227 }; 228 229 static unsigned int max_io_queues(void) 230 { 231 return num_possible_cpus() + write_queues + poll_queues; 232 } 233 234 static unsigned int max_queue_count(void) 235 { 236 /* IO queues + admin queue */ 237 return 1 + max_io_queues(); 238 } 239 240 static inline unsigned int nvme_dbbuf_size(u32 stride) 241 { 242 return (max_queue_count() * 8 * stride); 243 } 244 245 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 246 { 247 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 248 249 if (dev->dbbuf_dbs) 250 return 0; 251 252 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 253 &dev->dbbuf_dbs_dma_addr, 254 GFP_KERNEL); 255 if (!dev->dbbuf_dbs) 256 return -ENOMEM; 257 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 258 &dev->dbbuf_eis_dma_addr, 259 GFP_KERNEL); 260 if (!dev->dbbuf_eis) { 261 dma_free_coherent(dev->dev, mem_size, 262 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 263 dev->dbbuf_dbs = NULL; 264 return -ENOMEM; 265 } 266 267 return 0; 268 } 269 270 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 271 { 272 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 273 274 if (dev->dbbuf_dbs) { 275 dma_free_coherent(dev->dev, mem_size, 276 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 277 dev->dbbuf_dbs = NULL; 278 } 279 if (dev->dbbuf_eis) { 280 dma_free_coherent(dev->dev, mem_size, 281 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 282 dev->dbbuf_eis = NULL; 283 } 284 } 285 286 static void nvme_dbbuf_init(struct nvme_dev *dev, 287 struct nvme_queue *nvmeq, int qid) 288 { 289 if (!dev->dbbuf_dbs || !qid) 290 return; 291 292 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 293 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 294 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 295 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 296 } 297 298 static void nvme_dbbuf_set(struct nvme_dev *dev) 299 { 300 struct nvme_command c; 301 302 if (!dev->dbbuf_dbs) 303 return; 304 305 memset(&c, 0, sizeof(c)); 306 c.dbbuf.opcode = nvme_admin_dbbuf; 307 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 308 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 309 310 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 311 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 312 /* Free memory and continue on */ 313 nvme_dbbuf_dma_free(dev); 314 } 315 } 316 317 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 318 { 319 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 320 } 321 322 /* Update dbbuf and return true if an MMIO is required */ 323 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 324 volatile u32 *dbbuf_ei) 325 { 326 if (dbbuf_db) { 327 u16 old_value; 328 329 /* 330 * Ensure that the queue is written before updating 331 * the doorbell in memory 332 */ 333 wmb(); 334 335 old_value = *dbbuf_db; 336 *dbbuf_db = value; 337 338 /* 339 * Ensure that the doorbell is updated before reading the event 340 * index from memory. The controller needs to provide similar 341 * ordering to ensure the envent index is updated before reading 342 * the doorbell. 343 */ 344 mb(); 345 346 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 347 return false; 348 } 349 350 return true; 351 } 352 353 /* 354 * Will slightly overestimate the number of pages needed. This is OK 355 * as it only leads to a small amount of wasted memory for the lifetime of 356 * the I/O. 357 */ 358 static int nvme_npages(unsigned size, struct nvme_dev *dev) 359 { 360 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 361 dev->ctrl.page_size); 362 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 363 } 364 365 /* 366 * Calculates the number of pages needed for the SGL segments. For example a 4k 367 * page can accommodate 256 SGL descriptors. 368 */ 369 static int nvme_pci_npages_sgl(unsigned int num_seg) 370 { 371 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 372 } 373 374 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 375 unsigned int size, unsigned int nseg, bool use_sgl) 376 { 377 size_t alloc_size; 378 379 if (use_sgl) 380 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 381 else 382 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 383 384 return alloc_size + sizeof(struct scatterlist) * nseg; 385 } 386 387 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 388 unsigned int hctx_idx) 389 { 390 struct nvme_dev *dev = data; 391 struct nvme_queue *nvmeq = &dev->queues[0]; 392 393 WARN_ON(hctx_idx != 0); 394 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 395 WARN_ON(nvmeq->tags); 396 397 hctx->driver_data = nvmeq; 398 nvmeq->tags = &dev->admin_tagset.tags[0]; 399 return 0; 400 } 401 402 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 403 { 404 struct nvme_queue *nvmeq = hctx->driver_data; 405 406 nvmeq->tags = NULL; 407 } 408 409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 410 unsigned int hctx_idx) 411 { 412 struct nvme_dev *dev = data; 413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 414 415 if (!nvmeq->tags) 416 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 417 418 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 419 hctx->driver_data = nvmeq; 420 return 0; 421 } 422 423 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 424 unsigned int hctx_idx, unsigned int numa_node) 425 { 426 struct nvme_dev *dev = set->driver_data; 427 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 428 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 429 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 430 431 BUG_ON(!nvmeq); 432 iod->nvmeq = nvmeq; 433 434 nvme_req(req)->ctrl = &dev->ctrl; 435 return 0; 436 } 437 438 static int queue_irq_offset(struct nvme_dev *dev) 439 { 440 /* if we have more than 1 vec, admin queue offsets us by 1 */ 441 if (dev->num_vecs > 1) 442 return 1; 443 444 return 0; 445 } 446 447 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 448 { 449 struct nvme_dev *dev = set->driver_data; 450 int i, qoff, offset; 451 452 offset = queue_irq_offset(dev); 453 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 454 struct blk_mq_queue_map *map = &set->map[i]; 455 456 map->nr_queues = dev->io_queues[i]; 457 if (!map->nr_queues) { 458 BUG_ON(i == HCTX_TYPE_DEFAULT); 459 continue; 460 } 461 462 /* 463 * The poll queue(s) doesn't have an IRQ (and hence IRQ 464 * affinity), so use the regular blk-mq cpu mapping 465 */ 466 map->queue_offset = qoff; 467 if (i != HCTX_TYPE_POLL && offset) 468 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 469 else 470 blk_mq_map_queues(map); 471 qoff += map->nr_queues; 472 offset += map->nr_queues; 473 } 474 475 return 0; 476 } 477 478 /* 479 * Write sq tail if we are asked to, or if the next command would wrap. 480 */ 481 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 482 { 483 if (!write_sq) { 484 u16 next_tail = nvmeq->sq_tail + 1; 485 486 if (next_tail == nvmeq->q_depth) 487 next_tail = 0; 488 if (next_tail != nvmeq->last_sq_tail) 489 return; 490 } 491 492 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 493 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 494 writel(nvmeq->sq_tail, nvmeq->q_db); 495 nvmeq->last_sq_tail = nvmeq->sq_tail; 496 } 497 498 /** 499 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 500 * @nvmeq: The queue to use 501 * @cmd: The command to send 502 * @write_sq: whether to write to the SQ doorbell 503 */ 504 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 505 bool write_sq) 506 { 507 spin_lock(&nvmeq->sq_lock); 508 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 509 if (++nvmeq->sq_tail == nvmeq->q_depth) 510 nvmeq->sq_tail = 0; 511 nvme_write_sq_db(nvmeq, write_sq); 512 spin_unlock(&nvmeq->sq_lock); 513 } 514 515 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 516 { 517 struct nvme_queue *nvmeq = hctx->driver_data; 518 519 spin_lock(&nvmeq->sq_lock); 520 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 521 nvme_write_sq_db(nvmeq, true); 522 spin_unlock(&nvmeq->sq_lock); 523 } 524 525 static void **nvme_pci_iod_list(struct request *req) 526 { 527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 528 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 529 } 530 531 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 532 { 533 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 534 int nseg = blk_rq_nr_phys_segments(req); 535 unsigned int avg_seg_size; 536 537 if (nseg == 0) 538 return false; 539 540 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 541 542 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 543 return false; 544 if (!iod->nvmeq->qid) 545 return false; 546 if (!sgl_threshold || avg_seg_size < sgl_threshold) 547 return false; 548 return true; 549 } 550 551 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 552 { 553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 554 enum dma_data_direction dma_dir = rq_data_dir(req) ? 555 DMA_TO_DEVICE : DMA_FROM_DEVICE; 556 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 557 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 558 int i; 559 560 if (iod->dma_len) { 561 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); 562 return; 563 } 564 565 WARN_ON_ONCE(!iod->nents); 566 567 /* P2PDMA requests do not need to be unmapped */ 568 if (!is_pci_p2pdma_page(sg_page(iod->sg))) 569 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 570 571 572 if (iod->npages == 0) 573 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 574 dma_addr); 575 576 for (i = 0; i < iod->npages; i++) { 577 void *addr = nvme_pci_iod_list(req)[i]; 578 579 if (iod->use_sgl) { 580 struct nvme_sgl_desc *sg_list = addr; 581 582 next_dma_addr = 583 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 584 } else { 585 __le64 *prp_list = addr; 586 587 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 588 } 589 590 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 591 dma_addr = next_dma_addr; 592 } 593 594 mempool_free(iod->sg, dev->iod_mempool); 595 } 596 597 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 598 { 599 int i; 600 struct scatterlist *sg; 601 602 for_each_sg(sgl, sg, nents, i) { 603 dma_addr_t phys = sg_phys(sg); 604 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 605 "dma_address:%pad dma_length:%d\n", 606 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 607 sg_dma_len(sg)); 608 } 609 } 610 611 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 612 struct request *req, struct nvme_rw_command *cmnd) 613 { 614 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 615 struct dma_pool *pool; 616 int length = blk_rq_payload_bytes(req); 617 struct scatterlist *sg = iod->sg; 618 int dma_len = sg_dma_len(sg); 619 u64 dma_addr = sg_dma_address(sg); 620 u32 page_size = dev->ctrl.page_size; 621 int offset = dma_addr & (page_size - 1); 622 __le64 *prp_list; 623 void **list = nvme_pci_iod_list(req); 624 dma_addr_t prp_dma; 625 int nprps, i; 626 627 length -= (page_size - offset); 628 if (length <= 0) { 629 iod->first_dma = 0; 630 goto done; 631 } 632 633 dma_len -= (page_size - offset); 634 if (dma_len) { 635 dma_addr += (page_size - offset); 636 } else { 637 sg = sg_next(sg); 638 dma_addr = sg_dma_address(sg); 639 dma_len = sg_dma_len(sg); 640 } 641 642 if (length <= page_size) { 643 iod->first_dma = dma_addr; 644 goto done; 645 } 646 647 nprps = DIV_ROUND_UP(length, page_size); 648 if (nprps <= (256 / 8)) { 649 pool = dev->prp_small_pool; 650 iod->npages = 0; 651 } else { 652 pool = dev->prp_page_pool; 653 iod->npages = 1; 654 } 655 656 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 657 if (!prp_list) { 658 iod->first_dma = dma_addr; 659 iod->npages = -1; 660 return BLK_STS_RESOURCE; 661 } 662 list[0] = prp_list; 663 iod->first_dma = prp_dma; 664 i = 0; 665 for (;;) { 666 if (i == page_size >> 3) { 667 __le64 *old_prp_list = prp_list; 668 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 669 if (!prp_list) 670 return BLK_STS_RESOURCE; 671 list[iod->npages++] = prp_list; 672 prp_list[0] = old_prp_list[i - 1]; 673 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 674 i = 1; 675 } 676 prp_list[i++] = cpu_to_le64(dma_addr); 677 dma_len -= page_size; 678 dma_addr += page_size; 679 length -= page_size; 680 if (length <= 0) 681 break; 682 if (dma_len > 0) 683 continue; 684 if (unlikely(dma_len < 0)) 685 goto bad_sgl; 686 sg = sg_next(sg); 687 dma_addr = sg_dma_address(sg); 688 dma_len = sg_dma_len(sg); 689 } 690 691 done: 692 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 693 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 694 695 return BLK_STS_OK; 696 697 bad_sgl: 698 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 699 "Invalid SGL for payload:%d nents:%d\n", 700 blk_rq_payload_bytes(req), iod->nents); 701 return BLK_STS_IOERR; 702 } 703 704 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 705 struct scatterlist *sg) 706 { 707 sge->addr = cpu_to_le64(sg_dma_address(sg)); 708 sge->length = cpu_to_le32(sg_dma_len(sg)); 709 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 710 } 711 712 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 713 dma_addr_t dma_addr, int entries) 714 { 715 sge->addr = cpu_to_le64(dma_addr); 716 if (entries < SGES_PER_PAGE) { 717 sge->length = cpu_to_le32(entries * sizeof(*sge)); 718 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 719 } else { 720 sge->length = cpu_to_le32(PAGE_SIZE); 721 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 722 } 723 } 724 725 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 726 struct request *req, struct nvme_rw_command *cmd, int entries) 727 { 728 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 729 struct dma_pool *pool; 730 struct nvme_sgl_desc *sg_list; 731 struct scatterlist *sg = iod->sg; 732 dma_addr_t sgl_dma; 733 int i = 0; 734 735 /* setting the transfer type as SGL */ 736 cmd->flags = NVME_CMD_SGL_METABUF; 737 738 if (entries == 1) { 739 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 740 return BLK_STS_OK; 741 } 742 743 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 744 pool = dev->prp_small_pool; 745 iod->npages = 0; 746 } else { 747 pool = dev->prp_page_pool; 748 iod->npages = 1; 749 } 750 751 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 752 if (!sg_list) { 753 iod->npages = -1; 754 return BLK_STS_RESOURCE; 755 } 756 757 nvme_pci_iod_list(req)[0] = sg_list; 758 iod->first_dma = sgl_dma; 759 760 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 761 762 do { 763 if (i == SGES_PER_PAGE) { 764 struct nvme_sgl_desc *old_sg_desc = sg_list; 765 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 766 767 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 768 if (!sg_list) 769 return BLK_STS_RESOURCE; 770 771 i = 0; 772 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 773 sg_list[i++] = *link; 774 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 775 } 776 777 nvme_pci_sgl_set_data(&sg_list[i++], sg); 778 sg = sg_next(sg); 779 } while (--entries > 0); 780 781 return BLK_STS_OK; 782 } 783 784 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 785 struct request *req, struct nvme_rw_command *cmnd, 786 struct bio_vec *bv) 787 { 788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 789 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 790 791 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 792 if (dma_mapping_error(dev->dev, iod->first_dma)) 793 return BLK_STS_RESOURCE; 794 iod->dma_len = bv->bv_len; 795 796 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 797 if (bv->bv_len > first_prp_len) 798 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 799 return 0; 800 } 801 802 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 803 struct request *req, struct nvme_rw_command *cmnd, 804 struct bio_vec *bv) 805 { 806 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 807 808 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 809 if (dma_mapping_error(dev->dev, iod->first_dma)) 810 return BLK_STS_RESOURCE; 811 iod->dma_len = bv->bv_len; 812 813 cmnd->flags = NVME_CMD_SGL_METABUF; 814 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 815 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 816 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 817 return 0; 818 } 819 820 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 821 struct nvme_command *cmnd) 822 { 823 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 824 blk_status_t ret = BLK_STS_RESOURCE; 825 int nr_mapped; 826 827 if (blk_rq_nr_phys_segments(req) == 1) { 828 struct bio_vec bv = req_bvec(req); 829 830 if (!is_pci_p2pdma_page(bv.bv_page)) { 831 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 832 return nvme_setup_prp_simple(dev, req, 833 &cmnd->rw, &bv); 834 835 if (iod->nvmeq->qid && 836 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 837 return nvme_setup_sgl_simple(dev, req, 838 &cmnd->rw, &bv); 839 } 840 } 841 842 iod->dma_len = 0; 843 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 844 if (!iod->sg) 845 return BLK_STS_RESOURCE; 846 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 847 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 848 if (!iod->nents) 849 goto out; 850 851 if (is_pci_p2pdma_page(sg_page(iod->sg))) 852 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 853 rq_dma_dir(req)); 854 else 855 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 856 rq_dma_dir(req), DMA_ATTR_NO_WARN); 857 if (!nr_mapped) 858 goto out; 859 860 iod->use_sgl = nvme_pci_use_sgls(dev, req); 861 if (iod->use_sgl) 862 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 863 else 864 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 865 out: 866 if (ret != BLK_STS_OK) 867 nvme_unmap_data(dev, req); 868 return ret; 869 } 870 871 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 872 struct nvme_command *cmnd) 873 { 874 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 875 876 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 877 rq_dma_dir(req), 0); 878 if (dma_mapping_error(dev->dev, iod->meta_dma)) 879 return BLK_STS_IOERR; 880 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 881 return 0; 882 } 883 884 /* 885 * NOTE: ns is NULL when called on the admin queue. 886 */ 887 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 888 const struct blk_mq_queue_data *bd) 889 { 890 struct nvme_ns *ns = hctx->queue->queuedata; 891 struct nvme_queue *nvmeq = hctx->driver_data; 892 struct nvme_dev *dev = nvmeq->dev; 893 struct request *req = bd->rq; 894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 895 struct nvme_command cmnd; 896 blk_status_t ret; 897 898 iod->aborted = 0; 899 iod->npages = -1; 900 iod->nents = 0; 901 902 /* 903 * We should not need to do this, but we're still using this to 904 * ensure we can drain requests on a dying queue. 905 */ 906 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 907 return BLK_STS_IOERR; 908 909 ret = nvme_setup_cmd(ns, req, &cmnd); 910 if (ret) 911 return ret; 912 913 if (blk_rq_nr_phys_segments(req)) { 914 ret = nvme_map_data(dev, req, &cmnd); 915 if (ret) 916 goto out_free_cmd; 917 } 918 919 if (blk_integrity_rq(req)) { 920 ret = nvme_map_metadata(dev, req, &cmnd); 921 if (ret) 922 goto out_unmap_data; 923 } 924 925 blk_mq_start_request(req); 926 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 927 return BLK_STS_OK; 928 out_unmap_data: 929 nvme_unmap_data(dev, req); 930 out_free_cmd: 931 nvme_cleanup_cmd(req); 932 return ret; 933 } 934 935 static void nvme_pci_complete_rq(struct request *req) 936 { 937 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 938 struct nvme_dev *dev = iod->nvmeq->dev; 939 940 nvme_cleanup_cmd(req); 941 if (blk_integrity_rq(req)) 942 dma_unmap_page(dev->dev, iod->meta_dma, 943 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 944 if (blk_rq_nr_phys_segments(req)) 945 nvme_unmap_data(dev, req); 946 nvme_complete_rq(req); 947 } 948 949 /* We read the CQE phase first to check if the rest of the entry is valid */ 950 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 951 { 952 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 953 nvmeq->cq_phase; 954 } 955 956 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 957 { 958 u16 head = nvmeq->cq_head; 959 960 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 961 nvmeq->dbbuf_cq_ei)) 962 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 963 } 964 965 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 966 { 967 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 968 struct request *req; 969 970 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 971 dev_warn(nvmeq->dev->ctrl.device, 972 "invalid id %d completed on queue %d\n", 973 cqe->command_id, le16_to_cpu(cqe->sq_id)); 974 return; 975 } 976 977 /* 978 * AEN requests are special as they don't time out and can 979 * survive any kind of queue freeze and often don't respond to 980 * aborts. We don't even bother to allocate a struct request 981 * for them but rather special case them here. 982 */ 983 if (unlikely(nvmeq->qid == 0 && 984 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 985 nvme_complete_async_event(&nvmeq->dev->ctrl, 986 cqe->status, &cqe->result); 987 return; 988 } 989 990 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 991 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 992 nvme_end_request(req, cqe->status, cqe->result); 993 } 994 995 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 996 { 997 while (start != end) { 998 nvme_handle_cqe(nvmeq, start); 999 if (++start == nvmeq->q_depth) 1000 start = 0; 1001 } 1002 } 1003 1004 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1005 { 1006 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1007 nvmeq->cq_head = 0; 1008 nvmeq->cq_phase = !nvmeq->cq_phase; 1009 } else { 1010 nvmeq->cq_head++; 1011 } 1012 } 1013 1014 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 1015 u16 *end, unsigned int tag) 1016 { 1017 int found = 0; 1018 1019 *start = nvmeq->cq_head; 1020 while (nvme_cqe_pending(nvmeq)) { 1021 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1022 found++; 1023 nvme_update_cq_head(nvmeq); 1024 } 1025 *end = nvmeq->cq_head; 1026 1027 if (*start != *end) 1028 nvme_ring_cq_doorbell(nvmeq); 1029 return found; 1030 } 1031 1032 static irqreturn_t nvme_irq(int irq, void *data) 1033 { 1034 struct nvme_queue *nvmeq = data; 1035 irqreturn_t ret = IRQ_NONE; 1036 u16 start, end; 1037 1038 /* 1039 * The rmb/wmb pair ensures we see all updates from a previous run of 1040 * the irq handler, even if that was on another CPU. 1041 */ 1042 rmb(); 1043 if (nvmeq->cq_head != nvmeq->last_cq_head) 1044 ret = IRQ_HANDLED; 1045 nvme_process_cq(nvmeq, &start, &end, -1); 1046 nvmeq->last_cq_head = nvmeq->cq_head; 1047 wmb(); 1048 1049 if (start != end) { 1050 nvme_complete_cqes(nvmeq, start, end); 1051 return IRQ_HANDLED; 1052 } 1053 1054 return ret; 1055 } 1056 1057 static irqreturn_t nvme_irq_check(int irq, void *data) 1058 { 1059 struct nvme_queue *nvmeq = data; 1060 if (nvme_cqe_pending(nvmeq)) 1061 return IRQ_WAKE_THREAD; 1062 return IRQ_NONE; 1063 } 1064 1065 /* 1066 * Poll for completions any queue, including those not dedicated to polling. 1067 * Can be called from any context. 1068 */ 1069 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1070 { 1071 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1072 u16 start, end; 1073 int found; 1074 1075 /* 1076 * For a poll queue we need to protect against the polling thread 1077 * using the CQ lock. For normal interrupt driven threads we have 1078 * to disable the interrupt to avoid racing with it. 1079 */ 1080 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1081 spin_lock(&nvmeq->cq_poll_lock); 1082 found = nvme_process_cq(nvmeq, &start, &end, tag); 1083 spin_unlock(&nvmeq->cq_poll_lock); 1084 } else { 1085 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1086 found = nvme_process_cq(nvmeq, &start, &end, tag); 1087 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1088 } 1089 1090 nvme_complete_cqes(nvmeq, start, end); 1091 return found; 1092 } 1093 1094 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1095 { 1096 struct nvme_queue *nvmeq = hctx->driver_data; 1097 u16 start, end; 1098 bool found; 1099 1100 if (!nvme_cqe_pending(nvmeq)) 1101 return 0; 1102 1103 spin_lock(&nvmeq->cq_poll_lock); 1104 found = nvme_process_cq(nvmeq, &start, &end, -1); 1105 spin_unlock(&nvmeq->cq_poll_lock); 1106 1107 nvme_complete_cqes(nvmeq, start, end); 1108 return found; 1109 } 1110 1111 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1112 { 1113 struct nvme_dev *dev = to_nvme_dev(ctrl); 1114 struct nvme_queue *nvmeq = &dev->queues[0]; 1115 struct nvme_command c; 1116 1117 memset(&c, 0, sizeof(c)); 1118 c.common.opcode = nvme_admin_async_event; 1119 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1120 nvme_submit_cmd(nvmeq, &c, true); 1121 } 1122 1123 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1124 { 1125 struct nvme_command c; 1126 1127 memset(&c, 0, sizeof(c)); 1128 c.delete_queue.opcode = opcode; 1129 c.delete_queue.qid = cpu_to_le16(id); 1130 1131 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1132 } 1133 1134 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1135 struct nvme_queue *nvmeq, s16 vector) 1136 { 1137 struct nvme_command c; 1138 int flags = NVME_QUEUE_PHYS_CONTIG; 1139 1140 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1141 flags |= NVME_CQ_IRQ_ENABLED; 1142 1143 /* 1144 * Note: we (ab)use the fact that the prp fields survive if no data 1145 * is attached to the request. 1146 */ 1147 memset(&c, 0, sizeof(c)); 1148 c.create_cq.opcode = nvme_admin_create_cq; 1149 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1150 c.create_cq.cqid = cpu_to_le16(qid); 1151 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1152 c.create_cq.cq_flags = cpu_to_le16(flags); 1153 c.create_cq.irq_vector = cpu_to_le16(vector); 1154 1155 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1156 } 1157 1158 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1159 struct nvme_queue *nvmeq) 1160 { 1161 struct nvme_ctrl *ctrl = &dev->ctrl; 1162 struct nvme_command c; 1163 int flags = NVME_QUEUE_PHYS_CONTIG; 1164 1165 /* 1166 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1167 * set. Since URGENT priority is zeroes, it makes all queues 1168 * URGENT. 1169 */ 1170 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1171 flags |= NVME_SQ_PRIO_MEDIUM; 1172 1173 /* 1174 * Note: we (ab)use the fact that the prp fields survive if no data 1175 * is attached to the request. 1176 */ 1177 memset(&c, 0, sizeof(c)); 1178 c.create_sq.opcode = nvme_admin_create_sq; 1179 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1180 c.create_sq.sqid = cpu_to_le16(qid); 1181 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1182 c.create_sq.sq_flags = cpu_to_le16(flags); 1183 c.create_sq.cqid = cpu_to_le16(qid); 1184 1185 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1186 } 1187 1188 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1189 { 1190 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1191 } 1192 1193 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1194 { 1195 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1196 } 1197 1198 static void abort_endio(struct request *req, blk_status_t error) 1199 { 1200 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1201 struct nvme_queue *nvmeq = iod->nvmeq; 1202 1203 dev_warn(nvmeq->dev->ctrl.device, 1204 "Abort status: 0x%x", nvme_req(req)->status); 1205 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1206 blk_mq_free_request(req); 1207 } 1208 1209 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1210 { 1211 1212 /* If true, indicates loss of adapter communication, possibly by a 1213 * NVMe Subsystem reset. 1214 */ 1215 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1216 1217 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1218 switch (dev->ctrl.state) { 1219 case NVME_CTRL_RESETTING: 1220 case NVME_CTRL_CONNECTING: 1221 return false; 1222 default: 1223 break; 1224 } 1225 1226 /* We shouldn't reset unless the controller is on fatal error state 1227 * _or_ if we lost the communication with it. 1228 */ 1229 if (!(csts & NVME_CSTS_CFS) && !nssro) 1230 return false; 1231 1232 return true; 1233 } 1234 1235 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1236 { 1237 /* Read a config register to help see what died. */ 1238 u16 pci_status; 1239 int result; 1240 1241 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1242 &pci_status); 1243 if (result == PCIBIOS_SUCCESSFUL) 1244 dev_warn(dev->ctrl.device, 1245 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1246 csts, pci_status); 1247 else 1248 dev_warn(dev->ctrl.device, 1249 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1250 csts, result); 1251 } 1252 1253 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1254 { 1255 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1256 struct nvme_queue *nvmeq = iod->nvmeq; 1257 struct nvme_dev *dev = nvmeq->dev; 1258 struct request *abort_req; 1259 struct nvme_command cmd; 1260 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1261 1262 /* If PCI error recovery process is happening, we cannot reset or 1263 * the recovery mechanism will surely fail. 1264 */ 1265 mb(); 1266 if (pci_channel_offline(to_pci_dev(dev->dev))) 1267 return BLK_EH_RESET_TIMER; 1268 1269 /* 1270 * Reset immediately if the controller is failed 1271 */ 1272 if (nvme_should_reset(dev, csts)) { 1273 nvme_warn_reset(dev, csts); 1274 nvme_dev_disable(dev, false); 1275 nvme_reset_ctrl(&dev->ctrl); 1276 return BLK_EH_DONE; 1277 } 1278 1279 /* 1280 * Did we miss an interrupt? 1281 */ 1282 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1283 dev_warn(dev->ctrl.device, 1284 "I/O %d QID %d timeout, completion polled\n", 1285 req->tag, nvmeq->qid); 1286 return BLK_EH_DONE; 1287 } 1288 1289 /* 1290 * Shutdown immediately if controller times out while starting. The 1291 * reset work will see the pci device disabled when it gets the forced 1292 * cancellation error. All outstanding requests are completed on 1293 * shutdown, so we return BLK_EH_DONE. 1294 */ 1295 switch (dev->ctrl.state) { 1296 case NVME_CTRL_CONNECTING: 1297 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1298 /* fall through */ 1299 case NVME_CTRL_DELETING: 1300 dev_warn_ratelimited(dev->ctrl.device, 1301 "I/O %d QID %d timeout, disable controller\n", 1302 req->tag, nvmeq->qid); 1303 nvme_dev_disable(dev, true); 1304 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1305 return BLK_EH_DONE; 1306 case NVME_CTRL_RESETTING: 1307 return BLK_EH_RESET_TIMER; 1308 default: 1309 break; 1310 } 1311 1312 /* 1313 * Shutdown the controller immediately and schedule a reset if the 1314 * command was already aborted once before and still hasn't been 1315 * returned to the driver, or if this is the admin queue. 1316 */ 1317 if (!nvmeq->qid || iod->aborted) { 1318 dev_warn(dev->ctrl.device, 1319 "I/O %d QID %d timeout, reset controller\n", 1320 req->tag, nvmeq->qid); 1321 nvme_dev_disable(dev, false); 1322 nvme_reset_ctrl(&dev->ctrl); 1323 1324 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1325 return BLK_EH_DONE; 1326 } 1327 1328 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1329 atomic_inc(&dev->ctrl.abort_limit); 1330 return BLK_EH_RESET_TIMER; 1331 } 1332 iod->aborted = 1; 1333 1334 memset(&cmd, 0, sizeof(cmd)); 1335 cmd.abort.opcode = nvme_admin_abort_cmd; 1336 cmd.abort.cid = req->tag; 1337 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1338 1339 dev_warn(nvmeq->dev->ctrl.device, 1340 "I/O %d QID %d timeout, aborting\n", 1341 req->tag, nvmeq->qid); 1342 1343 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1344 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1345 if (IS_ERR(abort_req)) { 1346 atomic_inc(&dev->ctrl.abort_limit); 1347 return BLK_EH_RESET_TIMER; 1348 } 1349 1350 abort_req->timeout = ADMIN_TIMEOUT; 1351 abort_req->end_io_data = NULL; 1352 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1353 1354 /* 1355 * The aborted req will be completed on receiving the abort req. 1356 * We enable the timer again. If hit twice, it'll cause a device reset, 1357 * as the device then is in a faulty state. 1358 */ 1359 return BLK_EH_RESET_TIMER; 1360 } 1361 1362 static void nvme_free_queue(struct nvme_queue *nvmeq) 1363 { 1364 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 1365 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1366 if (!nvmeq->sq_cmds) 1367 return; 1368 1369 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1370 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1371 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 1372 } else { 1373 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 1374 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1375 } 1376 } 1377 1378 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1379 { 1380 int i; 1381 1382 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1383 dev->ctrl.queue_count--; 1384 nvme_free_queue(&dev->queues[i]); 1385 } 1386 } 1387 1388 /** 1389 * nvme_suspend_queue - put queue into suspended state 1390 * @nvmeq: queue to suspend 1391 */ 1392 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1393 { 1394 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1395 return 1; 1396 1397 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1398 mb(); 1399 1400 nvmeq->dev->online_queues--; 1401 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1402 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1403 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1404 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1405 return 0; 1406 } 1407 1408 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1409 { 1410 int i; 1411 1412 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1413 nvme_suspend_queue(&dev->queues[i]); 1414 } 1415 1416 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1417 { 1418 struct nvme_queue *nvmeq = &dev->queues[0]; 1419 1420 if (shutdown) 1421 nvme_shutdown_ctrl(&dev->ctrl); 1422 else 1423 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1424 1425 nvme_poll_irqdisable(nvmeq, -1); 1426 } 1427 1428 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1429 int entry_size) 1430 { 1431 int q_depth = dev->q_depth; 1432 unsigned q_size_aligned = roundup(q_depth * entry_size, 1433 dev->ctrl.page_size); 1434 1435 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1436 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1437 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1438 q_depth = div_u64(mem_per_q, entry_size); 1439 1440 /* 1441 * Ensure the reduced q_depth is above some threshold where it 1442 * would be better to map queues in system memory with the 1443 * original depth 1444 */ 1445 if (q_depth < 64) 1446 return -ENOMEM; 1447 } 1448 1449 return q_depth; 1450 } 1451 1452 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1453 int qid, int depth) 1454 { 1455 struct pci_dev *pdev = to_pci_dev(dev->dev); 1456 1457 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1458 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 1459 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1460 nvmeq->sq_cmds); 1461 if (nvmeq->sq_dma_addr) { 1462 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1463 return 0; 1464 } 1465 } 1466 1467 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1468 &nvmeq->sq_dma_addr, GFP_KERNEL); 1469 if (!nvmeq->sq_cmds) 1470 return -ENOMEM; 1471 return 0; 1472 } 1473 1474 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1475 { 1476 struct nvme_queue *nvmeq = &dev->queues[qid]; 1477 1478 if (dev->ctrl.queue_count > qid) 1479 return 0; 1480 1481 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 1482 &nvmeq->cq_dma_addr, GFP_KERNEL); 1483 if (!nvmeq->cqes) 1484 goto free_nvmeq; 1485 1486 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1487 goto free_cqdma; 1488 1489 nvmeq->dev = dev; 1490 spin_lock_init(&nvmeq->sq_lock); 1491 spin_lock_init(&nvmeq->cq_poll_lock); 1492 nvmeq->cq_head = 0; 1493 nvmeq->cq_phase = 1; 1494 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1495 nvmeq->q_depth = depth; 1496 nvmeq->qid = qid; 1497 dev->ctrl.queue_count++; 1498 1499 return 0; 1500 1501 free_cqdma: 1502 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1503 nvmeq->cq_dma_addr); 1504 free_nvmeq: 1505 return -ENOMEM; 1506 } 1507 1508 static int queue_request_irq(struct nvme_queue *nvmeq) 1509 { 1510 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1511 int nr = nvmeq->dev->ctrl.instance; 1512 1513 if (use_threaded_interrupts) { 1514 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1515 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1516 } else { 1517 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1518 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1519 } 1520 } 1521 1522 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1523 { 1524 struct nvme_dev *dev = nvmeq->dev; 1525 1526 nvmeq->sq_tail = 0; 1527 nvmeq->last_sq_tail = 0; 1528 nvmeq->cq_head = 0; 1529 nvmeq->cq_phase = 1; 1530 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1531 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1532 nvme_dbbuf_init(dev, nvmeq, qid); 1533 dev->online_queues++; 1534 wmb(); /* ensure the first interrupt sees the initialization */ 1535 } 1536 1537 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1538 { 1539 struct nvme_dev *dev = nvmeq->dev; 1540 int result; 1541 u16 vector = 0; 1542 1543 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1544 1545 /* 1546 * A queue's vector matches the queue identifier unless the controller 1547 * has only one vector available. 1548 */ 1549 if (!polled) 1550 vector = dev->num_vecs == 1 ? 0 : qid; 1551 else 1552 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1553 1554 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1555 if (result) 1556 return result; 1557 1558 result = adapter_alloc_sq(dev, qid, nvmeq); 1559 if (result < 0) 1560 return result; 1561 else if (result) 1562 goto release_cq; 1563 1564 nvmeq->cq_vector = vector; 1565 nvme_init_queue(nvmeq, qid); 1566 1567 if (!polled) { 1568 nvmeq->cq_vector = vector; 1569 result = queue_request_irq(nvmeq); 1570 if (result < 0) 1571 goto release_sq; 1572 } 1573 1574 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1575 return result; 1576 1577 release_sq: 1578 dev->online_queues--; 1579 adapter_delete_sq(dev, qid); 1580 release_cq: 1581 adapter_delete_cq(dev, qid); 1582 return result; 1583 } 1584 1585 static const struct blk_mq_ops nvme_mq_admin_ops = { 1586 .queue_rq = nvme_queue_rq, 1587 .complete = nvme_pci_complete_rq, 1588 .init_hctx = nvme_admin_init_hctx, 1589 .exit_hctx = nvme_admin_exit_hctx, 1590 .init_request = nvme_init_request, 1591 .timeout = nvme_timeout, 1592 }; 1593 1594 static const struct blk_mq_ops nvme_mq_ops = { 1595 .queue_rq = nvme_queue_rq, 1596 .complete = nvme_pci_complete_rq, 1597 .commit_rqs = nvme_commit_rqs, 1598 .init_hctx = nvme_init_hctx, 1599 .init_request = nvme_init_request, 1600 .map_queues = nvme_pci_map_queues, 1601 .timeout = nvme_timeout, 1602 .poll = nvme_poll, 1603 }; 1604 1605 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1606 { 1607 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1608 /* 1609 * If the controller was reset during removal, it's possible 1610 * user requests may be waiting on a stopped queue. Start the 1611 * queue to flush these to completion. 1612 */ 1613 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1614 blk_cleanup_queue(dev->ctrl.admin_q); 1615 blk_mq_free_tag_set(&dev->admin_tagset); 1616 } 1617 } 1618 1619 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1620 { 1621 if (!dev->ctrl.admin_q) { 1622 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1623 dev->admin_tagset.nr_hw_queues = 1; 1624 1625 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1626 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1627 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1628 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1629 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1630 dev->admin_tagset.driver_data = dev; 1631 1632 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1633 return -ENOMEM; 1634 dev->ctrl.admin_tagset = &dev->admin_tagset; 1635 1636 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1637 if (IS_ERR(dev->ctrl.admin_q)) { 1638 blk_mq_free_tag_set(&dev->admin_tagset); 1639 return -ENOMEM; 1640 } 1641 if (!blk_get_queue(dev->ctrl.admin_q)) { 1642 nvme_dev_remove_admin(dev); 1643 dev->ctrl.admin_q = NULL; 1644 return -ENODEV; 1645 } 1646 } else 1647 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1648 1649 return 0; 1650 } 1651 1652 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1653 { 1654 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1655 } 1656 1657 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1658 { 1659 struct pci_dev *pdev = to_pci_dev(dev->dev); 1660 1661 if (size <= dev->bar_mapped_size) 1662 return 0; 1663 if (size > pci_resource_len(pdev, 0)) 1664 return -ENOMEM; 1665 if (dev->bar) 1666 iounmap(dev->bar); 1667 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1668 if (!dev->bar) { 1669 dev->bar_mapped_size = 0; 1670 return -ENOMEM; 1671 } 1672 dev->bar_mapped_size = size; 1673 dev->dbs = dev->bar + NVME_REG_DBS; 1674 1675 return 0; 1676 } 1677 1678 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1679 { 1680 int result; 1681 u32 aqa; 1682 struct nvme_queue *nvmeq; 1683 1684 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1685 if (result < 0) 1686 return result; 1687 1688 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1689 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1690 1691 if (dev->subsystem && 1692 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1693 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1694 1695 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1696 if (result < 0) 1697 return result; 1698 1699 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1700 if (result) 1701 return result; 1702 1703 nvmeq = &dev->queues[0]; 1704 aqa = nvmeq->q_depth - 1; 1705 aqa |= aqa << 16; 1706 1707 writel(aqa, dev->bar + NVME_REG_AQA); 1708 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1709 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1710 1711 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 1712 if (result) 1713 return result; 1714 1715 nvmeq->cq_vector = 0; 1716 nvme_init_queue(nvmeq, 0); 1717 result = queue_request_irq(nvmeq); 1718 if (result) { 1719 dev->online_queues--; 1720 return result; 1721 } 1722 1723 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1724 return result; 1725 } 1726 1727 static int nvme_create_io_queues(struct nvme_dev *dev) 1728 { 1729 unsigned i, max, rw_queues; 1730 int ret = 0; 1731 1732 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1733 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1734 ret = -ENOMEM; 1735 break; 1736 } 1737 } 1738 1739 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1740 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1741 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1742 dev->io_queues[HCTX_TYPE_READ]; 1743 } else { 1744 rw_queues = max; 1745 } 1746 1747 for (i = dev->online_queues; i <= max; i++) { 1748 bool polled = i > rw_queues; 1749 1750 ret = nvme_create_queue(&dev->queues[i], i, polled); 1751 if (ret) 1752 break; 1753 } 1754 1755 /* 1756 * Ignore failing Create SQ/CQ commands, we can continue with less 1757 * than the desired amount of queues, and even a controller without 1758 * I/O queues can still be used to issue admin commands. This might 1759 * be useful to upgrade a buggy firmware for example. 1760 */ 1761 return ret >= 0 ? 0 : ret; 1762 } 1763 1764 static ssize_t nvme_cmb_show(struct device *dev, 1765 struct device_attribute *attr, 1766 char *buf) 1767 { 1768 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1769 1770 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1771 ndev->cmbloc, ndev->cmbsz); 1772 } 1773 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1774 1775 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1776 { 1777 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1778 1779 return 1ULL << (12 + 4 * szu); 1780 } 1781 1782 static u32 nvme_cmb_size(struct nvme_dev *dev) 1783 { 1784 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1785 } 1786 1787 static void nvme_map_cmb(struct nvme_dev *dev) 1788 { 1789 u64 size, offset; 1790 resource_size_t bar_size; 1791 struct pci_dev *pdev = to_pci_dev(dev->dev); 1792 int bar; 1793 1794 if (dev->cmb_size) 1795 return; 1796 1797 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1798 if (!dev->cmbsz) 1799 return; 1800 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1801 1802 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1803 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1804 bar = NVME_CMB_BIR(dev->cmbloc); 1805 bar_size = pci_resource_len(pdev, bar); 1806 1807 if (offset > bar_size) 1808 return; 1809 1810 /* 1811 * Controllers may support a CMB size larger than their BAR, 1812 * for example, due to being behind a bridge. Reduce the CMB to 1813 * the reported size of the BAR 1814 */ 1815 if (size > bar_size - offset) 1816 size = bar_size - offset; 1817 1818 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1819 dev_warn(dev->ctrl.device, 1820 "failed to register the CMB\n"); 1821 return; 1822 } 1823 1824 dev->cmb_size = size; 1825 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1826 1827 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1828 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1829 pci_p2pmem_publish(pdev, true); 1830 1831 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1832 &dev_attr_cmb.attr, NULL)) 1833 dev_warn(dev->ctrl.device, 1834 "failed to add sysfs attribute for CMB\n"); 1835 } 1836 1837 static inline void nvme_release_cmb(struct nvme_dev *dev) 1838 { 1839 if (dev->cmb_size) { 1840 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1841 &dev_attr_cmb.attr, NULL); 1842 dev->cmb_size = 0; 1843 } 1844 } 1845 1846 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1847 { 1848 u64 dma_addr = dev->host_mem_descs_dma; 1849 struct nvme_command c; 1850 int ret; 1851 1852 memset(&c, 0, sizeof(c)); 1853 c.features.opcode = nvme_admin_set_features; 1854 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1855 c.features.dword11 = cpu_to_le32(bits); 1856 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1857 ilog2(dev->ctrl.page_size)); 1858 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1859 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1860 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1861 1862 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1863 if (ret) { 1864 dev_warn(dev->ctrl.device, 1865 "failed to set host mem (err %d, flags %#x).\n", 1866 ret, bits); 1867 } 1868 return ret; 1869 } 1870 1871 static void nvme_free_host_mem(struct nvme_dev *dev) 1872 { 1873 int i; 1874 1875 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1876 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1877 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1878 1879 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1880 le64_to_cpu(desc->addr), 1881 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1882 } 1883 1884 kfree(dev->host_mem_desc_bufs); 1885 dev->host_mem_desc_bufs = NULL; 1886 dma_free_coherent(dev->dev, 1887 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1888 dev->host_mem_descs, dev->host_mem_descs_dma); 1889 dev->host_mem_descs = NULL; 1890 dev->nr_host_mem_descs = 0; 1891 } 1892 1893 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1894 u32 chunk_size) 1895 { 1896 struct nvme_host_mem_buf_desc *descs; 1897 u32 max_entries, len; 1898 dma_addr_t descs_dma; 1899 int i = 0; 1900 void **bufs; 1901 u64 size, tmp; 1902 1903 tmp = (preferred + chunk_size - 1); 1904 do_div(tmp, chunk_size); 1905 max_entries = tmp; 1906 1907 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1908 max_entries = dev->ctrl.hmmaxd; 1909 1910 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1911 &descs_dma, GFP_KERNEL); 1912 if (!descs) 1913 goto out; 1914 1915 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1916 if (!bufs) 1917 goto out_free_descs; 1918 1919 for (size = 0; size < preferred && i < max_entries; size += len) { 1920 dma_addr_t dma_addr; 1921 1922 len = min_t(u64, chunk_size, preferred - size); 1923 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1924 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1925 if (!bufs[i]) 1926 break; 1927 1928 descs[i].addr = cpu_to_le64(dma_addr); 1929 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1930 i++; 1931 } 1932 1933 if (!size) 1934 goto out_free_bufs; 1935 1936 dev->nr_host_mem_descs = i; 1937 dev->host_mem_size = size; 1938 dev->host_mem_descs = descs; 1939 dev->host_mem_descs_dma = descs_dma; 1940 dev->host_mem_desc_bufs = bufs; 1941 return 0; 1942 1943 out_free_bufs: 1944 while (--i >= 0) { 1945 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1946 1947 dma_free_attrs(dev->dev, size, bufs[i], 1948 le64_to_cpu(descs[i].addr), 1949 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1950 } 1951 1952 kfree(bufs); 1953 out_free_descs: 1954 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1955 descs_dma); 1956 out: 1957 dev->host_mem_descs = NULL; 1958 return -ENOMEM; 1959 } 1960 1961 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1962 { 1963 u32 chunk_size; 1964 1965 /* start big and work our way down */ 1966 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1967 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1968 chunk_size /= 2) { 1969 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1970 if (!min || dev->host_mem_size >= min) 1971 return 0; 1972 nvme_free_host_mem(dev); 1973 } 1974 } 1975 1976 return -ENOMEM; 1977 } 1978 1979 static int nvme_setup_host_mem(struct nvme_dev *dev) 1980 { 1981 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1982 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1983 u64 min = (u64)dev->ctrl.hmmin * 4096; 1984 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1985 int ret; 1986 1987 preferred = min(preferred, max); 1988 if (min > max) { 1989 dev_warn(dev->ctrl.device, 1990 "min host memory (%lld MiB) above limit (%d MiB).\n", 1991 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1992 nvme_free_host_mem(dev); 1993 return 0; 1994 } 1995 1996 /* 1997 * If we already have a buffer allocated check if we can reuse it. 1998 */ 1999 if (dev->host_mem_descs) { 2000 if (dev->host_mem_size >= min) 2001 enable_bits |= NVME_HOST_MEM_RETURN; 2002 else 2003 nvme_free_host_mem(dev); 2004 } 2005 2006 if (!dev->host_mem_descs) { 2007 if (nvme_alloc_host_mem(dev, min, preferred)) { 2008 dev_warn(dev->ctrl.device, 2009 "failed to allocate host memory buffer.\n"); 2010 return 0; /* controller must work without HMB */ 2011 } 2012 2013 dev_info(dev->ctrl.device, 2014 "allocated %lld MiB host memory buffer.\n", 2015 dev->host_mem_size >> ilog2(SZ_1M)); 2016 } 2017 2018 ret = nvme_set_host_mem(dev, enable_bits); 2019 if (ret) 2020 nvme_free_host_mem(dev); 2021 return ret; 2022 } 2023 2024 /* 2025 * nirqs is the number of interrupts available for write and read 2026 * queues. The core already reserved an interrupt for the admin queue. 2027 */ 2028 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2029 { 2030 struct nvme_dev *dev = affd->priv; 2031 unsigned int nr_read_queues; 2032 2033 /* 2034 * If there is no interupt available for queues, ensure that 2035 * the default queue is set to 1. The affinity set size is 2036 * also set to one, but the irq core ignores it for this case. 2037 * 2038 * If only one interrupt is available or 'write_queue' == 0, combine 2039 * write and read queues. 2040 * 2041 * If 'write_queues' > 0, ensure it leaves room for at least one read 2042 * queue. 2043 */ 2044 if (!nrirqs) { 2045 nrirqs = 1; 2046 nr_read_queues = 0; 2047 } else if (nrirqs == 1 || !write_queues) { 2048 nr_read_queues = 0; 2049 } else if (write_queues >= nrirqs) { 2050 nr_read_queues = 1; 2051 } else { 2052 nr_read_queues = nrirqs - write_queues; 2053 } 2054 2055 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2056 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2057 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2058 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2059 affd->nr_sets = nr_read_queues ? 2 : 1; 2060 } 2061 2062 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2063 { 2064 struct pci_dev *pdev = to_pci_dev(dev->dev); 2065 struct irq_affinity affd = { 2066 .pre_vectors = 1, 2067 .calc_sets = nvme_calc_irq_sets, 2068 .priv = dev, 2069 }; 2070 unsigned int irq_queues, this_p_queues; 2071 2072 /* 2073 * Poll queues don't need interrupts, but we need at least one IO 2074 * queue left over for non-polled IO. 2075 */ 2076 this_p_queues = poll_queues; 2077 if (this_p_queues >= nr_io_queues) { 2078 this_p_queues = nr_io_queues - 1; 2079 irq_queues = 1; 2080 } else { 2081 irq_queues = nr_io_queues - this_p_queues + 1; 2082 } 2083 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2084 2085 /* Initialize for the single interrupt case */ 2086 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2087 dev->io_queues[HCTX_TYPE_READ] = 0; 2088 2089 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2090 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2091 } 2092 2093 static void nvme_disable_io_queues(struct nvme_dev *dev) 2094 { 2095 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2096 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2097 } 2098 2099 static int nvme_setup_io_queues(struct nvme_dev *dev) 2100 { 2101 struct nvme_queue *adminq = &dev->queues[0]; 2102 struct pci_dev *pdev = to_pci_dev(dev->dev); 2103 int result, nr_io_queues; 2104 unsigned long size; 2105 2106 nr_io_queues = max_io_queues(); 2107 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2108 if (result < 0) 2109 return result; 2110 2111 if (nr_io_queues == 0) 2112 return 0; 2113 2114 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2115 2116 if (dev->cmb_use_sqes) { 2117 result = nvme_cmb_qdepth(dev, nr_io_queues, 2118 sizeof(struct nvme_command)); 2119 if (result > 0) 2120 dev->q_depth = result; 2121 else 2122 dev->cmb_use_sqes = false; 2123 } 2124 2125 do { 2126 size = db_bar_size(dev, nr_io_queues); 2127 result = nvme_remap_bar(dev, size); 2128 if (!result) 2129 break; 2130 if (!--nr_io_queues) 2131 return -ENOMEM; 2132 } while (1); 2133 adminq->q_db = dev->dbs; 2134 2135 retry: 2136 /* Deregister the admin queue's interrupt */ 2137 pci_free_irq(pdev, 0, adminq); 2138 2139 /* 2140 * If we enable msix early due to not intx, disable it again before 2141 * setting up the full range we need. 2142 */ 2143 pci_free_irq_vectors(pdev); 2144 2145 result = nvme_setup_irqs(dev, nr_io_queues); 2146 if (result <= 0) 2147 return -EIO; 2148 2149 dev->num_vecs = result; 2150 result = max(result - 1, 1); 2151 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2152 2153 /* 2154 * Should investigate if there's a performance win from allocating 2155 * more queues than interrupt vectors; it might allow the submission 2156 * path to scale better, even if the receive path is limited by the 2157 * number of interrupts. 2158 */ 2159 result = queue_request_irq(adminq); 2160 if (result) 2161 return result; 2162 set_bit(NVMEQ_ENABLED, &adminq->flags); 2163 2164 result = nvme_create_io_queues(dev); 2165 if (result || dev->online_queues < 2) 2166 return result; 2167 2168 if (dev->online_queues - 1 < dev->max_qid) { 2169 nr_io_queues = dev->online_queues - 1; 2170 nvme_disable_io_queues(dev); 2171 nvme_suspend_io_queues(dev); 2172 goto retry; 2173 } 2174 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2175 dev->io_queues[HCTX_TYPE_DEFAULT], 2176 dev->io_queues[HCTX_TYPE_READ], 2177 dev->io_queues[HCTX_TYPE_POLL]); 2178 return 0; 2179 } 2180 2181 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2182 { 2183 struct nvme_queue *nvmeq = req->end_io_data; 2184 2185 blk_mq_free_request(req); 2186 complete(&nvmeq->delete_done); 2187 } 2188 2189 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2190 { 2191 struct nvme_queue *nvmeq = req->end_io_data; 2192 2193 if (error) 2194 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2195 2196 nvme_del_queue_end(req, error); 2197 } 2198 2199 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2200 { 2201 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2202 struct request *req; 2203 struct nvme_command cmd; 2204 2205 memset(&cmd, 0, sizeof(cmd)); 2206 cmd.delete_queue.opcode = opcode; 2207 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2208 2209 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2210 if (IS_ERR(req)) 2211 return PTR_ERR(req); 2212 2213 req->timeout = ADMIN_TIMEOUT; 2214 req->end_io_data = nvmeq; 2215 2216 init_completion(&nvmeq->delete_done); 2217 blk_execute_rq_nowait(q, NULL, req, false, 2218 opcode == nvme_admin_delete_cq ? 2219 nvme_del_cq_end : nvme_del_queue_end); 2220 return 0; 2221 } 2222 2223 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2224 { 2225 int nr_queues = dev->online_queues - 1, sent = 0; 2226 unsigned long timeout; 2227 2228 retry: 2229 timeout = ADMIN_TIMEOUT; 2230 while (nr_queues > 0) { 2231 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2232 break; 2233 nr_queues--; 2234 sent++; 2235 } 2236 while (sent) { 2237 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2238 2239 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2240 timeout); 2241 if (timeout == 0) 2242 return false; 2243 2244 /* handle any remaining CQEs */ 2245 if (opcode == nvme_admin_delete_cq && 2246 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2247 nvme_poll_irqdisable(nvmeq, -1); 2248 2249 sent--; 2250 if (nr_queues) 2251 goto retry; 2252 } 2253 return true; 2254 } 2255 2256 /* 2257 * return error value only when tagset allocation failed 2258 */ 2259 static int nvme_dev_add(struct nvme_dev *dev) 2260 { 2261 int ret; 2262 2263 if (!dev->ctrl.tagset) { 2264 dev->tagset.ops = &nvme_mq_ops; 2265 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2266 dev->tagset.nr_maps = 2; /* default + read */ 2267 if (dev->io_queues[HCTX_TYPE_POLL]) 2268 dev->tagset.nr_maps++; 2269 dev->tagset.timeout = NVME_IO_TIMEOUT; 2270 dev->tagset.numa_node = dev_to_node(dev->dev); 2271 dev->tagset.queue_depth = 2272 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2273 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2274 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2275 dev->tagset.driver_data = dev; 2276 2277 ret = blk_mq_alloc_tag_set(&dev->tagset); 2278 if (ret) { 2279 dev_warn(dev->ctrl.device, 2280 "IO queues tagset allocation failed %d\n", ret); 2281 return ret; 2282 } 2283 dev->ctrl.tagset = &dev->tagset; 2284 } else { 2285 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2286 2287 /* Free previously allocated queues that are no longer usable */ 2288 nvme_free_queues(dev, dev->online_queues); 2289 } 2290 2291 nvme_dbbuf_set(dev); 2292 return 0; 2293 } 2294 2295 static int nvme_pci_enable(struct nvme_dev *dev) 2296 { 2297 int result = -ENOMEM; 2298 struct pci_dev *pdev = to_pci_dev(dev->dev); 2299 2300 if (pci_enable_device_mem(pdev)) 2301 return result; 2302 2303 pci_set_master(pdev); 2304 2305 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 2306 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 2307 goto disable; 2308 2309 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2310 result = -ENODEV; 2311 goto disable; 2312 } 2313 2314 /* 2315 * Some devices and/or platforms don't advertise or work with INTx 2316 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2317 * adjust this later. 2318 */ 2319 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2320 if (result < 0) 2321 return result; 2322 2323 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2324 2325 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2326 io_queue_depth); 2327 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2328 dev->dbs = dev->bar + 4096; 2329 2330 /* 2331 * Temporary fix for the Apple controller found in the MacBook8,1 and 2332 * some MacBook7,1 to avoid controller resets and data loss. 2333 */ 2334 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2335 dev->q_depth = 2; 2336 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2337 "set queue depth=%u to work around controller resets\n", 2338 dev->q_depth); 2339 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2340 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2341 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2342 dev->q_depth = 64; 2343 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2344 "set queue depth=%u\n", dev->q_depth); 2345 } 2346 2347 nvme_map_cmb(dev); 2348 2349 pci_enable_pcie_error_reporting(pdev); 2350 pci_save_state(pdev); 2351 return 0; 2352 2353 disable: 2354 pci_disable_device(pdev); 2355 return result; 2356 } 2357 2358 static void nvme_dev_unmap(struct nvme_dev *dev) 2359 { 2360 if (dev->bar) 2361 iounmap(dev->bar); 2362 pci_release_mem_regions(to_pci_dev(dev->dev)); 2363 } 2364 2365 static void nvme_pci_disable(struct nvme_dev *dev) 2366 { 2367 struct pci_dev *pdev = to_pci_dev(dev->dev); 2368 2369 pci_free_irq_vectors(pdev); 2370 2371 if (pci_is_enabled(pdev)) { 2372 pci_disable_pcie_error_reporting(pdev); 2373 pci_disable_device(pdev); 2374 } 2375 } 2376 2377 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2378 { 2379 bool dead = true, freeze = false; 2380 struct pci_dev *pdev = to_pci_dev(dev->dev); 2381 2382 mutex_lock(&dev->shutdown_lock); 2383 if (pci_is_enabled(pdev)) { 2384 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2385 2386 if (dev->ctrl.state == NVME_CTRL_LIVE || 2387 dev->ctrl.state == NVME_CTRL_RESETTING) { 2388 freeze = true; 2389 nvme_start_freeze(&dev->ctrl); 2390 } 2391 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2392 pdev->error_state != pci_channel_io_normal); 2393 } 2394 2395 /* 2396 * Give the controller a chance to complete all entered requests if 2397 * doing a safe shutdown. 2398 */ 2399 if (!dead && shutdown && freeze) 2400 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2401 2402 nvme_stop_queues(&dev->ctrl); 2403 2404 if (!dead && dev->ctrl.queue_count > 0) { 2405 nvme_disable_io_queues(dev); 2406 nvme_disable_admin_queue(dev, shutdown); 2407 } 2408 nvme_suspend_io_queues(dev); 2409 nvme_suspend_queue(&dev->queues[0]); 2410 nvme_pci_disable(dev); 2411 2412 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2413 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2414 2415 /* 2416 * The driver will not be starting up queues again if shutting down so 2417 * must flush all entered requests to their failed completion to avoid 2418 * deadlocking blk-mq hot-cpu notifier. 2419 */ 2420 if (shutdown) { 2421 nvme_start_queues(&dev->ctrl); 2422 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2423 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2424 } 2425 mutex_unlock(&dev->shutdown_lock); 2426 } 2427 2428 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2429 { 2430 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2431 PAGE_SIZE, PAGE_SIZE, 0); 2432 if (!dev->prp_page_pool) 2433 return -ENOMEM; 2434 2435 /* Optimisation for I/Os between 4k and 128k */ 2436 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2437 256, 256, 0); 2438 if (!dev->prp_small_pool) { 2439 dma_pool_destroy(dev->prp_page_pool); 2440 return -ENOMEM; 2441 } 2442 return 0; 2443 } 2444 2445 static void nvme_release_prp_pools(struct nvme_dev *dev) 2446 { 2447 dma_pool_destroy(dev->prp_page_pool); 2448 dma_pool_destroy(dev->prp_small_pool); 2449 } 2450 2451 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2452 { 2453 struct nvme_dev *dev = to_nvme_dev(ctrl); 2454 2455 nvme_dbbuf_dma_free(dev); 2456 put_device(dev->dev); 2457 if (dev->tagset.tags) 2458 blk_mq_free_tag_set(&dev->tagset); 2459 if (dev->ctrl.admin_q) 2460 blk_put_queue(dev->ctrl.admin_q); 2461 kfree(dev->queues); 2462 free_opal_dev(dev->ctrl.opal_dev); 2463 mempool_destroy(dev->iod_mempool); 2464 kfree(dev); 2465 } 2466 2467 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2468 { 2469 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2470 2471 nvme_get_ctrl(&dev->ctrl); 2472 nvme_dev_disable(dev, false); 2473 nvme_kill_queues(&dev->ctrl); 2474 if (!queue_work(nvme_wq, &dev->remove_work)) 2475 nvme_put_ctrl(&dev->ctrl); 2476 } 2477 2478 static void nvme_reset_work(struct work_struct *work) 2479 { 2480 struct nvme_dev *dev = 2481 container_of(work, struct nvme_dev, ctrl.reset_work); 2482 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2483 int result = -ENODEV; 2484 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2485 2486 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2487 goto out; 2488 2489 /* 2490 * If we're called to reset a live controller first shut it down before 2491 * moving on. 2492 */ 2493 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2494 nvme_dev_disable(dev, false); 2495 nvme_sync_queues(&dev->ctrl); 2496 2497 mutex_lock(&dev->shutdown_lock); 2498 result = nvme_pci_enable(dev); 2499 if (result) 2500 goto out_unlock; 2501 2502 result = nvme_pci_configure_admin_queue(dev); 2503 if (result) 2504 goto out_unlock; 2505 2506 result = nvme_alloc_admin_tags(dev); 2507 if (result) 2508 goto out_unlock; 2509 2510 /* 2511 * Limit the max command size to prevent iod->sg allocations going 2512 * over a single page. 2513 */ 2514 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2515 dev->ctrl.max_segments = NVME_MAX_SEGS; 2516 2517 /* 2518 * Don't limit the IOMMU merged segment size. 2519 */ 2520 dma_set_max_seg_size(dev->dev, 0xffffffff); 2521 2522 mutex_unlock(&dev->shutdown_lock); 2523 2524 /* 2525 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2526 * initializing procedure here. 2527 */ 2528 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2529 dev_warn(dev->ctrl.device, 2530 "failed to mark controller CONNECTING\n"); 2531 goto out; 2532 } 2533 2534 result = nvme_init_identify(&dev->ctrl); 2535 if (result) 2536 goto out; 2537 2538 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2539 if (!dev->ctrl.opal_dev) 2540 dev->ctrl.opal_dev = 2541 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2542 else if (was_suspend) 2543 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2544 } else { 2545 free_opal_dev(dev->ctrl.opal_dev); 2546 dev->ctrl.opal_dev = NULL; 2547 } 2548 2549 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2550 result = nvme_dbbuf_dma_alloc(dev); 2551 if (result) 2552 dev_warn(dev->dev, 2553 "unable to allocate dma for dbbuf\n"); 2554 } 2555 2556 if (dev->ctrl.hmpre) { 2557 result = nvme_setup_host_mem(dev); 2558 if (result < 0) 2559 goto out; 2560 } 2561 2562 result = nvme_setup_io_queues(dev); 2563 if (result) 2564 goto out; 2565 2566 /* 2567 * Keep the controller around but remove all namespaces if we don't have 2568 * any working I/O queue. 2569 */ 2570 if (dev->online_queues < 2) { 2571 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2572 nvme_kill_queues(&dev->ctrl); 2573 nvme_remove_namespaces(&dev->ctrl); 2574 new_state = NVME_CTRL_ADMIN_ONLY; 2575 } else { 2576 nvme_start_queues(&dev->ctrl); 2577 nvme_wait_freeze(&dev->ctrl); 2578 /* hit this only when allocate tagset fails */ 2579 if (nvme_dev_add(dev)) 2580 new_state = NVME_CTRL_ADMIN_ONLY; 2581 nvme_unfreeze(&dev->ctrl); 2582 } 2583 2584 /* 2585 * If only admin queue live, keep it to do further investigation or 2586 * recovery. 2587 */ 2588 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2589 dev_warn(dev->ctrl.device, 2590 "failed to mark controller state %d\n", new_state); 2591 goto out; 2592 } 2593 2594 nvme_start_ctrl(&dev->ctrl); 2595 return; 2596 2597 out_unlock: 2598 mutex_unlock(&dev->shutdown_lock); 2599 out: 2600 nvme_remove_dead_ctrl(dev, result); 2601 } 2602 2603 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2604 { 2605 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2606 struct pci_dev *pdev = to_pci_dev(dev->dev); 2607 2608 if (pci_get_drvdata(pdev)) 2609 device_release_driver(&pdev->dev); 2610 nvme_put_ctrl(&dev->ctrl); 2611 } 2612 2613 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2614 { 2615 *val = readl(to_nvme_dev(ctrl)->bar + off); 2616 return 0; 2617 } 2618 2619 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2620 { 2621 writel(val, to_nvme_dev(ctrl)->bar + off); 2622 return 0; 2623 } 2624 2625 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2626 { 2627 *val = readq(to_nvme_dev(ctrl)->bar + off); 2628 return 0; 2629 } 2630 2631 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2632 { 2633 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2634 2635 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2636 } 2637 2638 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2639 .name = "pcie", 2640 .module = THIS_MODULE, 2641 .flags = NVME_F_METADATA_SUPPORTED | 2642 NVME_F_PCI_P2PDMA, 2643 .reg_read32 = nvme_pci_reg_read32, 2644 .reg_write32 = nvme_pci_reg_write32, 2645 .reg_read64 = nvme_pci_reg_read64, 2646 .free_ctrl = nvme_pci_free_ctrl, 2647 .submit_async_event = nvme_pci_submit_async_event, 2648 .get_address = nvme_pci_get_address, 2649 }; 2650 2651 static int nvme_dev_map(struct nvme_dev *dev) 2652 { 2653 struct pci_dev *pdev = to_pci_dev(dev->dev); 2654 2655 if (pci_request_mem_regions(pdev, "nvme")) 2656 return -ENODEV; 2657 2658 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2659 goto release; 2660 2661 return 0; 2662 release: 2663 pci_release_mem_regions(pdev); 2664 return -ENODEV; 2665 } 2666 2667 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2668 { 2669 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2670 /* 2671 * Several Samsung devices seem to drop off the PCIe bus 2672 * randomly when APST is on and uses the deepest sleep state. 2673 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2674 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2675 * 950 PRO 256GB", but it seems to be restricted to two Dell 2676 * laptops. 2677 */ 2678 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2679 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2680 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2681 return NVME_QUIRK_NO_DEEPEST_PS; 2682 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2683 /* 2684 * Samsung SSD 960 EVO drops off the PCIe bus after system 2685 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2686 * within few minutes after bootup on a Coffee Lake board - 2687 * ASUS PRIME Z370-A 2688 */ 2689 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2690 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2691 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2692 return NVME_QUIRK_NO_APST; 2693 } 2694 2695 return 0; 2696 } 2697 2698 static void nvme_async_probe(void *data, async_cookie_t cookie) 2699 { 2700 struct nvme_dev *dev = data; 2701 2702 nvme_reset_ctrl_sync(&dev->ctrl); 2703 flush_work(&dev->ctrl.scan_work); 2704 nvme_put_ctrl(&dev->ctrl); 2705 } 2706 2707 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2708 { 2709 int node, result = -ENOMEM; 2710 struct nvme_dev *dev; 2711 unsigned long quirks = id->driver_data; 2712 size_t alloc_size; 2713 2714 node = dev_to_node(&pdev->dev); 2715 if (node == NUMA_NO_NODE) 2716 set_dev_node(&pdev->dev, first_memory_node); 2717 2718 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2719 if (!dev) 2720 return -ENOMEM; 2721 2722 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2723 GFP_KERNEL, node); 2724 if (!dev->queues) 2725 goto free; 2726 2727 dev->dev = get_device(&pdev->dev); 2728 pci_set_drvdata(pdev, dev); 2729 2730 result = nvme_dev_map(dev); 2731 if (result) 2732 goto put_pci; 2733 2734 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2735 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2736 mutex_init(&dev->shutdown_lock); 2737 2738 result = nvme_setup_prp_pools(dev); 2739 if (result) 2740 goto unmap; 2741 2742 quirks |= check_vendor_combination_bug(pdev); 2743 2744 /* 2745 * Double check that our mempool alloc size will cover the biggest 2746 * command we support. 2747 */ 2748 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2749 NVME_MAX_SEGS, true); 2750 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2751 2752 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2753 mempool_kfree, 2754 (void *) alloc_size, 2755 GFP_KERNEL, node); 2756 if (!dev->iod_mempool) { 2757 result = -ENOMEM; 2758 goto release_pools; 2759 } 2760 2761 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2762 quirks); 2763 if (result) 2764 goto release_mempool; 2765 2766 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2767 2768 nvme_get_ctrl(&dev->ctrl); 2769 async_schedule(nvme_async_probe, dev); 2770 2771 return 0; 2772 2773 release_mempool: 2774 mempool_destroy(dev->iod_mempool); 2775 release_pools: 2776 nvme_release_prp_pools(dev); 2777 unmap: 2778 nvme_dev_unmap(dev); 2779 put_pci: 2780 put_device(dev->dev); 2781 free: 2782 kfree(dev->queues); 2783 kfree(dev); 2784 return result; 2785 } 2786 2787 static void nvme_reset_prepare(struct pci_dev *pdev) 2788 { 2789 struct nvme_dev *dev = pci_get_drvdata(pdev); 2790 nvme_dev_disable(dev, false); 2791 } 2792 2793 static void nvme_reset_done(struct pci_dev *pdev) 2794 { 2795 struct nvme_dev *dev = pci_get_drvdata(pdev); 2796 nvme_reset_ctrl_sync(&dev->ctrl); 2797 } 2798 2799 static void nvme_shutdown(struct pci_dev *pdev) 2800 { 2801 struct nvme_dev *dev = pci_get_drvdata(pdev); 2802 nvme_dev_disable(dev, true); 2803 } 2804 2805 /* 2806 * The driver's remove may be called on a device in a partially initialized 2807 * state. This function must not have any dependencies on the device state in 2808 * order to proceed. 2809 */ 2810 static void nvme_remove(struct pci_dev *pdev) 2811 { 2812 struct nvme_dev *dev = pci_get_drvdata(pdev); 2813 2814 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2815 pci_set_drvdata(pdev, NULL); 2816 2817 if (!pci_device_is_present(pdev)) { 2818 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2819 nvme_dev_disable(dev, true); 2820 nvme_dev_remove_admin(dev); 2821 } 2822 2823 flush_work(&dev->ctrl.reset_work); 2824 nvme_stop_ctrl(&dev->ctrl); 2825 nvme_remove_namespaces(&dev->ctrl); 2826 nvme_dev_disable(dev, true); 2827 nvme_release_cmb(dev); 2828 nvme_free_host_mem(dev); 2829 nvme_dev_remove_admin(dev); 2830 nvme_free_queues(dev, 0); 2831 nvme_uninit_ctrl(&dev->ctrl); 2832 nvme_release_prp_pools(dev); 2833 nvme_dev_unmap(dev); 2834 nvme_put_ctrl(&dev->ctrl); 2835 } 2836 2837 #ifdef CONFIG_PM_SLEEP 2838 static int nvme_suspend(struct device *dev) 2839 { 2840 struct pci_dev *pdev = to_pci_dev(dev); 2841 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2842 2843 nvme_dev_disable(ndev, true); 2844 return 0; 2845 } 2846 2847 static int nvme_resume(struct device *dev) 2848 { 2849 struct pci_dev *pdev = to_pci_dev(dev); 2850 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2851 2852 nvme_reset_ctrl(&ndev->ctrl); 2853 return 0; 2854 } 2855 #endif 2856 2857 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2858 2859 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2860 pci_channel_state_t state) 2861 { 2862 struct nvme_dev *dev = pci_get_drvdata(pdev); 2863 2864 /* 2865 * A frozen channel requires a reset. When detected, this method will 2866 * shutdown the controller to quiesce. The controller will be restarted 2867 * after the slot reset through driver's slot_reset callback. 2868 */ 2869 switch (state) { 2870 case pci_channel_io_normal: 2871 return PCI_ERS_RESULT_CAN_RECOVER; 2872 case pci_channel_io_frozen: 2873 dev_warn(dev->ctrl.device, 2874 "frozen state error detected, reset controller\n"); 2875 nvme_dev_disable(dev, false); 2876 return PCI_ERS_RESULT_NEED_RESET; 2877 case pci_channel_io_perm_failure: 2878 dev_warn(dev->ctrl.device, 2879 "failure state error detected, request disconnect\n"); 2880 return PCI_ERS_RESULT_DISCONNECT; 2881 } 2882 return PCI_ERS_RESULT_NEED_RESET; 2883 } 2884 2885 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2886 { 2887 struct nvme_dev *dev = pci_get_drvdata(pdev); 2888 2889 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2890 pci_restore_state(pdev); 2891 nvme_reset_ctrl(&dev->ctrl); 2892 return PCI_ERS_RESULT_RECOVERED; 2893 } 2894 2895 static void nvme_error_resume(struct pci_dev *pdev) 2896 { 2897 struct nvme_dev *dev = pci_get_drvdata(pdev); 2898 2899 flush_work(&dev->ctrl.reset_work); 2900 } 2901 2902 static const struct pci_error_handlers nvme_err_handler = { 2903 .error_detected = nvme_error_detected, 2904 .slot_reset = nvme_slot_reset, 2905 .resume = nvme_error_resume, 2906 .reset_prepare = nvme_reset_prepare, 2907 .reset_done = nvme_reset_done, 2908 }; 2909 2910 static const struct pci_device_id nvme_id_table[] = { 2911 { PCI_VDEVICE(INTEL, 0x0953), 2912 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2913 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2914 { PCI_VDEVICE(INTEL, 0x0a53), 2915 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2916 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2917 { PCI_VDEVICE(INTEL, 0x0a54), 2918 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2919 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2920 { PCI_VDEVICE(INTEL, 0x0a55), 2921 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2922 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2923 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 2924 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 2925 NVME_QUIRK_MEDIUM_PRIO_SQ }, 2926 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 2927 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2928 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2929 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 2930 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 2931 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 2932 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2933 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 2934 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2935 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 2936 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2937 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2938 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2939 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2940 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2941 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2942 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2943 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2944 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2945 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2946 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2947 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2948 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2949 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2950 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2951 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 2952 { 0, } 2953 }; 2954 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2955 2956 static struct pci_driver nvme_driver = { 2957 .name = "nvme", 2958 .id_table = nvme_id_table, 2959 .probe = nvme_probe, 2960 .remove = nvme_remove, 2961 .shutdown = nvme_shutdown, 2962 .driver = { 2963 .pm = &nvme_dev_pm_ops, 2964 }, 2965 .sriov_configure = pci_sriov_configure_simple, 2966 .err_handler = &nvme_err_handler, 2967 }; 2968 2969 static int __init nvme_init(void) 2970 { 2971 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 2972 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 2973 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 2974 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 2975 return pci_register_driver(&nvme_driver); 2976 } 2977 2978 static void __exit nvme_exit(void) 2979 { 2980 pci_unregister_driver(&nvme_driver); 2981 flush_workqueue(nvme_wq); 2982 } 2983 2984 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2985 MODULE_LICENSE("GPL"); 2986 MODULE_VERSION("1.0"); 2987 module_init(nvme_init); 2988 module_exit(nvme_exit); 2989