1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2011-2014, Intel Corporation. 4 */ 5 6 #ifndef _NVME_H 7 #define _NVME_H 8 9 #include <linux/nvme.h> 10 #include <linux/cdev.h> 11 #include <linux/pci.h> 12 #include <linux/kref.h> 13 #include <linux/blk-mq.h> 14 #include <linux/sed-opal.h> 15 #include <linux/fault-inject.h> 16 #include <linux/rcupdate.h> 17 #include <linux/wait.h> 18 #include <linux/t10-pi.h> 19 #include <linux/ratelimit_types.h> 20 21 #include <trace/events/block.h> 22 23 extern const struct pr_ops nvme_pr_ops; 24 25 extern unsigned int nvme_io_timeout; 26 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 27 28 extern unsigned int admin_timeout; 29 #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) 30 31 #define NVME_DEFAULT_KATO 5 32 33 #ifdef CONFIG_ARCH_NO_SG_CHAIN 34 #define NVME_INLINE_SG_CNT 0 35 #define NVME_INLINE_METADATA_SG_CNT 0 36 #else 37 #define NVME_INLINE_SG_CNT 2 38 #define NVME_INLINE_METADATA_SG_CNT 1 39 #endif 40 41 /* 42 * Default to a 4K page size, with the intention to update this 43 * path in the future to accommodate architectures with differing 44 * kernel and IO page sizes. 45 */ 46 #define NVME_CTRL_PAGE_SHIFT 12 47 #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) 48 49 extern struct workqueue_struct *nvme_wq; 50 extern struct workqueue_struct *nvme_reset_wq; 51 extern struct workqueue_struct *nvme_delete_wq; 52 53 /* 54 * List of workarounds for devices that required behavior not specified in 55 * the standard. 56 */ 57 enum nvme_quirks { 58 /* 59 * Prefers I/O aligned to a stripe size specified in a vendor 60 * specific Identify field. 61 */ 62 NVME_QUIRK_STRIPE_SIZE = (1 << 0), 63 64 /* 65 * The controller doesn't handle Identify value others than 0 or 1 66 * correctly. 67 */ 68 NVME_QUIRK_IDENTIFY_CNS = (1 << 1), 69 70 /* 71 * The controller deterministically returns O's on reads to 72 * logical blocks that deallocate was called on. 73 */ 74 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), 75 76 /* 77 * The controller needs a delay before starts checking the device 78 * readiness, which is done by reading the NVME_CSTS_RDY bit. 79 */ 80 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), 81 82 /* 83 * APST should not be used. 84 */ 85 NVME_QUIRK_NO_APST = (1 << 4), 86 87 /* 88 * The deepest sleep state should not be used. 89 */ 90 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), 91 92 /* 93 * Set MEDIUM priority on SQ creation 94 */ 95 NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), 96 97 /* 98 * Ignore device provided subnqn. 99 */ 100 NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), 101 102 /* 103 * Broken Write Zeroes. 104 */ 105 NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), 106 107 /* 108 * Force simple suspend/resume path. 109 */ 110 NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), 111 112 /* 113 * Use only one interrupt vector for all queues 114 */ 115 NVME_QUIRK_SINGLE_VECTOR = (1 << 11), 116 117 /* 118 * Use non-standard 128 bytes SQEs. 119 */ 120 NVME_QUIRK_128_BYTES_SQES = (1 << 12), 121 122 /* 123 * Prevent tag overlap between queues 124 */ 125 NVME_QUIRK_SHARED_TAGS = (1 << 13), 126 127 /* 128 * Don't change the value of the temperature threshold feature 129 */ 130 NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), 131 132 /* 133 * The controller doesn't handle the Identify Namespace 134 * Identification Descriptor list subcommand despite claiming 135 * NVMe 1.3 compliance. 136 */ 137 NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), 138 139 /* 140 * The controller does not properly handle DMA addresses over 141 * 48 bits. 142 */ 143 NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), 144 145 /* 146 * The controller requires the command_id value be limited, so skip 147 * encoding the generation sequence number. 148 */ 149 NVME_QUIRK_SKIP_CID_GEN = (1 << 17), 150 151 /* 152 * Reports garbage in the namespace identifiers (eui64, nguid, uuid). 153 */ 154 NVME_QUIRK_BOGUS_NID = (1 << 18), 155 156 /* 157 * No temperature thresholds for channels other than 0 (Composite). 158 */ 159 NVME_QUIRK_NO_SECONDARY_TEMP_THRESH = (1 << 19), 160 161 /* 162 * Disables simple suspend/resume path. 163 */ 164 NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND = (1 << 20), 165 }; 166 167 /* 168 * Common request structure for NVMe passthrough. All drivers must have 169 * this structure as the first member of their request-private data. 170 */ 171 struct nvme_request { 172 struct nvme_command *cmd; 173 union nvme_result result; 174 u8 genctr; 175 u8 retries; 176 u8 flags; 177 u16 status; 178 #ifdef CONFIG_NVME_MULTIPATH 179 unsigned long start_time; 180 #endif 181 struct nvme_ctrl *ctrl; 182 }; 183 184 /* 185 * Mark a bio as coming in through the mpath node. 186 */ 187 #define REQ_NVME_MPATH REQ_DRV 188 189 enum { 190 NVME_REQ_CANCELLED = (1 << 0), 191 NVME_REQ_USERCMD = (1 << 1), 192 NVME_MPATH_IO_STATS = (1 << 2), 193 }; 194 195 static inline struct nvme_request *nvme_req(struct request *req) 196 { 197 return blk_mq_rq_to_pdu(req); 198 } 199 200 static inline u16 nvme_req_qid(struct request *req) 201 { 202 if (!req->q->queuedata) 203 return 0; 204 205 return req->mq_hctx->queue_num + 1; 206 } 207 208 /* The below value is the specific amount of delay needed before checking 209 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the 210 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was 211 * found empirically. 212 */ 213 #define NVME_QUIRK_DELAY_AMOUNT 2300 214 215 /* 216 * enum nvme_ctrl_state: Controller state 217 * 218 * @NVME_CTRL_NEW: New controller just allocated, initial state 219 * @NVME_CTRL_LIVE: Controller is connected and I/O capable 220 * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) 221 * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the 222 * transport 223 * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) 224 * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not 225 * disabled/failed immediately. This state comes 226 * after all async event processing took place and 227 * before ns removal and the controller deletion 228 * progress 229 * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during 230 * shutdown or removal. In this case we forcibly 231 * kill all inflight I/O as they have no chance to 232 * complete 233 */ 234 enum nvme_ctrl_state { 235 NVME_CTRL_NEW, 236 NVME_CTRL_LIVE, 237 NVME_CTRL_RESETTING, 238 NVME_CTRL_CONNECTING, 239 NVME_CTRL_DELETING, 240 NVME_CTRL_DELETING_NOIO, 241 NVME_CTRL_DEAD, 242 }; 243 244 struct nvme_fault_inject { 245 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 246 struct fault_attr attr; 247 struct dentry *parent; 248 bool dont_retry; /* DNR, do not retry */ 249 u16 status; /* status code */ 250 #endif 251 }; 252 253 enum nvme_ctrl_flags { 254 NVME_CTRL_FAILFAST_EXPIRED = 0, 255 NVME_CTRL_ADMIN_Q_STOPPED = 1, 256 NVME_CTRL_STARTED_ONCE = 2, 257 NVME_CTRL_STOPPED = 3, 258 NVME_CTRL_SKIP_ID_CNS_CS = 4, 259 NVME_CTRL_DIRTY_CAPABILITY = 5, 260 NVME_CTRL_FROZEN = 6, 261 }; 262 263 struct nvme_ctrl { 264 bool comp_seen; 265 bool identified; 266 enum nvme_ctrl_state state; 267 spinlock_t lock; 268 struct mutex scan_lock; 269 const struct nvme_ctrl_ops *ops; 270 struct request_queue *admin_q; 271 struct request_queue *connect_q; 272 struct request_queue *fabrics_q; 273 struct device *dev; 274 int instance; 275 int numa_node; 276 struct blk_mq_tag_set *tagset; 277 struct blk_mq_tag_set *admin_tagset; 278 struct list_head namespaces; 279 struct rw_semaphore namespaces_rwsem; 280 struct device ctrl_device; 281 struct device *device; /* char device */ 282 #ifdef CONFIG_NVME_HWMON 283 struct device *hwmon_device; 284 #endif 285 struct cdev cdev; 286 struct work_struct reset_work; 287 struct work_struct delete_work; 288 wait_queue_head_t state_wq; 289 290 struct nvme_subsystem *subsys; 291 struct list_head subsys_entry; 292 293 struct opal_dev *opal_dev; 294 295 char name[12]; 296 u16 cntlid; 297 298 u16 mtfa; 299 u32 ctrl_config; 300 u32 queue_count; 301 302 u64 cap; 303 u32 max_hw_sectors; 304 u32 max_segments; 305 u32 max_integrity_segments; 306 u32 max_zeroes_sectors; 307 #ifdef CONFIG_BLK_DEV_ZONED 308 u32 max_zone_append; 309 #endif 310 u16 crdt[3]; 311 u16 oncs; 312 u8 dmrl; 313 u32 dmrsl; 314 u16 oacs; 315 u16 sqsize; 316 u32 max_namespaces; 317 atomic_t abort_limit; 318 u8 vwc; 319 u32 vs; 320 u32 sgls; 321 u16 kas; 322 u8 npss; 323 u8 apsta; 324 u16 wctemp; 325 u16 cctemp; 326 u32 oaes; 327 u32 aen_result; 328 u32 ctratt; 329 unsigned int shutdown_timeout; 330 unsigned int kato; 331 bool subsystem; 332 unsigned long quirks; 333 struct nvme_id_power_state psd[32]; 334 struct nvme_effects_log *effects; 335 struct xarray cels; 336 struct work_struct scan_work; 337 struct work_struct async_event_work; 338 struct delayed_work ka_work; 339 struct delayed_work failfast_work; 340 struct nvme_command ka_cmd; 341 unsigned long ka_last_check_time; 342 struct work_struct fw_act_work; 343 unsigned long events; 344 345 #ifdef CONFIG_NVME_MULTIPATH 346 /* asymmetric namespace access: */ 347 u8 anacap; 348 u8 anatt; 349 u32 anagrpmax; 350 u32 nanagrpid; 351 struct mutex ana_lock; 352 struct nvme_ana_rsp_hdr *ana_log_buf; 353 size_t ana_log_size; 354 struct timer_list anatt_timer; 355 struct work_struct ana_work; 356 #endif 357 358 #ifdef CONFIG_NVME_HOST_AUTH 359 struct work_struct dhchap_auth_work; 360 struct mutex dhchap_auth_mutex; 361 struct nvme_dhchap_queue_context *dhchap_ctxs; 362 struct nvme_dhchap_key *host_key; 363 struct nvme_dhchap_key *ctrl_key; 364 u16 transaction; 365 #endif 366 struct key *tls_key; 367 368 /* Power saving configuration */ 369 u64 ps_max_latency_us; 370 bool apst_enabled; 371 372 /* PCIe only: */ 373 u16 hmmaxd; 374 u32 hmpre; 375 u32 hmmin; 376 u32 hmminds; 377 378 /* Fabrics only */ 379 u32 ioccsz; 380 u32 iorcsz; 381 u16 icdoff; 382 u16 maxcmd; 383 int nr_reconnects; 384 unsigned long flags; 385 struct nvmf_ctrl_options *opts; 386 387 struct page *discard_page; 388 unsigned long discard_page_busy; 389 390 struct nvme_fault_inject fault_inject; 391 392 enum nvme_ctrl_type cntrltype; 393 enum nvme_dctype dctype; 394 }; 395 396 static inline enum nvme_ctrl_state nvme_ctrl_state(struct nvme_ctrl *ctrl) 397 { 398 return READ_ONCE(ctrl->state); 399 } 400 401 enum nvme_iopolicy { 402 NVME_IOPOLICY_NUMA, 403 NVME_IOPOLICY_RR, 404 }; 405 406 struct nvme_subsystem { 407 int instance; 408 struct device dev; 409 /* 410 * Because we unregister the device on the last put we need 411 * a separate refcount. 412 */ 413 struct kref ref; 414 struct list_head entry; 415 struct mutex lock; 416 struct list_head ctrls; 417 struct list_head nsheads; 418 char subnqn[NVMF_NQN_SIZE]; 419 char serial[20]; 420 char model[40]; 421 char firmware_rev[8]; 422 u8 cmic; 423 enum nvme_subsys_type subtype; 424 u16 vendor_id; 425 u16 awupf; /* 0's based awupf value. */ 426 struct ida ns_ida; 427 #ifdef CONFIG_NVME_MULTIPATH 428 enum nvme_iopolicy iopolicy; 429 #endif 430 }; 431 432 /* 433 * Container structure for uniqueue namespace identifiers. 434 */ 435 struct nvme_ns_ids { 436 u8 eui64[8]; 437 u8 nguid[16]; 438 uuid_t uuid; 439 u8 csi; 440 }; 441 442 /* 443 * Anchor structure for namespaces. There is one for each namespace in a 444 * NVMe subsystem that any of our controllers can see, and the namespace 445 * structure for each controller is chained of it. For private namespaces 446 * there is a 1:1 relation to our namespace structures, that is ->list 447 * only ever has a single entry for private namespaces. 448 */ 449 struct nvme_ns_head { 450 struct list_head list; 451 struct srcu_struct srcu; 452 struct nvme_subsystem *subsys; 453 struct nvme_ns_ids ids; 454 struct list_head entry; 455 struct kref ref; 456 bool shared; 457 int instance; 458 struct nvme_effects_log *effects; 459 u64 nuse; 460 unsigned ns_id; 461 int lba_shift; 462 u16 ms; 463 u16 pi_size; 464 u8 pi_type; 465 u8 guard_type; 466 u16 sgs; 467 u32 sws; 468 #ifdef CONFIG_BLK_DEV_ZONED 469 u64 zsze; 470 #endif 471 unsigned long features; 472 473 struct ratelimit_state rs_nuse; 474 475 struct cdev cdev; 476 struct device cdev_device; 477 478 struct gendisk *disk; 479 #ifdef CONFIG_NVME_MULTIPATH 480 struct bio_list requeue_list; 481 spinlock_t requeue_lock; 482 struct work_struct requeue_work; 483 struct mutex lock; 484 unsigned long flags; 485 #define NVME_NSHEAD_DISK_LIVE 0 486 struct nvme_ns __rcu *current_path[]; 487 #endif 488 }; 489 490 static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) 491 { 492 return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; 493 } 494 495 enum nvme_ns_features { 496 NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ 497 NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ 498 NVME_NS_DEAC, /* DEAC bit in Write Zeores supported */ 499 }; 500 501 struct nvme_ns { 502 struct list_head list; 503 504 struct nvme_ctrl *ctrl; 505 struct request_queue *queue; 506 struct gendisk *disk; 507 #ifdef CONFIG_NVME_MULTIPATH 508 enum nvme_ana_state ana_state; 509 u32 ana_grpid; 510 #endif 511 struct list_head siblings; 512 struct kref kref; 513 struct nvme_ns_head *head; 514 515 unsigned long flags; 516 #define NVME_NS_REMOVING 0 517 #define NVME_NS_ANA_PENDING 2 518 #define NVME_NS_FORCE_RO 3 519 #define NVME_NS_READY 4 520 521 struct cdev cdev; 522 struct device cdev_device; 523 524 struct nvme_fault_inject fault_inject; 525 526 }; 527 528 /* NVMe ns supports metadata actions by the controller (generate/strip) */ 529 static inline bool nvme_ns_has_pi(struct nvme_ns_head *head) 530 { 531 return head->pi_type && head->ms == head->pi_size; 532 } 533 534 struct nvme_ctrl_ops { 535 const char *name; 536 struct module *module; 537 unsigned int flags; 538 #define NVME_F_FABRICS (1 << 0) 539 #define NVME_F_METADATA_SUPPORTED (1 << 1) 540 #define NVME_F_BLOCKING (1 << 2) 541 542 const struct attribute_group **dev_attr_groups; 543 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); 544 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); 545 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); 546 void (*free_ctrl)(struct nvme_ctrl *ctrl); 547 void (*submit_async_event)(struct nvme_ctrl *ctrl); 548 void (*delete_ctrl)(struct nvme_ctrl *ctrl); 549 void (*stop_ctrl)(struct nvme_ctrl *ctrl); 550 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); 551 void (*print_device_info)(struct nvme_ctrl *ctrl); 552 bool (*supports_pci_p2pdma)(struct nvme_ctrl *ctrl); 553 }; 554 555 /* 556 * nvme command_id is constructed as such: 557 * | xxxx | xxxxxxxxxxxx | 558 * gen request tag 559 */ 560 #define nvme_genctr_mask(gen) (gen & 0xf) 561 #define nvme_cid_install_genctr(gen) (nvme_genctr_mask(gen) << 12) 562 #define nvme_genctr_from_cid(cid) ((cid & 0xf000) >> 12) 563 #define nvme_tag_from_cid(cid) (cid & 0xfff) 564 565 static inline u16 nvme_cid(struct request *rq) 566 { 567 return nvme_cid_install_genctr(nvme_req(rq)->genctr) | rq->tag; 568 } 569 570 static inline struct request *nvme_find_rq(struct blk_mq_tags *tags, 571 u16 command_id) 572 { 573 u8 genctr = nvme_genctr_from_cid(command_id); 574 u16 tag = nvme_tag_from_cid(command_id); 575 struct request *rq; 576 577 rq = blk_mq_tag_to_rq(tags, tag); 578 if (unlikely(!rq)) { 579 pr_err("could not locate request for tag %#x\n", 580 tag); 581 return NULL; 582 } 583 if (unlikely(nvme_genctr_mask(nvme_req(rq)->genctr) != genctr)) { 584 dev_err(nvme_req(rq)->ctrl->device, 585 "request %#x genctr mismatch (got %#x expected %#x)\n", 586 tag, genctr, nvme_genctr_mask(nvme_req(rq)->genctr)); 587 return NULL; 588 } 589 return rq; 590 } 591 592 static inline struct request *nvme_cid_to_rq(struct blk_mq_tags *tags, 593 u16 command_id) 594 { 595 return blk_mq_tag_to_rq(tags, nvme_tag_from_cid(command_id)); 596 } 597 598 /* 599 * Return the length of the string without the space padding 600 */ 601 static inline int nvme_strlen(char *s, int len) 602 { 603 while (s[len - 1] == ' ') 604 len--; 605 return len; 606 } 607 608 static inline void nvme_print_device_info(struct nvme_ctrl *ctrl) 609 { 610 struct nvme_subsystem *subsys = ctrl->subsys; 611 612 if (ctrl->ops->print_device_info) { 613 ctrl->ops->print_device_info(ctrl); 614 return; 615 } 616 617 dev_err(ctrl->device, 618 "VID:%04x model:%.*s firmware:%.*s\n", subsys->vendor_id, 619 nvme_strlen(subsys->model, sizeof(subsys->model)), 620 subsys->model, nvme_strlen(subsys->firmware_rev, 621 sizeof(subsys->firmware_rev)), 622 subsys->firmware_rev); 623 } 624 625 #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS 626 void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 627 const char *dev_name); 628 void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); 629 void nvme_should_fail(struct request *req); 630 #else 631 static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, 632 const char *dev_name) 633 { 634 } 635 static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) 636 { 637 } 638 static inline void nvme_should_fail(struct request *req) {} 639 #endif 640 641 bool nvme_wait_reset(struct nvme_ctrl *ctrl); 642 int nvme_try_sched_reset(struct nvme_ctrl *ctrl); 643 644 static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) 645 { 646 int ret; 647 648 if (!ctrl->subsystem) 649 return -ENOTTY; 650 if (!nvme_wait_reset(ctrl)) 651 return -EBUSY; 652 653 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); 654 if (ret) 655 return ret; 656 657 return nvme_try_sched_reset(ctrl); 658 } 659 660 /* 661 * Convert a 512B sector number to a device logical block number. 662 */ 663 static inline u64 nvme_sect_to_lba(struct nvme_ns_head *head, sector_t sector) 664 { 665 return sector >> (head->lba_shift - SECTOR_SHIFT); 666 } 667 668 /* 669 * Convert a device logical block number to a 512B sector number. 670 */ 671 static inline sector_t nvme_lba_to_sect(struct nvme_ns_head *head, u64 lba) 672 { 673 return lba << (head->lba_shift - SECTOR_SHIFT); 674 } 675 676 /* 677 * Convert byte length to nvme's 0-based num dwords 678 */ 679 static inline u32 nvme_bytes_to_numd(size_t len) 680 { 681 return (len >> 2) - 1; 682 } 683 684 static inline bool nvme_is_ana_error(u16 status) 685 { 686 switch (status & 0x7ff) { 687 case NVME_SC_ANA_TRANSITION: 688 case NVME_SC_ANA_INACCESSIBLE: 689 case NVME_SC_ANA_PERSISTENT_LOSS: 690 return true; 691 default: 692 return false; 693 } 694 } 695 696 static inline bool nvme_is_path_error(u16 status) 697 { 698 /* check for a status code type of 'path related status' */ 699 return (status & 0x700) == 0x300; 700 } 701 702 /* 703 * Fill in the status and result information from the CQE, and then figure out 704 * if blk-mq will need to use IPI magic to complete the request, and if yes do 705 * so. If not let the caller complete the request without an indirect function 706 * call. 707 */ 708 static inline bool nvme_try_complete_req(struct request *req, __le16 status, 709 union nvme_result result) 710 { 711 struct nvme_request *rq = nvme_req(req); 712 struct nvme_ctrl *ctrl = rq->ctrl; 713 714 if (!(ctrl->quirks & NVME_QUIRK_SKIP_CID_GEN)) 715 rq->genctr++; 716 717 rq->status = le16_to_cpu(status) >> 1; 718 rq->result = result; 719 /* inject error when permitted by fault injection framework */ 720 nvme_should_fail(req); 721 if (unlikely(blk_should_fake_timeout(req->q))) 722 return true; 723 return blk_mq_complete_request_remote(req); 724 } 725 726 static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) 727 { 728 get_device(ctrl->device); 729 } 730 731 static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) 732 { 733 put_device(ctrl->device); 734 } 735 736 static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) 737 { 738 return !qid && 739 nvme_tag_from_cid(command_id) >= NVME_AQ_BLK_MQ_DEPTH; 740 } 741 742 void nvme_complete_rq(struct request *req); 743 void nvme_complete_batch_req(struct request *req); 744 745 static __always_inline void nvme_complete_batch(struct io_comp_batch *iob, 746 void (*fn)(struct request *rq)) 747 { 748 struct request *req; 749 750 rq_list_for_each(&iob->req_list, req) { 751 fn(req); 752 nvme_complete_batch_req(req); 753 } 754 blk_mq_end_request_batch(iob); 755 } 756 757 blk_status_t nvme_host_path_error(struct request *req); 758 bool nvme_cancel_request(struct request *req, void *data); 759 void nvme_cancel_tagset(struct nvme_ctrl *ctrl); 760 void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); 761 bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 762 enum nvme_ctrl_state new_state); 763 int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown); 764 int nvme_enable_ctrl(struct nvme_ctrl *ctrl); 765 int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 766 const struct nvme_ctrl_ops *ops, unsigned long quirks); 767 void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); 768 void nvme_start_ctrl(struct nvme_ctrl *ctrl); 769 void nvme_stop_ctrl(struct nvme_ctrl *ctrl); 770 int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended); 771 int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 772 const struct blk_mq_ops *ops, unsigned int cmd_size); 773 void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl); 774 int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 775 const struct blk_mq_ops *ops, unsigned int nr_maps, 776 unsigned int cmd_size); 777 void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl); 778 779 void nvme_remove_namespaces(struct nvme_ctrl *ctrl); 780 781 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 782 volatile union nvme_result *res); 783 784 void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl); 785 void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl); 786 void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl); 787 void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl); 788 void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl); 789 void nvme_sync_queues(struct nvme_ctrl *ctrl); 790 void nvme_sync_io_queues(struct nvme_ctrl *ctrl); 791 void nvme_unfreeze(struct nvme_ctrl *ctrl); 792 void nvme_wait_freeze(struct nvme_ctrl *ctrl); 793 int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); 794 void nvme_start_freeze(struct nvme_ctrl *ctrl); 795 796 static inline enum req_op nvme_req_op(struct nvme_command *cmd) 797 { 798 return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN; 799 } 800 801 #define NVME_QID_ANY -1 802 void nvme_init_request(struct request *req, struct nvme_command *cmd); 803 void nvme_cleanup_cmd(struct request *req); 804 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); 805 blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 806 struct request *req); 807 bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 808 bool queue_live); 809 810 static inline bool nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 811 bool queue_live) 812 { 813 if (likely(ctrl->state == NVME_CTRL_LIVE)) 814 return true; 815 if (ctrl->ops->flags & NVME_F_FABRICS && 816 ctrl->state == NVME_CTRL_DELETING) 817 return queue_live; 818 return __nvme_check_ready(ctrl, rq, queue_live); 819 } 820 821 /* 822 * NSID shall be unique for all shared namespaces, or if at least one of the 823 * following conditions is met: 824 * 1. Namespace Management is supported by the controller 825 * 2. ANA is supported by the controller 826 * 3. NVM Set are supported by the controller 827 * 828 * In other case, private namespace are not required to report a unique NSID. 829 */ 830 static inline bool nvme_is_unique_nsid(struct nvme_ctrl *ctrl, 831 struct nvme_ns_head *head) 832 { 833 return head->shared || 834 (ctrl->oacs & NVME_CTRL_OACS_NS_MNGT_SUPP) || 835 (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) || 836 (ctrl->ctratt & NVME_CTRL_CTRATT_NVM_SETS); 837 } 838 839 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 840 void *buf, unsigned bufflen); 841 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 842 union nvme_result *result, void *buffer, unsigned bufflen, 843 int qid, int at_head, 844 blk_mq_req_flags_t flags); 845 int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 846 unsigned int dword11, void *buffer, size_t buflen, 847 u32 *result); 848 int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 849 unsigned int dword11, void *buffer, size_t buflen, 850 u32 *result); 851 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); 852 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); 853 int nvme_reset_ctrl(struct nvme_ctrl *ctrl); 854 int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); 855 int nvme_delete_ctrl(struct nvme_ctrl *ctrl); 856 void nvme_queue_scan(struct nvme_ctrl *ctrl); 857 int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 858 void *log, size_t size, u64 offset); 859 bool nvme_tryget_ns_head(struct nvme_ns_head *head); 860 void nvme_put_ns_head(struct nvme_ns_head *head); 861 int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 862 const struct file_operations *fops, struct module *owner); 863 void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device); 864 int nvme_ioctl(struct block_device *bdev, blk_mode_t mode, 865 unsigned int cmd, unsigned long arg); 866 long nvme_ns_chr_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 867 int nvme_ns_head_ioctl(struct block_device *bdev, blk_mode_t mode, 868 unsigned int cmd, unsigned long arg); 869 long nvme_ns_head_chr_ioctl(struct file *file, unsigned int cmd, 870 unsigned long arg); 871 long nvme_dev_ioctl(struct file *file, unsigned int cmd, 872 unsigned long arg); 873 int nvme_ns_chr_uring_cmd_iopoll(struct io_uring_cmd *ioucmd, 874 struct io_comp_batch *iob, unsigned int poll_flags); 875 int nvme_ns_chr_uring_cmd(struct io_uring_cmd *ioucmd, 876 unsigned int issue_flags); 877 int nvme_ns_head_chr_uring_cmd(struct io_uring_cmd *ioucmd, 878 unsigned int issue_flags); 879 int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid, 880 struct nvme_id_ns **id); 881 int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo); 882 int nvme_dev_uring_cmd(struct io_uring_cmd *ioucmd, unsigned int issue_flags); 883 884 extern const struct attribute_group *nvme_ns_attr_groups[]; 885 extern const struct pr_ops nvme_pr_ops; 886 extern const struct block_device_operations nvme_ns_head_ops; 887 extern const struct attribute_group nvme_dev_attrs_group; 888 extern const struct attribute_group *nvme_subsys_attrs_groups[]; 889 extern const struct attribute_group *nvme_dev_attr_groups[]; 890 extern const struct block_device_operations nvme_bdev_ops; 891 892 void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); 893 struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); 894 #ifdef CONFIG_NVME_MULTIPATH 895 static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 896 { 897 return ctrl->ana_log_buf != NULL; 898 } 899 900 void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); 901 void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); 902 void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); 903 void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys); 904 void nvme_failover_req(struct request *req); 905 void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); 906 int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); 907 void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid); 908 void nvme_mpath_remove_disk(struct nvme_ns_head *head); 909 int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); 910 void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl); 911 void nvme_mpath_update(struct nvme_ctrl *ctrl); 912 void nvme_mpath_uninit(struct nvme_ctrl *ctrl); 913 void nvme_mpath_stop(struct nvme_ctrl *ctrl); 914 bool nvme_mpath_clear_current_path(struct nvme_ns *ns); 915 void nvme_mpath_revalidate_paths(struct nvme_ns *ns); 916 void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); 917 void nvme_mpath_shutdown_disk(struct nvme_ns_head *head); 918 void nvme_mpath_start_request(struct request *rq); 919 void nvme_mpath_end_request(struct request *rq); 920 921 static inline void nvme_trace_bio_complete(struct request *req) 922 { 923 struct nvme_ns *ns = req->q->queuedata; 924 925 if ((req->cmd_flags & REQ_NVME_MPATH) && req->bio) 926 trace_block_bio_complete(ns->head->disk->queue, req->bio); 927 } 928 929 extern bool multipath; 930 extern struct device_attribute dev_attr_ana_grpid; 931 extern struct device_attribute dev_attr_ana_state; 932 extern struct device_attribute subsys_attr_iopolicy; 933 934 static inline bool nvme_disk_is_ns_head(struct gendisk *disk) 935 { 936 return disk->fops == &nvme_ns_head_ops; 937 } 938 #else 939 #define multipath false 940 static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) 941 { 942 return false; 943 } 944 static inline void nvme_failover_req(struct request *req) 945 { 946 } 947 static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) 948 { 949 } 950 static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, 951 struct nvme_ns_head *head) 952 { 953 return 0; 954 } 955 static inline void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid) 956 { 957 } 958 static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) 959 { 960 } 961 static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) 962 { 963 return false; 964 } 965 static inline void nvme_mpath_revalidate_paths(struct nvme_ns *ns) 966 { 967 } 968 static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) 969 { 970 } 971 static inline void nvme_mpath_shutdown_disk(struct nvme_ns_head *head) 972 { 973 } 974 static inline void nvme_trace_bio_complete(struct request *req) 975 { 976 } 977 static inline void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl) 978 { 979 } 980 static inline int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, 981 struct nvme_id_ctrl *id) 982 { 983 if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) 984 dev_warn(ctrl->device, 985 "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); 986 return 0; 987 } 988 static inline void nvme_mpath_update(struct nvme_ctrl *ctrl) 989 { 990 } 991 static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) 992 { 993 } 994 static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) 995 { 996 } 997 static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) 998 { 999 } 1000 static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) 1001 { 1002 } 1003 static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) 1004 { 1005 } 1006 static inline void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys) 1007 { 1008 } 1009 static inline void nvme_mpath_start_request(struct request *rq) 1010 { 1011 } 1012 static inline void nvme_mpath_end_request(struct request *rq) 1013 { 1014 } 1015 static inline bool nvme_disk_is_ns_head(struct gendisk *disk) 1016 { 1017 return false; 1018 } 1019 #endif /* CONFIG_NVME_MULTIPATH */ 1020 1021 int nvme_revalidate_zones(struct nvme_ns *ns); 1022 int nvme_ns_report_zones(struct nvme_ns *ns, sector_t sector, 1023 unsigned int nr_zones, report_zones_cb cb, void *data); 1024 #ifdef CONFIG_BLK_DEV_ZONED 1025 int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf); 1026 blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, 1027 struct nvme_command *cmnd, 1028 enum nvme_zone_mgmt_action action); 1029 #else 1030 static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, 1031 struct request *req, struct nvme_command *cmnd, 1032 enum nvme_zone_mgmt_action action) 1033 { 1034 return BLK_STS_NOTSUPP; 1035 } 1036 1037 static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf) 1038 { 1039 dev_warn(ns->ctrl->device, 1040 "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n"); 1041 return -EPROTONOSUPPORT; 1042 } 1043 #endif 1044 1045 static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) 1046 { 1047 struct gendisk *disk = dev_to_disk(dev); 1048 1049 WARN_ON(nvme_disk_is_ns_head(disk)); 1050 return disk->private_data; 1051 } 1052 1053 #ifdef CONFIG_NVME_HWMON 1054 int nvme_hwmon_init(struct nvme_ctrl *ctrl); 1055 void nvme_hwmon_exit(struct nvme_ctrl *ctrl); 1056 #else 1057 static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) 1058 { 1059 return 0; 1060 } 1061 1062 static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) 1063 { 1064 } 1065 #endif 1066 1067 static inline void nvme_start_request(struct request *rq) 1068 { 1069 if (rq->cmd_flags & REQ_NVME_MPATH) 1070 nvme_mpath_start_request(rq); 1071 blk_mq_start_request(rq); 1072 } 1073 1074 static inline bool nvme_ctrl_sgl_supported(struct nvme_ctrl *ctrl) 1075 { 1076 return ctrl->sgls & ((1 << 0) | (1 << 1)); 1077 } 1078 1079 #ifdef CONFIG_NVME_HOST_AUTH 1080 int __init nvme_init_auth(void); 1081 void __exit nvme_exit_auth(void); 1082 int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl); 1083 void nvme_auth_stop(struct nvme_ctrl *ctrl); 1084 int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid); 1085 int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid); 1086 void nvme_auth_free(struct nvme_ctrl *ctrl); 1087 #else 1088 static inline int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl) 1089 { 1090 return 0; 1091 } 1092 static inline int __init nvme_init_auth(void) 1093 { 1094 return 0; 1095 } 1096 static inline void __exit nvme_exit_auth(void) 1097 { 1098 } 1099 static inline void nvme_auth_stop(struct nvme_ctrl *ctrl) {}; 1100 static inline int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid) 1101 { 1102 return -EPROTONOSUPPORT; 1103 } 1104 static inline int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid) 1105 { 1106 return NVME_SC_AUTH_REQUIRED; 1107 } 1108 static inline void nvme_auth_free(struct nvme_ctrl *ctrl) {}; 1109 #endif 1110 1111 u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, 1112 u8 opcode); 1113 u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode); 1114 int nvme_execute_rq(struct request *rq, bool at_head); 1115 void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects, 1116 struct nvme_command *cmd, int status); 1117 struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); 1118 struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); 1119 void nvme_put_ns(struct nvme_ns *ns); 1120 1121 static inline bool nvme_multi_css(struct nvme_ctrl *ctrl) 1122 { 1123 return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI; 1124 } 1125 1126 #ifdef CONFIG_NVME_VERBOSE_ERRORS 1127 const unsigned char *nvme_get_error_status_str(u16 status); 1128 const unsigned char *nvme_get_opcode_str(u8 opcode); 1129 const unsigned char *nvme_get_admin_opcode_str(u8 opcode); 1130 const unsigned char *nvme_get_fabrics_opcode_str(u8 opcode); 1131 #else /* CONFIG_NVME_VERBOSE_ERRORS */ 1132 static inline const unsigned char *nvme_get_error_status_str(u16 status) 1133 { 1134 return "I/O Error"; 1135 } 1136 static inline const unsigned char *nvme_get_opcode_str(u8 opcode) 1137 { 1138 return "I/O Cmd"; 1139 } 1140 static inline const unsigned char *nvme_get_admin_opcode_str(u8 opcode) 1141 { 1142 return "Admin Cmd"; 1143 } 1144 1145 static inline const unsigned char *nvme_get_fabrics_opcode_str(u8 opcode) 1146 { 1147 return "Fabrics Cmd"; 1148 } 1149 #endif /* CONFIG_NVME_VERBOSE_ERRORS */ 1150 1151 static inline const unsigned char *nvme_opcode_str(int qid, u8 opcode, u8 fctype) 1152 { 1153 if (opcode == nvme_fabrics_command) 1154 return nvme_get_fabrics_opcode_str(fctype); 1155 return qid ? nvme_get_opcode_str(opcode) : 1156 nvme_get_admin_opcode_str(opcode); 1157 } 1158 #endif /* _NVME_H */ 1159