1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/async.h> 8 #include <linux/blkdev.h> 9 #include <linux/blk-mq.h> 10 #include <linux/blk-integrity.h> 11 #include <linux/compat.h> 12 #include <linux/delay.h> 13 #include <linux/errno.h> 14 #include <linux/hdreg.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/backing-dev.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 #include <linux/pr.h> 21 #include <linux/ptrace.h> 22 #include <linux/nvme_ioctl.h> 23 #include <linux/pm_qos.h> 24 #include <linux/ratelimit.h> 25 #include <linux/unaligned.h> 26 27 #include "nvme.h" 28 #include "fabrics.h" 29 #include <linux/nvme-auth.h> 30 31 #define CREATE_TRACE_POINTS 32 #include "trace.h" 33 34 #define NVME_MINORS (1U << MINORBITS) 35 36 struct nvme_ns_info { 37 struct nvme_ns_ids ids; 38 u32 nsid; 39 __le32 anagrpid; 40 u8 pi_offset; 41 u16 endgid; 42 u64 runs; 43 bool is_shared; 44 bool is_readonly; 45 bool is_ready; 46 bool is_removed; 47 bool is_rotational; 48 bool no_vwc; 49 }; 50 51 unsigned int admin_timeout = 60; 52 module_param(admin_timeout, uint, 0644); 53 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); 54 EXPORT_SYMBOL_GPL(admin_timeout); 55 56 unsigned int nvme_io_timeout = 30; 57 module_param_named(io_timeout, nvme_io_timeout, uint, 0644); 58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); 59 EXPORT_SYMBOL_GPL(nvme_io_timeout); 60 61 static unsigned char shutdown_timeout = 5; 62 module_param(shutdown_timeout, byte, 0644); 63 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); 64 65 static u8 nvme_max_retries = 5; 66 module_param_named(max_retries, nvme_max_retries, byte, 0644); 67 MODULE_PARM_DESC(max_retries, "max number of retries a command may have"); 68 69 static unsigned long default_ps_max_latency_us = 100000; 70 module_param(default_ps_max_latency_us, ulong, 0644); 71 MODULE_PARM_DESC(default_ps_max_latency_us, 72 "max power saving latency for new devices; use PM QOS to change per device"); 73 74 static bool force_apst; 75 module_param(force_apst, bool, 0644); 76 MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off"); 77 78 static unsigned long apst_primary_timeout_ms = 100; 79 module_param(apst_primary_timeout_ms, ulong, 0644); 80 MODULE_PARM_DESC(apst_primary_timeout_ms, 81 "primary APST timeout in ms"); 82 83 static unsigned long apst_secondary_timeout_ms = 2000; 84 module_param(apst_secondary_timeout_ms, ulong, 0644); 85 MODULE_PARM_DESC(apst_secondary_timeout_ms, 86 "secondary APST timeout in ms"); 87 88 static unsigned long apst_primary_latency_tol_us = 15000; 89 module_param(apst_primary_latency_tol_us, ulong, 0644); 90 MODULE_PARM_DESC(apst_primary_latency_tol_us, 91 "primary APST latency tolerance in us"); 92 93 static unsigned long apst_secondary_latency_tol_us = 100000; 94 module_param(apst_secondary_latency_tol_us, ulong, 0644); 95 MODULE_PARM_DESC(apst_secondary_latency_tol_us, 96 "secondary APST latency tolerance in us"); 97 98 /* 99 * Older kernels didn't enable protection information if it was at an offset. 100 * Newer kernels do, so it breaks reads on the upgrade if such formats were 101 * used in prior kernels since the metadata written did not contain a valid 102 * checksum. 103 */ 104 static bool disable_pi_offsets = false; 105 module_param(disable_pi_offsets, bool, 0444); 106 MODULE_PARM_DESC(disable_pi_offsets, 107 "disable protection information if it has an offset"); 108 109 /* 110 * nvme_wq - hosts nvme related works that are not reset or delete 111 * nvme_reset_wq - hosts nvme reset works 112 * nvme_delete_wq - hosts nvme delete works 113 * 114 * nvme_wq will host works such as scan, aen handling, fw activation, 115 * keep-alive, periodic reconnects etc. nvme_reset_wq 116 * runs reset works which also flush works hosted on nvme_wq for 117 * serialization purposes. nvme_delete_wq host controller deletion 118 * works which flush reset works for serialization. 119 */ 120 struct workqueue_struct *nvme_wq; 121 EXPORT_SYMBOL_GPL(nvme_wq); 122 123 struct workqueue_struct *nvme_reset_wq; 124 EXPORT_SYMBOL_GPL(nvme_reset_wq); 125 126 struct workqueue_struct *nvme_delete_wq; 127 EXPORT_SYMBOL_GPL(nvme_delete_wq); 128 129 static LIST_HEAD(nvme_subsystems); 130 DEFINE_MUTEX(nvme_subsystems_lock); 131 132 static DEFINE_IDA(nvme_instance_ida); 133 static dev_t nvme_ctrl_base_chr_devt; 134 static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env); 135 static const struct class nvme_class = { 136 .name = "nvme", 137 .dev_uevent = nvme_class_uevent, 138 }; 139 140 static const struct class nvme_subsys_class = { 141 .name = "nvme-subsystem", 142 }; 143 144 static DEFINE_IDA(nvme_ns_chr_minor_ida); 145 static dev_t nvme_ns_chr_devt; 146 static const struct class nvme_ns_chr_class = { 147 .name = "nvme-generic", 148 }; 149 150 static void nvme_put_subsystem(struct nvme_subsystem *subsys); 151 static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl, 152 unsigned nsid); 153 static void nvme_update_keep_alive(struct nvme_ctrl *ctrl, 154 struct nvme_command *cmd); 155 static int nvme_get_log_lsi(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, 156 u8 lsp, u8 csi, void *log, size_t size, u64 offset, u16 lsi); 157 158 void nvme_queue_scan(struct nvme_ctrl *ctrl) 159 { 160 /* 161 * Only new queue scan work when admin and IO queues are both alive 162 */ 163 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE && ctrl->tagset) 164 queue_work(nvme_wq, &ctrl->scan_work); 165 } 166 167 /* 168 * Use this function to proceed with scheduling reset_work for a controller 169 * that had previously been set to the resetting state. This is intended for 170 * code paths that can't be interrupted by other reset attempts. A hot removal 171 * may prevent this from succeeding. 172 */ 173 int nvme_try_sched_reset(struct nvme_ctrl *ctrl) 174 { 175 if (nvme_ctrl_state(ctrl) != NVME_CTRL_RESETTING) 176 return -EBUSY; 177 if (!queue_work(nvme_reset_wq, &ctrl->reset_work)) 178 return -EBUSY; 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(nvme_try_sched_reset); 182 183 static void nvme_failfast_work(struct work_struct *work) 184 { 185 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work), 186 struct nvme_ctrl, failfast_work); 187 188 if (nvme_ctrl_state(ctrl) != NVME_CTRL_CONNECTING) 189 return; 190 191 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); 192 dev_info(ctrl->device, "failfast expired\n"); 193 nvme_kick_requeue_lists(ctrl); 194 } 195 196 static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl) 197 { 198 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1) 199 return; 200 201 schedule_delayed_work(&ctrl->failfast_work, 202 ctrl->opts->fast_io_fail_tmo * HZ); 203 } 204 205 static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl) 206 { 207 if (!ctrl->opts) 208 return; 209 210 cancel_delayed_work_sync(&ctrl->failfast_work); 211 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); 212 } 213 214 215 int nvme_reset_ctrl(struct nvme_ctrl *ctrl) 216 { 217 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) 218 return -EBUSY; 219 if (!queue_work(nvme_reset_wq, &ctrl->reset_work)) 220 return -EBUSY; 221 return 0; 222 } 223 EXPORT_SYMBOL_GPL(nvme_reset_ctrl); 224 225 int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl) 226 { 227 int ret; 228 229 ret = nvme_reset_ctrl(ctrl); 230 if (!ret) { 231 flush_work(&ctrl->reset_work); 232 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE) 233 ret = -ENETRESET; 234 } 235 236 return ret; 237 } 238 239 static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl) 240 { 241 dev_info(ctrl->device, 242 "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl)); 243 244 flush_work(&ctrl->reset_work); 245 nvme_stop_ctrl(ctrl); 246 nvme_remove_namespaces(ctrl); 247 ctrl->ops->delete_ctrl(ctrl); 248 nvme_uninit_ctrl(ctrl); 249 } 250 251 static void nvme_delete_ctrl_work(struct work_struct *work) 252 { 253 struct nvme_ctrl *ctrl = 254 container_of(work, struct nvme_ctrl, delete_work); 255 256 nvme_do_delete_ctrl(ctrl); 257 } 258 259 int nvme_delete_ctrl(struct nvme_ctrl *ctrl) 260 { 261 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING)) 262 return -EBUSY; 263 if (!queue_work(nvme_delete_wq, &ctrl->delete_work)) 264 return -EBUSY; 265 return 0; 266 } 267 EXPORT_SYMBOL_GPL(nvme_delete_ctrl); 268 269 void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl) 270 { 271 /* 272 * Keep a reference until nvme_do_delete_ctrl() complete, 273 * since ->delete_ctrl can free the controller. 274 */ 275 nvme_get_ctrl(ctrl); 276 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING)) 277 nvme_do_delete_ctrl(ctrl); 278 nvme_put_ctrl(ctrl); 279 } 280 281 static blk_status_t nvme_error_status(u16 status) 282 { 283 switch (status & NVME_SCT_SC_MASK) { 284 case NVME_SC_SUCCESS: 285 return BLK_STS_OK; 286 case NVME_SC_CAP_EXCEEDED: 287 return BLK_STS_NOSPC; 288 case NVME_SC_LBA_RANGE: 289 case NVME_SC_CMD_INTERRUPTED: 290 case NVME_SC_NS_NOT_READY: 291 return BLK_STS_TARGET; 292 case NVME_SC_BAD_ATTRIBUTES: 293 case NVME_SC_ONCS_NOT_SUPPORTED: 294 case NVME_SC_INVALID_OPCODE: 295 case NVME_SC_INVALID_FIELD: 296 case NVME_SC_INVALID_NS: 297 return BLK_STS_NOTSUPP; 298 case NVME_SC_WRITE_FAULT: 299 case NVME_SC_READ_ERROR: 300 case NVME_SC_UNWRITTEN_BLOCK: 301 case NVME_SC_ACCESS_DENIED: 302 case NVME_SC_READ_ONLY: 303 case NVME_SC_COMPARE_FAILED: 304 return BLK_STS_MEDIUM; 305 case NVME_SC_GUARD_CHECK: 306 case NVME_SC_APPTAG_CHECK: 307 case NVME_SC_REFTAG_CHECK: 308 case NVME_SC_INVALID_PI: 309 return BLK_STS_PROTECTION; 310 case NVME_SC_RESERVATION_CONFLICT: 311 return BLK_STS_RESV_CONFLICT; 312 case NVME_SC_HOST_PATH_ERROR: 313 return BLK_STS_TRANSPORT; 314 case NVME_SC_ZONE_TOO_MANY_ACTIVE: 315 return BLK_STS_ZONE_ACTIVE_RESOURCE; 316 case NVME_SC_ZONE_TOO_MANY_OPEN: 317 return BLK_STS_ZONE_OPEN_RESOURCE; 318 default: 319 return BLK_STS_IOERR; 320 } 321 } 322 323 static void nvme_retry_req(struct request *req) 324 { 325 unsigned long delay = 0; 326 u16 crd; 327 328 /* The mask and shift result must be <= 3 */ 329 crd = (nvme_req(req)->status & NVME_STATUS_CRD) >> 11; 330 if (crd) 331 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100; 332 333 nvme_req(req)->retries++; 334 blk_mq_requeue_request(req, false); 335 blk_mq_delay_kick_requeue_list(req->q, delay); 336 } 337 338 static void nvme_log_error(struct request *req) 339 { 340 struct nvme_ns *ns = req->q->queuedata; 341 struct nvme_request *nr = nvme_req(req); 342 343 if (ns) { 344 pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %u blocks, %s (sct 0x%x / sc 0x%x) %s%s\n", 345 ns->disk ? ns->disk->disk_name : "?", 346 nvme_get_opcode_str(nr->cmd->common.opcode), 347 nr->cmd->common.opcode, 348 nvme_sect_to_lba(ns->head, blk_rq_pos(req)), 349 blk_rq_bytes(req) >> ns->head->lba_shift, 350 nvme_get_error_status_str(nr->status), 351 NVME_SCT(nr->status), /* Status Code Type */ 352 nr->status & NVME_SC_MASK, /* Status Code */ 353 nr->status & NVME_STATUS_MORE ? "MORE " : "", 354 nr->status & NVME_STATUS_DNR ? "DNR " : ""); 355 return; 356 } 357 358 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n", 359 dev_name(nr->ctrl->device), 360 nvme_get_admin_opcode_str(nr->cmd->common.opcode), 361 nr->cmd->common.opcode, 362 nvme_get_error_status_str(nr->status), 363 NVME_SCT(nr->status), /* Status Code Type */ 364 nr->status & NVME_SC_MASK, /* Status Code */ 365 nr->status & NVME_STATUS_MORE ? "MORE " : "", 366 nr->status & NVME_STATUS_DNR ? "DNR " : ""); 367 } 368 369 static void nvme_log_err_passthru(struct request *req) 370 { 371 struct nvme_ns *ns = req->q->queuedata; 372 struct nvme_request *nr = nvme_req(req); 373 374 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s" 375 "cdw10=0x%x cdw11=0x%x cdw12=0x%x cdw13=0x%x cdw14=0x%x cdw15=0x%x\n", 376 ns ? ns->disk->disk_name : dev_name(nr->ctrl->device), 377 ns ? nvme_get_opcode_str(nr->cmd->common.opcode) : 378 nvme_get_admin_opcode_str(nr->cmd->common.opcode), 379 nr->cmd->common.opcode, 380 nvme_get_error_status_str(nr->status), 381 NVME_SCT(nr->status), /* Status Code Type */ 382 nr->status & NVME_SC_MASK, /* Status Code */ 383 nr->status & NVME_STATUS_MORE ? "MORE " : "", 384 nr->status & NVME_STATUS_DNR ? "DNR " : "", 385 nr->cmd->common.cdw10, 386 nr->cmd->common.cdw11, 387 nr->cmd->common.cdw12, 388 nr->cmd->common.cdw13, 389 nr->cmd->common.cdw14, 390 nr->cmd->common.cdw14); 391 } 392 393 enum nvme_disposition { 394 COMPLETE, 395 RETRY, 396 FAILOVER, 397 AUTHENTICATE, 398 }; 399 400 static inline enum nvme_disposition nvme_decide_disposition(struct request *req) 401 { 402 if (likely(nvme_req(req)->status == 0)) 403 return COMPLETE; 404 405 if (blk_noretry_request(req) || 406 (nvme_req(req)->status & NVME_STATUS_DNR) || 407 nvme_req(req)->retries >= nvme_max_retries) 408 return COMPLETE; 409 410 if ((nvme_req(req)->status & NVME_SCT_SC_MASK) == NVME_SC_AUTH_REQUIRED) 411 return AUTHENTICATE; 412 413 if (req->cmd_flags & REQ_NVME_MPATH) { 414 if (nvme_is_path_error(nvme_req(req)->status) || 415 blk_queue_dying(req->q)) 416 return FAILOVER; 417 } else { 418 if (blk_queue_dying(req->q)) 419 return COMPLETE; 420 } 421 422 return RETRY; 423 } 424 425 static inline void nvme_end_req_zoned(struct request *req) 426 { 427 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) && 428 req_op(req) == REQ_OP_ZONE_APPEND) { 429 struct nvme_ns *ns = req->q->queuedata; 430 431 req->__sector = nvme_lba_to_sect(ns->head, 432 le64_to_cpu(nvme_req(req)->result.u64)); 433 } 434 } 435 436 static inline void __nvme_end_req(struct request *req) 437 { 438 if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) { 439 if (blk_rq_is_passthrough(req)) 440 nvme_log_err_passthru(req); 441 else 442 nvme_log_error(req); 443 } 444 nvme_end_req_zoned(req); 445 nvme_trace_bio_complete(req); 446 if (req->cmd_flags & REQ_NVME_MPATH) 447 nvme_mpath_end_request(req); 448 } 449 450 void nvme_end_req(struct request *req) 451 { 452 blk_status_t status = nvme_error_status(nvme_req(req)->status); 453 454 __nvme_end_req(req); 455 blk_mq_end_request(req, status); 456 } 457 458 void nvme_complete_rq(struct request *req) 459 { 460 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; 461 462 trace_nvme_complete_rq(req); 463 nvme_cleanup_cmd(req); 464 465 /* 466 * Completions of long-running commands should not be able to 467 * defer sending of periodic keep alives, since the controller 468 * may have completed processing such commands a long time ago 469 * (arbitrarily close to command submission time). 470 * req->deadline - req->timeout is the command submission time 471 * in jiffies. 472 */ 473 if (ctrl->kas && 474 req->deadline - req->timeout >= ctrl->ka_last_check_time) 475 ctrl->comp_seen = true; 476 477 switch (nvme_decide_disposition(req)) { 478 case COMPLETE: 479 nvme_end_req(req); 480 return; 481 case RETRY: 482 nvme_retry_req(req); 483 return; 484 case FAILOVER: 485 nvme_failover_req(req); 486 return; 487 case AUTHENTICATE: 488 #ifdef CONFIG_NVME_HOST_AUTH 489 queue_work(nvme_wq, &ctrl->dhchap_auth_work); 490 nvme_retry_req(req); 491 #else 492 nvme_end_req(req); 493 #endif 494 return; 495 } 496 } 497 EXPORT_SYMBOL_GPL(nvme_complete_rq); 498 499 void nvme_complete_batch_req(struct request *req) 500 { 501 trace_nvme_complete_rq(req); 502 nvme_cleanup_cmd(req); 503 __nvme_end_req(req); 504 } 505 EXPORT_SYMBOL_GPL(nvme_complete_batch_req); 506 507 /* 508 * Called to unwind from ->queue_rq on a failed command submission so that the 509 * multipathing code gets called to potentially failover to another path. 510 * The caller needs to unwind all transport specific resource allocations and 511 * must return propagate the return value. 512 */ 513 blk_status_t nvme_host_path_error(struct request *req) 514 { 515 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR; 516 blk_mq_set_request_complete(req); 517 nvme_complete_rq(req); 518 return BLK_STS_OK; 519 } 520 EXPORT_SYMBOL_GPL(nvme_host_path_error); 521 522 bool nvme_cancel_request(struct request *req, void *data) 523 { 524 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device, 525 "Cancelling I/O %d", req->tag); 526 527 /* don't abort one completed or idle request */ 528 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) 529 return true; 530 531 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD; 532 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 533 blk_mq_complete_request(req); 534 return true; 535 } 536 EXPORT_SYMBOL_GPL(nvme_cancel_request); 537 538 void nvme_cancel_tagset(struct nvme_ctrl *ctrl) 539 { 540 if (ctrl->tagset) { 541 blk_mq_tagset_busy_iter(ctrl->tagset, 542 nvme_cancel_request, ctrl); 543 blk_mq_tagset_wait_completed_request(ctrl->tagset); 544 } 545 } 546 EXPORT_SYMBOL_GPL(nvme_cancel_tagset); 547 548 void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl) 549 { 550 if (ctrl->admin_tagset) { 551 blk_mq_tagset_busy_iter(ctrl->admin_tagset, 552 nvme_cancel_request, ctrl); 553 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset); 554 } 555 } 556 EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset); 557 558 bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, 559 enum nvme_ctrl_state new_state) 560 { 561 enum nvme_ctrl_state old_state; 562 unsigned long flags; 563 bool changed = false; 564 565 spin_lock_irqsave(&ctrl->lock, flags); 566 567 old_state = nvme_ctrl_state(ctrl); 568 switch (new_state) { 569 case NVME_CTRL_LIVE: 570 switch (old_state) { 571 case NVME_CTRL_CONNECTING: 572 changed = true; 573 fallthrough; 574 default: 575 break; 576 } 577 break; 578 case NVME_CTRL_RESETTING: 579 switch (old_state) { 580 case NVME_CTRL_NEW: 581 case NVME_CTRL_LIVE: 582 changed = true; 583 fallthrough; 584 default: 585 break; 586 } 587 break; 588 case NVME_CTRL_CONNECTING: 589 switch (old_state) { 590 case NVME_CTRL_NEW: 591 case NVME_CTRL_RESETTING: 592 changed = true; 593 fallthrough; 594 default: 595 break; 596 } 597 break; 598 case NVME_CTRL_DELETING: 599 switch (old_state) { 600 case NVME_CTRL_LIVE: 601 case NVME_CTRL_RESETTING: 602 case NVME_CTRL_CONNECTING: 603 changed = true; 604 fallthrough; 605 default: 606 break; 607 } 608 break; 609 case NVME_CTRL_DELETING_NOIO: 610 switch (old_state) { 611 case NVME_CTRL_DELETING: 612 case NVME_CTRL_DEAD: 613 changed = true; 614 fallthrough; 615 default: 616 break; 617 } 618 break; 619 case NVME_CTRL_DEAD: 620 switch (old_state) { 621 case NVME_CTRL_DELETING: 622 changed = true; 623 fallthrough; 624 default: 625 break; 626 } 627 break; 628 default: 629 break; 630 } 631 632 if (changed) { 633 WRITE_ONCE(ctrl->state, new_state); 634 wake_up_all(&ctrl->state_wq); 635 } 636 637 spin_unlock_irqrestore(&ctrl->lock, flags); 638 if (!changed) 639 return false; 640 641 if (new_state == NVME_CTRL_LIVE) { 642 if (old_state == NVME_CTRL_CONNECTING) 643 nvme_stop_failfast_work(ctrl); 644 nvme_kick_requeue_lists(ctrl); 645 } else if (new_state == NVME_CTRL_CONNECTING && 646 old_state == NVME_CTRL_RESETTING) { 647 nvme_start_failfast_work(ctrl); 648 } 649 return changed; 650 } 651 EXPORT_SYMBOL_GPL(nvme_change_ctrl_state); 652 653 /* 654 * Waits for the controller state to be resetting, or returns false if it is 655 * not possible to ever transition to that state. 656 */ 657 bool nvme_wait_reset(struct nvme_ctrl *ctrl) 658 { 659 wait_event(ctrl->state_wq, 660 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) || 661 nvme_state_terminal(ctrl)); 662 return nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING; 663 } 664 EXPORT_SYMBOL_GPL(nvme_wait_reset); 665 666 static void nvme_free_ns_head(struct kref *ref) 667 { 668 struct nvme_ns_head *head = 669 container_of(ref, struct nvme_ns_head, ref); 670 671 nvme_mpath_put_disk(head); 672 ida_free(&head->subsys->ns_ida, head->instance); 673 cleanup_srcu_struct(&head->srcu); 674 nvme_put_subsystem(head->subsys); 675 kfree(head->plids); 676 kfree(head); 677 } 678 679 bool nvme_tryget_ns_head(struct nvme_ns_head *head) 680 { 681 return kref_get_unless_zero(&head->ref); 682 } 683 684 void nvme_put_ns_head(struct nvme_ns_head *head) 685 { 686 kref_put(&head->ref, nvme_free_ns_head); 687 } 688 689 static void nvme_free_ns(struct kref *kref) 690 { 691 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref); 692 693 put_disk(ns->disk); 694 nvme_put_ns_head(ns->head); 695 nvme_put_ctrl(ns->ctrl); 696 kfree(ns); 697 } 698 699 bool nvme_get_ns(struct nvme_ns *ns) 700 { 701 return kref_get_unless_zero(&ns->kref); 702 } 703 704 void nvme_put_ns(struct nvme_ns *ns) 705 { 706 kref_put(&ns->kref, nvme_free_ns); 707 } 708 EXPORT_SYMBOL_NS_GPL(nvme_put_ns, "NVME_TARGET_PASSTHRU"); 709 710 static inline void nvme_clear_nvme_request(struct request *req) 711 { 712 nvme_req(req)->status = 0; 713 nvme_req(req)->retries = 0; 714 nvme_req(req)->flags = 0; 715 req->rq_flags |= RQF_DONTPREP; 716 } 717 718 /* initialize a passthrough request */ 719 void nvme_init_request(struct request *req, struct nvme_command *cmd) 720 { 721 struct nvme_request *nr = nvme_req(req); 722 bool logging_enabled; 723 724 if (req->q->queuedata) { 725 struct nvme_ns *ns = req->q->disk->private_data; 726 727 logging_enabled = ns->head->passthru_err_log_enabled; 728 req->timeout = NVME_IO_TIMEOUT; 729 } else { /* no queuedata implies admin queue */ 730 logging_enabled = nr->ctrl->passthru_err_log_enabled; 731 req->timeout = NVME_ADMIN_TIMEOUT; 732 } 733 734 if (!logging_enabled) 735 req->rq_flags |= RQF_QUIET; 736 737 /* passthru commands should let the driver set the SGL flags */ 738 cmd->common.flags &= ~NVME_CMD_SGL_ALL; 739 740 req->cmd_flags |= REQ_FAILFAST_DRIVER; 741 if (req->mq_hctx->type == HCTX_TYPE_POLL) 742 req->cmd_flags |= REQ_POLLED; 743 nvme_clear_nvme_request(req); 744 memcpy(nr->cmd, cmd, sizeof(*cmd)); 745 } 746 EXPORT_SYMBOL_GPL(nvme_init_request); 747 748 /* 749 * For something we're not in a state to send to the device the default action 750 * is to busy it and retry it after the controller state is recovered. However, 751 * if the controller is deleting or if anything is marked for failfast or 752 * nvme multipath it is immediately failed. 753 * 754 * Note: commands used to initialize the controller will be marked for failfast. 755 * Note: nvme cli/ioctl commands are marked for failfast. 756 */ 757 blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, 758 struct request *rq) 759 { 760 enum nvme_ctrl_state state = nvme_ctrl_state(ctrl); 761 762 if (state != NVME_CTRL_DELETING_NOIO && 763 state != NVME_CTRL_DELETING && 764 state != NVME_CTRL_DEAD && 765 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) && 766 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH)) 767 return BLK_STS_RESOURCE; 768 return nvme_host_path_error(rq); 769 } 770 EXPORT_SYMBOL_GPL(nvme_fail_nonready_command); 771 772 bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, 773 bool queue_live, enum nvme_ctrl_state state) 774 { 775 struct nvme_request *req = nvme_req(rq); 776 777 /* 778 * currently we have a problem sending passthru commands 779 * on the admin_q if the controller is not LIVE because we can't 780 * make sure that they are going out after the admin connect, 781 * controller enable and/or other commands in the initialization 782 * sequence. until the controller will be LIVE, fail with 783 * BLK_STS_RESOURCE so that they will be rescheduled. 784 */ 785 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD)) 786 return false; 787 788 if (ctrl->ops->flags & NVME_F_FABRICS) { 789 /* 790 * Only allow commands on a live queue, except for the connect 791 * command, which is require to set the queue live in the 792 * appropinquate states. 793 */ 794 switch (state) { 795 case NVME_CTRL_CONNECTING: 796 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) && 797 (req->cmd->fabrics.fctype == nvme_fabrics_type_connect || 798 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send || 799 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive)) 800 return true; 801 break; 802 default: 803 break; 804 case NVME_CTRL_DEAD: 805 return false; 806 } 807 } 808 809 return queue_live; 810 } 811 EXPORT_SYMBOL_GPL(__nvme_check_ready); 812 813 static inline void nvme_setup_flush(struct nvme_ns *ns, 814 struct nvme_command *cmnd) 815 { 816 memset(cmnd, 0, sizeof(*cmnd)); 817 cmnd->common.opcode = nvme_cmd_flush; 818 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id); 819 } 820 821 static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req, 822 struct nvme_command *cmnd) 823 { 824 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0; 825 struct nvme_dsm_range *range; 826 struct bio *bio; 827 828 /* 829 * Some devices do not consider the DSM 'Number of Ranges' field when 830 * determining how much data to DMA. Always allocate memory for maximum 831 * number of segments to prevent device reading beyond end of buffer. 832 */ 833 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES; 834 835 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN); 836 if (!range) { 837 /* 838 * If we fail allocation our range, fallback to the controller 839 * discard page. If that's also busy, it's safe to return 840 * busy, as we know we can make progress once that's freed. 841 */ 842 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy)) 843 return BLK_STS_RESOURCE; 844 845 range = page_address(ns->ctrl->discard_page); 846 } 847 848 if (queue_max_discard_segments(req->q) == 1) { 849 u64 slba = nvme_sect_to_lba(ns->head, blk_rq_pos(req)); 850 u32 nlb = blk_rq_sectors(req) >> (ns->head->lba_shift - 9); 851 852 range[0].cattr = cpu_to_le32(0); 853 range[0].nlb = cpu_to_le32(nlb); 854 range[0].slba = cpu_to_le64(slba); 855 n = 1; 856 } else { 857 __rq_for_each_bio(bio, req) { 858 u64 slba = nvme_sect_to_lba(ns->head, 859 bio->bi_iter.bi_sector); 860 u32 nlb = bio->bi_iter.bi_size >> ns->head->lba_shift; 861 862 if (n < segments) { 863 range[n].cattr = cpu_to_le32(0); 864 range[n].nlb = cpu_to_le32(nlb); 865 range[n].slba = cpu_to_le64(slba); 866 } 867 n++; 868 } 869 } 870 871 if (WARN_ON_ONCE(n != segments)) { 872 if (virt_to_page(range) == ns->ctrl->discard_page) 873 clear_bit_unlock(0, &ns->ctrl->discard_page_busy); 874 else 875 kfree(range); 876 return BLK_STS_IOERR; 877 } 878 879 memset(cmnd, 0, sizeof(*cmnd)); 880 cmnd->dsm.opcode = nvme_cmd_dsm; 881 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id); 882 cmnd->dsm.nr = cpu_to_le32(segments - 1); 883 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); 884 885 bvec_set_virt(&req->special_vec, range, alloc_size); 886 req->rq_flags |= RQF_SPECIAL_PAYLOAD; 887 888 return BLK_STS_OK; 889 } 890 891 static void nvme_set_app_tag(struct request *req, struct nvme_command *cmnd) 892 { 893 cmnd->rw.lbat = cpu_to_le16(bio_integrity(req->bio)->app_tag); 894 cmnd->rw.lbatm = cpu_to_le16(0xffff); 895 } 896 897 static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd, 898 struct request *req) 899 { 900 u32 upper, lower; 901 u64 ref48; 902 903 /* both rw and write zeroes share the same reftag format */ 904 switch (ns->head->guard_type) { 905 case NVME_NVM_NS_16B_GUARD: 906 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req)); 907 break; 908 case NVME_NVM_NS_64B_GUARD: 909 ref48 = ext_pi_ref_tag(req); 910 lower = lower_32_bits(ref48); 911 upper = upper_32_bits(ref48); 912 913 cmnd->rw.reftag = cpu_to_le32(lower); 914 cmnd->rw.cdw3 = cpu_to_le32(upper); 915 break; 916 default: 917 break; 918 } 919 } 920 921 static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns, 922 struct request *req, struct nvme_command *cmnd) 923 { 924 memset(cmnd, 0, sizeof(*cmnd)); 925 926 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) 927 return nvme_setup_discard(ns, req, cmnd); 928 929 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes; 930 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id); 931 cmnd->write_zeroes.slba = 932 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req))); 933 cmnd->write_zeroes.length = 934 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1); 935 936 if (!(req->cmd_flags & REQ_NOUNMAP) && 937 (ns->head->features & NVME_NS_DEAC)) 938 cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC); 939 940 if (nvme_ns_has_pi(ns->head)) { 941 cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT); 942 943 switch (ns->head->pi_type) { 944 case NVME_NS_DPS_PI_TYPE1: 945 case NVME_NS_DPS_PI_TYPE2: 946 nvme_set_ref_tag(ns, cmnd, req); 947 break; 948 } 949 } 950 951 return BLK_STS_OK; 952 } 953 954 /* 955 * NVMe does not support a dedicated command to issue an atomic write. A write 956 * which does adhere to the device atomic limits will silently be executed 957 * non-atomically. The request issuer should ensure that the write is within 958 * the queue atomic writes limits, but just validate this in case it is not. 959 */ 960 static bool nvme_valid_atomic_write(struct request *req) 961 { 962 struct request_queue *q = req->q; 963 u32 boundary_bytes = queue_atomic_write_boundary_bytes(q); 964 965 if (blk_rq_bytes(req) > queue_atomic_write_unit_max_bytes(q)) 966 return false; 967 968 if (boundary_bytes) { 969 u64 mask = boundary_bytes - 1, imask = ~mask; 970 u64 start = blk_rq_pos(req) << SECTOR_SHIFT; 971 u64 end = start + blk_rq_bytes(req) - 1; 972 973 /* If greater then must be crossing a boundary */ 974 if (blk_rq_bytes(req) > boundary_bytes) 975 return false; 976 977 if ((start & imask) != (end & imask)) 978 return false; 979 } 980 981 return true; 982 } 983 984 static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns, 985 struct request *req, struct nvme_command *cmnd, 986 enum nvme_opcode op) 987 { 988 u16 control = 0; 989 u32 dsmgmt = 0; 990 991 if (req->cmd_flags & REQ_FUA) 992 control |= NVME_RW_FUA; 993 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) 994 control |= NVME_RW_LR; 995 996 if (req->cmd_flags & REQ_RAHEAD) 997 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; 998 999 if (op == nvme_cmd_write && ns->head->nr_plids) { 1000 u16 write_stream = req->bio->bi_write_stream; 1001 1002 if (WARN_ON_ONCE(write_stream > ns->head->nr_plids)) 1003 return BLK_STS_INVAL; 1004 1005 if (write_stream) { 1006 dsmgmt |= ns->head->plids[write_stream - 1] << 16; 1007 control |= NVME_RW_DTYPE_DPLCMT; 1008 } 1009 } 1010 1011 if (req->cmd_flags & REQ_ATOMIC && !nvme_valid_atomic_write(req)) 1012 return BLK_STS_INVAL; 1013 1014 cmnd->rw.opcode = op; 1015 cmnd->rw.flags = 0; 1016 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id); 1017 cmnd->rw.cdw2 = 0; 1018 cmnd->rw.cdw3 = 0; 1019 cmnd->rw.metadata = 0; 1020 cmnd->rw.slba = 1021 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req))); 1022 cmnd->rw.length = 1023 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1); 1024 cmnd->rw.reftag = 0; 1025 cmnd->rw.lbat = 0; 1026 cmnd->rw.lbatm = 0; 1027 1028 if (ns->head->ms) { 1029 /* 1030 * If formated with metadata, the block layer always provides a 1031 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else 1032 * we enable the PRACT bit for protection information or set the 1033 * namespace capacity to zero to prevent any I/O. 1034 */ 1035 if (!blk_integrity_rq(req)) { 1036 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns->head))) 1037 return BLK_STS_NOTSUPP; 1038 control |= NVME_RW_PRINFO_PRACT; 1039 } 1040 1041 if (bio_integrity_flagged(req->bio, BIP_CHECK_GUARD)) 1042 control |= NVME_RW_PRINFO_PRCHK_GUARD; 1043 if (bio_integrity_flagged(req->bio, BIP_CHECK_REFTAG)) { 1044 control |= NVME_RW_PRINFO_PRCHK_REF; 1045 if (op == nvme_cmd_zone_append) 1046 control |= NVME_RW_APPEND_PIREMAP; 1047 nvme_set_ref_tag(ns, cmnd, req); 1048 } 1049 if (bio_integrity_flagged(req->bio, BIP_CHECK_APPTAG)) { 1050 control |= NVME_RW_PRINFO_PRCHK_APP; 1051 nvme_set_app_tag(req, cmnd); 1052 } 1053 } 1054 1055 cmnd->rw.control = cpu_to_le16(control); 1056 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); 1057 return 0; 1058 } 1059 1060 void nvme_cleanup_cmd(struct request *req) 1061 { 1062 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { 1063 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; 1064 1065 if (req->special_vec.bv_page == ctrl->discard_page) 1066 clear_bit_unlock(0, &ctrl->discard_page_busy); 1067 else 1068 kfree(bvec_virt(&req->special_vec)); 1069 req->rq_flags &= ~RQF_SPECIAL_PAYLOAD; 1070 } 1071 } 1072 EXPORT_SYMBOL_GPL(nvme_cleanup_cmd); 1073 1074 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req) 1075 { 1076 struct nvme_command *cmd = nvme_req(req)->cmd; 1077 blk_status_t ret = BLK_STS_OK; 1078 1079 if (!(req->rq_flags & RQF_DONTPREP)) 1080 nvme_clear_nvme_request(req); 1081 1082 switch (req_op(req)) { 1083 case REQ_OP_DRV_IN: 1084 case REQ_OP_DRV_OUT: 1085 /* these are setup prior to execution in nvme_init_request() */ 1086 break; 1087 case REQ_OP_FLUSH: 1088 nvme_setup_flush(ns, cmd); 1089 break; 1090 case REQ_OP_ZONE_RESET_ALL: 1091 case REQ_OP_ZONE_RESET: 1092 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET); 1093 break; 1094 case REQ_OP_ZONE_OPEN: 1095 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN); 1096 break; 1097 case REQ_OP_ZONE_CLOSE: 1098 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE); 1099 break; 1100 case REQ_OP_ZONE_FINISH: 1101 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH); 1102 break; 1103 case REQ_OP_WRITE_ZEROES: 1104 ret = nvme_setup_write_zeroes(ns, req, cmd); 1105 break; 1106 case REQ_OP_DISCARD: 1107 ret = nvme_setup_discard(ns, req, cmd); 1108 break; 1109 case REQ_OP_READ: 1110 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read); 1111 break; 1112 case REQ_OP_WRITE: 1113 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write); 1114 break; 1115 case REQ_OP_ZONE_APPEND: 1116 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append); 1117 break; 1118 default: 1119 WARN_ON_ONCE(1); 1120 return BLK_STS_IOERR; 1121 } 1122 1123 cmd->common.command_id = nvme_cid(req); 1124 trace_nvme_setup_cmd(req, cmd); 1125 return ret; 1126 } 1127 EXPORT_SYMBOL_GPL(nvme_setup_cmd); 1128 1129 /* 1130 * Return values: 1131 * 0: success 1132 * >0: nvme controller's cqe status response 1133 * <0: kernel error in lieu of controller response 1134 */ 1135 int nvme_execute_rq(struct request *rq, bool at_head) 1136 { 1137 blk_status_t status; 1138 1139 status = blk_execute_rq(rq, at_head); 1140 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED) 1141 return -EINTR; 1142 if (nvme_req(rq)->status) 1143 return nvme_req(rq)->status; 1144 return blk_status_to_errno(status); 1145 } 1146 EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, "NVME_TARGET_PASSTHRU"); 1147 1148 /* 1149 * Returns 0 on success. If the result is negative, it's a Linux error code; 1150 * if the result is positive, it's an NVM Express status code 1151 */ 1152 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 1153 union nvme_result *result, void *buffer, unsigned bufflen, 1154 int qid, nvme_submit_flags_t flags) 1155 { 1156 struct request *req; 1157 int ret; 1158 blk_mq_req_flags_t blk_flags = 0; 1159 1160 if (flags & NVME_SUBMIT_NOWAIT) 1161 blk_flags |= BLK_MQ_REQ_NOWAIT; 1162 if (flags & NVME_SUBMIT_RESERVED) 1163 blk_flags |= BLK_MQ_REQ_RESERVED; 1164 if (qid == NVME_QID_ANY) 1165 req = blk_mq_alloc_request(q, nvme_req_op(cmd), blk_flags); 1166 else 1167 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), blk_flags, 1168 qid - 1); 1169 1170 if (IS_ERR(req)) 1171 return PTR_ERR(req); 1172 nvme_init_request(req, cmd); 1173 if (flags & NVME_SUBMIT_RETRY) 1174 req->cmd_flags &= ~REQ_FAILFAST_DRIVER; 1175 1176 if (buffer && bufflen) { 1177 ret = blk_rq_map_kern(req, buffer, bufflen, GFP_KERNEL); 1178 if (ret) 1179 goto out; 1180 } 1181 1182 ret = nvme_execute_rq(req, flags & NVME_SUBMIT_AT_HEAD); 1183 if (result && ret >= 0) 1184 *result = nvme_req(req)->result; 1185 out: 1186 blk_mq_free_request(req); 1187 return ret; 1188 } 1189 EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd); 1190 1191 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 1192 void *buffer, unsigned bufflen) 1193 { 1194 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 1195 NVME_QID_ANY, 0); 1196 } 1197 EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd); 1198 1199 u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode) 1200 { 1201 u32 effects = 0; 1202 1203 if (ns) { 1204 effects = le32_to_cpu(ns->head->effects->iocs[opcode]); 1205 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC)) 1206 dev_warn_once(ctrl->device, 1207 "IO command:%02x has unusual effects:%08x\n", 1208 opcode, effects); 1209 1210 /* 1211 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues, 1212 * which would deadlock when done on an I/O command. Note that 1213 * We already warn about an unusual effect above. 1214 */ 1215 effects &= ~NVME_CMD_EFFECTS_CSE_MASK; 1216 } else { 1217 effects = le32_to_cpu(ctrl->effects->acs[opcode]); 1218 1219 /* Ignore execution restrictions if any relaxation bits are set */ 1220 if (effects & NVME_CMD_EFFECTS_CSER_MASK) 1221 effects &= ~NVME_CMD_EFFECTS_CSE_MASK; 1222 } 1223 1224 return effects; 1225 } 1226 EXPORT_SYMBOL_NS_GPL(nvme_command_effects, "NVME_TARGET_PASSTHRU"); 1227 1228 u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode) 1229 { 1230 u32 effects = nvme_command_effects(ctrl, ns, opcode); 1231 1232 /* 1233 * For simplicity, IO to all namespaces is quiesced even if the command 1234 * effects say only one namespace is affected. 1235 */ 1236 if (effects & NVME_CMD_EFFECTS_CSE_MASK) { 1237 mutex_lock(&ctrl->scan_lock); 1238 mutex_lock(&ctrl->subsys->lock); 1239 nvme_mpath_start_freeze(ctrl->subsys); 1240 nvme_mpath_wait_freeze(ctrl->subsys); 1241 nvme_start_freeze(ctrl); 1242 nvme_wait_freeze(ctrl); 1243 } 1244 return effects; 1245 } 1246 EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, "NVME_TARGET_PASSTHRU"); 1247 1248 void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects, 1249 struct nvme_command *cmd, int status) 1250 { 1251 if (effects & NVME_CMD_EFFECTS_CSE_MASK) { 1252 nvme_unfreeze(ctrl); 1253 nvme_mpath_unfreeze(ctrl->subsys); 1254 mutex_unlock(&ctrl->subsys->lock); 1255 mutex_unlock(&ctrl->scan_lock); 1256 } 1257 if (effects & NVME_CMD_EFFECTS_CCC) { 1258 if (!test_and_set_bit(NVME_CTRL_DIRTY_CAPABILITY, 1259 &ctrl->flags)) { 1260 dev_info(ctrl->device, 1261 "controller capabilities changed, reset may be required to take effect.\n"); 1262 } 1263 } 1264 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) { 1265 nvme_queue_scan(ctrl); 1266 flush_work(&ctrl->scan_work); 1267 } 1268 if (ns) 1269 return; 1270 1271 switch (cmd->common.opcode) { 1272 case nvme_admin_set_features: 1273 switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) { 1274 case NVME_FEAT_KATO: 1275 /* 1276 * Keep alive commands interval on the host should be 1277 * updated when KATO is modified by Set Features 1278 * commands. 1279 */ 1280 if (!status) 1281 nvme_update_keep_alive(ctrl, cmd); 1282 break; 1283 default: 1284 break; 1285 } 1286 break; 1287 default: 1288 break; 1289 } 1290 } 1291 EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, "NVME_TARGET_PASSTHRU"); 1292 1293 /* 1294 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1: 1295 * 1296 * The host should send Keep Alive commands at half of the Keep Alive Timeout 1297 * accounting for transport roundtrip times [..]. 1298 */ 1299 static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) 1300 { 1301 unsigned long delay = ctrl->kato * HZ / 2; 1302 1303 /* 1304 * When using Traffic Based Keep Alive, we need to run 1305 * nvme_keep_alive_work at twice the normal frequency, as one 1306 * command completion can postpone sending a keep alive command 1307 * by up to twice the delay between runs. 1308 */ 1309 if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) 1310 delay /= 2; 1311 return delay; 1312 } 1313 1314 static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl) 1315 { 1316 unsigned long now = jiffies; 1317 unsigned long delay = nvme_keep_alive_work_period(ctrl); 1318 unsigned long ka_next_check_tm = ctrl->ka_last_check_time + delay; 1319 1320 if (time_after(now, ka_next_check_tm)) 1321 delay = 0; 1322 else 1323 delay = ka_next_check_tm - now; 1324 1325 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay); 1326 } 1327 1328 static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq, 1329 blk_status_t status) 1330 { 1331 struct nvme_ctrl *ctrl = rq->end_io_data; 1332 unsigned long rtt = jiffies - (rq->deadline - rq->timeout); 1333 unsigned long delay = nvme_keep_alive_work_period(ctrl); 1334 enum nvme_ctrl_state state = nvme_ctrl_state(ctrl); 1335 1336 /* 1337 * Subtract off the keepalive RTT so nvme_keep_alive_work runs 1338 * at the desired frequency. 1339 */ 1340 if (rtt <= delay) { 1341 delay -= rtt; 1342 } else { 1343 dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n", 1344 jiffies_to_msecs(rtt)); 1345 delay = 0; 1346 } 1347 1348 blk_mq_free_request(rq); 1349 1350 if (status) { 1351 dev_err(ctrl->device, 1352 "failed nvme_keep_alive_end_io error=%d\n", 1353 status); 1354 return RQ_END_IO_NONE; 1355 } 1356 1357 ctrl->ka_last_check_time = jiffies; 1358 ctrl->comp_seen = false; 1359 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_CONNECTING) 1360 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay); 1361 return RQ_END_IO_NONE; 1362 } 1363 1364 static void nvme_keep_alive_work(struct work_struct *work) 1365 { 1366 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work), 1367 struct nvme_ctrl, ka_work); 1368 bool comp_seen = ctrl->comp_seen; 1369 struct request *rq; 1370 1371 ctrl->ka_last_check_time = jiffies; 1372 1373 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) { 1374 dev_dbg(ctrl->device, 1375 "reschedule traffic based keep-alive timer\n"); 1376 ctrl->comp_seen = false; 1377 nvme_queue_keep_alive_work(ctrl); 1378 return; 1379 } 1380 1381 rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd), 1382 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT); 1383 if (IS_ERR(rq)) { 1384 /* allocation failure, reset the controller */ 1385 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq)); 1386 nvme_reset_ctrl(ctrl); 1387 return; 1388 } 1389 nvme_init_request(rq, &ctrl->ka_cmd); 1390 1391 rq->timeout = ctrl->kato * HZ; 1392 rq->end_io = nvme_keep_alive_end_io; 1393 rq->end_io_data = ctrl; 1394 blk_execute_rq_nowait(rq, false); 1395 } 1396 1397 static void nvme_start_keep_alive(struct nvme_ctrl *ctrl) 1398 { 1399 if (unlikely(ctrl->kato == 0)) 1400 return; 1401 1402 nvme_queue_keep_alive_work(ctrl); 1403 } 1404 1405 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl) 1406 { 1407 if (unlikely(ctrl->kato == 0)) 1408 return; 1409 1410 cancel_delayed_work_sync(&ctrl->ka_work); 1411 } 1412 EXPORT_SYMBOL_GPL(nvme_stop_keep_alive); 1413 1414 static void nvme_update_keep_alive(struct nvme_ctrl *ctrl, 1415 struct nvme_command *cmd) 1416 { 1417 unsigned int new_kato = 1418 DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000); 1419 1420 dev_info(ctrl->device, 1421 "keep alive interval updated from %u ms to %u ms\n", 1422 ctrl->kato * 1000 / 2, new_kato * 1000 / 2); 1423 1424 nvme_stop_keep_alive(ctrl); 1425 ctrl->kato = new_kato; 1426 nvme_start_keep_alive(ctrl); 1427 } 1428 1429 static bool nvme_id_cns_ok(struct nvme_ctrl *ctrl, u8 cns) 1430 { 1431 /* 1432 * The CNS field occupies a full byte starting with NVMe 1.2 1433 */ 1434 if (ctrl->vs >= NVME_VS(1, 2, 0)) 1435 return true; 1436 1437 /* 1438 * NVMe 1.1 expanded the CNS value to two bits, which means values 1439 * larger than that could get truncated and treated as an incorrect 1440 * value. 1441 * 1442 * Qemu implemented 1.0 behavior for controllers claiming 1.1 1443 * compliance, so they need to be quirked here. 1444 */ 1445 if (ctrl->vs >= NVME_VS(1, 1, 0) && 1446 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) 1447 return cns <= 3; 1448 1449 /* 1450 * NVMe 1.0 used a single bit for the CNS value. 1451 */ 1452 return cns <= 1; 1453 } 1454 1455 static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id) 1456 { 1457 struct nvme_command c = { }; 1458 int error; 1459 1460 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ 1461 c.identify.opcode = nvme_admin_identify; 1462 c.identify.cns = NVME_ID_CNS_CTRL; 1463 1464 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); 1465 if (!*id) 1466 return -ENOMEM; 1467 1468 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, 1469 sizeof(struct nvme_id_ctrl)); 1470 if (error) { 1471 kfree(*id); 1472 *id = NULL; 1473 } 1474 return error; 1475 } 1476 1477 static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids, 1478 struct nvme_ns_id_desc *cur, bool *csi_seen) 1479 { 1480 const char *warn_str = "ctrl returned bogus length:"; 1481 void *data = cur; 1482 1483 switch (cur->nidt) { 1484 case NVME_NIDT_EUI64: 1485 if (cur->nidl != NVME_NIDT_EUI64_LEN) { 1486 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n", 1487 warn_str, cur->nidl); 1488 return -1; 1489 } 1490 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) 1491 return NVME_NIDT_EUI64_LEN; 1492 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN); 1493 return NVME_NIDT_EUI64_LEN; 1494 case NVME_NIDT_NGUID: 1495 if (cur->nidl != NVME_NIDT_NGUID_LEN) { 1496 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n", 1497 warn_str, cur->nidl); 1498 return -1; 1499 } 1500 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) 1501 return NVME_NIDT_NGUID_LEN; 1502 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN); 1503 return NVME_NIDT_NGUID_LEN; 1504 case NVME_NIDT_UUID: 1505 if (cur->nidl != NVME_NIDT_UUID_LEN) { 1506 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n", 1507 warn_str, cur->nidl); 1508 return -1; 1509 } 1510 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) 1511 return NVME_NIDT_UUID_LEN; 1512 uuid_copy(&ids->uuid, data + sizeof(*cur)); 1513 return NVME_NIDT_UUID_LEN; 1514 case NVME_NIDT_CSI: 1515 if (cur->nidl != NVME_NIDT_CSI_LEN) { 1516 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n", 1517 warn_str, cur->nidl); 1518 return -1; 1519 } 1520 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN); 1521 *csi_seen = true; 1522 return NVME_NIDT_CSI_LEN; 1523 default: 1524 /* Skip unknown types */ 1525 return cur->nidl; 1526 } 1527 } 1528 1529 static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, 1530 struct nvme_ns_info *info) 1531 { 1532 struct nvme_command c = { }; 1533 bool csi_seen = false; 1534 int status, pos, len; 1535 void *data; 1536 1537 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl)) 1538 return 0; 1539 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST) 1540 return 0; 1541 1542 c.identify.opcode = nvme_admin_identify; 1543 c.identify.nsid = cpu_to_le32(info->nsid); 1544 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST; 1545 1546 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL); 1547 if (!data) 1548 return -ENOMEM; 1549 1550 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data, 1551 NVME_IDENTIFY_DATA_SIZE); 1552 if (status) { 1553 dev_warn(ctrl->device, 1554 "Identify Descriptors failed (nsid=%u, status=0x%x)\n", 1555 info->nsid, status); 1556 goto free_data; 1557 } 1558 1559 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) { 1560 struct nvme_ns_id_desc *cur = data + pos; 1561 1562 if (cur->nidl == 0) 1563 break; 1564 1565 len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen); 1566 if (len < 0) 1567 break; 1568 1569 len += sizeof(*cur); 1570 } 1571 1572 if (nvme_multi_css(ctrl) && !csi_seen) { 1573 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n", 1574 info->nsid); 1575 status = -EINVAL; 1576 } 1577 1578 free_data: 1579 kfree(data); 1580 return status; 1581 } 1582 1583 int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid, 1584 struct nvme_id_ns **id) 1585 { 1586 struct nvme_command c = { }; 1587 int error; 1588 1589 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ 1590 c.identify.opcode = nvme_admin_identify; 1591 c.identify.nsid = cpu_to_le32(nsid); 1592 c.identify.cns = NVME_ID_CNS_NS; 1593 1594 *id = kmalloc(sizeof(**id), GFP_KERNEL); 1595 if (!*id) 1596 return -ENOMEM; 1597 1598 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id)); 1599 if (error) { 1600 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error); 1601 kfree(*id); 1602 *id = NULL; 1603 } 1604 return error; 1605 } 1606 1607 static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl, 1608 struct nvme_ns_info *info) 1609 { 1610 struct nvme_ns_ids *ids = &info->ids; 1611 struct nvme_id_ns *id; 1612 int ret; 1613 1614 ret = nvme_identify_ns(ctrl, info->nsid, &id); 1615 if (ret) 1616 return ret; 1617 1618 if (id->ncap == 0) { 1619 /* namespace not allocated or attached */ 1620 info->is_removed = true; 1621 ret = -ENODEV; 1622 goto error; 1623 } 1624 1625 info->anagrpid = id->anagrpid; 1626 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED; 1627 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO; 1628 info->is_ready = true; 1629 info->endgid = le16_to_cpu(id->endgid); 1630 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) { 1631 dev_info(ctrl->device, 1632 "Ignoring bogus Namespace Identifiers\n"); 1633 } else { 1634 if (ctrl->vs >= NVME_VS(1, 1, 0) && 1635 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64))) 1636 memcpy(ids->eui64, id->eui64, sizeof(ids->eui64)); 1637 if (ctrl->vs >= NVME_VS(1, 2, 0) && 1638 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid))) 1639 memcpy(ids->nguid, id->nguid, sizeof(ids->nguid)); 1640 } 1641 1642 error: 1643 kfree(id); 1644 return ret; 1645 } 1646 1647 static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl, 1648 struct nvme_ns_info *info) 1649 { 1650 struct nvme_id_ns_cs_indep *id; 1651 struct nvme_command c = { 1652 .identify.opcode = nvme_admin_identify, 1653 .identify.nsid = cpu_to_le32(info->nsid), 1654 .identify.cns = NVME_ID_CNS_NS_CS_INDEP, 1655 }; 1656 int ret; 1657 1658 id = kmalloc(sizeof(*id), GFP_KERNEL); 1659 if (!id) 1660 return -ENOMEM; 1661 1662 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id)); 1663 if (!ret) { 1664 info->anagrpid = id->anagrpid; 1665 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED; 1666 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO; 1667 info->is_ready = id->nstat & NVME_NSTAT_NRDY; 1668 info->is_rotational = id->nsfeat & NVME_NS_ROTATIONAL; 1669 info->no_vwc = id->nsfeat & NVME_NS_VWC_NOT_PRESENT; 1670 info->endgid = le16_to_cpu(id->endgid); 1671 } 1672 kfree(id); 1673 return ret; 1674 } 1675 1676 static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid, 1677 unsigned int dword11, void *buffer, size_t buflen, u32 *result) 1678 { 1679 union nvme_result res = { 0 }; 1680 struct nvme_command c = { }; 1681 int ret; 1682 1683 c.features.opcode = op; 1684 c.features.fid = cpu_to_le32(fid); 1685 c.features.dword11 = cpu_to_le32(dword11); 1686 1687 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, 1688 buffer, buflen, NVME_QID_ANY, 0); 1689 if (ret >= 0 && result) 1690 *result = le32_to_cpu(res.u32); 1691 return ret; 1692 } 1693 1694 int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, 1695 unsigned int dword11, void *buffer, size_t buflen, 1696 void *result) 1697 { 1698 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer, 1699 buflen, result); 1700 } 1701 EXPORT_SYMBOL_GPL(nvme_set_features); 1702 1703 int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, 1704 unsigned int dword11, void *buffer, size_t buflen, 1705 void *result) 1706 { 1707 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer, 1708 buflen, result); 1709 } 1710 EXPORT_SYMBOL_GPL(nvme_get_features); 1711 1712 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count) 1713 { 1714 u32 q_count = (*count - 1) | ((*count - 1) << 16); 1715 u32 result; 1716 int status, nr_io_queues; 1717 1718 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0, 1719 &result); 1720 1721 /* 1722 * It's either a kernel error or the host observed a connection 1723 * lost. In either case it's not possible communicate with the 1724 * controller and thus enter the error code path. 1725 */ 1726 if (status < 0 || status == NVME_SC_HOST_PATH_ERROR) 1727 return status; 1728 1729 /* 1730 * Degraded controllers might return an error when setting the queue 1731 * count. We still want to be able to bring them online and offer 1732 * access to the admin queue, as that might be only way to fix them up. 1733 */ 1734 if (status > 0) { 1735 dev_err(ctrl->device, "Could not set queue count (%d)\n", status); 1736 *count = 0; 1737 } else { 1738 nr_io_queues = min(result & 0xffff, result >> 16) + 1; 1739 *count = min(*count, nr_io_queues); 1740 } 1741 1742 return 0; 1743 } 1744 EXPORT_SYMBOL_GPL(nvme_set_queue_count); 1745 1746 #define NVME_AEN_SUPPORTED \ 1747 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \ 1748 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE) 1749 1750 static void nvme_enable_aen(struct nvme_ctrl *ctrl) 1751 { 1752 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED; 1753 int status; 1754 1755 if (!supported_aens) 1756 return; 1757 1758 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens, 1759 NULL, 0, &result); 1760 if (status) 1761 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n", 1762 supported_aens); 1763 1764 queue_work(nvme_wq, &ctrl->async_event_work); 1765 } 1766 1767 static int nvme_ns_open(struct nvme_ns *ns) 1768 { 1769 1770 /* should never be called due to GENHD_FL_HIDDEN */ 1771 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head))) 1772 goto fail; 1773 if (!nvme_get_ns(ns)) 1774 goto fail; 1775 if (!try_module_get(ns->ctrl->ops->module)) 1776 goto fail_put_ns; 1777 1778 return 0; 1779 1780 fail_put_ns: 1781 nvme_put_ns(ns); 1782 fail: 1783 return -ENXIO; 1784 } 1785 1786 static void nvme_ns_release(struct nvme_ns *ns) 1787 { 1788 1789 module_put(ns->ctrl->ops->module); 1790 nvme_put_ns(ns); 1791 } 1792 1793 static int nvme_open(struct gendisk *disk, blk_mode_t mode) 1794 { 1795 return nvme_ns_open(disk->private_data); 1796 } 1797 1798 static void nvme_release(struct gendisk *disk) 1799 { 1800 nvme_ns_release(disk->private_data); 1801 } 1802 1803 int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo) 1804 { 1805 /* some standard values */ 1806 geo->heads = 1 << 6; 1807 geo->sectors = 1 << 5; 1808 geo->cylinders = get_capacity(bdev->bd_disk) >> 11; 1809 return 0; 1810 } 1811 1812 static bool nvme_init_integrity(struct nvme_ns_head *head, 1813 struct queue_limits *lim, struct nvme_ns_info *info) 1814 { 1815 struct blk_integrity *bi = &lim->integrity; 1816 1817 memset(bi, 0, sizeof(*bi)); 1818 1819 if (!head->ms) 1820 return true; 1821 1822 /* 1823 * PI can always be supported as we can ask the controller to simply 1824 * insert/strip it, which is not possible for other kinds of metadata. 1825 */ 1826 if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) || 1827 !(head->features & NVME_NS_METADATA_SUPPORTED)) 1828 return nvme_ns_has_pi(head); 1829 1830 switch (head->pi_type) { 1831 case NVME_NS_DPS_PI_TYPE3: 1832 switch (head->guard_type) { 1833 case NVME_NVM_NS_16B_GUARD: 1834 bi->csum_type = BLK_INTEGRITY_CSUM_CRC; 1835 bi->tag_size = sizeof(u16) + sizeof(u32); 1836 bi->flags |= BLK_INTEGRITY_DEVICE_CAPABLE; 1837 break; 1838 case NVME_NVM_NS_64B_GUARD: 1839 bi->csum_type = BLK_INTEGRITY_CSUM_CRC64; 1840 bi->tag_size = sizeof(u16) + 6; 1841 bi->flags |= BLK_INTEGRITY_DEVICE_CAPABLE; 1842 break; 1843 default: 1844 break; 1845 } 1846 break; 1847 case NVME_NS_DPS_PI_TYPE1: 1848 case NVME_NS_DPS_PI_TYPE2: 1849 switch (head->guard_type) { 1850 case NVME_NVM_NS_16B_GUARD: 1851 bi->csum_type = BLK_INTEGRITY_CSUM_CRC; 1852 bi->tag_size = sizeof(u16); 1853 bi->flags |= BLK_INTEGRITY_DEVICE_CAPABLE | 1854 BLK_INTEGRITY_REF_TAG; 1855 break; 1856 case NVME_NVM_NS_64B_GUARD: 1857 bi->csum_type = BLK_INTEGRITY_CSUM_CRC64; 1858 bi->tag_size = sizeof(u16); 1859 bi->flags |= BLK_INTEGRITY_DEVICE_CAPABLE | 1860 BLK_INTEGRITY_REF_TAG; 1861 break; 1862 default: 1863 break; 1864 } 1865 break; 1866 default: 1867 break; 1868 } 1869 1870 bi->tuple_size = head->ms; 1871 bi->pi_offset = info->pi_offset; 1872 return true; 1873 } 1874 1875 static void nvme_config_discard(struct nvme_ns *ns, struct queue_limits *lim) 1876 { 1877 struct nvme_ctrl *ctrl = ns->ctrl; 1878 1879 if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(ns->head, UINT_MAX)) 1880 lim->max_hw_discard_sectors = 1881 nvme_lba_to_sect(ns->head, ctrl->dmrsl); 1882 else if (ctrl->oncs & NVME_CTRL_ONCS_DSM) 1883 lim->max_hw_discard_sectors = UINT_MAX; 1884 else 1885 lim->max_hw_discard_sectors = 0; 1886 1887 lim->discard_granularity = lim->logical_block_size; 1888 1889 if (ctrl->dmrl) 1890 lim->max_discard_segments = ctrl->dmrl; 1891 else 1892 lim->max_discard_segments = NVME_DSM_MAX_RANGES; 1893 } 1894 1895 static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b) 1896 { 1897 return uuid_equal(&a->uuid, &b->uuid) && 1898 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 && 1899 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 && 1900 a->csi == b->csi; 1901 } 1902 1903 static int nvme_identify_ns_nvm(struct nvme_ctrl *ctrl, unsigned int nsid, 1904 struct nvme_id_ns_nvm **nvmp) 1905 { 1906 struct nvme_command c = { 1907 .identify.opcode = nvme_admin_identify, 1908 .identify.nsid = cpu_to_le32(nsid), 1909 .identify.cns = NVME_ID_CNS_CS_NS, 1910 .identify.csi = NVME_CSI_NVM, 1911 }; 1912 struct nvme_id_ns_nvm *nvm; 1913 int ret; 1914 1915 nvm = kzalloc(sizeof(*nvm), GFP_KERNEL); 1916 if (!nvm) 1917 return -ENOMEM; 1918 1919 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, nvm, sizeof(*nvm)); 1920 if (ret) 1921 kfree(nvm); 1922 else 1923 *nvmp = nvm; 1924 return ret; 1925 } 1926 1927 static void nvme_configure_pi_elbas(struct nvme_ns_head *head, 1928 struct nvme_id_ns *id, struct nvme_id_ns_nvm *nvm) 1929 { 1930 u32 elbaf = le32_to_cpu(nvm->elbaf[nvme_lbaf_index(id->flbas)]); 1931 u8 guard_type; 1932 1933 /* no support for storage tag formats right now */ 1934 if (nvme_elbaf_sts(elbaf)) 1935 return; 1936 1937 guard_type = nvme_elbaf_guard_type(elbaf); 1938 if ((nvm->pic & NVME_ID_NS_NVM_QPIFS) && 1939 guard_type == NVME_NVM_NS_QTYPE_GUARD) 1940 guard_type = nvme_elbaf_qualified_guard_type(elbaf); 1941 1942 head->guard_type = guard_type; 1943 switch (head->guard_type) { 1944 case NVME_NVM_NS_64B_GUARD: 1945 head->pi_size = sizeof(struct crc64_pi_tuple); 1946 break; 1947 case NVME_NVM_NS_16B_GUARD: 1948 head->pi_size = sizeof(struct t10_pi_tuple); 1949 break; 1950 default: 1951 break; 1952 } 1953 } 1954 1955 static void nvme_configure_metadata(struct nvme_ctrl *ctrl, 1956 struct nvme_ns_head *head, struct nvme_id_ns *id, 1957 struct nvme_id_ns_nvm *nvm, struct nvme_ns_info *info) 1958 { 1959 head->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS); 1960 head->pi_type = 0; 1961 head->pi_size = 0; 1962 head->ms = le16_to_cpu(id->lbaf[nvme_lbaf_index(id->flbas)].ms); 1963 if (!head->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)) 1964 return; 1965 1966 if (nvm && (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) { 1967 nvme_configure_pi_elbas(head, id, nvm); 1968 } else { 1969 head->pi_size = sizeof(struct t10_pi_tuple); 1970 head->guard_type = NVME_NVM_NS_16B_GUARD; 1971 } 1972 1973 if (head->pi_size && head->ms >= head->pi_size) 1974 head->pi_type = id->dps & NVME_NS_DPS_PI_MASK; 1975 if (!(id->dps & NVME_NS_DPS_PI_FIRST)) { 1976 if (disable_pi_offsets) 1977 head->pi_type = 0; 1978 else 1979 info->pi_offset = head->ms - head->pi_size; 1980 } 1981 1982 if (ctrl->ops->flags & NVME_F_FABRICS) { 1983 /* 1984 * The NVMe over Fabrics specification only supports metadata as 1985 * part of the extended data LBA. We rely on HCA/HBA support to 1986 * remap the separate metadata buffer from the block layer. 1987 */ 1988 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT))) 1989 return; 1990 1991 head->features |= NVME_NS_EXT_LBAS; 1992 1993 /* 1994 * The current fabrics transport drivers support namespace 1995 * metadata formats only if nvme_ns_has_pi() returns true. 1996 * Suppress support for all other formats so the namespace will 1997 * have a 0 capacity and not be usable through the block stack. 1998 * 1999 * Note, this check will need to be modified if any drivers 2000 * gain the ability to use other metadata formats. 2001 */ 2002 if (ctrl->max_integrity_segments && nvme_ns_has_pi(head)) 2003 head->features |= NVME_NS_METADATA_SUPPORTED; 2004 } else { 2005 /* 2006 * For PCIe controllers, we can't easily remap the separate 2007 * metadata buffer from the block layer and thus require a 2008 * separate metadata buffer for block layer metadata/PI support. 2009 * We allow extended LBAs for the passthrough interface, though. 2010 */ 2011 if (id->flbas & NVME_NS_FLBAS_META_EXT) 2012 head->features |= NVME_NS_EXT_LBAS; 2013 else 2014 head->features |= NVME_NS_METADATA_SUPPORTED; 2015 } 2016 } 2017 2018 2019 static void nvme_update_atomic_write_disk_info(struct nvme_ns *ns, 2020 struct nvme_id_ns *id, struct queue_limits *lim, 2021 u32 bs, u32 atomic_bs) 2022 { 2023 unsigned int boundary = 0; 2024 2025 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf) { 2026 if (le16_to_cpu(id->nabspf)) 2027 boundary = (le16_to_cpu(id->nabspf) + 1) * bs; 2028 } 2029 lim->atomic_write_hw_max = atomic_bs; 2030 lim->atomic_write_hw_boundary = boundary; 2031 lim->atomic_write_hw_unit_min = bs; 2032 lim->atomic_write_hw_unit_max = rounddown_pow_of_two(atomic_bs); 2033 lim->features |= BLK_FEAT_ATOMIC_WRITES; 2034 } 2035 2036 static u32 nvme_max_drv_segments(struct nvme_ctrl *ctrl) 2037 { 2038 return ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> SECTOR_SHIFT) + 1; 2039 } 2040 2041 static void nvme_set_ctrl_limits(struct nvme_ctrl *ctrl, 2042 struct queue_limits *lim) 2043 { 2044 lim->max_hw_sectors = ctrl->max_hw_sectors; 2045 lim->max_segments = min_t(u32, USHRT_MAX, 2046 min_not_zero(nvme_max_drv_segments(ctrl), ctrl->max_segments)); 2047 lim->max_integrity_segments = ctrl->max_integrity_segments; 2048 lim->virt_boundary_mask = NVME_CTRL_PAGE_SIZE - 1; 2049 lim->max_segment_size = UINT_MAX; 2050 lim->dma_alignment = 3; 2051 } 2052 2053 static bool nvme_update_disk_info(struct nvme_ns *ns, struct nvme_id_ns *id, 2054 struct queue_limits *lim) 2055 { 2056 struct nvme_ns_head *head = ns->head; 2057 u32 bs = 1U << head->lba_shift; 2058 u32 atomic_bs, phys_bs, io_opt = 0; 2059 bool valid = true; 2060 2061 /* 2062 * The block layer can't support LBA sizes larger than the page size 2063 * or smaller than a sector size yet, so catch this early and don't 2064 * allow block I/O. 2065 */ 2066 if (blk_validate_block_size(bs)) { 2067 bs = (1 << 9); 2068 valid = false; 2069 } 2070 2071 atomic_bs = phys_bs = bs; 2072 if (id->nabo == 0) { 2073 /* 2074 * Bit 1 indicates whether NAWUPF is defined for this namespace 2075 * and whether it should be used instead of AWUPF. If NAWUPF == 2076 * 0 then AWUPF must be used instead. 2077 */ 2078 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf) 2079 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs; 2080 else 2081 atomic_bs = (1 + ns->ctrl->awupf) * bs; 2082 2083 /* 2084 * Set subsystem atomic bs. 2085 */ 2086 if (ns->ctrl->subsys->atomic_bs) { 2087 if (atomic_bs != ns->ctrl->subsys->atomic_bs) { 2088 dev_err_ratelimited(ns->ctrl->device, 2089 "%s: Inconsistent Atomic Write Size, Namespace will not be added: Subsystem=%d bytes, Controller/Namespace=%d bytes\n", 2090 ns->disk ? ns->disk->disk_name : "?", 2091 ns->ctrl->subsys->atomic_bs, 2092 atomic_bs); 2093 } 2094 } else 2095 ns->ctrl->subsys->atomic_bs = atomic_bs; 2096 2097 nvme_update_atomic_write_disk_info(ns, id, lim, bs, atomic_bs); 2098 } 2099 2100 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) { 2101 /* NPWG = Namespace Preferred Write Granularity */ 2102 phys_bs = bs * (1 + le16_to_cpu(id->npwg)); 2103 /* NOWS = Namespace Optimal Write Size */ 2104 if (id->nows) 2105 io_opt = bs * (1 + le16_to_cpu(id->nows)); 2106 } 2107 2108 /* 2109 * Linux filesystems assume writing a single physical block is 2110 * an atomic operation. Hence limit the physical block size to the 2111 * value of the Atomic Write Unit Power Fail parameter. 2112 */ 2113 lim->logical_block_size = bs; 2114 lim->physical_block_size = min(phys_bs, atomic_bs); 2115 lim->io_min = phys_bs; 2116 lim->io_opt = io_opt; 2117 if ((ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) && 2118 (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)) 2119 lim->max_write_zeroes_sectors = UINT_MAX; 2120 else 2121 lim->max_write_zeroes_sectors = ns->ctrl->max_zeroes_sectors; 2122 return valid; 2123 } 2124 2125 static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info) 2126 { 2127 return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags); 2128 } 2129 2130 static inline bool nvme_first_scan(struct gendisk *disk) 2131 { 2132 /* nvme_alloc_ns() scans the disk prior to adding it */ 2133 return !disk_live(disk); 2134 } 2135 2136 static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id, 2137 struct queue_limits *lim) 2138 { 2139 struct nvme_ctrl *ctrl = ns->ctrl; 2140 u32 iob; 2141 2142 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) && 2143 is_power_of_2(ctrl->max_hw_sectors)) 2144 iob = ctrl->max_hw_sectors; 2145 else 2146 iob = nvme_lba_to_sect(ns->head, le16_to_cpu(id->noiob)); 2147 2148 if (!iob) 2149 return; 2150 2151 if (!is_power_of_2(iob)) { 2152 if (nvme_first_scan(ns->disk)) 2153 pr_warn("%s: ignoring unaligned IO boundary:%u\n", 2154 ns->disk->disk_name, iob); 2155 return; 2156 } 2157 2158 if (blk_queue_is_zoned(ns->disk->queue)) { 2159 if (nvme_first_scan(ns->disk)) 2160 pr_warn("%s: ignoring zoned namespace IO boundary\n", 2161 ns->disk->disk_name); 2162 return; 2163 } 2164 2165 lim->chunk_sectors = iob; 2166 } 2167 2168 static int nvme_update_ns_info_generic(struct nvme_ns *ns, 2169 struct nvme_ns_info *info) 2170 { 2171 struct queue_limits lim; 2172 unsigned int memflags; 2173 int ret; 2174 2175 lim = queue_limits_start_update(ns->disk->queue); 2176 nvme_set_ctrl_limits(ns->ctrl, &lim); 2177 2178 memflags = blk_mq_freeze_queue(ns->disk->queue); 2179 ret = queue_limits_commit_update(ns->disk->queue, &lim); 2180 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info)); 2181 blk_mq_unfreeze_queue(ns->disk->queue, memflags); 2182 2183 /* Hide the block-interface for these devices */ 2184 if (!ret) 2185 ret = -ENODEV; 2186 return ret; 2187 } 2188 2189 static int nvme_query_fdp_granularity(struct nvme_ctrl *ctrl, 2190 struct nvme_ns_info *info, u8 fdp_idx) 2191 { 2192 struct nvme_fdp_config_log hdr, *h; 2193 struct nvme_fdp_config_desc *desc; 2194 size_t size = sizeof(hdr); 2195 void *log, *end; 2196 int i, n, ret; 2197 2198 ret = nvme_get_log_lsi(ctrl, 0, NVME_LOG_FDP_CONFIGS, 0, 2199 NVME_CSI_NVM, &hdr, size, 0, info->endgid); 2200 if (ret) { 2201 dev_warn(ctrl->device, 2202 "FDP configs log header status:0x%x endgid:%d\n", ret, 2203 info->endgid); 2204 return ret; 2205 } 2206 2207 size = le32_to_cpu(hdr.sze); 2208 if (size > PAGE_SIZE * MAX_ORDER_NR_PAGES) { 2209 dev_warn(ctrl->device, "FDP config size too large:%zu\n", 2210 size); 2211 return 0; 2212 } 2213 2214 h = kvmalloc(size, GFP_KERNEL); 2215 if (!h) 2216 return -ENOMEM; 2217 2218 ret = nvme_get_log_lsi(ctrl, 0, NVME_LOG_FDP_CONFIGS, 0, 2219 NVME_CSI_NVM, h, size, 0, info->endgid); 2220 if (ret) { 2221 dev_warn(ctrl->device, 2222 "FDP configs log status:0x%x endgid:%d\n", ret, 2223 info->endgid); 2224 goto out; 2225 } 2226 2227 n = le16_to_cpu(h->numfdpc) + 1; 2228 if (fdp_idx > n) { 2229 dev_warn(ctrl->device, "FDP index:%d out of range:%d\n", 2230 fdp_idx, n); 2231 /* Proceed without registering FDP streams */ 2232 ret = 0; 2233 goto out; 2234 } 2235 2236 log = h + 1; 2237 desc = log; 2238 end = log + size - sizeof(*h); 2239 for (i = 0; i < fdp_idx; i++) { 2240 log += le16_to_cpu(desc->dsze); 2241 desc = log; 2242 if (log >= end) { 2243 dev_warn(ctrl->device, 2244 "FDP invalid config descriptor list\n"); 2245 ret = 0; 2246 goto out; 2247 } 2248 } 2249 2250 if (le32_to_cpu(desc->nrg) > 1) { 2251 dev_warn(ctrl->device, "FDP NRG > 1 not supported\n"); 2252 ret = 0; 2253 goto out; 2254 } 2255 2256 info->runs = le64_to_cpu(desc->runs); 2257 out: 2258 kvfree(h); 2259 return ret; 2260 } 2261 2262 static int nvme_query_fdp_info(struct nvme_ns *ns, struct nvme_ns_info *info) 2263 { 2264 struct nvme_ns_head *head = ns->head; 2265 struct nvme_ctrl *ctrl = ns->ctrl; 2266 struct nvme_fdp_ruh_status *ruhs; 2267 struct nvme_fdp_config fdp; 2268 struct nvme_command c = {}; 2269 size_t size; 2270 int i, ret; 2271 2272 /* 2273 * The FDP configuration is static for the lifetime of the namespace, 2274 * so return immediately if we've already registered this namespace's 2275 * streams. 2276 */ 2277 if (head->nr_plids) 2278 return 0; 2279 2280 ret = nvme_get_features(ctrl, NVME_FEAT_FDP, info->endgid, NULL, 0, 2281 &fdp); 2282 if (ret) { 2283 dev_warn(ctrl->device, "FDP get feature status:0x%x\n", ret); 2284 return ret; 2285 } 2286 2287 if (!(fdp.flags & FDPCFG_FDPE)) 2288 return 0; 2289 2290 ret = nvme_query_fdp_granularity(ctrl, info, fdp.fdpcidx); 2291 if (!info->runs) 2292 return ret; 2293 2294 size = struct_size(ruhs, ruhsd, S8_MAX - 1); 2295 ruhs = kzalloc(size, GFP_KERNEL); 2296 if (!ruhs) 2297 return -ENOMEM; 2298 2299 c.imr.opcode = nvme_cmd_io_mgmt_recv; 2300 c.imr.nsid = cpu_to_le32(head->ns_id); 2301 c.imr.mo = NVME_IO_MGMT_RECV_MO_RUHS; 2302 c.imr.numd = cpu_to_le32(nvme_bytes_to_numd(size)); 2303 ret = nvme_submit_sync_cmd(ns->queue, &c, ruhs, size); 2304 if (ret) { 2305 dev_warn(ctrl->device, "FDP io-mgmt status:0x%x\n", ret); 2306 goto free; 2307 } 2308 2309 head->nr_plids = le16_to_cpu(ruhs->nruhsd); 2310 if (!head->nr_plids) 2311 goto free; 2312 2313 head->plids = kcalloc(head->nr_plids, sizeof(*head->plids), 2314 GFP_KERNEL); 2315 if (!head->plids) { 2316 dev_warn(ctrl->device, 2317 "failed to allocate %u FDP placement IDs\n", 2318 head->nr_plids); 2319 head->nr_plids = 0; 2320 ret = -ENOMEM; 2321 goto free; 2322 } 2323 2324 for (i = 0; i < head->nr_plids; i++) 2325 head->plids[i] = le16_to_cpu(ruhs->ruhsd[i].pid); 2326 free: 2327 kfree(ruhs); 2328 return ret; 2329 } 2330 2331 static int nvme_update_ns_info_block(struct nvme_ns *ns, 2332 struct nvme_ns_info *info) 2333 { 2334 struct queue_limits lim; 2335 struct nvme_id_ns_nvm *nvm = NULL; 2336 struct nvme_zone_info zi = {}; 2337 struct nvme_id_ns *id; 2338 unsigned int memflags; 2339 sector_t capacity; 2340 unsigned lbaf; 2341 int ret; 2342 2343 ret = nvme_identify_ns(ns->ctrl, info->nsid, &id); 2344 if (ret) 2345 return ret; 2346 2347 if (id->ncap == 0) { 2348 /* namespace not allocated or attached */ 2349 info->is_removed = true; 2350 ret = -ENXIO; 2351 goto out; 2352 } 2353 lbaf = nvme_lbaf_index(id->flbas); 2354 2355 if (ns->ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) { 2356 ret = nvme_identify_ns_nvm(ns->ctrl, info->nsid, &nvm); 2357 if (ret < 0) 2358 goto out; 2359 } 2360 2361 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) && 2362 ns->head->ids.csi == NVME_CSI_ZNS) { 2363 ret = nvme_query_zone_info(ns, lbaf, &zi); 2364 if (ret < 0) 2365 goto out; 2366 } 2367 2368 if (ns->ctrl->ctratt & NVME_CTRL_ATTR_FDPS) { 2369 ret = nvme_query_fdp_info(ns, info); 2370 if (ret < 0) 2371 goto out; 2372 } 2373 2374 lim = queue_limits_start_update(ns->disk->queue); 2375 2376 memflags = blk_mq_freeze_queue(ns->disk->queue); 2377 ns->head->lba_shift = id->lbaf[lbaf].ds; 2378 ns->head->nuse = le64_to_cpu(id->nuse); 2379 capacity = nvme_lba_to_sect(ns->head, le64_to_cpu(id->nsze)); 2380 nvme_set_ctrl_limits(ns->ctrl, &lim); 2381 nvme_configure_metadata(ns->ctrl, ns->head, id, nvm, info); 2382 nvme_set_chunk_sectors(ns, id, &lim); 2383 if (!nvme_update_disk_info(ns, id, &lim)) 2384 capacity = 0; 2385 2386 /* 2387 * Validate the max atomic write size fits within the subsystem's 2388 * atomic write capabilities. 2389 */ 2390 if (lim.atomic_write_hw_max > ns->ctrl->subsys->atomic_bs) { 2391 blk_mq_unfreeze_queue(ns->disk->queue, memflags); 2392 ret = -ENXIO; 2393 goto out; 2394 } 2395 2396 nvme_config_discard(ns, &lim); 2397 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) && 2398 ns->head->ids.csi == NVME_CSI_ZNS) 2399 nvme_update_zone_info(ns, &lim, &zi); 2400 2401 if ((ns->ctrl->vwc & NVME_CTRL_VWC_PRESENT) && !info->no_vwc) 2402 lim.features |= BLK_FEAT_WRITE_CACHE | BLK_FEAT_FUA; 2403 else 2404 lim.features &= ~(BLK_FEAT_WRITE_CACHE | BLK_FEAT_FUA); 2405 2406 if (info->is_rotational) 2407 lim.features |= BLK_FEAT_ROTATIONAL; 2408 2409 /* 2410 * Register a metadata profile for PI, or the plain non-integrity NVMe 2411 * metadata masquerading as Type 0 if supported, otherwise reject block 2412 * I/O to namespaces with metadata except when the namespace supports 2413 * PI, as it can strip/insert in that case. 2414 */ 2415 if (!nvme_init_integrity(ns->head, &lim, info)) 2416 capacity = 0; 2417 2418 lim.max_write_streams = ns->head->nr_plids; 2419 if (lim.max_write_streams) 2420 lim.write_stream_granularity = min(info->runs, U32_MAX); 2421 else 2422 lim.write_stream_granularity = 0; 2423 2424 ret = queue_limits_commit_update(ns->disk->queue, &lim); 2425 if (ret) { 2426 blk_mq_unfreeze_queue(ns->disk->queue, memflags); 2427 goto out; 2428 } 2429 2430 set_capacity_and_notify(ns->disk, capacity); 2431 2432 /* 2433 * Only set the DEAC bit if the device guarantees that reads from 2434 * deallocated data return zeroes. While the DEAC bit does not 2435 * require that, it must be a no-op if reads from deallocated data 2436 * do not return zeroes. 2437 */ 2438 if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3))) 2439 ns->head->features |= NVME_NS_DEAC; 2440 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info)); 2441 set_bit(NVME_NS_READY, &ns->flags); 2442 blk_mq_unfreeze_queue(ns->disk->queue, memflags); 2443 2444 if (blk_queue_is_zoned(ns->queue)) { 2445 ret = blk_revalidate_disk_zones(ns->disk); 2446 if (ret && !nvme_first_scan(ns->disk)) 2447 goto out; 2448 } 2449 2450 ret = 0; 2451 out: 2452 kfree(nvm); 2453 kfree(id); 2454 return ret; 2455 } 2456 2457 static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info) 2458 { 2459 bool unsupported = false; 2460 int ret; 2461 2462 switch (info->ids.csi) { 2463 case NVME_CSI_ZNS: 2464 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) { 2465 dev_info(ns->ctrl->device, 2466 "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n", 2467 info->nsid); 2468 ret = nvme_update_ns_info_generic(ns, info); 2469 break; 2470 } 2471 ret = nvme_update_ns_info_block(ns, info); 2472 break; 2473 case NVME_CSI_NVM: 2474 ret = nvme_update_ns_info_block(ns, info); 2475 break; 2476 default: 2477 dev_info(ns->ctrl->device, 2478 "block device for nsid %u not supported (csi %u)\n", 2479 info->nsid, info->ids.csi); 2480 ret = nvme_update_ns_info_generic(ns, info); 2481 break; 2482 } 2483 2484 /* 2485 * If probing fails due an unsupported feature, hide the block device, 2486 * but still allow other access. 2487 */ 2488 if (ret == -ENODEV) { 2489 ns->disk->flags |= GENHD_FL_HIDDEN; 2490 set_bit(NVME_NS_READY, &ns->flags); 2491 unsupported = true; 2492 ret = 0; 2493 } 2494 2495 if (!ret && nvme_ns_head_multipath(ns->head)) { 2496 struct queue_limits *ns_lim = &ns->disk->queue->limits; 2497 struct queue_limits lim; 2498 unsigned int memflags; 2499 2500 lim = queue_limits_start_update(ns->head->disk->queue); 2501 memflags = blk_mq_freeze_queue(ns->head->disk->queue); 2502 /* 2503 * queue_limits mixes values that are the hardware limitations 2504 * for bio splitting with what is the device configuration. 2505 * 2506 * For NVMe the device configuration can change after e.g. a 2507 * Format command, and we really want to pick up the new format 2508 * value here. But we must still stack the queue limits to the 2509 * least common denominator for multipathing to split the bios 2510 * properly. 2511 * 2512 * To work around this, we explicitly set the device 2513 * configuration to those that we just queried, but only stack 2514 * the splitting limits in to make sure we still obey possibly 2515 * lower limitations of other controllers. 2516 */ 2517 lim.logical_block_size = ns_lim->logical_block_size; 2518 lim.physical_block_size = ns_lim->physical_block_size; 2519 lim.io_min = ns_lim->io_min; 2520 lim.io_opt = ns_lim->io_opt; 2521 queue_limits_stack_bdev(&lim, ns->disk->part0, 0, 2522 ns->head->disk->disk_name); 2523 if (unsupported) 2524 ns->head->disk->flags |= GENHD_FL_HIDDEN; 2525 else 2526 nvme_init_integrity(ns->head, &lim, info); 2527 lim.max_write_streams = ns_lim->max_write_streams; 2528 lim.write_stream_granularity = ns_lim->write_stream_granularity; 2529 ret = queue_limits_commit_update(ns->head->disk->queue, &lim); 2530 2531 set_capacity_and_notify(ns->head->disk, get_capacity(ns->disk)); 2532 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info)); 2533 nvme_mpath_revalidate_paths(ns); 2534 2535 blk_mq_unfreeze_queue(ns->head->disk->queue, memflags); 2536 } 2537 2538 return ret; 2539 } 2540 2541 int nvme_ns_get_unique_id(struct nvme_ns *ns, u8 id[16], 2542 enum blk_unique_id type) 2543 { 2544 struct nvme_ns_ids *ids = &ns->head->ids; 2545 2546 if (type != BLK_UID_EUI64) 2547 return -EINVAL; 2548 2549 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid))) { 2550 memcpy(id, &ids->nguid, sizeof(ids->nguid)); 2551 return sizeof(ids->nguid); 2552 } 2553 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64))) { 2554 memcpy(id, &ids->eui64, sizeof(ids->eui64)); 2555 return sizeof(ids->eui64); 2556 } 2557 2558 return -EINVAL; 2559 } 2560 2561 static int nvme_get_unique_id(struct gendisk *disk, u8 id[16], 2562 enum blk_unique_id type) 2563 { 2564 return nvme_ns_get_unique_id(disk->private_data, id, type); 2565 } 2566 2567 #ifdef CONFIG_BLK_SED_OPAL 2568 static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, 2569 bool send) 2570 { 2571 struct nvme_ctrl *ctrl = data; 2572 struct nvme_command cmd = { }; 2573 2574 if (send) 2575 cmd.common.opcode = nvme_admin_security_send; 2576 else 2577 cmd.common.opcode = nvme_admin_security_recv; 2578 cmd.common.nsid = 0; 2579 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8); 2580 cmd.common.cdw11 = cpu_to_le32(len); 2581 2582 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len, 2583 NVME_QID_ANY, NVME_SUBMIT_AT_HEAD); 2584 } 2585 2586 static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended) 2587 { 2588 if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) { 2589 if (!ctrl->opal_dev) 2590 ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit); 2591 else if (was_suspended) 2592 opal_unlock_from_suspend(ctrl->opal_dev); 2593 } else { 2594 free_opal_dev(ctrl->opal_dev); 2595 ctrl->opal_dev = NULL; 2596 } 2597 } 2598 #else 2599 static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended) 2600 { 2601 } 2602 #endif /* CONFIG_BLK_SED_OPAL */ 2603 2604 #ifdef CONFIG_BLK_DEV_ZONED 2605 static int nvme_report_zones(struct gendisk *disk, sector_t sector, 2606 unsigned int nr_zones, report_zones_cb cb, void *data) 2607 { 2608 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb, 2609 data); 2610 } 2611 #else 2612 #define nvme_report_zones NULL 2613 #endif /* CONFIG_BLK_DEV_ZONED */ 2614 2615 const struct block_device_operations nvme_bdev_ops = { 2616 .owner = THIS_MODULE, 2617 .ioctl = nvme_ioctl, 2618 .compat_ioctl = blkdev_compat_ptr_ioctl, 2619 .open = nvme_open, 2620 .release = nvme_release, 2621 .getgeo = nvme_getgeo, 2622 .get_unique_id = nvme_get_unique_id, 2623 .report_zones = nvme_report_zones, 2624 .pr_ops = &nvme_pr_ops, 2625 }; 2626 2627 static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val, 2628 u32 timeout, const char *op) 2629 { 2630 unsigned long timeout_jiffies = jiffies + timeout * HZ; 2631 u32 csts; 2632 int ret; 2633 2634 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) { 2635 if (csts == ~0) 2636 return -ENODEV; 2637 if ((csts & mask) == val) 2638 break; 2639 2640 usleep_range(1000, 2000); 2641 if (fatal_signal_pending(current)) 2642 return -EINTR; 2643 if (time_after(jiffies, timeout_jiffies)) { 2644 dev_err(ctrl->device, 2645 "Device not ready; aborting %s, CSTS=0x%x\n", 2646 op, csts); 2647 return -ENODEV; 2648 } 2649 } 2650 2651 return ret; 2652 } 2653 2654 int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown) 2655 { 2656 int ret; 2657 2658 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK; 2659 if (shutdown) 2660 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL; 2661 else 2662 ctrl->ctrl_config &= ~NVME_CC_ENABLE; 2663 2664 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); 2665 if (ret) 2666 return ret; 2667 2668 if (shutdown) { 2669 return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK, 2670 NVME_CSTS_SHST_CMPLT, 2671 ctrl->shutdown_timeout, "shutdown"); 2672 } 2673 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) 2674 msleep(NVME_QUIRK_DELAY_AMOUNT); 2675 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0, 2676 (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset"); 2677 } 2678 EXPORT_SYMBOL_GPL(nvme_disable_ctrl); 2679 2680 int nvme_enable_ctrl(struct nvme_ctrl *ctrl) 2681 { 2682 unsigned dev_page_min; 2683 u32 timeout; 2684 int ret; 2685 2686 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap); 2687 if (ret) { 2688 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret); 2689 return ret; 2690 } 2691 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12; 2692 2693 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) { 2694 dev_err(ctrl->device, 2695 "Minimum device page size %u too large for host (%u)\n", 2696 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT); 2697 return -ENODEV; 2698 } 2699 2700 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI) 2701 ctrl->ctrl_config = NVME_CC_CSS_CSI; 2702 else 2703 ctrl->ctrl_config = NVME_CC_CSS_NVM; 2704 2705 /* 2706 * Setting CRIME results in CSTS.RDY before the media is ready. This 2707 * makes it possible for media related commands to return the error 2708 * NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY. Until the driver is 2709 * restructured to handle retries, disable CC.CRIME. 2710 */ 2711 ctrl->ctrl_config &= ~NVME_CC_CRIME; 2712 2713 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; 2714 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE; 2715 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; 2716 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); 2717 if (ret) 2718 return ret; 2719 2720 /* CAP value may change after initial CC write */ 2721 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap); 2722 if (ret) 2723 return ret; 2724 2725 timeout = NVME_CAP_TIMEOUT(ctrl->cap); 2726 if (ctrl->cap & NVME_CAP_CRMS_CRWMS) { 2727 u32 crto, ready_timeout; 2728 2729 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto); 2730 if (ret) { 2731 dev_err(ctrl->device, "Reading CRTO failed (%d)\n", 2732 ret); 2733 return ret; 2734 } 2735 2736 /* 2737 * CRTO should always be greater or equal to CAP.TO, but some 2738 * devices are known to get this wrong. Use the larger of the 2739 * two values. 2740 */ 2741 ready_timeout = NVME_CRTO_CRWMT(crto); 2742 2743 if (ready_timeout < timeout) 2744 dev_warn_once(ctrl->device, "bad crto:%x cap:%llx\n", 2745 crto, ctrl->cap); 2746 else 2747 timeout = ready_timeout; 2748 } 2749 2750 ctrl->ctrl_config |= NVME_CC_ENABLE; 2751 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); 2752 if (ret) 2753 return ret; 2754 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY, 2755 (timeout + 1) / 2, "initialisation"); 2756 } 2757 EXPORT_SYMBOL_GPL(nvme_enable_ctrl); 2758 2759 static int nvme_configure_timestamp(struct nvme_ctrl *ctrl) 2760 { 2761 __le64 ts; 2762 int ret; 2763 2764 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP)) 2765 return 0; 2766 2767 ts = cpu_to_le64(ktime_to_ms(ktime_get_real())); 2768 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts), 2769 NULL); 2770 if (ret) 2771 dev_warn_once(ctrl->device, 2772 "could not set timestamp (%d)\n", ret); 2773 return ret; 2774 } 2775 2776 static int nvme_configure_host_options(struct nvme_ctrl *ctrl) 2777 { 2778 struct nvme_feat_host_behavior *host; 2779 u8 acre = 0, lbafee = 0; 2780 int ret; 2781 2782 /* Don't bother enabling the feature if retry delay is not reported */ 2783 if (ctrl->crdt[0]) 2784 acre = NVME_ENABLE_ACRE; 2785 if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) 2786 lbafee = NVME_ENABLE_LBAFEE; 2787 2788 if (!acre && !lbafee) 2789 return 0; 2790 2791 host = kzalloc(sizeof(*host), GFP_KERNEL); 2792 if (!host) 2793 return 0; 2794 2795 host->acre = acre; 2796 host->lbafee = lbafee; 2797 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0, 2798 host, sizeof(*host), NULL); 2799 kfree(host); 2800 return ret; 2801 } 2802 2803 /* 2804 * The function checks whether the given total (exlat + enlat) latency of 2805 * a power state allows the latter to be used as an APST transition target. 2806 * It does so by comparing the latency to the primary and secondary latency 2807 * tolerances defined by module params. If there's a match, the corresponding 2808 * timeout value is returned and the matching tolerance index (1 or 2) is 2809 * reported. 2810 */ 2811 static bool nvme_apst_get_transition_time(u64 total_latency, 2812 u64 *transition_time, unsigned *last_index) 2813 { 2814 if (total_latency <= apst_primary_latency_tol_us) { 2815 if (*last_index == 1) 2816 return false; 2817 *last_index = 1; 2818 *transition_time = apst_primary_timeout_ms; 2819 return true; 2820 } 2821 if (apst_secondary_timeout_ms && 2822 total_latency <= apst_secondary_latency_tol_us) { 2823 if (*last_index <= 2) 2824 return false; 2825 *last_index = 2; 2826 *transition_time = apst_secondary_timeout_ms; 2827 return true; 2828 } 2829 return false; 2830 } 2831 2832 /* 2833 * APST (Autonomous Power State Transition) lets us program a table of power 2834 * state transitions that the controller will perform automatically. 2835 * 2836 * Depending on module params, one of the two supported techniques will be used: 2837 * 2838 * - If the parameters provide explicit timeouts and tolerances, they will be 2839 * used to build a table with up to 2 non-operational states to transition to. 2840 * The default parameter values were selected based on the values used by 2841 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic 2842 * regeneration of the APST table in the event of switching between external 2843 * and battery power, the timeouts and tolerances reflect a compromise 2844 * between values used by Microsoft for AC and battery scenarios. 2845 * - If not, we'll configure the table with a simple heuristic: we are willing 2846 * to spend at most 2% of the time transitioning between power states. 2847 * Therefore, when running in any given state, we will enter the next 2848 * lower-power non-operational state after waiting 50 * (enlat + exlat) 2849 * microseconds, as long as that state's exit latency is under the requested 2850 * maximum latency. 2851 * 2852 * We will not autonomously enter any non-operational state for which the total 2853 * latency exceeds ps_max_latency_us. 2854 * 2855 * Users can set ps_max_latency_us to zero to turn off APST. 2856 */ 2857 static int nvme_configure_apst(struct nvme_ctrl *ctrl) 2858 { 2859 struct nvme_feat_auto_pst *table; 2860 unsigned apste = 0; 2861 u64 max_lat_us = 0; 2862 __le64 target = 0; 2863 int max_ps = -1; 2864 int state; 2865 int ret; 2866 unsigned last_lt_index = UINT_MAX; 2867 2868 /* 2869 * If APST isn't supported or if we haven't been initialized yet, 2870 * then don't do anything. 2871 */ 2872 if (!ctrl->apsta) 2873 return 0; 2874 2875 if (ctrl->npss > 31) { 2876 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n"); 2877 return 0; 2878 } 2879 2880 table = kzalloc(sizeof(*table), GFP_KERNEL); 2881 if (!table) 2882 return 0; 2883 2884 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) { 2885 /* Turn off APST. */ 2886 dev_dbg(ctrl->device, "APST disabled\n"); 2887 goto done; 2888 } 2889 2890 /* 2891 * Walk through all states from lowest- to highest-power. 2892 * According to the spec, lower-numbered states use more power. NPSS, 2893 * despite the name, is the index of the lowest-power state, not the 2894 * number of states. 2895 */ 2896 for (state = (int)ctrl->npss; state >= 0; state--) { 2897 u64 total_latency_us, exit_latency_us, transition_ms; 2898 2899 if (target) 2900 table->entries[state] = target; 2901 2902 /* 2903 * Don't allow transitions to the deepest state if it's quirked 2904 * off. 2905 */ 2906 if (state == ctrl->npss && 2907 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) 2908 continue; 2909 2910 /* 2911 * Is this state a useful non-operational state for higher-power 2912 * states to autonomously transition to? 2913 */ 2914 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE)) 2915 continue; 2916 2917 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat); 2918 if (exit_latency_us > ctrl->ps_max_latency_us) 2919 continue; 2920 2921 total_latency_us = exit_latency_us + 2922 le32_to_cpu(ctrl->psd[state].entry_lat); 2923 2924 /* 2925 * This state is good. It can be used as the APST idle target 2926 * for higher power states. 2927 */ 2928 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) { 2929 if (!nvme_apst_get_transition_time(total_latency_us, 2930 &transition_ms, &last_lt_index)) 2931 continue; 2932 } else { 2933 transition_ms = total_latency_us + 19; 2934 do_div(transition_ms, 20); 2935 if (transition_ms > (1 << 24) - 1) 2936 transition_ms = (1 << 24) - 1; 2937 } 2938 2939 target = cpu_to_le64((state << 3) | (transition_ms << 8)); 2940 if (max_ps == -1) 2941 max_ps = state; 2942 if (total_latency_us > max_lat_us) 2943 max_lat_us = total_latency_us; 2944 } 2945 2946 if (max_ps == -1) 2947 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n"); 2948 else 2949 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n", 2950 max_ps, max_lat_us, (int)sizeof(*table), table); 2951 apste = 1; 2952 2953 done: 2954 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste, 2955 table, sizeof(*table), NULL); 2956 if (ret) 2957 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret); 2958 kfree(table); 2959 return ret; 2960 } 2961 2962 static void nvme_set_latency_tolerance(struct device *dev, s32 val) 2963 { 2964 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); 2965 u64 latency; 2966 2967 switch (val) { 2968 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT: 2969 case PM_QOS_LATENCY_ANY: 2970 latency = U64_MAX; 2971 break; 2972 2973 default: 2974 latency = val; 2975 } 2976 2977 if (ctrl->ps_max_latency_us != latency) { 2978 ctrl->ps_max_latency_us = latency; 2979 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE) 2980 nvme_configure_apst(ctrl); 2981 } 2982 } 2983 2984 struct nvme_core_quirk_entry { 2985 /* 2986 * NVMe model and firmware strings are padded with spaces. For 2987 * simplicity, strings in the quirk table are padded with NULLs 2988 * instead. 2989 */ 2990 u16 vid; 2991 const char *mn; 2992 const char *fr; 2993 unsigned long quirks; 2994 }; 2995 2996 static const struct nvme_core_quirk_entry core_quirks[] = { 2997 { 2998 /* 2999 * This Toshiba device seems to die using any APST states. See: 3000 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11 3001 */ 3002 .vid = 0x1179, 3003 .mn = "THNSF5256GPUK TOSHIBA", 3004 .quirks = NVME_QUIRK_NO_APST, 3005 }, 3006 { 3007 /* 3008 * This LiteON CL1-3D*-Q11 firmware version has a race 3009 * condition associated with actions related to suspend to idle 3010 * LiteON has resolved the problem in future firmware 3011 */ 3012 .vid = 0x14a4, 3013 .fr = "22301111", 3014 .quirks = NVME_QUIRK_SIMPLE_SUSPEND, 3015 }, 3016 { 3017 /* 3018 * This Kioxia CD6-V Series / HPE PE8030 device times out and 3019 * aborts I/O during any load, but more easily reproducible 3020 * with discards (fstrim). 3021 * 3022 * The device is left in a state where it is also not possible 3023 * to use "nvme set-feature" to disable APST, but booting with 3024 * nvme_core.default_ps_max_latency=0 works. 3025 */ 3026 .vid = 0x1e0f, 3027 .mn = "KCD6XVUL6T40", 3028 .quirks = NVME_QUIRK_NO_APST, 3029 }, 3030 { 3031 /* 3032 * The external Samsung X5 SSD fails initialization without a 3033 * delay before checking if it is ready and has a whole set of 3034 * other problems. To make this even more interesting, it 3035 * shares the PCI ID with internal Samsung 970 Evo Plus that 3036 * does not need or want these quirks. 3037 */ 3038 .vid = 0x144d, 3039 .mn = "Samsung Portable SSD X5", 3040 .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3041 NVME_QUIRK_NO_DEEPEST_PS | 3042 NVME_QUIRK_IGNORE_DEV_SUBNQN, 3043 } 3044 }; 3045 3046 /* match is null-terminated but idstr is space-padded. */ 3047 static bool string_matches(const char *idstr, const char *match, size_t len) 3048 { 3049 size_t matchlen; 3050 3051 if (!match) 3052 return true; 3053 3054 matchlen = strlen(match); 3055 WARN_ON_ONCE(matchlen > len); 3056 3057 if (memcmp(idstr, match, matchlen)) 3058 return false; 3059 3060 for (; matchlen < len; matchlen++) 3061 if (idstr[matchlen] != ' ') 3062 return false; 3063 3064 return true; 3065 } 3066 3067 static bool quirk_matches(const struct nvme_id_ctrl *id, 3068 const struct nvme_core_quirk_entry *q) 3069 { 3070 return q->vid == le16_to_cpu(id->vid) && 3071 string_matches(id->mn, q->mn, sizeof(id->mn)) && 3072 string_matches(id->fr, q->fr, sizeof(id->fr)); 3073 } 3074 3075 static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl, 3076 struct nvme_id_ctrl *id) 3077 { 3078 size_t nqnlen; 3079 int off; 3080 3081 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) { 3082 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE); 3083 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) { 3084 strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE); 3085 return; 3086 } 3087 3088 if (ctrl->vs >= NVME_VS(1, 2, 1)) 3089 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n"); 3090 } 3091 3092 /* 3093 * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe 3094 * Base Specification 2.0. It is slightly different from the format 3095 * specified there due to historic reasons, and we can't change it now. 3096 */ 3097 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE, 3098 "nqn.2014.08.org.nvmexpress:%04x%04x", 3099 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid)); 3100 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn)); 3101 off += sizeof(id->sn); 3102 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn)); 3103 off += sizeof(id->mn); 3104 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off); 3105 } 3106 3107 static void nvme_release_subsystem(struct device *dev) 3108 { 3109 struct nvme_subsystem *subsys = 3110 container_of(dev, struct nvme_subsystem, dev); 3111 3112 if (subsys->instance >= 0) 3113 ida_free(&nvme_instance_ida, subsys->instance); 3114 kfree(subsys); 3115 } 3116 3117 static void nvme_destroy_subsystem(struct kref *ref) 3118 { 3119 struct nvme_subsystem *subsys = 3120 container_of(ref, struct nvme_subsystem, ref); 3121 3122 mutex_lock(&nvme_subsystems_lock); 3123 list_del(&subsys->entry); 3124 mutex_unlock(&nvme_subsystems_lock); 3125 3126 ida_destroy(&subsys->ns_ida); 3127 device_del(&subsys->dev); 3128 put_device(&subsys->dev); 3129 } 3130 3131 static void nvme_put_subsystem(struct nvme_subsystem *subsys) 3132 { 3133 kref_put(&subsys->ref, nvme_destroy_subsystem); 3134 } 3135 3136 static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn) 3137 { 3138 struct nvme_subsystem *subsys; 3139 3140 lockdep_assert_held(&nvme_subsystems_lock); 3141 3142 /* 3143 * Fail matches for discovery subsystems. This results 3144 * in each discovery controller bound to a unique subsystem. 3145 * This avoids issues with validating controller values 3146 * that can only be true when there is a single unique subsystem. 3147 * There may be multiple and completely independent entities 3148 * that provide discovery controllers. 3149 */ 3150 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME)) 3151 return NULL; 3152 3153 list_for_each_entry(subsys, &nvme_subsystems, entry) { 3154 if (strcmp(subsys->subnqn, subsysnqn)) 3155 continue; 3156 if (!kref_get_unless_zero(&subsys->ref)) 3157 continue; 3158 return subsys; 3159 } 3160 3161 return NULL; 3162 } 3163 3164 static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl) 3165 { 3166 return ctrl->opts && ctrl->opts->discovery_nqn; 3167 } 3168 3169 static bool nvme_validate_cntlid(struct nvme_subsystem *subsys, 3170 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 3171 { 3172 struct nvme_ctrl *tmp; 3173 3174 lockdep_assert_held(&nvme_subsystems_lock); 3175 3176 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) { 3177 if (nvme_state_terminal(tmp)) 3178 continue; 3179 3180 if (tmp->cntlid == ctrl->cntlid) { 3181 dev_err(ctrl->device, 3182 "Duplicate cntlid %u with %s, subsys %s, rejecting\n", 3183 ctrl->cntlid, dev_name(tmp->device), 3184 subsys->subnqn); 3185 return false; 3186 } 3187 3188 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) || 3189 nvme_discovery_ctrl(ctrl)) 3190 continue; 3191 3192 dev_err(ctrl->device, 3193 "Subsystem does not support multiple controllers\n"); 3194 return false; 3195 } 3196 3197 return true; 3198 } 3199 3200 static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 3201 { 3202 struct nvme_subsystem *subsys, *found; 3203 int ret; 3204 3205 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL); 3206 if (!subsys) 3207 return -ENOMEM; 3208 3209 subsys->instance = -1; 3210 mutex_init(&subsys->lock); 3211 kref_init(&subsys->ref); 3212 INIT_LIST_HEAD(&subsys->ctrls); 3213 INIT_LIST_HEAD(&subsys->nsheads); 3214 nvme_init_subnqn(subsys, ctrl, id); 3215 memcpy(subsys->serial, id->sn, sizeof(subsys->serial)); 3216 memcpy(subsys->model, id->mn, sizeof(subsys->model)); 3217 subsys->vendor_id = le16_to_cpu(id->vid); 3218 subsys->cmic = id->cmic; 3219 3220 /* Versions prior to 1.4 don't necessarily report a valid type */ 3221 if (id->cntrltype == NVME_CTRL_DISC || 3222 !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME)) 3223 subsys->subtype = NVME_NQN_DISC; 3224 else 3225 subsys->subtype = NVME_NQN_NVME; 3226 3227 if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) { 3228 dev_err(ctrl->device, 3229 "Subsystem %s is not a discovery controller", 3230 subsys->subnqn); 3231 kfree(subsys); 3232 return -EINVAL; 3233 } 3234 nvme_mpath_default_iopolicy(subsys); 3235 3236 subsys->dev.class = &nvme_subsys_class; 3237 subsys->dev.release = nvme_release_subsystem; 3238 subsys->dev.groups = nvme_subsys_attrs_groups; 3239 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance); 3240 device_initialize(&subsys->dev); 3241 3242 mutex_lock(&nvme_subsystems_lock); 3243 found = __nvme_find_get_subsystem(subsys->subnqn); 3244 if (found) { 3245 put_device(&subsys->dev); 3246 subsys = found; 3247 3248 if (!nvme_validate_cntlid(subsys, ctrl, id)) { 3249 ret = -EINVAL; 3250 goto out_put_subsystem; 3251 } 3252 } else { 3253 ret = device_add(&subsys->dev); 3254 if (ret) { 3255 dev_err(ctrl->device, 3256 "failed to register subsystem device.\n"); 3257 put_device(&subsys->dev); 3258 goto out_unlock; 3259 } 3260 ida_init(&subsys->ns_ida); 3261 list_add_tail(&subsys->entry, &nvme_subsystems); 3262 } 3263 3264 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj, 3265 dev_name(ctrl->device)); 3266 if (ret) { 3267 dev_err(ctrl->device, 3268 "failed to create sysfs link from subsystem.\n"); 3269 goto out_put_subsystem; 3270 } 3271 3272 if (!found) 3273 subsys->instance = ctrl->instance; 3274 ctrl->subsys = subsys; 3275 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls); 3276 mutex_unlock(&nvme_subsystems_lock); 3277 return 0; 3278 3279 out_put_subsystem: 3280 nvme_put_subsystem(subsys); 3281 out_unlock: 3282 mutex_unlock(&nvme_subsystems_lock); 3283 return ret; 3284 } 3285 3286 static int nvme_get_log_lsi(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, 3287 u8 lsp, u8 csi, void *log, size_t size, u64 offset, u16 lsi) 3288 { 3289 struct nvme_command c = { }; 3290 u32 dwlen = nvme_bytes_to_numd(size); 3291 3292 c.get_log_page.opcode = nvme_admin_get_log_page; 3293 c.get_log_page.nsid = cpu_to_le32(nsid); 3294 c.get_log_page.lid = log_page; 3295 c.get_log_page.lsp = lsp; 3296 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1)); 3297 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16); 3298 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset)); 3299 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset)); 3300 c.get_log_page.csi = csi; 3301 c.get_log_page.lsi = cpu_to_le16(lsi); 3302 3303 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size); 3304 } 3305 3306 int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, 3307 void *log, size_t size, u64 offset) 3308 { 3309 return nvme_get_log_lsi(ctrl, nsid, log_page, lsp, csi, log, size, 3310 offset, 0); 3311 } 3312 3313 static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi, 3314 struct nvme_effects_log **log) 3315 { 3316 struct nvme_effects_log *old, *cel = xa_load(&ctrl->cels, csi); 3317 int ret; 3318 3319 if (cel) 3320 goto out; 3321 3322 cel = kzalloc(sizeof(*cel), GFP_KERNEL); 3323 if (!cel) 3324 return -ENOMEM; 3325 3326 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi, 3327 cel, sizeof(*cel), 0); 3328 if (ret) { 3329 kfree(cel); 3330 return ret; 3331 } 3332 3333 old = xa_store(&ctrl->cels, csi, cel, GFP_KERNEL); 3334 if (xa_is_err(old)) { 3335 kfree(cel); 3336 return xa_err(old); 3337 } 3338 out: 3339 *log = cel; 3340 return 0; 3341 } 3342 3343 static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units) 3344 { 3345 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val; 3346 3347 if (check_shl_overflow(1U, units + page_shift - 9, &val)) 3348 return UINT_MAX; 3349 return val; 3350 } 3351 3352 static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl) 3353 { 3354 struct nvme_command c = { }; 3355 struct nvme_id_ctrl_nvm *id; 3356 int ret; 3357 3358 /* 3359 * Even though NVMe spec explicitly states that MDTS is not applicable 3360 * to the write-zeroes, we are cautious and limit the size to the 3361 * controllers max_hw_sectors value, which is based on the MDTS field 3362 * and possibly other limiting factors. 3363 */ 3364 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) && 3365 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES)) 3366 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors; 3367 else 3368 ctrl->max_zeroes_sectors = 0; 3369 3370 if (ctrl->subsys->subtype != NVME_NQN_NVME || 3371 !nvme_id_cns_ok(ctrl, NVME_ID_CNS_CS_CTRL) || 3372 test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags)) 3373 return 0; 3374 3375 id = kzalloc(sizeof(*id), GFP_KERNEL); 3376 if (!id) 3377 return -ENOMEM; 3378 3379 c.identify.opcode = nvme_admin_identify; 3380 c.identify.cns = NVME_ID_CNS_CS_CTRL; 3381 c.identify.csi = NVME_CSI_NVM; 3382 3383 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id)); 3384 if (ret) 3385 goto free_data; 3386 3387 ctrl->dmrl = id->dmrl; 3388 ctrl->dmrsl = le32_to_cpu(id->dmrsl); 3389 if (id->wzsl) 3390 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl); 3391 3392 free_data: 3393 if (ret > 0) 3394 set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags); 3395 kfree(id); 3396 return ret; 3397 } 3398 3399 static int nvme_init_effects_log(struct nvme_ctrl *ctrl, 3400 u8 csi, struct nvme_effects_log **log) 3401 { 3402 struct nvme_effects_log *effects, *old; 3403 3404 effects = kzalloc(sizeof(*effects), GFP_KERNEL); 3405 if (!effects) 3406 return -ENOMEM; 3407 3408 old = xa_store(&ctrl->cels, csi, effects, GFP_KERNEL); 3409 if (xa_is_err(old)) { 3410 kfree(effects); 3411 return xa_err(old); 3412 } 3413 3414 *log = effects; 3415 return 0; 3416 } 3417 3418 static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl) 3419 { 3420 struct nvme_effects_log *log = ctrl->effects; 3421 3422 log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC | 3423 NVME_CMD_EFFECTS_NCC | 3424 NVME_CMD_EFFECTS_CSE_MASK); 3425 log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC | 3426 NVME_CMD_EFFECTS_CSE_MASK); 3427 3428 /* 3429 * The spec says the result of a security receive command depends on 3430 * the previous security send command. As such, many vendors log this 3431 * command as one to submitted only when no other commands to the same 3432 * namespace are outstanding. The intention is to tell the host to 3433 * prevent mixing security send and receive. 3434 * 3435 * This driver can only enforce such exclusive access against IO 3436 * queues, though. We are not readily able to enforce such a rule for 3437 * two commands to the admin queue, which is the only queue that 3438 * matters for this command. 3439 * 3440 * Rather than blindly freezing the IO queues for this effect that 3441 * doesn't even apply to IO, mask it off. 3442 */ 3443 log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK); 3444 3445 log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); 3446 log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); 3447 log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); 3448 } 3449 3450 static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 3451 { 3452 int ret = 0; 3453 3454 if (ctrl->effects) 3455 return 0; 3456 3457 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) { 3458 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects); 3459 if (ret < 0) 3460 return ret; 3461 } 3462 3463 if (!ctrl->effects) { 3464 ret = nvme_init_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects); 3465 if (ret < 0) 3466 return ret; 3467 } 3468 3469 nvme_init_known_nvm_effects(ctrl); 3470 return 0; 3471 } 3472 3473 static int nvme_check_ctrl_fabric_info(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) 3474 { 3475 /* 3476 * In fabrics we need to verify the cntlid matches the 3477 * admin connect 3478 */ 3479 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) { 3480 dev_err(ctrl->device, 3481 "Mismatching cntlid: Connect %u vs Identify %u, rejecting\n", 3482 ctrl->cntlid, le16_to_cpu(id->cntlid)); 3483 return -EINVAL; 3484 } 3485 3486 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) { 3487 dev_err(ctrl->device, 3488 "keep-alive support is mandatory for fabrics\n"); 3489 return -EINVAL; 3490 } 3491 3492 if (!nvme_discovery_ctrl(ctrl) && ctrl->ioccsz < 4) { 3493 dev_err(ctrl->device, 3494 "I/O queue command capsule supported size %d < 4\n", 3495 ctrl->ioccsz); 3496 return -EINVAL; 3497 } 3498 3499 if (!nvme_discovery_ctrl(ctrl) && ctrl->iorcsz < 1) { 3500 dev_err(ctrl->device, 3501 "I/O queue response capsule supported size %d < 1\n", 3502 ctrl->iorcsz); 3503 return -EINVAL; 3504 } 3505 3506 if (!ctrl->maxcmd) { 3507 dev_warn(ctrl->device, 3508 "Firmware bug: maximum outstanding commands is 0\n"); 3509 ctrl->maxcmd = ctrl->sqsize + 1; 3510 } 3511 3512 return 0; 3513 } 3514 3515 static int nvme_init_identify(struct nvme_ctrl *ctrl) 3516 { 3517 struct queue_limits lim; 3518 struct nvme_id_ctrl *id; 3519 u32 max_hw_sectors; 3520 bool prev_apst_enabled; 3521 int ret; 3522 3523 ret = nvme_identify_ctrl(ctrl, &id); 3524 if (ret) { 3525 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret); 3526 return -EIO; 3527 } 3528 3529 if (!(ctrl->ops->flags & NVME_F_FABRICS)) 3530 ctrl->cntlid = le16_to_cpu(id->cntlid); 3531 3532 if (!ctrl->identified) { 3533 unsigned int i; 3534 3535 /* 3536 * Check for quirks. Quirk can depend on firmware version, 3537 * so, in principle, the set of quirks present can change 3538 * across a reset. As a possible future enhancement, we 3539 * could re-scan for quirks every time we reinitialize 3540 * the device, but we'd have to make sure that the driver 3541 * behaves intelligently if the quirks change. 3542 */ 3543 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) { 3544 if (quirk_matches(id, &core_quirks[i])) 3545 ctrl->quirks |= core_quirks[i].quirks; 3546 } 3547 3548 ret = nvme_init_subsystem(ctrl, id); 3549 if (ret) 3550 goto out_free; 3551 3552 ret = nvme_init_effects(ctrl, id); 3553 if (ret) 3554 goto out_free; 3555 } 3556 memcpy(ctrl->subsys->firmware_rev, id->fr, 3557 sizeof(ctrl->subsys->firmware_rev)); 3558 3559 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) { 3560 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n"); 3561 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS; 3562 } 3563 3564 ctrl->crdt[0] = le16_to_cpu(id->crdt1); 3565 ctrl->crdt[1] = le16_to_cpu(id->crdt2); 3566 ctrl->crdt[2] = le16_to_cpu(id->crdt3); 3567 3568 ctrl->oacs = le16_to_cpu(id->oacs); 3569 ctrl->oncs = le16_to_cpu(id->oncs); 3570 ctrl->mtfa = le16_to_cpu(id->mtfa); 3571 ctrl->oaes = le32_to_cpu(id->oaes); 3572 ctrl->wctemp = le16_to_cpu(id->wctemp); 3573 ctrl->cctemp = le16_to_cpu(id->cctemp); 3574 3575 atomic_set(&ctrl->abort_limit, id->acl + 1); 3576 ctrl->vwc = id->vwc; 3577 if (id->mdts) 3578 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts); 3579 else 3580 max_hw_sectors = UINT_MAX; 3581 ctrl->max_hw_sectors = 3582 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors); 3583 3584 lim = queue_limits_start_update(ctrl->admin_q); 3585 nvme_set_ctrl_limits(ctrl, &lim); 3586 ret = queue_limits_commit_update(ctrl->admin_q, &lim); 3587 if (ret) 3588 goto out_free; 3589 3590 ctrl->sgls = le32_to_cpu(id->sgls); 3591 ctrl->kas = le16_to_cpu(id->kas); 3592 ctrl->max_namespaces = le32_to_cpu(id->mnan); 3593 ctrl->ctratt = le32_to_cpu(id->ctratt); 3594 3595 ctrl->cntrltype = id->cntrltype; 3596 ctrl->dctype = id->dctype; 3597 3598 if (id->rtd3e) { 3599 /* us -> s */ 3600 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC; 3601 3602 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time, 3603 shutdown_timeout, 60); 3604 3605 if (ctrl->shutdown_timeout != shutdown_timeout) 3606 dev_info(ctrl->device, 3607 "D3 entry latency set to %u seconds\n", 3608 ctrl->shutdown_timeout); 3609 } else 3610 ctrl->shutdown_timeout = shutdown_timeout; 3611 3612 ctrl->npss = id->npss; 3613 ctrl->apsta = id->apsta; 3614 prev_apst_enabled = ctrl->apst_enabled; 3615 if (ctrl->quirks & NVME_QUIRK_NO_APST) { 3616 if (force_apst && id->apsta) { 3617 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n"); 3618 ctrl->apst_enabled = true; 3619 } else { 3620 ctrl->apst_enabled = false; 3621 } 3622 } else { 3623 ctrl->apst_enabled = id->apsta; 3624 } 3625 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd)); 3626 3627 if (ctrl->ops->flags & NVME_F_FABRICS) { 3628 ctrl->icdoff = le16_to_cpu(id->icdoff); 3629 ctrl->ioccsz = le32_to_cpu(id->ioccsz); 3630 ctrl->iorcsz = le32_to_cpu(id->iorcsz); 3631 ctrl->maxcmd = le16_to_cpu(id->maxcmd); 3632 3633 ret = nvme_check_ctrl_fabric_info(ctrl, id); 3634 if (ret) 3635 goto out_free; 3636 } else { 3637 ctrl->hmpre = le32_to_cpu(id->hmpre); 3638 ctrl->hmmin = le32_to_cpu(id->hmmin); 3639 ctrl->hmminds = le32_to_cpu(id->hmminds); 3640 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd); 3641 } 3642 3643 ret = nvme_mpath_init_identify(ctrl, id); 3644 if (ret < 0) 3645 goto out_free; 3646 3647 if (ctrl->apst_enabled && !prev_apst_enabled) 3648 dev_pm_qos_expose_latency_tolerance(ctrl->device); 3649 else if (!ctrl->apst_enabled && prev_apst_enabled) 3650 dev_pm_qos_hide_latency_tolerance(ctrl->device); 3651 ctrl->awupf = le16_to_cpu(id->awupf); 3652 out_free: 3653 kfree(id); 3654 return ret; 3655 } 3656 3657 /* 3658 * Initialize the cached copies of the Identify data and various controller 3659 * register in our nvme_ctrl structure. This should be called as soon as 3660 * the admin queue is fully up and running. 3661 */ 3662 int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended) 3663 { 3664 int ret; 3665 3666 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs); 3667 if (ret) { 3668 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret); 3669 return ret; 3670 } 3671 3672 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize); 3673 3674 if (ctrl->vs >= NVME_VS(1, 1, 0)) 3675 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap); 3676 3677 ret = nvme_init_identify(ctrl); 3678 if (ret) 3679 return ret; 3680 3681 ret = nvme_configure_apst(ctrl); 3682 if (ret < 0) 3683 return ret; 3684 3685 ret = nvme_configure_timestamp(ctrl); 3686 if (ret < 0) 3687 return ret; 3688 3689 ret = nvme_configure_host_options(ctrl); 3690 if (ret < 0) 3691 return ret; 3692 3693 nvme_configure_opal(ctrl, was_suspended); 3694 3695 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) { 3696 /* 3697 * Do not return errors unless we are in a controller reset, 3698 * the controller works perfectly fine without hwmon. 3699 */ 3700 ret = nvme_hwmon_init(ctrl); 3701 if (ret == -EINTR) 3702 return ret; 3703 } 3704 3705 clear_bit(NVME_CTRL_DIRTY_CAPABILITY, &ctrl->flags); 3706 ctrl->identified = true; 3707 3708 nvme_start_keep_alive(ctrl); 3709 3710 return 0; 3711 } 3712 EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish); 3713 3714 static int nvme_dev_open(struct inode *inode, struct file *file) 3715 { 3716 struct nvme_ctrl *ctrl = 3717 container_of(inode->i_cdev, struct nvme_ctrl, cdev); 3718 3719 switch (nvme_ctrl_state(ctrl)) { 3720 case NVME_CTRL_LIVE: 3721 break; 3722 default: 3723 return -EWOULDBLOCK; 3724 } 3725 3726 nvme_get_ctrl(ctrl); 3727 if (!try_module_get(ctrl->ops->module)) { 3728 nvme_put_ctrl(ctrl); 3729 return -EINVAL; 3730 } 3731 3732 file->private_data = ctrl; 3733 return 0; 3734 } 3735 3736 static int nvme_dev_release(struct inode *inode, struct file *file) 3737 { 3738 struct nvme_ctrl *ctrl = 3739 container_of(inode->i_cdev, struct nvme_ctrl, cdev); 3740 3741 module_put(ctrl->ops->module); 3742 nvme_put_ctrl(ctrl); 3743 return 0; 3744 } 3745 3746 static const struct file_operations nvme_dev_fops = { 3747 .owner = THIS_MODULE, 3748 .open = nvme_dev_open, 3749 .release = nvme_dev_release, 3750 .unlocked_ioctl = nvme_dev_ioctl, 3751 .compat_ioctl = compat_ptr_ioctl, 3752 .uring_cmd = nvme_dev_uring_cmd, 3753 }; 3754 3755 static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl, 3756 unsigned nsid) 3757 { 3758 struct nvme_ns_head *h; 3759 3760 lockdep_assert_held(&ctrl->subsys->lock); 3761 3762 list_for_each_entry(h, &ctrl->subsys->nsheads, entry) { 3763 /* 3764 * Private namespaces can share NSIDs under some conditions. 3765 * In that case we can't use the same ns_head for namespaces 3766 * with the same NSID. 3767 */ 3768 if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h)) 3769 continue; 3770 if (nvme_tryget_ns_head(h)) 3771 return h; 3772 } 3773 3774 return NULL; 3775 } 3776 3777 static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys, 3778 struct nvme_ns_ids *ids) 3779 { 3780 bool has_uuid = !uuid_is_null(&ids->uuid); 3781 bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid)); 3782 bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64)); 3783 struct nvme_ns_head *h; 3784 3785 lockdep_assert_held(&subsys->lock); 3786 3787 list_for_each_entry(h, &subsys->nsheads, entry) { 3788 if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid)) 3789 return -EINVAL; 3790 if (has_nguid && 3791 memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0) 3792 return -EINVAL; 3793 if (has_eui64 && 3794 memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0) 3795 return -EINVAL; 3796 } 3797 3798 return 0; 3799 } 3800 3801 static void nvme_cdev_rel(struct device *dev) 3802 { 3803 ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt)); 3804 } 3805 3806 void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device) 3807 { 3808 cdev_device_del(cdev, cdev_device); 3809 put_device(cdev_device); 3810 } 3811 3812 int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, 3813 const struct file_operations *fops, struct module *owner) 3814 { 3815 int minor, ret; 3816 3817 minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL); 3818 if (minor < 0) 3819 return minor; 3820 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor); 3821 cdev_device->class = &nvme_ns_chr_class; 3822 cdev_device->release = nvme_cdev_rel; 3823 device_initialize(cdev_device); 3824 cdev_init(cdev, fops); 3825 cdev->owner = owner; 3826 ret = cdev_device_add(cdev, cdev_device); 3827 if (ret) 3828 put_device(cdev_device); 3829 3830 return ret; 3831 } 3832 3833 static int nvme_ns_chr_open(struct inode *inode, struct file *file) 3834 { 3835 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev)); 3836 } 3837 3838 static int nvme_ns_chr_release(struct inode *inode, struct file *file) 3839 { 3840 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev)); 3841 return 0; 3842 } 3843 3844 static const struct file_operations nvme_ns_chr_fops = { 3845 .owner = THIS_MODULE, 3846 .open = nvme_ns_chr_open, 3847 .release = nvme_ns_chr_release, 3848 .unlocked_ioctl = nvme_ns_chr_ioctl, 3849 .compat_ioctl = compat_ptr_ioctl, 3850 .uring_cmd = nvme_ns_chr_uring_cmd, 3851 .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll, 3852 }; 3853 3854 static int nvme_add_ns_cdev(struct nvme_ns *ns) 3855 { 3856 int ret; 3857 3858 ns->cdev_device.parent = ns->ctrl->device; 3859 ret = dev_set_name(&ns->cdev_device, "ng%dn%d", 3860 ns->ctrl->instance, ns->head->instance); 3861 if (ret) 3862 return ret; 3863 3864 return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops, 3865 ns->ctrl->ops->module); 3866 } 3867 3868 static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl, 3869 struct nvme_ns_info *info) 3870 { 3871 struct nvme_ns_head *head; 3872 size_t size = sizeof(*head); 3873 int ret = -ENOMEM; 3874 3875 #ifdef CONFIG_NVME_MULTIPATH 3876 size += num_possible_nodes() * sizeof(struct nvme_ns *); 3877 #endif 3878 3879 head = kzalloc(size, GFP_KERNEL); 3880 if (!head) 3881 goto out; 3882 ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL); 3883 if (ret < 0) 3884 goto out_free_head; 3885 head->instance = ret; 3886 INIT_LIST_HEAD(&head->list); 3887 ret = init_srcu_struct(&head->srcu); 3888 if (ret) 3889 goto out_ida_remove; 3890 head->subsys = ctrl->subsys; 3891 head->ns_id = info->nsid; 3892 head->ids = info->ids; 3893 head->shared = info->is_shared; 3894 head->rotational = info->is_rotational; 3895 ratelimit_state_init(&head->rs_nuse, 5 * HZ, 1); 3896 ratelimit_set_flags(&head->rs_nuse, RATELIMIT_MSG_ON_RELEASE); 3897 kref_init(&head->ref); 3898 3899 if (head->ids.csi) { 3900 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects); 3901 if (ret) 3902 goto out_cleanup_srcu; 3903 } else 3904 head->effects = ctrl->effects; 3905 3906 ret = nvme_mpath_alloc_disk(ctrl, head); 3907 if (ret) 3908 goto out_cleanup_srcu; 3909 3910 list_add_tail(&head->entry, &ctrl->subsys->nsheads); 3911 3912 kref_get(&ctrl->subsys->ref); 3913 3914 return head; 3915 out_cleanup_srcu: 3916 cleanup_srcu_struct(&head->srcu); 3917 out_ida_remove: 3918 ida_free(&ctrl->subsys->ns_ida, head->instance); 3919 out_free_head: 3920 kfree(head); 3921 out: 3922 if (ret > 0) 3923 ret = blk_status_to_errno(nvme_error_status(ret)); 3924 return ERR_PTR(ret); 3925 } 3926 3927 static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this, 3928 struct nvme_ns_ids *ids) 3929 { 3930 struct nvme_subsystem *s; 3931 int ret = 0; 3932 3933 /* 3934 * Note that this check is racy as we try to avoid holding the global 3935 * lock over the whole ns_head creation. But it is only intended as 3936 * a sanity check anyway. 3937 */ 3938 mutex_lock(&nvme_subsystems_lock); 3939 list_for_each_entry(s, &nvme_subsystems, entry) { 3940 if (s == this) 3941 continue; 3942 mutex_lock(&s->lock); 3943 ret = nvme_subsys_check_duplicate_ids(s, ids); 3944 mutex_unlock(&s->lock); 3945 if (ret) 3946 break; 3947 } 3948 mutex_unlock(&nvme_subsystems_lock); 3949 3950 return ret; 3951 } 3952 3953 static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info) 3954 { 3955 struct nvme_ctrl *ctrl = ns->ctrl; 3956 struct nvme_ns_head *head = NULL; 3957 int ret; 3958 3959 ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids); 3960 if (ret) { 3961 /* 3962 * We've found two different namespaces on two different 3963 * subsystems that report the same ID. This is pretty nasty 3964 * for anything that actually requires unique device 3965 * identification. In the kernel we need this for multipathing, 3966 * and in user space the /dev/disk/by-id/ links rely on it. 3967 * 3968 * If the device also claims to be multi-path capable back off 3969 * here now and refuse the probe the second device as this is a 3970 * recipe for data corruption. If not this is probably a 3971 * cheap consumer device if on the PCIe bus, so let the user 3972 * proceed and use the shiny toy, but warn that with changing 3973 * probing order (which due to our async probing could just be 3974 * device taking longer to startup) the other device could show 3975 * up at any time. 3976 */ 3977 nvme_print_device_info(ctrl); 3978 if ((ns->ctrl->ops->flags & NVME_F_FABRICS) || /* !PCIe */ 3979 ((ns->ctrl->subsys->cmic & NVME_CTRL_CMIC_MULTI_CTRL) && 3980 info->is_shared)) { 3981 dev_err(ctrl->device, 3982 "ignoring nsid %d because of duplicate IDs\n", 3983 info->nsid); 3984 return ret; 3985 } 3986 3987 dev_err(ctrl->device, 3988 "clearing duplicate IDs for nsid %d\n", info->nsid); 3989 dev_err(ctrl->device, 3990 "use of /dev/disk/by-id/ may cause data corruption\n"); 3991 memset(&info->ids.nguid, 0, sizeof(info->ids.nguid)); 3992 memset(&info->ids.uuid, 0, sizeof(info->ids.uuid)); 3993 memset(&info->ids.eui64, 0, sizeof(info->ids.eui64)); 3994 ctrl->quirks |= NVME_QUIRK_BOGUS_NID; 3995 } 3996 3997 mutex_lock(&ctrl->subsys->lock); 3998 head = nvme_find_ns_head(ctrl, info->nsid); 3999 if (!head) { 4000 ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids); 4001 if (ret) { 4002 dev_err(ctrl->device, 4003 "duplicate IDs in subsystem for nsid %d\n", 4004 info->nsid); 4005 goto out_unlock; 4006 } 4007 head = nvme_alloc_ns_head(ctrl, info); 4008 if (IS_ERR(head)) { 4009 ret = PTR_ERR(head); 4010 goto out_unlock; 4011 } 4012 } else { 4013 ret = -EINVAL; 4014 if ((!info->is_shared || !head->shared) && 4015 !list_empty(&head->list)) { 4016 dev_err(ctrl->device, 4017 "Duplicate unshared namespace %d\n", 4018 info->nsid); 4019 goto out_put_ns_head; 4020 } 4021 if (!nvme_ns_ids_equal(&head->ids, &info->ids)) { 4022 dev_err(ctrl->device, 4023 "IDs don't match for shared namespace %d\n", 4024 info->nsid); 4025 goto out_put_ns_head; 4026 } 4027 4028 if (!multipath) { 4029 dev_warn(ctrl->device, 4030 "Found shared namespace %d, but multipathing not supported.\n", 4031 info->nsid); 4032 dev_warn_once(ctrl->device, 4033 "Shared namespace support requires core_nvme.multipath=Y.\n"); 4034 } 4035 } 4036 4037 list_add_tail_rcu(&ns->siblings, &head->list); 4038 ns->head = head; 4039 mutex_unlock(&ctrl->subsys->lock); 4040 return 0; 4041 4042 out_put_ns_head: 4043 nvme_put_ns_head(head); 4044 out_unlock: 4045 mutex_unlock(&ctrl->subsys->lock); 4046 return ret; 4047 } 4048 4049 struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid) 4050 { 4051 struct nvme_ns *ns, *ret = NULL; 4052 int srcu_idx; 4053 4054 srcu_idx = srcu_read_lock(&ctrl->srcu); 4055 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 4056 srcu_read_lock_held(&ctrl->srcu)) { 4057 if (ns->head->ns_id == nsid) { 4058 if (!nvme_get_ns(ns)) 4059 continue; 4060 ret = ns; 4061 break; 4062 } 4063 if (ns->head->ns_id > nsid) 4064 break; 4065 } 4066 srcu_read_unlock(&ctrl->srcu, srcu_idx); 4067 return ret; 4068 } 4069 EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, "NVME_TARGET_PASSTHRU"); 4070 4071 /* 4072 * Add the namespace to the controller list while keeping the list ordered. 4073 */ 4074 static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns) 4075 { 4076 struct nvme_ns *tmp; 4077 4078 list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) { 4079 if (tmp->head->ns_id < ns->head->ns_id) { 4080 list_add_rcu(&ns->list, &tmp->list); 4081 return; 4082 } 4083 } 4084 list_add(&ns->list, &ns->ctrl->namespaces); 4085 } 4086 4087 static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info) 4088 { 4089 struct queue_limits lim = { }; 4090 struct nvme_ns *ns; 4091 struct gendisk *disk; 4092 int node = ctrl->numa_node; 4093 4094 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); 4095 if (!ns) 4096 return; 4097 4098 if (ctrl->opts && ctrl->opts->data_digest) 4099 lim.features |= BLK_FEAT_STABLE_WRITES; 4100 if (ctrl->ops->supports_pci_p2pdma && 4101 ctrl->ops->supports_pci_p2pdma(ctrl)) 4102 lim.features |= BLK_FEAT_PCI_P2PDMA; 4103 4104 disk = blk_mq_alloc_disk(ctrl->tagset, &lim, ns); 4105 if (IS_ERR(disk)) 4106 goto out_free_ns; 4107 disk->fops = &nvme_bdev_ops; 4108 disk->private_data = ns; 4109 4110 ns->disk = disk; 4111 ns->queue = disk->queue; 4112 ns->ctrl = ctrl; 4113 kref_init(&ns->kref); 4114 4115 if (nvme_init_ns_head(ns, info)) 4116 goto out_cleanup_disk; 4117 4118 /* 4119 * If multipathing is enabled, the device name for all disks and not 4120 * just those that represent shared namespaces needs to be based on the 4121 * subsystem instance. Using the controller instance for private 4122 * namespaces could lead to naming collisions between shared and private 4123 * namespaces if they don't use a common numbering scheme. 4124 * 4125 * If multipathing is not enabled, disk names must use the controller 4126 * instance as shared namespaces will show up as multiple block 4127 * devices. 4128 */ 4129 if (nvme_ns_head_multipath(ns->head)) { 4130 sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance, 4131 ctrl->instance, ns->head->instance); 4132 disk->flags |= GENHD_FL_HIDDEN; 4133 } else if (multipath) { 4134 sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance, 4135 ns->head->instance); 4136 } else { 4137 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance, 4138 ns->head->instance); 4139 } 4140 4141 if (nvme_update_ns_info(ns, info)) 4142 goto out_unlink_ns; 4143 4144 mutex_lock(&ctrl->namespaces_lock); 4145 /* 4146 * Ensure that no namespaces are added to the ctrl list after the queues 4147 * are frozen, thereby avoiding a deadlock between scan and reset. 4148 */ 4149 if (test_bit(NVME_CTRL_FROZEN, &ctrl->flags)) { 4150 mutex_unlock(&ctrl->namespaces_lock); 4151 goto out_unlink_ns; 4152 } 4153 nvme_ns_add_to_ctrl_list(ns); 4154 mutex_unlock(&ctrl->namespaces_lock); 4155 synchronize_srcu(&ctrl->srcu); 4156 nvme_get_ctrl(ctrl); 4157 4158 if (device_add_disk(ctrl->device, ns->disk, nvme_ns_attr_groups)) 4159 goto out_cleanup_ns_from_list; 4160 4161 if (!nvme_ns_head_multipath(ns->head)) 4162 nvme_add_ns_cdev(ns); 4163 4164 nvme_mpath_add_disk(ns, info->anagrpid); 4165 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name); 4166 4167 /* 4168 * Set ns->disk->device->driver_data to ns so we can access 4169 * ns->head->passthru_err_log_enabled in 4170 * nvme_io_passthru_err_log_enabled_[store | show](). 4171 */ 4172 dev_set_drvdata(disk_to_dev(ns->disk), ns); 4173 4174 return; 4175 4176 out_cleanup_ns_from_list: 4177 nvme_put_ctrl(ctrl); 4178 mutex_lock(&ctrl->namespaces_lock); 4179 list_del_rcu(&ns->list); 4180 mutex_unlock(&ctrl->namespaces_lock); 4181 synchronize_srcu(&ctrl->srcu); 4182 out_unlink_ns: 4183 mutex_lock(&ctrl->subsys->lock); 4184 list_del_rcu(&ns->siblings); 4185 if (list_empty(&ns->head->list)) 4186 list_del_init(&ns->head->entry); 4187 mutex_unlock(&ctrl->subsys->lock); 4188 nvme_put_ns_head(ns->head); 4189 out_cleanup_disk: 4190 put_disk(disk); 4191 out_free_ns: 4192 kfree(ns); 4193 } 4194 4195 static void nvme_ns_remove(struct nvme_ns *ns) 4196 { 4197 bool last_path = false; 4198 4199 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags)) 4200 return; 4201 4202 clear_bit(NVME_NS_READY, &ns->flags); 4203 set_capacity(ns->disk, 0); 4204 nvme_fault_inject_fini(&ns->fault_inject); 4205 4206 /* 4207 * Ensure that !NVME_NS_READY is seen by other threads to prevent 4208 * this ns going back into current_path. 4209 */ 4210 synchronize_srcu(&ns->head->srcu); 4211 4212 /* wait for concurrent submissions */ 4213 if (nvme_mpath_clear_current_path(ns)) 4214 synchronize_srcu(&ns->head->srcu); 4215 4216 mutex_lock(&ns->ctrl->subsys->lock); 4217 list_del_rcu(&ns->siblings); 4218 if (list_empty(&ns->head->list)) { 4219 if (!nvme_mpath_queue_if_no_path(ns->head)) 4220 list_del_init(&ns->head->entry); 4221 last_path = true; 4222 } 4223 mutex_unlock(&ns->ctrl->subsys->lock); 4224 4225 /* guarantee not available in head->list */ 4226 synchronize_srcu(&ns->head->srcu); 4227 4228 if (!nvme_ns_head_multipath(ns->head)) 4229 nvme_cdev_del(&ns->cdev, &ns->cdev_device); 4230 4231 nvme_mpath_remove_sysfs_link(ns); 4232 4233 del_gendisk(ns->disk); 4234 4235 mutex_lock(&ns->ctrl->namespaces_lock); 4236 list_del_rcu(&ns->list); 4237 mutex_unlock(&ns->ctrl->namespaces_lock); 4238 synchronize_srcu(&ns->ctrl->srcu); 4239 4240 if (last_path) 4241 nvme_mpath_remove_disk(ns->head); 4242 nvme_put_ns(ns); 4243 } 4244 4245 static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid) 4246 { 4247 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid); 4248 4249 if (ns) { 4250 nvme_ns_remove(ns); 4251 nvme_put_ns(ns); 4252 } 4253 } 4254 4255 static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info) 4256 { 4257 int ret = NVME_SC_INVALID_NS | NVME_STATUS_DNR; 4258 4259 if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) { 4260 dev_err(ns->ctrl->device, 4261 "identifiers changed for nsid %d\n", ns->head->ns_id); 4262 goto out; 4263 } 4264 4265 ret = nvme_update_ns_info(ns, info); 4266 out: 4267 /* 4268 * Only remove the namespace if we got a fatal error back from the 4269 * device, otherwise ignore the error and just move on. 4270 * 4271 * TODO: we should probably schedule a delayed retry here. 4272 */ 4273 if (ret > 0 && (ret & NVME_STATUS_DNR)) 4274 nvme_ns_remove(ns); 4275 } 4276 4277 static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid) 4278 { 4279 struct nvme_ns_info info = { .nsid = nsid }; 4280 struct nvme_ns *ns; 4281 int ret = 1; 4282 4283 if (nvme_identify_ns_descs(ctrl, &info)) 4284 return; 4285 4286 if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) { 4287 dev_warn(ctrl->device, 4288 "command set not reported for nsid: %d\n", nsid); 4289 return; 4290 } 4291 4292 /* 4293 * If available try to use the Command Set Idependent Identify Namespace 4294 * data structure to find all the generic information that is needed to 4295 * set up a namespace. If not fall back to the legacy version. 4296 */ 4297 if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) || 4298 (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS) || 4299 ctrl->vs >= NVME_VS(2, 0, 0)) 4300 ret = nvme_ns_info_from_id_cs_indep(ctrl, &info); 4301 if (ret > 0) 4302 ret = nvme_ns_info_from_identify(ctrl, &info); 4303 4304 if (info.is_removed) 4305 nvme_ns_remove_by_nsid(ctrl, nsid); 4306 4307 /* 4308 * Ignore the namespace if it is not ready. We will get an AEN once it 4309 * becomes ready and restart the scan. 4310 */ 4311 if (ret || !info.is_ready) 4312 return; 4313 4314 ns = nvme_find_get_ns(ctrl, nsid); 4315 if (ns) { 4316 nvme_validate_ns(ns, &info); 4317 nvme_put_ns(ns); 4318 } else { 4319 nvme_alloc_ns(ctrl, &info); 4320 } 4321 } 4322 4323 /** 4324 * struct async_scan_info - keeps track of controller & NSIDs to scan 4325 * @ctrl: Controller on which namespaces are being scanned 4326 * @next_nsid: Index of next NSID to scan in ns_list 4327 * @ns_list: Pointer to list of NSIDs to scan 4328 * 4329 * Note: There is a single async_scan_info structure shared by all instances 4330 * of nvme_scan_ns_async() scanning a given controller, so the atomic 4331 * operations on next_nsid are critical to ensure each instance scans a unique 4332 * NSID. 4333 */ 4334 struct async_scan_info { 4335 struct nvme_ctrl *ctrl; 4336 atomic_t next_nsid; 4337 __le32 *ns_list; 4338 }; 4339 4340 static void nvme_scan_ns_async(void *data, async_cookie_t cookie) 4341 { 4342 struct async_scan_info *scan_info = data; 4343 int idx; 4344 u32 nsid; 4345 4346 idx = (u32)atomic_fetch_inc(&scan_info->next_nsid); 4347 nsid = le32_to_cpu(scan_info->ns_list[idx]); 4348 4349 nvme_scan_ns(scan_info->ctrl, nsid); 4350 } 4351 4352 static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl, 4353 unsigned nsid) 4354 { 4355 struct nvme_ns *ns, *next; 4356 LIST_HEAD(rm_list); 4357 4358 mutex_lock(&ctrl->namespaces_lock); 4359 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) { 4360 if (ns->head->ns_id > nsid) { 4361 list_del_rcu(&ns->list); 4362 synchronize_srcu(&ctrl->srcu); 4363 list_add_tail_rcu(&ns->list, &rm_list); 4364 } 4365 } 4366 mutex_unlock(&ctrl->namespaces_lock); 4367 4368 list_for_each_entry_safe(ns, next, &rm_list, list) 4369 nvme_ns_remove(ns); 4370 } 4371 4372 static int nvme_scan_ns_list(struct nvme_ctrl *ctrl) 4373 { 4374 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32); 4375 __le32 *ns_list; 4376 u32 prev = 0; 4377 int ret = 0, i; 4378 ASYNC_DOMAIN(domain); 4379 struct async_scan_info scan_info; 4380 4381 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL); 4382 if (!ns_list) 4383 return -ENOMEM; 4384 4385 scan_info.ctrl = ctrl; 4386 scan_info.ns_list = ns_list; 4387 for (;;) { 4388 struct nvme_command cmd = { 4389 .identify.opcode = nvme_admin_identify, 4390 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST, 4391 .identify.nsid = cpu_to_le32(prev), 4392 }; 4393 4394 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list, 4395 NVME_IDENTIFY_DATA_SIZE); 4396 if (ret) { 4397 dev_warn(ctrl->device, 4398 "Identify NS List failed (status=0x%x)\n", ret); 4399 goto free; 4400 } 4401 4402 atomic_set(&scan_info.next_nsid, 0); 4403 for (i = 0; i < nr_entries; i++) { 4404 u32 nsid = le32_to_cpu(ns_list[i]); 4405 4406 if (!nsid) /* end of the list? */ 4407 goto out; 4408 async_schedule_domain(nvme_scan_ns_async, &scan_info, 4409 &domain); 4410 while (++prev < nsid) 4411 nvme_ns_remove_by_nsid(ctrl, prev); 4412 } 4413 async_synchronize_full_domain(&domain); 4414 } 4415 out: 4416 nvme_remove_invalid_namespaces(ctrl, prev); 4417 free: 4418 async_synchronize_full_domain(&domain); 4419 kfree(ns_list); 4420 return ret; 4421 } 4422 4423 static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl) 4424 { 4425 struct nvme_id_ctrl *id; 4426 u32 nn, i; 4427 4428 if (nvme_identify_ctrl(ctrl, &id)) 4429 return; 4430 nn = le32_to_cpu(id->nn); 4431 kfree(id); 4432 4433 for (i = 1; i <= nn; i++) 4434 nvme_scan_ns(ctrl, i); 4435 4436 nvme_remove_invalid_namespaces(ctrl, nn); 4437 } 4438 4439 static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl) 4440 { 4441 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32); 4442 __le32 *log; 4443 int error; 4444 4445 log = kzalloc(log_size, GFP_KERNEL); 4446 if (!log) 4447 return; 4448 4449 /* 4450 * We need to read the log to clear the AEN, but we don't want to rely 4451 * on it for the changed namespace information as userspace could have 4452 * raced with us in reading the log page, which could cause us to miss 4453 * updates. 4454 */ 4455 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, 4456 NVME_CSI_NVM, log, log_size, 0); 4457 if (error) 4458 dev_warn(ctrl->device, 4459 "reading changed ns log failed: %d\n", error); 4460 4461 kfree(log); 4462 } 4463 4464 static void nvme_scan_work(struct work_struct *work) 4465 { 4466 struct nvme_ctrl *ctrl = 4467 container_of(work, struct nvme_ctrl, scan_work); 4468 int ret; 4469 4470 /* No tagset on a live ctrl means IO queues could not created */ 4471 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE || !ctrl->tagset) 4472 return; 4473 4474 /* 4475 * Identify controller limits can change at controller reset due to 4476 * new firmware download, even though it is not common we cannot ignore 4477 * such scenario. Controller's non-mdts limits are reported in the unit 4478 * of logical blocks that is dependent on the format of attached 4479 * namespace. Hence re-read the limits at the time of ns allocation. 4480 */ 4481 ret = nvme_init_non_mdts_limits(ctrl); 4482 if (ret < 0) { 4483 dev_warn(ctrl->device, 4484 "reading non-mdts-limits failed: %d\n", ret); 4485 return; 4486 } 4487 4488 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) { 4489 dev_info(ctrl->device, "rescanning namespaces.\n"); 4490 nvme_clear_changed_ns_log(ctrl); 4491 } 4492 4493 mutex_lock(&ctrl->scan_lock); 4494 if (!nvme_id_cns_ok(ctrl, NVME_ID_CNS_NS_ACTIVE_LIST)) { 4495 nvme_scan_ns_sequential(ctrl); 4496 } else { 4497 /* 4498 * Fall back to sequential scan if DNR is set to handle broken 4499 * devices which should support Identify NS List (as per the VS 4500 * they report) but don't actually support it. 4501 */ 4502 ret = nvme_scan_ns_list(ctrl); 4503 if (ret > 0 && ret & NVME_STATUS_DNR) 4504 nvme_scan_ns_sequential(ctrl); 4505 } 4506 mutex_unlock(&ctrl->scan_lock); 4507 4508 /* Requeue if we have missed AENs */ 4509 if (test_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) 4510 nvme_queue_scan(ctrl); 4511 #ifdef CONFIG_NVME_MULTIPATH 4512 else if (ctrl->ana_log_buf) 4513 /* Re-read the ANA log page to not miss updates */ 4514 queue_work(nvme_wq, &ctrl->ana_work); 4515 #endif 4516 } 4517 4518 /* 4519 * This function iterates the namespace list unlocked to allow recovery from 4520 * controller failure. It is up to the caller to ensure the namespace list is 4521 * not modified by scan work while this function is executing. 4522 */ 4523 void nvme_remove_namespaces(struct nvme_ctrl *ctrl) 4524 { 4525 struct nvme_ns *ns, *next; 4526 LIST_HEAD(ns_list); 4527 4528 /* 4529 * make sure to requeue I/O to all namespaces as these 4530 * might result from the scan itself and must complete 4531 * for the scan_work to make progress 4532 */ 4533 nvme_mpath_clear_ctrl_paths(ctrl); 4534 4535 /* 4536 * Unquiesce io queues so any pending IO won't hang, especially 4537 * those submitted from scan work 4538 */ 4539 nvme_unquiesce_io_queues(ctrl); 4540 4541 /* prevent racing with ns scanning */ 4542 flush_work(&ctrl->scan_work); 4543 4544 /* 4545 * The dead states indicates the controller was not gracefully 4546 * disconnected. In that case, we won't be able to flush any data while 4547 * removing the namespaces' disks; fail all the queues now to avoid 4548 * potentially having to clean up the failed sync later. 4549 */ 4550 if (nvme_ctrl_state(ctrl) == NVME_CTRL_DEAD) 4551 nvme_mark_namespaces_dead(ctrl); 4552 4553 /* this is a no-op when called from the controller reset handler */ 4554 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO); 4555 4556 mutex_lock(&ctrl->namespaces_lock); 4557 list_splice_init_rcu(&ctrl->namespaces, &ns_list, synchronize_rcu); 4558 mutex_unlock(&ctrl->namespaces_lock); 4559 synchronize_srcu(&ctrl->srcu); 4560 4561 list_for_each_entry_safe(ns, next, &ns_list, list) 4562 nvme_ns_remove(ns); 4563 } 4564 EXPORT_SYMBOL_GPL(nvme_remove_namespaces); 4565 4566 static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env) 4567 { 4568 const struct nvme_ctrl *ctrl = 4569 container_of(dev, struct nvme_ctrl, ctrl_device); 4570 struct nvmf_ctrl_options *opts = ctrl->opts; 4571 int ret; 4572 4573 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name); 4574 if (ret) 4575 return ret; 4576 4577 if (opts) { 4578 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr); 4579 if (ret) 4580 return ret; 4581 4582 ret = add_uevent_var(env, "NVME_TRSVCID=%s", 4583 opts->trsvcid ?: "none"); 4584 if (ret) 4585 return ret; 4586 4587 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s", 4588 opts->host_traddr ?: "none"); 4589 if (ret) 4590 return ret; 4591 4592 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s", 4593 opts->host_iface ?: "none"); 4594 } 4595 return ret; 4596 } 4597 4598 static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata) 4599 { 4600 char *envp[2] = { envdata, NULL }; 4601 4602 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp); 4603 } 4604 4605 static void nvme_aen_uevent(struct nvme_ctrl *ctrl) 4606 { 4607 char *envp[2] = { NULL, NULL }; 4608 u32 aen_result = ctrl->aen_result; 4609 4610 ctrl->aen_result = 0; 4611 if (!aen_result) 4612 return; 4613 4614 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result); 4615 if (!envp[0]) 4616 return; 4617 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp); 4618 kfree(envp[0]); 4619 } 4620 4621 static void nvme_async_event_work(struct work_struct *work) 4622 { 4623 struct nvme_ctrl *ctrl = 4624 container_of(work, struct nvme_ctrl, async_event_work); 4625 4626 nvme_aen_uevent(ctrl); 4627 4628 /* 4629 * The transport drivers must guarantee AER submission here is safe by 4630 * flushing ctrl async_event_work after changing the controller state 4631 * from LIVE and before freeing the admin queue. 4632 */ 4633 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE) 4634 ctrl->ops->submit_async_event(ctrl); 4635 } 4636 4637 static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl) 4638 { 4639 4640 u32 csts; 4641 4642 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) 4643 return false; 4644 4645 if (csts == ~0) 4646 return false; 4647 4648 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP)); 4649 } 4650 4651 static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl) 4652 { 4653 struct nvme_fw_slot_info_log *log; 4654 u8 next_fw_slot, cur_fw_slot; 4655 4656 log = kmalloc(sizeof(*log), GFP_KERNEL); 4657 if (!log) 4658 return; 4659 4660 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM, 4661 log, sizeof(*log), 0)) { 4662 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n"); 4663 goto out_free_log; 4664 } 4665 4666 cur_fw_slot = log->afi & 0x7; 4667 next_fw_slot = (log->afi & 0x70) >> 4; 4668 if (!cur_fw_slot || (next_fw_slot && (cur_fw_slot != next_fw_slot))) { 4669 dev_info(ctrl->device, 4670 "Firmware is activated after next Controller Level Reset\n"); 4671 goto out_free_log; 4672 } 4673 4674 memcpy(ctrl->subsys->firmware_rev, &log->frs[cur_fw_slot - 1], 4675 sizeof(ctrl->subsys->firmware_rev)); 4676 4677 out_free_log: 4678 kfree(log); 4679 } 4680 4681 static void nvme_fw_act_work(struct work_struct *work) 4682 { 4683 struct nvme_ctrl *ctrl = container_of(work, 4684 struct nvme_ctrl, fw_act_work); 4685 unsigned long fw_act_timeout; 4686 4687 nvme_auth_stop(ctrl); 4688 4689 if (ctrl->mtfa) 4690 fw_act_timeout = jiffies + msecs_to_jiffies(ctrl->mtfa * 100); 4691 else 4692 fw_act_timeout = jiffies + secs_to_jiffies(admin_timeout); 4693 4694 nvme_quiesce_io_queues(ctrl); 4695 while (nvme_ctrl_pp_status(ctrl)) { 4696 if (time_after(jiffies, fw_act_timeout)) { 4697 dev_warn(ctrl->device, 4698 "Fw activation timeout, reset controller\n"); 4699 nvme_try_sched_reset(ctrl); 4700 return; 4701 } 4702 msleep(100); 4703 } 4704 4705 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_CONNECTING) || 4706 !nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE)) 4707 return; 4708 4709 nvme_unquiesce_io_queues(ctrl); 4710 /* read FW slot information to clear the AER */ 4711 nvme_get_fw_slot_info(ctrl); 4712 4713 queue_work(nvme_wq, &ctrl->async_event_work); 4714 } 4715 4716 static u32 nvme_aer_type(u32 result) 4717 { 4718 return result & 0x7; 4719 } 4720 4721 static u32 nvme_aer_subtype(u32 result) 4722 { 4723 return (result & 0xff00) >> 8; 4724 } 4725 4726 static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result) 4727 { 4728 u32 aer_notice_type = nvme_aer_subtype(result); 4729 bool requeue = true; 4730 4731 switch (aer_notice_type) { 4732 case NVME_AER_NOTICE_NS_CHANGED: 4733 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events); 4734 nvme_queue_scan(ctrl); 4735 break; 4736 case NVME_AER_NOTICE_FW_ACT_STARTING: 4737 /* 4738 * We are (ab)using the RESETTING state to prevent subsequent 4739 * recovery actions from interfering with the controller's 4740 * firmware activation. 4741 */ 4742 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) { 4743 requeue = false; 4744 queue_work(nvme_wq, &ctrl->fw_act_work); 4745 } 4746 break; 4747 #ifdef CONFIG_NVME_MULTIPATH 4748 case NVME_AER_NOTICE_ANA: 4749 if (!ctrl->ana_log_buf) 4750 break; 4751 queue_work(nvme_wq, &ctrl->ana_work); 4752 break; 4753 #endif 4754 case NVME_AER_NOTICE_DISC_CHANGED: 4755 ctrl->aen_result = result; 4756 break; 4757 default: 4758 dev_warn(ctrl->device, "async event result %08x\n", result); 4759 } 4760 return requeue; 4761 } 4762 4763 static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl) 4764 { 4765 dev_warn(ctrl->device, 4766 "resetting controller due to persistent internal error\n"); 4767 nvme_reset_ctrl(ctrl); 4768 } 4769 4770 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, 4771 volatile union nvme_result *res) 4772 { 4773 u32 result = le32_to_cpu(res->u32); 4774 u32 aer_type = nvme_aer_type(result); 4775 u32 aer_subtype = nvme_aer_subtype(result); 4776 bool requeue = true; 4777 4778 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS) 4779 return; 4780 4781 trace_nvme_async_event(ctrl, result); 4782 switch (aer_type) { 4783 case NVME_AER_NOTICE: 4784 requeue = nvme_handle_aen_notice(ctrl, result); 4785 break; 4786 case NVME_AER_ERROR: 4787 /* 4788 * For a persistent internal error, don't run async_event_work 4789 * to submit a new AER. The controller reset will do it. 4790 */ 4791 if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) { 4792 nvme_handle_aer_persistent_error(ctrl); 4793 return; 4794 } 4795 fallthrough; 4796 case NVME_AER_SMART: 4797 case NVME_AER_CSS: 4798 case NVME_AER_VS: 4799 ctrl->aen_result = result; 4800 break; 4801 default: 4802 break; 4803 } 4804 4805 if (requeue) 4806 queue_work(nvme_wq, &ctrl->async_event_work); 4807 } 4808 EXPORT_SYMBOL_GPL(nvme_complete_async_event); 4809 4810 int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 4811 const struct blk_mq_ops *ops, unsigned int cmd_size) 4812 { 4813 struct queue_limits lim = {}; 4814 int ret; 4815 4816 memset(set, 0, sizeof(*set)); 4817 set->ops = ops; 4818 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 4819 if (ctrl->ops->flags & NVME_F_FABRICS) 4820 /* Reserved for fabric connect and keep alive */ 4821 set->reserved_tags = 2; 4822 set->numa_node = ctrl->numa_node; 4823 if (ctrl->ops->flags & NVME_F_BLOCKING) 4824 set->flags |= BLK_MQ_F_BLOCKING; 4825 set->cmd_size = cmd_size; 4826 set->driver_data = ctrl; 4827 set->nr_hw_queues = 1; 4828 set->timeout = NVME_ADMIN_TIMEOUT; 4829 ret = blk_mq_alloc_tag_set(set); 4830 if (ret) 4831 return ret; 4832 4833 ctrl->admin_q = blk_mq_alloc_queue(set, &lim, NULL); 4834 if (IS_ERR(ctrl->admin_q)) { 4835 ret = PTR_ERR(ctrl->admin_q); 4836 goto out_free_tagset; 4837 } 4838 4839 if (ctrl->ops->flags & NVME_F_FABRICS) { 4840 ctrl->fabrics_q = blk_mq_alloc_queue(set, NULL, NULL); 4841 if (IS_ERR(ctrl->fabrics_q)) { 4842 ret = PTR_ERR(ctrl->fabrics_q); 4843 goto out_cleanup_admin_q; 4844 } 4845 } 4846 4847 ctrl->admin_tagset = set; 4848 return 0; 4849 4850 out_cleanup_admin_q: 4851 blk_mq_destroy_queue(ctrl->admin_q); 4852 blk_put_queue(ctrl->admin_q); 4853 out_free_tagset: 4854 blk_mq_free_tag_set(set); 4855 ctrl->admin_q = NULL; 4856 ctrl->fabrics_q = NULL; 4857 return ret; 4858 } 4859 EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set); 4860 4861 void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl) 4862 { 4863 /* 4864 * As we're about to destroy the queue and free tagset 4865 * we can not have keep-alive work running. 4866 */ 4867 nvme_stop_keep_alive(ctrl); 4868 blk_mq_destroy_queue(ctrl->admin_q); 4869 blk_put_queue(ctrl->admin_q); 4870 if (ctrl->ops->flags & NVME_F_FABRICS) { 4871 blk_mq_destroy_queue(ctrl->fabrics_q); 4872 blk_put_queue(ctrl->fabrics_q); 4873 } 4874 blk_mq_free_tag_set(ctrl->admin_tagset); 4875 } 4876 EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set); 4877 4878 int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, 4879 const struct blk_mq_ops *ops, unsigned int nr_maps, 4880 unsigned int cmd_size) 4881 { 4882 int ret; 4883 4884 memset(set, 0, sizeof(*set)); 4885 set->ops = ops; 4886 set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1); 4887 /* 4888 * Some Apple controllers requires tags to be unique across admin and 4889 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue. 4890 */ 4891 if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS) 4892 set->reserved_tags = NVME_AQ_DEPTH; 4893 else if (ctrl->ops->flags & NVME_F_FABRICS) 4894 /* Reserved for fabric connect */ 4895 set->reserved_tags = 1; 4896 set->numa_node = ctrl->numa_node; 4897 if (ctrl->ops->flags & NVME_F_BLOCKING) 4898 set->flags |= BLK_MQ_F_BLOCKING; 4899 set->cmd_size = cmd_size; 4900 set->driver_data = ctrl; 4901 set->nr_hw_queues = ctrl->queue_count - 1; 4902 set->timeout = NVME_IO_TIMEOUT; 4903 set->nr_maps = nr_maps; 4904 ret = blk_mq_alloc_tag_set(set); 4905 if (ret) 4906 return ret; 4907 4908 if (ctrl->ops->flags & NVME_F_FABRICS) { 4909 struct queue_limits lim = { 4910 .features = BLK_FEAT_SKIP_TAGSET_QUIESCE, 4911 }; 4912 4913 ctrl->connect_q = blk_mq_alloc_queue(set, &lim, NULL); 4914 if (IS_ERR(ctrl->connect_q)) { 4915 ret = PTR_ERR(ctrl->connect_q); 4916 goto out_free_tag_set; 4917 } 4918 } 4919 4920 ctrl->tagset = set; 4921 return 0; 4922 4923 out_free_tag_set: 4924 blk_mq_free_tag_set(set); 4925 ctrl->connect_q = NULL; 4926 return ret; 4927 } 4928 EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set); 4929 4930 void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl) 4931 { 4932 if (ctrl->ops->flags & NVME_F_FABRICS) { 4933 blk_mq_destroy_queue(ctrl->connect_q); 4934 blk_put_queue(ctrl->connect_q); 4935 } 4936 blk_mq_free_tag_set(ctrl->tagset); 4937 } 4938 EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set); 4939 4940 void nvme_stop_ctrl(struct nvme_ctrl *ctrl) 4941 { 4942 nvme_mpath_stop(ctrl); 4943 nvme_auth_stop(ctrl); 4944 nvme_stop_failfast_work(ctrl); 4945 flush_work(&ctrl->async_event_work); 4946 cancel_work_sync(&ctrl->fw_act_work); 4947 if (ctrl->ops->stop_ctrl) 4948 ctrl->ops->stop_ctrl(ctrl); 4949 } 4950 EXPORT_SYMBOL_GPL(nvme_stop_ctrl); 4951 4952 void nvme_start_ctrl(struct nvme_ctrl *ctrl) 4953 { 4954 nvme_enable_aen(ctrl); 4955 4956 /* 4957 * persistent discovery controllers need to send indication to userspace 4958 * to re-read the discovery log page to learn about possible changes 4959 * that were missed. We identify persistent discovery controllers by 4960 * checking that they started once before, hence are reconnecting back. 4961 */ 4962 if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) && 4963 nvme_discovery_ctrl(ctrl)) 4964 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover"); 4965 4966 if (ctrl->queue_count > 1) { 4967 nvme_queue_scan(ctrl); 4968 nvme_unquiesce_io_queues(ctrl); 4969 nvme_mpath_update(ctrl); 4970 } 4971 4972 nvme_change_uevent(ctrl, "NVME_EVENT=connected"); 4973 set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags); 4974 } 4975 EXPORT_SYMBOL_GPL(nvme_start_ctrl); 4976 4977 void nvme_uninit_ctrl(struct nvme_ctrl *ctrl) 4978 { 4979 nvme_stop_keep_alive(ctrl); 4980 nvme_hwmon_exit(ctrl); 4981 nvme_fault_inject_fini(&ctrl->fault_inject); 4982 dev_pm_qos_hide_latency_tolerance(ctrl->device); 4983 cdev_device_del(&ctrl->cdev, ctrl->device); 4984 nvme_put_ctrl(ctrl); 4985 } 4986 EXPORT_SYMBOL_GPL(nvme_uninit_ctrl); 4987 4988 static void nvme_free_cels(struct nvme_ctrl *ctrl) 4989 { 4990 struct nvme_effects_log *cel; 4991 unsigned long i; 4992 4993 xa_for_each(&ctrl->cels, i, cel) { 4994 xa_erase(&ctrl->cels, i); 4995 kfree(cel); 4996 } 4997 4998 xa_destroy(&ctrl->cels); 4999 } 5000 5001 static void nvme_free_ctrl(struct device *dev) 5002 { 5003 struct nvme_ctrl *ctrl = 5004 container_of(dev, struct nvme_ctrl, ctrl_device); 5005 struct nvme_subsystem *subsys = ctrl->subsys; 5006 5007 if (!subsys || ctrl->instance != subsys->instance) 5008 ida_free(&nvme_instance_ida, ctrl->instance); 5009 nvme_free_cels(ctrl); 5010 nvme_mpath_uninit(ctrl); 5011 cleanup_srcu_struct(&ctrl->srcu); 5012 nvme_auth_stop(ctrl); 5013 nvme_auth_free(ctrl); 5014 __free_page(ctrl->discard_page); 5015 free_opal_dev(ctrl->opal_dev); 5016 5017 if (subsys) { 5018 mutex_lock(&nvme_subsystems_lock); 5019 list_del(&ctrl->subsys_entry); 5020 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device)); 5021 mutex_unlock(&nvme_subsystems_lock); 5022 } 5023 5024 ctrl->ops->free_ctrl(ctrl); 5025 5026 if (subsys) 5027 nvme_put_subsystem(subsys); 5028 } 5029 5030 /* 5031 * Initialize a NVMe controller structures. This needs to be called during 5032 * earliest initialization so that we have the initialized structured around 5033 * during probing. 5034 * 5035 * On success, the caller must use the nvme_put_ctrl() to release this when 5036 * needed, which also invokes the ops->free_ctrl() callback. 5037 */ 5038 int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, 5039 const struct nvme_ctrl_ops *ops, unsigned long quirks) 5040 { 5041 int ret; 5042 5043 WRITE_ONCE(ctrl->state, NVME_CTRL_NEW); 5044 ctrl->passthru_err_log_enabled = false; 5045 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); 5046 spin_lock_init(&ctrl->lock); 5047 mutex_init(&ctrl->namespaces_lock); 5048 5049 ret = init_srcu_struct(&ctrl->srcu); 5050 if (ret) 5051 return ret; 5052 5053 mutex_init(&ctrl->scan_lock); 5054 INIT_LIST_HEAD(&ctrl->namespaces); 5055 xa_init(&ctrl->cels); 5056 ctrl->dev = dev; 5057 ctrl->ops = ops; 5058 ctrl->quirks = quirks; 5059 ctrl->numa_node = NUMA_NO_NODE; 5060 INIT_WORK(&ctrl->scan_work, nvme_scan_work); 5061 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work); 5062 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work); 5063 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work); 5064 init_waitqueue_head(&ctrl->state_wq); 5065 5066 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work); 5067 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work); 5068 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd)); 5069 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive; 5070 ctrl->ka_last_check_time = jiffies; 5071 5072 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) > 5073 PAGE_SIZE); 5074 ctrl->discard_page = alloc_page(GFP_KERNEL); 5075 if (!ctrl->discard_page) { 5076 ret = -ENOMEM; 5077 goto out; 5078 } 5079 5080 ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL); 5081 if (ret < 0) 5082 goto out; 5083 ctrl->instance = ret; 5084 5085 ret = nvme_auth_init_ctrl(ctrl); 5086 if (ret) 5087 goto out_release_instance; 5088 5089 nvme_mpath_init_ctrl(ctrl); 5090 5091 device_initialize(&ctrl->ctrl_device); 5092 ctrl->device = &ctrl->ctrl_device; 5093 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt), 5094 ctrl->instance); 5095 ctrl->device->class = &nvme_class; 5096 ctrl->device->parent = ctrl->dev; 5097 if (ops->dev_attr_groups) 5098 ctrl->device->groups = ops->dev_attr_groups; 5099 else 5100 ctrl->device->groups = nvme_dev_attr_groups; 5101 ctrl->device->release = nvme_free_ctrl; 5102 dev_set_drvdata(ctrl->device, ctrl); 5103 5104 return ret; 5105 5106 out_release_instance: 5107 ida_free(&nvme_instance_ida, ctrl->instance); 5108 out: 5109 if (ctrl->discard_page) 5110 __free_page(ctrl->discard_page); 5111 cleanup_srcu_struct(&ctrl->srcu); 5112 return ret; 5113 } 5114 EXPORT_SYMBOL_GPL(nvme_init_ctrl); 5115 5116 /* 5117 * On success, returns with an elevated controller reference and caller must 5118 * use nvme_uninit_ctrl() to properly free resources associated with the ctrl. 5119 */ 5120 int nvme_add_ctrl(struct nvme_ctrl *ctrl) 5121 { 5122 int ret; 5123 5124 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance); 5125 if (ret) 5126 return ret; 5127 5128 cdev_init(&ctrl->cdev, &nvme_dev_fops); 5129 ctrl->cdev.owner = ctrl->ops->module; 5130 ret = cdev_device_add(&ctrl->cdev, ctrl->device); 5131 if (ret) 5132 return ret; 5133 5134 /* 5135 * Initialize latency tolerance controls. The sysfs files won't 5136 * be visible to userspace unless the device actually supports APST. 5137 */ 5138 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance; 5139 dev_pm_qos_update_user_latency_tolerance(ctrl->device, 5140 min(default_ps_max_latency_us, (unsigned long)S32_MAX)); 5141 5142 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device)); 5143 nvme_get_ctrl(ctrl); 5144 5145 return 0; 5146 } 5147 EXPORT_SYMBOL_GPL(nvme_add_ctrl); 5148 5149 /* let I/O to all namespaces fail in preparation for surprise removal */ 5150 void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl) 5151 { 5152 struct nvme_ns *ns; 5153 int srcu_idx; 5154 5155 srcu_idx = srcu_read_lock(&ctrl->srcu); 5156 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 5157 srcu_read_lock_held(&ctrl->srcu)) 5158 blk_mark_disk_dead(ns->disk); 5159 srcu_read_unlock(&ctrl->srcu, srcu_idx); 5160 } 5161 EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead); 5162 5163 void nvme_unfreeze(struct nvme_ctrl *ctrl) 5164 { 5165 struct nvme_ns *ns; 5166 int srcu_idx; 5167 5168 srcu_idx = srcu_read_lock(&ctrl->srcu); 5169 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 5170 srcu_read_lock_held(&ctrl->srcu)) 5171 blk_mq_unfreeze_queue_non_owner(ns->queue); 5172 srcu_read_unlock(&ctrl->srcu, srcu_idx); 5173 clear_bit(NVME_CTRL_FROZEN, &ctrl->flags); 5174 } 5175 EXPORT_SYMBOL_GPL(nvme_unfreeze); 5176 5177 int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout) 5178 { 5179 struct nvme_ns *ns; 5180 int srcu_idx; 5181 5182 srcu_idx = srcu_read_lock(&ctrl->srcu); 5183 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 5184 srcu_read_lock_held(&ctrl->srcu)) { 5185 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout); 5186 if (timeout <= 0) 5187 break; 5188 } 5189 srcu_read_unlock(&ctrl->srcu, srcu_idx); 5190 return timeout; 5191 } 5192 EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout); 5193 5194 void nvme_wait_freeze(struct nvme_ctrl *ctrl) 5195 { 5196 struct nvme_ns *ns; 5197 int srcu_idx; 5198 5199 srcu_idx = srcu_read_lock(&ctrl->srcu); 5200 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 5201 srcu_read_lock_held(&ctrl->srcu)) 5202 blk_mq_freeze_queue_wait(ns->queue); 5203 srcu_read_unlock(&ctrl->srcu, srcu_idx); 5204 } 5205 EXPORT_SYMBOL_GPL(nvme_wait_freeze); 5206 5207 void nvme_start_freeze(struct nvme_ctrl *ctrl) 5208 { 5209 struct nvme_ns *ns; 5210 int srcu_idx; 5211 5212 set_bit(NVME_CTRL_FROZEN, &ctrl->flags); 5213 srcu_idx = srcu_read_lock(&ctrl->srcu); 5214 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 5215 srcu_read_lock_held(&ctrl->srcu)) 5216 /* 5217 * Typical non_owner use case is from pci driver, in which 5218 * start_freeze is called from timeout work function, but 5219 * unfreeze is done in reset work context 5220 */ 5221 blk_freeze_queue_start_non_owner(ns->queue); 5222 srcu_read_unlock(&ctrl->srcu, srcu_idx); 5223 } 5224 EXPORT_SYMBOL_GPL(nvme_start_freeze); 5225 5226 void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl) 5227 { 5228 if (!ctrl->tagset) 5229 return; 5230 if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags)) 5231 blk_mq_quiesce_tagset(ctrl->tagset); 5232 else 5233 blk_mq_wait_quiesce_done(ctrl->tagset); 5234 } 5235 EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues); 5236 5237 void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl) 5238 { 5239 if (!ctrl->tagset) 5240 return; 5241 if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags)) 5242 blk_mq_unquiesce_tagset(ctrl->tagset); 5243 } 5244 EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues); 5245 5246 void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl) 5247 { 5248 if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags)) 5249 blk_mq_quiesce_queue(ctrl->admin_q); 5250 else 5251 blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set); 5252 } 5253 EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue); 5254 5255 void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl) 5256 { 5257 if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags)) 5258 blk_mq_unquiesce_queue(ctrl->admin_q); 5259 } 5260 EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue); 5261 5262 void nvme_sync_io_queues(struct nvme_ctrl *ctrl) 5263 { 5264 struct nvme_ns *ns; 5265 int srcu_idx; 5266 5267 srcu_idx = srcu_read_lock(&ctrl->srcu); 5268 list_for_each_entry_srcu(ns, &ctrl->namespaces, list, 5269 srcu_read_lock_held(&ctrl->srcu)) 5270 blk_sync_queue(ns->queue); 5271 srcu_read_unlock(&ctrl->srcu, srcu_idx); 5272 } 5273 EXPORT_SYMBOL_GPL(nvme_sync_io_queues); 5274 5275 void nvme_sync_queues(struct nvme_ctrl *ctrl) 5276 { 5277 nvme_sync_io_queues(ctrl); 5278 if (ctrl->admin_q) 5279 blk_sync_queue(ctrl->admin_q); 5280 } 5281 EXPORT_SYMBOL_GPL(nvme_sync_queues); 5282 5283 struct nvme_ctrl *nvme_ctrl_from_file(struct file *file) 5284 { 5285 if (file->f_op != &nvme_dev_fops) 5286 return NULL; 5287 return file->private_data; 5288 } 5289 EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, "NVME_TARGET_PASSTHRU"); 5290 5291 /* 5292 * Check we didn't inadvertently grow the command structure sizes: 5293 */ 5294 static inline void _nvme_check_size(void) 5295 { 5296 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64); 5297 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 5298 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64); 5299 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 5300 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64); 5301 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 5302 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64); 5303 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64); 5304 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 5305 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64); 5306 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 5307 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 5308 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 5309 BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) != 5310 NVME_IDENTIFY_DATA_SIZE); 5311 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE); 5312 BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE); 5313 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE); 5314 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE); 5315 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 5316 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 5317 BUILD_BUG_ON(sizeof(struct nvme_endurance_group_log) != 512); 5318 BUILD_BUG_ON(sizeof(struct nvme_rotational_media_log) != 512); 5319 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 5320 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64); 5321 BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512); 5322 } 5323 5324 5325 static int __init nvme_core_init(void) 5326 { 5327 unsigned int wq_flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS; 5328 int result = -ENOMEM; 5329 5330 _nvme_check_size(); 5331 5332 nvme_wq = alloc_workqueue("nvme-wq", wq_flags, 0); 5333 if (!nvme_wq) 5334 goto out; 5335 5336 nvme_reset_wq = alloc_workqueue("nvme-reset-wq", wq_flags, 0); 5337 if (!nvme_reset_wq) 5338 goto destroy_wq; 5339 5340 nvme_delete_wq = alloc_workqueue("nvme-delete-wq", wq_flags, 0); 5341 if (!nvme_delete_wq) 5342 goto destroy_reset_wq; 5343 5344 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0, 5345 NVME_MINORS, "nvme"); 5346 if (result < 0) 5347 goto destroy_delete_wq; 5348 5349 result = class_register(&nvme_class); 5350 if (result) 5351 goto unregister_chrdev; 5352 5353 result = class_register(&nvme_subsys_class); 5354 if (result) 5355 goto destroy_class; 5356 5357 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS, 5358 "nvme-generic"); 5359 if (result < 0) 5360 goto destroy_subsys_class; 5361 5362 result = class_register(&nvme_ns_chr_class); 5363 if (result) 5364 goto unregister_generic_ns; 5365 5366 result = nvme_init_auth(); 5367 if (result) 5368 goto destroy_ns_chr; 5369 return 0; 5370 5371 destroy_ns_chr: 5372 class_unregister(&nvme_ns_chr_class); 5373 unregister_generic_ns: 5374 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS); 5375 destroy_subsys_class: 5376 class_unregister(&nvme_subsys_class); 5377 destroy_class: 5378 class_unregister(&nvme_class); 5379 unregister_chrdev: 5380 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS); 5381 destroy_delete_wq: 5382 destroy_workqueue(nvme_delete_wq); 5383 destroy_reset_wq: 5384 destroy_workqueue(nvme_reset_wq); 5385 destroy_wq: 5386 destroy_workqueue(nvme_wq); 5387 out: 5388 return result; 5389 } 5390 5391 static void __exit nvme_core_exit(void) 5392 { 5393 nvme_exit_auth(); 5394 class_unregister(&nvme_ns_chr_class); 5395 class_unregister(&nvme_subsys_class); 5396 class_unregister(&nvme_class); 5397 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS); 5398 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS); 5399 destroy_workqueue(nvme_delete_wq); 5400 destroy_workqueue(nvme_reset_wq); 5401 destroy_workqueue(nvme_wq); 5402 ida_destroy(&nvme_ns_chr_minor_ida); 5403 ida_destroy(&nvme_instance_ida); 5404 } 5405 5406 MODULE_LICENSE("GPL"); 5407 MODULE_VERSION("1.0"); 5408 MODULE_DESCRIPTION("NVMe host core framework"); 5409 module_init(nvme_core_init); 5410 module_exit(nvme_core_exit); 5411