1 /* 2 * Microsemi Switchtec(tm) PCIe Management Driver 3 * Copyright (c) 2017, Microsemi Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #include <linux/switchtec.h> 17 #include <linux/module.h> 18 #include <linux/delay.h> 19 #include <linux/kthread.h> 20 #include <linux/interrupt.h> 21 #include <linux/ntb.h> 22 23 MODULE_DESCRIPTION("Microsemi Switchtec(tm) NTB Driver"); 24 MODULE_VERSION("0.1"); 25 MODULE_LICENSE("GPL"); 26 MODULE_AUTHOR("Microsemi Corporation"); 27 28 static bool use_lut_mws; 29 module_param(use_lut_mws, bool, 0644); 30 MODULE_PARM_DESC(use_lut_mws, 31 "Enable the use of the LUT based memory windows"); 32 33 #ifndef ioread64 34 #ifdef readq 35 #define ioread64 readq 36 #else 37 #define ioread64 _ioread64 38 static inline u64 _ioread64(void __iomem *mmio) 39 { 40 u64 low, high; 41 42 low = ioread32(mmio); 43 high = ioread32(mmio + sizeof(u32)); 44 return low | (high << 32); 45 } 46 #endif 47 #endif 48 49 #ifndef iowrite64 50 #ifdef writeq 51 #define iowrite64 writeq 52 #else 53 #define iowrite64 _iowrite64 54 static inline void _iowrite64(u64 val, void __iomem *mmio) 55 { 56 iowrite32(val, mmio); 57 iowrite32(val >> 32, mmio + sizeof(u32)); 58 } 59 #endif 60 #endif 61 62 #define SWITCHTEC_NTB_MAGIC 0x45CC0001 63 #define MAX_MWS 128 64 65 struct shared_mw { 66 u32 magic; 67 u32 partition_id; 68 u64 mw_sizes[MAX_MWS]; 69 }; 70 71 #define MAX_DIRECT_MW ARRAY_SIZE(((struct ntb_ctrl_regs *)(0))->bar_entry) 72 #define LUT_SIZE SZ_64K 73 74 struct switchtec_ntb { 75 struct ntb_dev ntb; 76 struct switchtec_dev *stdev; 77 78 int self_partition; 79 int peer_partition; 80 81 int doorbell_irq; 82 int message_irq; 83 84 struct ntb_info_regs __iomem *mmio_ntb; 85 struct ntb_ctrl_regs __iomem *mmio_ctrl; 86 struct ntb_dbmsg_regs __iomem *mmio_dbmsg; 87 struct ntb_ctrl_regs __iomem *mmio_self_ctrl; 88 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 89 struct ntb_dbmsg_regs __iomem *mmio_self_dbmsg; 90 91 struct shared_mw *self_shared; 92 struct shared_mw __iomem *peer_shared; 93 dma_addr_t self_shared_dma; 94 95 u64 db_mask; 96 u64 db_valid_mask; 97 int db_shift; 98 int db_peer_shift; 99 100 int nr_direct_mw; 101 int nr_lut_mw; 102 int direct_mw_to_bar[MAX_DIRECT_MW]; 103 104 int peer_nr_direct_mw; 105 int peer_nr_lut_mw; 106 int peer_direct_mw_to_bar[MAX_DIRECT_MW]; 107 }; 108 109 static int switchtec_ntb_part_op(struct switchtec_ntb *sndev, 110 struct ntb_ctrl_regs __iomem *ctl, 111 u32 op, int wait_status) 112 { 113 static const char * const op_text[] = { 114 [NTB_CTRL_PART_OP_LOCK] = "lock", 115 [NTB_CTRL_PART_OP_CFG] = "configure", 116 [NTB_CTRL_PART_OP_RESET] = "reset", 117 }; 118 119 int i; 120 u32 ps; 121 int status; 122 123 switch (op) { 124 case NTB_CTRL_PART_OP_LOCK: 125 status = NTB_CTRL_PART_STATUS_LOCKING; 126 break; 127 case NTB_CTRL_PART_OP_CFG: 128 status = NTB_CTRL_PART_STATUS_CONFIGURING; 129 break; 130 case NTB_CTRL_PART_OP_RESET: 131 status = NTB_CTRL_PART_STATUS_RESETTING; 132 break; 133 default: 134 return -EINVAL; 135 } 136 137 iowrite32(op, &ctl->partition_op); 138 139 for (i = 0; i < 1000; i++) { 140 if (msleep_interruptible(50) != 0) { 141 iowrite32(NTB_CTRL_PART_OP_RESET, &ctl->partition_op); 142 return -EINTR; 143 } 144 145 ps = ioread32(&ctl->partition_status) & 0xFFFF; 146 147 if (ps != status) 148 break; 149 } 150 151 if (ps == wait_status) 152 return 0; 153 154 if (ps == status) { 155 dev_err(&sndev->stdev->dev, 156 "Timed out while peforming %s (%d). (%08x)", 157 op_text[op], op, 158 ioread32(&ctl->partition_status)); 159 160 return -ETIMEDOUT; 161 } 162 163 return -EIO; 164 } 165 166 static int switchtec_ntb_mw_count(struct ntb_dev *ntb, int pidx) 167 { 168 return 0; 169 } 170 171 static int switchtec_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, 172 int widx, resource_size_t *addr_align, 173 resource_size_t *size_align, 174 resource_size_t *size_max) 175 { 176 return 0; 177 } 178 179 static int switchtec_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx, 180 dma_addr_t addr, resource_size_t size) 181 { 182 return 0; 183 } 184 185 static int switchtec_ntb_peer_mw_count(struct ntb_dev *ntb) 186 { 187 return 0; 188 } 189 190 static int switchtec_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx, 191 phys_addr_t *base, 192 resource_size_t *size) 193 { 194 return 0; 195 } 196 197 static u64 switchtec_ntb_link_is_up(struct ntb_dev *ntb, 198 enum ntb_speed *speed, 199 enum ntb_width *width) 200 { 201 return 0; 202 } 203 204 static int switchtec_ntb_link_enable(struct ntb_dev *ntb, 205 enum ntb_speed max_speed, 206 enum ntb_width max_width) 207 { 208 return 0; 209 } 210 211 static int switchtec_ntb_link_disable(struct ntb_dev *ntb) 212 { 213 return 0; 214 } 215 216 static u64 switchtec_ntb_db_valid_mask(struct ntb_dev *ntb) 217 { 218 return 0; 219 } 220 221 static int switchtec_ntb_db_vector_count(struct ntb_dev *ntb) 222 { 223 return 0; 224 } 225 226 static u64 switchtec_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector) 227 { 228 return 0; 229 } 230 231 static u64 switchtec_ntb_db_read(struct ntb_dev *ntb) 232 { 233 return 0; 234 } 235 236 static int switchtec_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) 237 { 238 return 0; 239 } 240 241 static int switchtec_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) 242 { 243 return 0; 244 } 245 246 static int switchtec_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) 247 { 248 return 0; 249 } 250 251 static int switchtec_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 252 { 253 return 0; 254 } 255 256 static int switchtec_ntb_spad_count(struct ntb_dev *ntb) 257 { 258 return 0; 259 } 260 261 static u32 switchtec_ntb_spad_read(struct ntb_dev *ntb, int idx) 262 { 263 return 0; 264 } 265 266 static int switchtec_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val) 267 { 268 return 0; 269 } 270 271 static int switchtec_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, 272 int sidx, u32 val) 273 { 274 return 0; 275 } 276 277 static const struct ntb_dev_ops switchtec_ntb_ops = { 278 .mw_count = switchtec_ntb_mw_count, 279 .mw_get_align = switchtec_ntb_mw_get_align, 280 .mw_set_trans = switchtec_ntb_mw_set_trans, 281 .peer_mw_count = switchtec_ntb_peer_mw_count, 282 .peer_mw_get_addr = switchtec_ntb_peer_mw_get_addr, 283 .link_is_up = switchtec_ntb_link_is_up, 284 .link_enable = switchtec_ntb_link_enable, 285 .link_disable = switchtec_ntb_link_disable, 286 .db_valid_mask = switchtec_ntb_db_valid_mask, 287 .db_vector_count = switchtec_ntb_db_vector_count, 288 .db_vector_mask = switchtec_ntb_db_vector_mask, 289 .db_read = switchtec_ntb_db_read, 290 .db_clear = switchtec_ntb_db_clear, 291 .db_set_mask = switchtec_ntb_db_set_mask, 292 .db_clear_mask = switchtec_ntb_db_clear_mask, 293 .peer_db_set = switchtec_ntb_peer_db_set, 294 .spad_count = switchtec_ntb_spad_count, 295 .spad_read = switchtec_ntb_spad_read, 296 .spad_write = switchtec_ntb_spad_write, 297 .peer_spad_write = switchtec_ntb_peer_spad_write, 298 }; 299 300 static void switchtec_ntb_init_sndev(struct switchtec_ntb *sndev) 301 { 302 u64 part_map; 303 304 sndev->ntb.pdev = sndev->stdev->pdev; 305 sndev->ntb.topo = NTB_TOPO_SWITCH; 306 sndev->ntb.ops = &switchtec_ntb_ops; 307 308 sndev->self_partition = sndev->stdev->partition; 309 310 sndev->mmio_ntb = sndev->stdev->mmio_ntb; 311 part_map = ioread64(&sndev->mmio_ntb->ep_map); 312 part_map &= ~(1 << sndev->self_partition); 313 sndev->peer_partition = ffs(part_map) - 1; 314 315 dev_dbg(&sndev->stdev->dev, "Partition ID %d of %d (%llx)", 316 sndev->self_partition, sndev->stdev->partition_count, 317 part_map); 318 319 sndev->mmio_ctrl = (void * __iomem)sndev->mmio_ntb + 320 SWITCHTEC_NTB_REG_CTRL_OFFSET; 321 sndev->mmio_dbmsg = (void * __iomem)sndev->mmio_ntb + 322 SWITCHTEC_NTB_REG_DBMSG_OFFSET; 323 324 sndev->mmio_self_ctrl = &sndev->mmio_ctrl[sndev->self_partition]; 325 sndev->mmio_peer_ctrl = &sndev->mmio_ctrl[sndev->peer_partition]; 326 sndev->mmio_self_dbmsg = &sndev->mmio_dbmsg[sndev->self_partition]; 327 } 328 329 static int map_bars(int *map, struct ntb_ctrl_regs __iomem *ctrl) 330 { 331 int i; 332 int cnt = 0; 333 334 for (i = 0; i < ARRAY_SIZE(ctrl->bar_entry); i++) { 335 u32 r = ioread32(&ctrl->bar_entry[i].ctl); 336 337 if (r & NTB_CTRL_BAR_VALID) 338 map[cnt++] = i; 339 } 340 341 return cnt; 342 } 343 344 static void switchtec_ntb_init_mw(struct switchtec_ntb *sndev) 345 { 346 sndev->nr_direct_mw = map_bars(sndev->direct_mw_to_bar, 347 sndev->mmio_self_ctrl); 348 349 sndev->nr_lut_mw = ioread16(&sndev->mmio_self_ctrl->lut_table_entries); 350 sndev->nr_lut_mw = rounddown_pow_of_two(sndev->nr_lut_mw); 351 352 dev_dbg(&sndev->stdev->dev, "MWs: %d direct, %d lut", 353 sndev->nr_direct_mw, sndev->nr_lut_mw); 354 355 sndev->peer_nr_direct_mw = map_bars(sndev->peer_direct_mw_to_bar, 356 sndev->mmio_peer_ctrl); 357 358 sndev->peer_nr_lut_mw = 359 ioread16(&sndev->mmio_peer_ctrl->lut_table_entries); 360 sndev->peer_nr_lut_mw = rounddown_pow_of_two(sndev->peer_nr_lut_mw); 361 362 dev_dbg(&sndev->stdev->dev, "Peer MWs: %d direct, %d lut", 363 sndev->peer_nr_direct_mw, sndev->peer_nr_lut_mw); 364 365 } 366 367 /* 368 * There are 64 doorbells in the switch hardware but this is 369 * shared among all partitions. So we must split them in half 370 * (32 for each partition). However, the message interrupts are 371 * also shared with the top 4 doorbells so we just limit this to 372 * 28 doorbells per partition 373 */ 374 static void switchtec_ntb_init_db(struct switchtec_ntb *sndev) 375 { 376 sndev->db_valid_mask = 0x0FFFFFFF; 377 378 if (sndev->self_partition < sndev->peer_partition) { 379 sndev->db_shift = 0; 380 sndev->db_peer_shift = 32; 381 } else { 382 sndev->db_shift = 32; 383 sndev->db_peer_shift = 0; 384 } 385 386 sndev->db_mask = 0x0FFFFFFFFFFFFFFFULL; 387 iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); 388 iowrite64(sndev->db_valid_mask << sndev->db_peer_shift, 389 &sndev->mmio_self_dbmsg->odb_mask); 390 } 391 392 static void switchtec_ntb_init_msgs(struct switchtec_ntb *sndev) 393 { 394 int i; 395 u32 msg_map = 0; 396 397 for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) { 398 int m = i | sndev->peer_partition << 2; 399 400 msg_map |= m << i * 8; 401 } 402 403 iowrite32(msg_map, &sndev->mmio_self_dbmsg->msg_map); 404 405 for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) 406 iowrite64(NTB_DBMSG_IMSG_STATUS | NTB_DBMSG_IMSG_MASK, 407 &sndev->mmio_self_dbmsg->imsg[i]); 408 } 409 410 static int switchtec_ntb_init_req_id_table(struct switchtec_ntb *sndev) 411 { 412 int rc = 0; 413 u16 req_id; 414 u32 error; 415 416 req_id = ioread16(&sndev->mmio_ntb->requester_id); 417 418 if (ioread32(&sndev->mmio_self_ctrl->req_id_table_size) < 2) { 419 dev_err(&sndev->stdev->dev, 420 "Not enough requester IDs available."); 421 return -EFAULT; 422 } 423 424 rc = switchtec_ntb_part_op(sndev, sndev->mmio_self_ctrl, 425 NTB_CTRL_PART_OP_LOCK, 426 NTB_CTRL_PART_STATUS_LOCKED); 427 if (rc) 428 return rc; 429 430 iowrite32(NTB_PART_CTRL_ID_PROT_DIS, 431 &sndev->mmio_self_ctrl->partition_ctrl); 432 433 /* 434 * Root Complex Requester ID (which is 0:00.0) 435 */ 436 iowrite32(0 << 16 | NTB_CTRL_REQ_ID_EN, 437 &sndev->mmio_self_ctrl->req_id_table[0]); 438 439 /* 440 * Host Bridge Requester ID (as read from the mmap address) 441 */ 442 iowrite32(req_id << 16 | NTB_CTRL_REQ_ID_EN, 443 &sndev->mmio_self_ctrl->req_id_table[1]); 444 445 rc = switchtec_ntb_part_op(sndev, sndev->mmio_self_ctrl, 446 NTB_CTRL_PART_OP_CFG, 447 NTB_CTRL_PART_STATUS_NORMAL); 448 if (rc == -EIO) { 449 error = ioread32(&sndev->mmio_self_ctrl->req_id_error); 450 dev_err(&sndev->stdev->dev, 451 "Error setting up the requester ID table: %08x", 452 error); 453 } 454 455 return rc; 456 } 457 458 static void switchtec_ntb_init_shared(struct switchtec_ntb *sndev) 459 { 460 int i; 461 462 memset(sndev->self_shared, 0, LUT_SIZE); 463 sndev->self_shared->magic = SWITCHTEC_NTB_MAGIC; 464 sndev->self_shared->partition_id = sndev->stdev->partition; 465 466 for (i = 0; i < sndev->nr_direct_mw; i++) { 467 int bar = sndev->direct_mw_to_bar[i]; 468 resource_size_t sz = pci_resource_len(sndev->stdev->pdev, bar); 469 470 if (i == 0) 471 sz = min_t(resource_size_t, sz, 472 LUT_SIZE * sndev->nr_lut_mw); 473 474 sndev->self_shared->mw_sizes[i] = sz; 475 } 476 477 for (i = 0; i < sndev->nr_lut_mw; i++) { 478 int idx = sndev->nr_direct_mw + i; 479 480 sndev->self_shared->mw_sizes[idx] = LUT_SIZE; 481 } 482 } 483 484 static int switchtec_ntb_init_shared_mw(struct switchtec_ntb *sndev) 485 { 486 struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl; 487 int bar = sndev->direct_mw_to_bar[0]; 488 u32 ctl_val; 489 int rc; 490 491 sndev->self_shared = dma_zalloc_coherent(&sndev->stdev->pdev->dev, 492 LUT_SIZE, 493 &sndev->self_shared_dma, 494 GFP_KERNEL); 495 if (!sndev->self_shared) { 496 dev_err(&sndev->stdev->dev, 497 "unable to allocate memory for shared mw"); 498 return -ENOMEM; 499 } 500 501 switchtec_ntb_init_shared(sndev); 502 503 rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_LOCK, 504 NTB_CTRL_PART_STATUS_LOCKED); 505 if (rc) 506 goto unalloc_and_exit; 507 508 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); 509 ctl_val &= 0xFF; 510 ctl_val |= NTB_CTRL_BAR_LUT_WIN_EN; 511 ctl_val |= ilog2(LUT_SIZE) << 8; 512 ctl_val |= (sndev->nr_lut_mw - 1) << 14; 513 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 514 515 iowrite64((NTB_CTRL_LUT_EN | (sndev->self_partition << 1) | 516 sndev->self_shared_dma), 517 &ctl->lut_entry[0]); 518 519 rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG, 520 NTB_CTRL_PART_STATUS_NORMAL); 521 if (rc) { 522 u32 bar_error, lut_error; 523 524 bar_error = ioread32(&ctl->bar_error); 525 lut_error = ioread32(&ctl->lut_error); 526 dev_err(&sndev->stdev->dev, 527 "Error setting up shared MW: %08x / %08x", 528 bar_error, lut_error); 529 goto unalloc_and_exit; 530 } 531 532 sndev->peer_shared = pci_iomap(sndev->stdev->pdev, bar, LUT_SIZE); 533 if (!sndev->peer_shared) { 534 rc = -ENOMEM; 535 goto unalloc_and_exit; 536 } 537 538 dev_dbg(&sndev->stdev->dev, "Shared MW Ready"); 539 return 0; 540 541 unalloc_and_exit: 542 dma_free_coherent(&sndev->stdev->pdev->dev, LUT_SIZE, 543 sndev->self_shared, sndev->self_shared_dma); 544 545 return rc; 546 } 547 548 static void switchtec_ntb_deinit_shared_mw(struct switchtec_ntb *sndev) 549 { 550 if (sndev->peer_shared) 551 pci_iounmap(sndev->stdev->pdev, sndev->peer_shared); 552 553 if (sndev->self_shared) 554 dma_free_coherent(&sndev->stdev->pdev->dev, LUT_SIZE, 555 sndev->self_shared, 556 sndev->self_shared_dma); 557 } 558 559 static irqreturn_t switchtec_ntb_doorbell_isr(int irq, void *dev) 560 { 561 struct switchtec_ntb *sndev = dev; 562 563 dev_dbg(&sndev->stdev->dev, "doorbell\n"); 564 565 return IRQ_HANDLED; 566 } 567 568 static irqreturn_t switchtec_ntb_message_isr(int irq, void *dev) 569 { 570 int i; 571 struct switchtec_ntb *sndev = dev; 572 573 for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) { 574 u64 msg = ioread64(&sndev->mmio_self_dbmsg->imsg[i]); 575 576 if (msg & NTB_DBMSG_IMSG_STATUS) { 577 dev_dbg(&sndev->stdev->dev, "message: %d %08x\n", i, 578 (u32)msg); 579 iowrite8(1, &sndev->mmio_self_dbmsg->imsg[i].status); 580 } 581 } 582 583 return IRQ_HANDLED; 584 } 585 586 static int switchtec_ntb_init_db_msg_irq(struct switchtec_ntb *sndev) 587 { 588 int i; 589 int rc; 590 int doorbell_irq = 0; 591 int message_irq = 0; 592 int event_irq; 593 int idb_vecs = sizeof(sndev->mmio_self_dbmsg->idb_vec_map); 594 595 event_irq = ioread32(&sndev->stdev->mmio_part_cfg->vep_vector_number); 596 597 while (doorbell_irq == event_irq) 598 doorbell_irq++; 599 while (message_irq == doorbell_irq || 600 message_irq == event_irq) 601 message_irq++; 602 603 dev_dbg(&sndev->stdev->dev, "irqs - event: %d, db: %d, msgs: %d", 604 event_irq, doorbell_irq, message_irq); 605 606 for (i = 0; i < idb_vecs - 4; i++) 607 iowrite8(doorbell_irq, 608 &sndev->mmio_self_dbmsg->idb_vec_map[i]); 609 610 for (; i < idb_vecs; i++) 611 iowrite8(message_irq, 612 &sndev->mmio_self_dbmsg->idb_vec_map[i]); 613 614 sndev->doorbell_irq = pci_irq_vector(sndev->stdev->pdev, doorbell_irq); 615 sndev->message_irq = pci_irq_vector(sndev->stdev->pdev, message_irq); 616 617 rc = request_irq(sndev->doorbell_irq, 618 switchtec_ntb_doorbell_isr, 0, 619 "switchtec_ntb_doorbell", sndev); 620 if (rc) 621 return rc; 622 623 rc = request_irq(sndev->message_irq, 624 switchtec_ntb_message_isr, 0, 625 "switchtec_ntb_message", sndev); 626 if (rc) { 627 free_irq(sndev->doorbell_irq, sndev); 628 return rc; 629 } 630 631 return 0; 632 } 633 634 static void switchtec_ntb_deinit_db_msg_irq(struct switchtec_ntb *sndev) 635 { 636 free_irq(sndev->doorbell_irq, sndev); 637 free_irq(sndev->message_irq, sndev); 638 } 639 640 static int switchtec_ntb_add(struct device *dev, 641 struct class_interface *class_intf) 642 { 643 struct switchtec_dev *stdev = to_stdev(dev); 644 struct switchtec_ntb *sndev; 645 int rc; 646 647 stdev->sndev = NULL; 648 649 if (stdev->pdev->class != MICROSEMI_NTB_CLASSCODE) 650 return -ENODEV; 651 652 if (stdev->partition_count != 2) 653 dev_warn(dev, "ntb driver only supports 2 partitions"); 654 655 sndev = kzalloc_node(sizeof(*sndev), GFP_KERNEL, dev_to_node(dev)); 656 if (!sndev) 657 return -ENOMEM; 658 659 sndev->stdev = stdev; 660 switchtec_ntb_init_sndev(sndev); 661 switchtec_ntb_init_mw(sndev); 662 switchtec_ntb_init_db(sndev); 663 switchtec_ntb_init_msgs(sndev); 664 665 rc = switchtec_ntb_init_req_id_table(sndev); 666 if (rc) 667 goto free_and_exit; 668 669 rc = switchtec_ntb_init_shared_mw(sndev); 670 if (rc) 671 goto free_and_exit; 672 673 rc = switchtec_ntb_init_db_msg_irq(sndev); 674 if (rc) 675 goto deinit_shared_and_exit; 676 677 rc = ntb_register_device(&sndev->ntb); 678 if (rc) 679 goto deinit_and_exit; 680 681 stdev->sndev = sndev; 682 dev_info(dev, "NTB device registered"); 683 684 return 0; 685 686 deinit_and_exit: 687 switchtec_ntb_deinit_db_msg_irq(sndev); 688 deinit_shared_and_exit: 689 switchtec_ntb_deinit_shared_mw(sndev); 690 free_and_exit: 691 kfree(sndev); 692 dev_err(dev, "failed to register ntb device: %d", rc); 693 return rc; 694 } 695 696 void switchtec_ntb_remove(struct device *dev, 697 struct class_interface *class_intf) 698 { 699 struct switchtec_dev *stdev = to_stdev(dev); 700 struct switchtec_ntb *sndev = stdev->sndev; 701 702 if (!sndev) 703 return; 704 705 stdev->sndev = NULL; 706 ntb_unregister_device(&sndev->ntb); 707 switchtec_ntb_deinit_db_msg_irq(sndev); 708 switchtec_ntb_deinit_shared_mw(sndev); 709 kfree(sndev); 710 dev_info(dev, "ntb device unregistered"); 711 } 712 713 static struct class_interface switchtec_interface = { 714 .add_dev = switchtec_ntb_add, 715 .remove_dev = switchtec_ntb_remove, 716 }; 717 718 static int __init switchtec_ntb_init(void) 719 { 720 switchtec_interface.class = switchtec_class; 721 return class_interface_register(&switchtec_interface); 722 } 723 module_init(switchtec_ntb_init); 724 725 static void __exit switchtec_ntb_exit(void) 726 { 727 class_interface_unregister(&switchtec_interface); 728 } 729 module_exit(switchtec_ntb_exit); 730