1 /* 2 * Microsemi Switchtec(tm) PCIe Management Driver 3 * Copyright (c) 2017, Microsemi Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #include <linux/switchtec.h> 17 #include <linux/module.h> 18 #include <linux/delay.h> 19 #include <linux/kthread.h> 20 #include <linux/interrupt.h> 21 #include <linux/ntb.h> 22 23 MODULE_DESCRIPTION("Microsemi Switchtec(tm) NTB Driver"); 24 MODULE_VERSION("0.1"); 25 MODULE_LICENSE("GPL"); 26 MODULE_AUTHOR("Microsemi Corporation"); 27 28 static bool use_lut_mws; 29 module_param(use_lut_mws, bool, 0644); 30 MODULE_PARM_DESC(use_lut_mws, 31 "Enable the use of the LUT based memory windows"); 32 33 #ifndef ioread64 34 #ifdef readq 35 #define ioread64 readq 36 #else 37 #define ioread64 _ioread64 38 static inline u64 _ioread64(void __iomem *mmio) 39 { 40 u64 low, high; 41 42 low = ioread32(mmio); 43 high = ioread32(mmio + sizeof(u32)); 44 return low | (high << 32); 45 } 46 #endif 47 #endif 48 49 #ifndef iowrite64 50 #ifdef writeq 51 #define iowrite64 writeq 52 #else 53 #define iowrite64 _iowrite64 54 static inline void _iowrite64(u64 val, void __iomem *mmio) 55 { 56 iowrite32(val, mmio); 57 iowrite32(val >> 32, mmio + sizeof(u32)); 58 } 59 #endif 60 #endif 61 62 #define SWITCHTEC_NTB_MAGIC 0x45CC0001 63 #define MAX_MWS 128 64 65 struct shared_mw { 66 u32 magic; 67 u32 link_sta; 68 u32 partition_id; 69 u64 mw_sizes[MAX_MWS]; 70 }; 71 72 #define MAX_DIRECT_MW ARRAY_SIZE(((struct ntb_ctrl_regs *)(0))->bar_entry) 73 #define LUT_SIZE SZ_64K 74 75 struct switchtec_ntb { 76 struct ntb_dev ntb; 77 struct switchtec_dev *stdev; 78 79 int self_partition; 80 int peer_partition; 81 82 int doorbell_irq; 83 int message_irq; 84 85 struct ntb_info_regs __iomem *mmio_ntb; 86 struct ntb_ctrl_regs __iomem *mmio_ctrl; 87 struct ntb_dbmsg_regs __iomem *mmio_dbmsg; 88 struct ntb_ctrl_regs __iomem *mmio_self_ctrl; 89 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 90 struct ntb_dbmsg_regs __iomem *mmio_self_dbmsg; 91 92 struct shared_mw *self_shared; 93 struct shared_mw __iomem *peer_shared; 94 dma_addr_t self_shared_dma; 95 96 u64 db_mask; 97 u64 db_valid_mask; 98 int db_shift; 99 int db_peer_shift; 100 101 /* synchronize rmw access of db_mask and hw reg */ 102 spinlock_t db_mask_lock; 103 104 int nr_direct_mw; 105 int nr_lut_mw; 106 int direct_mw_to_bar[MAX_DIRECT_MW]; 107 108 int peer_nr_direct_mw; 109 int peer_nr_lut_mw; 110 int peer_direct_mw_to_bar[MAX_DIRECT_MW]; 111 112 bool link_is_up; 113 enum ntb_speed link_speed; 114 enum ntb_width link_width; 115 }; 116 117 static struct switchtec_ntb *ntb_sndev(struct ntb_dev *ntb) 118 { 119 return container_of(ntb, struct switchtec_ntb, ntb); 120 } 121 122 static int switchtec_ntb_part_op(struct switchtec_ntb *sndev, 123 struct ntb_ctrl_regs __iomem *ctl, 124 u32 op, int wait_status) 125 { 126 static const char * const op_text[] = { 127 [NTB_CTRL_PART_OP_LOCK] = "lock", 128 [NTB_CTRL_PART_OP_CFG] = "configure", 129 [NTB_CTRL_PART_OP_RESET] = "reset", 130 }; 131 132 int i; 133 u32 ps; 134 int status; 135 136 switch (op) { 137 case NTB_CTRL_PART_OP_LOCK: 138 status = NTB_CTRL_PART_STATUS_LOCKING; 139 break; 140 case NTB_CTRL_PART_OP_CFG: 141 status = NTB_CTRL_PART_STATUS_CONFIGURING; 142 break; 143 case NTB_CTRL_PART_OP_RESET: 144 status = NTB_CTRL_PART_STATUS_RESETTING; 145 break; 146 default: 147 return -EINVAL; 148 } 149 150 iowrite32(op, &ctl->partition_op); 151 152 for (i = 0; i < 1000; i++) { 153 if (msleep_interruptible(50) != 0) { 154 iowrite32(NTB_CTRL_PART_OP_RESET, &ctl->partition_op); 155 return -EINTR; 156 } 157 158 ps = ioread32(&ctl->partition_status) & 0xFFFF; 159 160 if (ps != status) 161 break; 162 } 163 164 if (ps == wait_status) 165 return 0; 166 167 if (ps == status) { 168 dev_err(&sndev->stdev->dev, 169 "Timed out while peforming %s (%d). (%08x)", 170 op_text[op], op, 171 ioread32(&ctl->partition_status)); 172 173 return -ETIMEDOUT; 174 } 175 176 return -EIO; 177 } 178 179 static int switchtec_ntb_send_msg(struct switchtec_ntb *sndev, int idx, 180 u32 val) 181 { 182 if (idx < 0 || idx >= ARRAY_SIZE(sndev->mmio_self_dbmsg->omsg)) 183 return -EINVAL; 184 185 iowrite32(val, &sndev->mmio_self_dbmsg->omsg[idx].msg); 186 187 return 0; 188 } 189 190 static int switchtec_ntb_mw_count(struct ntb_dev *ntb, int pidx) 191 { 192 return 0; 193 } 194 195 static int switchtec_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, 196 int widx, resource_size_t *addr_align, 197 resource_size_t *size_align, 198 resource_size_t *size_max) 199 { 200 return 0; 201 } 202 203 static int switchtec_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx, 204 dma_addr_t addr, resource_size_t size) 205 { 206 return 0; 207 } 208 209 static int switchtec_ntb_peer_mw_count(struct ntb_dev *ntb) 210 { 211 return 0; 212 } 213 214 static int switchtec_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx, 215 phys_addr_t *base, 216 resource_size_t *size) 217 { 218 return 0; 219 } 220 221 static void switchtec_ntb_part_link_speed(struct switchtec_ntb *sndev, 222 int partition, 223 enum ntb_speed *speed, 224 enum ntb_width *width) 225 { 226 struct switchtec_dev *stdev = sndev->stdev; 227 228 u32 pff = ioread32(&stdev->mmio_part_cfg[partition].vep_pff_inst_id); 229 u32 linksta = ioread32(&stdev->mmio_pff_csr[pff].pci_cap_region[13]); 230 231 if (speed) 232 *speed = (linksta >> 16) & 0xF; 233 234 if (width) 235 *width = (linksta >> 20) & 0x3F; 236 } 237 238 static void switchtec_ntb_set_link_speed(struct switchtec_ntb *sndev) 239 { 240 enum ntb_speed self_speed, peer_speed; 241 enum ntb_width self_width, peer_width; 242 243 if (!sndev->link_is_up) { 244 sndev->link_speed = NTB_SPEED_NONE; 245 sndev->link_width = NTB_WIDTH_NONE; 246 return; 247 } 248 249 switchtec_ntb_part_link_speed(sndev, sndev->self_partition, 250 &self_speed, &self_width); 251 switchtec_ntb_part_link_speed(sndev, sndev->peer_partition, 252 &peer_speed, &peer_width); 253 254 sndev->link_speed = min(self_speed, peer_speed); 255 sndev->link_width = min(self_width, peer_width); 256 } 257 258 enum { 259 LINK_MESSAGE = 0, 260 MSG_LINK_UP = 1, 261 MSG_LINK_DOWN = 2, 262 MSG_CHECK_LINK = 3, 263 }; 264 265 static void switchtec_ntb_check_link(struct switchtec_ntb *sndev) 266 { 267 int link_sta; 268 int old = sndev->link_is_up; 269 270 link_sta = sndev->self_shared->link_sta; 271 if (link_sta) { 272 u64 peer = ioread64(&sndev->peer_shared->magic); 273 274 if ((peer & 0xFFFFFFFF) == SWITCHTEC_NTB_MAGIC) 275 link_sta = peer >> 32; 276 else 277 link_sta = 0; 278 } 279 280 sndev->link_is_up = link_sta; 281 switchtec_ntb_set_link_speed(sndev); 282 283 if (link_sta != old) { 284 switchtec_ntb_send_msg(sndev, LINK_MESSAGE, MSG_CHECK_LINK); 285 ntb_link_event(&sndev->ntb); 286 dev_info(&sndev->stdev->dev, "ntb link %s", 287 link_sta ? "up" : "down"); 288 } 289 } 290 291 static void switchtec_ntb_link_notification(struct switchtec_dev *stdev) 292 { 293 struct switchtec_ntb *sndev = stdev->sndev; 294 295 switchtec_ntb_check_link(sndev); 296 } 297 298 static u64 switchtec_ntb_link_is_up(struct ntb_dev *ntb, 299 enum ntb_speed *speed, 300 enum ntb_width *width) 301 { 302 struct switchtec_ntb *sndev = ntb_sndev(ntb); 303 304 if (speed) 305 *speed = sndev->link_speed; 306 if (width) 307 *width = sndev->link_width; 308 309 return sndev->link_is_up; 310 } 311 312 static int switchtec_ntb_link_enable(struct ntb_dev *ntb, 313 enum ntb_speed max_speed, 314 enum ntb_width max_width) 315 { 316 struct switchtec_ntb *sndev = ntb_sndev(ntb); 317 318 dev_dbg(&sndev->stdev->dev, "enabling link"); 319 320 sndev->self_shared->link_sta = 1; 321 switchtec_ntb_send_msg(sndev, LINK_MESSAGE, MSG_LINK_UP); 322 323 switchtec_ntb_check_link(sndev); 324 325 return 0; 326 } 327 328 static int switchtec_ntb_link_disable(struct ntb_dev *ntb) 329 { 330 struct switchtec_ntb *sndev = ntb_sndev(ntb); 331 332 dev_dbg(&sndev->stdev->dev, "disabling link"); 333 334 sndev->self_shared->link_sta = 0; 335 switchtec_ntb_send_msg(sndev, LINK_MESSAGE, MSG_LINK_UP); 336 337 switchtec_ntb_check_link(sndev); 338 339 return 0; 340 } 341 342 static u64 switchtec_ntb_db_valid_mask(struct ntb_dev *ntb) 343 { 344 struct switchtec_ntb *sndev = ntb_sndev(ntb); 345 346 return sndev->db_valid_mask; 347 } 348 349 static int switchtec_ntb_db_vector_count(struct ntb_dev *ntb) 350 { 351 return 1; 352 } 353 354 static u64 switchtec_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector) 355 { 356 struct switchtec_ntb *sndev = ntb_sndev(ntb); 357 358 if (db_vector < 0 || db_vector > 1) 359 return 0; 360 361 return sndev->db_valid_mask; 362 } 363 364 static u64 switchtec_ntb_db_read(struct ntb_dev *ntb) 365 { 366 u64 ret; 367 struct switchtec_ntb *sndev = ntb_sndev(ntb); 368 369 ret = ioread64(&sndev->mmio_self_dbmsg->idb) >> sndev->db_shift; 370 371 return ret & sndev->db_valid_mask; 372 } 373 374 static int switchtec_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) 375 { 376 struct switchtec_ntb *sndev = ntb_sndev(ntb); 377 378 iowrite64(db_bits << sndev->db_shift, &sndev->mmio_self_dbmsg->idb); 379 380 return 0; 381 } 382 383 static int switchtec_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) 384 { 385 unsigned long irqflags; 386 struct switchtec_ntb *sndev = ntb_sndev(ntb); 387 388 if (db_bits & ~sndev->db_valid_mask) 389 return -EINVAL; 390 391 spin_lock_irqsave(&sndev->db_mask_lock, irqflags); 392 393 sndev->db_mask |= db_bits << sndev->db_shift; 394 iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); 395 396 spin_unlock_irqrestore(&sndev->db_mask_lock, irqflags); 397 398 return 0; 399 } 400 401 static int switchtec_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) 402 { 403 unsigned long irqflags; 404 struct switchtec_ntb *sndev = ntb_sndev(ntb); 405 406 if (db_bits & ~sndev->db_valid_mask) 407 return -EINVAL; 408 409 spin_lock_irqsave(&sndev->db_mask_lock, irqflags); 410 411 sndev->db_mask &= ~(db_bits << sndev->db_shift); 412 iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); 413 414 spin_unlock_irqrestore(&sndev->db_mask_lock, irqflags); 415 416 return 0; 417 } 418 419 static u64 switchtec_ntb_db_read_mask(struct ntb_dev *ntb) 420 { 421 struct switchtec_ntb *sndev = ntb_sndev(ntb); 422 423 return (sndev->db_mask >> sndev->db_shift) & sndev->db_valid_mask; 424 } 425 426 static int switchtec_ntb_peer_db_addr(struct ntb_dev *ntb, 427 phys_addr_t *db_addr, 428 resource_size_t *db_size) 429 { 430 struct switchtec_ntb *sndev = ntb_sndev(ntb); 431 unsigned long offset; 432 433 offset = (unsigned long)sndev->mmio_self_dbmsg->odb - 434 (unsigned long)sndev->stdev->mmio; 435 436 offset += sndev->db_shift / 8; 437 438 if (db_addr) 439 *db_addr = pci_resource_start(ntb->pdev, 0) + offset; 440 if (db_size) 441 *db_size = sizeof(u32); 442 443 return 0; 444 } 445 446 static int switchtec_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 447 { 448 struct switchtec_ntb *sndev = ntb_sndev(ntb); 449 450 iowrite64(db_bits << sndev->db_peer_shift, 451 &sndev->mmio_self_dbmsg->odb); 452 453 return 0; 454 } 455 456 static int switchtec_ntb_spad_count(struct ntb_dev *ntb) 457 { 458 return 0; 459 } 460 461 static u32 switchtec_ntb_spad_read(struct ntb_dev *ntb, int idx) 462 { 463 return 0; 464 } 465 466 static int switchtec_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val) 467 { 468 return 0; 469 } 470 471 static int switchtec_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, 472 int sidx, u32 val) 473 { 474 return 0; 475 } 476 477 static const struct ntb_dev_ops switchtec_ntb_ops = { 478 .mw_count = switchtec_ntb_mw_count, 479 .mw_get_align = switchtec_ntb_mw_get_align, 480 .mw_set_trans = switchtec_ntb_mw_set_trans, 481 .peer_mw_count = switchtec_ntb_peer_mw_count, 482 .peer_mw_get_addr = switchtec_ntb_peer_mw_get_addr, 483 .link_is_up = switchtec_ntb_link_is_up, 484 .link_enable = switchtec_ntb_link_enable, 485 .link_disable = switchtec_ntb_link_disable, 486 .db_valid_mask = switchtec_ntb_db_valid_mask, 487 .db_vector_count = switchtec_ntb_db_vector_count, 488 .db_vector_mask = switchtec_ntb_db_vector_mask, 489 .db_read = switchtec_ntb_db_read, 490 .db_clear = switchtec_ntb_db_clear, 491 .db_set_mask = switchtec_ntb_db_set_mask, 492 .db_clear_mask = switchtec_ntb_db_clear_mask, 493 .db_read_mask = switchtec_ntb_db_read_mask, 494 .peer_db_addr = switchtec_ntb_peer_db_addr, 495 .peer_db_set = switchtec_ntb_peer_db_set, 496 .spad_count = switchtec_ntb_spad_count, 497 .spad_read = switchtec_ntb_spad_read, 498 .spad_write = switchtec_ntb_spad_write, 499 .peer_spad_write = switchtec_ntb_peer_spad_write, 500 }; 501 502 static void switchtec_ntb_init_sndev(struct switchtec_ntb *sndev) 503 { 504 u64 part_map; 505 506 sndev->ntb.pdev = sndev->stdev->pdev; 507 sndev->ntb.topo = NTB_TOPO_SWITCH; 508 sndev->ntb.ops = &switchtec_ntb_ops; 509 510 sndev->self_partition = sndev->stdev->partition; 511 512 sndev->mmio_ntb = sndev->stdev->mmio_ntb; 513 part_map = ioread64(&sndev->mmio_ntb->ep_map); 514 part_map &= ~(1 << sndev->self_partition); 515 sndev->peer_partition = ffs(part_map) - 1; 516 517 dev_dbg(&sndev->stdev->dev, "Partition ID %d of %d (%llx)", 518 sndev->self_partition, sndev->stdev->partition_count, 519 part_map); 520 521 sndev->mmio_ctrl = (void * __iomem)sndev->mmio_ntb + 522 SWITCHTEC_NTB_REG_CTRL_OFFSET; 523 sndev->mmio_dbmsg = (void * __iomem)sndev->mmio_ntb + 524 SWITCHTEC_NTB_REG_DBMSG_OFFSET; 525 526 sndev->mmio_self_ctrl = &sndev->mmio_ctrl[sndev->self_partition]; 527 sndev->mmio_peer_ctrl = &sndev->mmio_ctrl[sndev->peer_partition]; 528 sndev->mmio_self_dbmsg = &sndev->mmio_dbmsg[sndev->self_partition]; 529 } 530 531 static int map_bars(int *map, struct ntb_ctrl_regs __iomem *ctrl) 532 { 533 int i; 534 int cnt = 0; 535 536 for (i = 0; i < ARRAY_SIZE(ctrl->bar_entry); i++) { 537 u32 r = ioread32(&ctrl->bar_entry[i].ctl); 538 539 if (r & NTB_CTRL_BAR_VALID) 540 map[cnt++] = i; 541 } 542 543 return cnt; 544 } 545 546 static void switchtec_ntb_init_mw(struct switchtec_ntb *sndev) 547 { 548 sndev->nr_direct_mw = map_bars(sndev->direct_mw_to_bar, 549 sndev->mmio_self_ctrl); 550 551 sndev->nr_lut_mw = ioread16(&sndev->mmio_self_ctrl->lut_table_entries); 552 sndev->nr_lut_mw = rounddown_pow_of_two(sndev->nr_lut_mw); 553 554 dev_dbg(&sndev->stdev->dev, "MWs: %d direct, %d lut", 555 sndev->nr_direct_mw, sndev->nr_lut_mw); 556 557 sndev->peer_nr_direct_mw = map_bars(sndev->peer_direct_mw_to_bar, 558 sndev->mmio_peer_ctrl); 559 560 sndev->peer_nr_lut_mw = 561 ioread16(&sndev->mmio_peer_ctrl->lut_table_entries); 562 sndev->peer_nr_lut_mw = rounddown_pow_of_two(sndev->peer_nr_lut_mw); 563 564 dev_dbg(&sndev->stdev->dev, "Peer MWs: %d direct, %d lut", 565 sndev->peer_nr_direct_mw, sndev->peer_nr_lut_mw); 566 567 } 568 569 /* 570 * There are 64 doorbells in the switch hardware but this is 571 * shared among all partitions. So we must split them in half 572 * (32 for each partition). However, the message interrupts are 573 * also shared with the top 4 doorbells so we just limit this to 574 * 28 doorbells per partition 575 */ 576 static void switchtec_ntb_init_db(struct switchtec_ntb *sndev) 577 { 578 sndev->db_valid_mask = 0x0FFFFFFF; 579 580 if (sndev->self_partition < sndev->peer_partition) { 581 sndev->db_shift = 0; 582 sndev->db_peer_shift = 32; 583 } else { 584 sndev->db_shift = 32; 585 sndev->db_peer_shift = 0; 586 } 587 588 sndev->db_mask = 0x0FFFFFFFFFFFFFFFULL; 589 iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); 590 iowrite64(sndev->db_valid_mask << sndev->db_peer_shift, 591 &sndev->mmio_self_dbmsg->odb_mask); 592 } 593 594 static void switchtec_ntb_init_msgs(struct switchtec_ntb *sndev) 595 { 596 int i; 597 u32 msg_map = 0; 598 599 for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) { 600 int m = i | sndev->peer_partition << 2; 601 602 msg_map |= m << i * 8; 603 } 604 605 iowrite32(msg_map, &sndev->mmio_self_dbmsg->msg_map); 606 607 for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) 608 iowrite64(NTB_DBMSG_IMSG_STATUS | NTB_DBMSG_IMSG_MASK, 609 &sndev->mmio_self_dbmsg->imsg[i]); 610 } 611 612 static int switchtec_ntb_init_req_id_table(struct switchtec_ntb *sndev) 613 { 614 int rc = 0; 615 u16 req_id; 616 u32 error; 617 618 req_id = ioread16(&sndev->mmio_ntb->requester_id); 619 620 if (ioread32(&sndev->mmio_self_ctrl->req_id_table_size) < 2) { 621 dev_err(&sndev->stdev->dev, 622 "Not enough requester IDs available."); 623 return -EFAULT; 624 } 625 626 rc = switchtec_ntb_part_op(sndev, sndev->mmio_self_ctrl, 627 NTB_CTRL_PART_OP_LOCK, 628 NTB_CTRL_PART_STATUS_LOCKED); 629 if (rc) 630 return rc; 631 632 iowrite32(NTB_PART_CTRL_ID_PROT_DIS, 633 &sndev->mmio_self_ctrl->partition_ctrl); 634 635 /* 636 * Root Complex Requester ID (which is 0:00.0) 637 */ 638 iowrite32(0 << 16 | NTB_CTRL_REQ_ID_EN, 639 &sndev->mmio_self_ctrl->req_id_table[0]); 640 641 /* 642 * Host Bridge Requester ID (as read from the mmap address) 643 */ 644 iowrite32(req_id << 16 | NTB_CTRL_REQ_ID_EN, 645 &sndev->mmio_self_ctrl->req_id_table[1]); 646 647 rc = switchtec_ntb_part_op(sndev, sndev->mmio_self_ctrl, 648 NTB_CTRL_PART_OP_CFG, 649 NTB_CTRL_PART_STATUS_NORMAL); 650 if (rc == -EIO) { 651 error = ioread32(&sndev->mmio_self_ctrl->req_id_error); 652 dev_err(&sndev->stdev->dev, 653 "Error setting up the requester ID table: %08x", 654 error); 655 } 656 657 return rc; 658 } 659 660 static void switchtec_ntb_init_shared(struct switchtec_ntb *sndev) 661 { 662 int i; 663 664 memset(sndev->self_shared, 0, LUT_SIZE); 665 sndev->self_shared->magic = SWITCHTEC_NTB_MAGIC; 666 sndev->self_shared->partition_id = sndev->stdev->partition; 667 668 for (i = 0; i < sndev->nr_direct_mw; i++) { 669 int bar = sndev->direct_mw_to_bar[i]; 670 resource_size_t sz = pci_resource_len(sndev->stdev->pdev, bar); 671 672 if (i == 0) 673 sz = min_t(resource_size_t, sz, 674 LUT_SIZE * sndev->nr_lut_mw); 675 676 sndev->self_shared->mw_sizes[i] = sz; 677 } 678 679 for (i = 0; i < sndev->nr_lut_mw; i++) { 680 int idx = sndev->nr_direct_mw + i; 681 682 sndev->self_shared->mw_sizes[idx] = LUT_SIZE; 683 } 684 } 685 686 static int switchtec_ntb_init_shared_mw(struct switchtec_ntb *sndev) 687 { 688 struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl; 689 int bar = sndev->direct_mw_to_bar[0]; 690 u32 ctl_val; 691 int rc; 692 693 sndev->self_shared = dma_zalloc_coherent(&sndev->stdev->pdev->dev, 694 LUT_SIZE, 695 &sndev->self_shared_dma, 696 GFP_KERNEL); 697 if (!sndev->self_shared) { 698 dev_err(&sndev->stdev->dev, 699 "unable to allocate memory for shared mw"); 700 return -ENOMEM; 701 } 702 703 switchtec_ntb_init_shared(sndev); 704 705 rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_LOCK, 706 NTB_CTRL_PART_STATUS_LOCKED); 707 if (rc) 708 goto unalloc_and_exit; 709 710 ctl_val = ioread32(&ctl->bar_entry[bar].ctl); 711 ctl_val &= 0xFF; 712 ctl_val |= NTB_CTRL_BAR_LUT_WIN_EN; 713 ctl_val |= ilog2(LUT_SIZE) << 8; 714 ctl_val |= (sndev->nr_lut_mw - 1) << 14; 715 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 716 717 iowrite64((NTB_CTRL_LUT_EN | (sndev->self_partition << 1) | 718 sndev->self_shared_dma), 719 &ctl->lut_entry[0]); 720 721 rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG, 722 NTB_CTRL_PART_STATUS_NORMAL); 723 if (rc) { 724 u32 bar_error, lut_error; 725 726 bar_error = ioread32(&ctl->bar_error); 727 lut_error = ioread32(&ctl->lut_error); 728 dev_err(&sndev->stdev->dev, 729 "Error setting up shared MW: %08x / %08x", 730 bar_error, lut_error); 731 goto unalloc_and_exit; 732 } 733 734 sndev->peer_shared = pci_iomap(sndev->stdev->pdev, bar, LUT_SIZE); 735 if (!sndev->peer_shared) { 736 rc = -ENOMEM; 737 goto unalloc_and_exit; 738 } 739 740 dev_dbg(&sndev->stdev->dev, "Shared MW Ready"); 741 return 0; 742 743 unalloc_and_exit: 744 dma_free_coherent(&sndev->stdev->pdev->dev, LUT_SIZE, 745 sndev->self_shared, sndev->self_shared_dma); 746 747 return rc; 748 } 749 750 static void switchtec_ntb_deinit_shared_mw(struct switchtec_ntb *sndev) 751 { 752 if (sndev->peer_shared) 753 pci_iounmap(sndev->stdev->pdev, sndev->peer_shared); 754 755 if (sndev->self_shared) 756 dma_free_coherent(&sndev->stdev->pdev->dev, LUT_SIZE, 757 sndev->self_shared, 758 sndev->self_shared_dma); 759 } 760 761 static irqreturn_t switchtec_ntb_doorbell_isr(int irq, void *dev) 762 { 763 struct switchtec_ntb *sndev = dev; 764 765 dev_dbg(&sndev->stdev->dev, "doorbell\n"); 766 767 ntb_db_event(&sndev->ntb, 0); 768 769 return IRQ_HANDLED; 770 } 771 772 static irqreturn_t switchtec_ntb_message_isr(int irq, void *dev) 773 { 774 int i; 775 struct switchtec_ntb *sndev = dev; 776 777 for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) { 778 u64 msg = ioread64(&sndev->mmio_self_dbmsg->imsg[i]); 779 780 if (msg & NTB_DBMSG_IMSG_STATUS) { 781 dev_dbg(&sndev->stdev->dev, "message: %d %08x\n", i, 782 (u32)msg); 783 iowrite8(1, &sndev->mmio_self_dbmsg->imsg[i].status); 784 785 if (i == LINK_MESSAGE) 786 switchtec_ntb_check_link(sndev); 787 } 788 } 789 790 return IRQ_HANDLED; 791 } 792 793 static int switchtec_ntb_init_db_msg_irq(struct switchtec_ntb *sndev) 794 { 795 int i; 796 int rc; 797 int doorbell_irq = 0; 798 int message_irq = 0; 799 int event_irq; 800 int idb_vecs = sizeof(sndev->mmio_self_dbmsg->idb_vec_map); 801 802 event_irq = ioread32(&sndev->stdev->mmio_part_cfg->vep_vector_number); 803 804 while (doorbell_irq == event_irq) 805 doorbell_irq++; 806 while (message_irq == doorbell_irq || 807 message_irq == event_irq) 808 message_irq++; 809 810 dev_dbg(&sndev->stdev->dev, "irqs - event: %d, db: %d, msgs: %d", 811 event_irq, doorbell_irq, message_irq); 812 813 for (i = 0; i < idb_vecs - 4; i++) 814 iowrite8(doorbell_irq, 815 &sndev->mmio_self_dbmsg->idb_vec_map[i]); 816 817 for (; i < idb_vecs; i++) 818 iowrite8(message_irq, 819 &sndev->mmio_self_dbmsg->idb_vec_map[i]); 820 821 sndev->doorbell_irq = pci_irq_vector(sndev->stdev->pdev, doorbell_irq); 822 sndev->message_irq = pci_irq_vector(sndev->stdev->pdev, message_irq); 823 824 rc = request_irq(sndev->doorbell_irq, 825 switchtec_ntb_doorbell_isr, 0, 826 "switchtec_ntb_doorbell", sndev); 827 if (rc) 828 return rc; 829 830 rc = request_irq(sndev->message_irq, 831 switchtec_ntb_message_isr, 0, 832 "switchtec_ntb_message", sndev); 833 if (rc) { 834 free_irq(sndev->doorbell_irq, sndev); 835 return rc; 836 } 837 838 return 0; 839 } 840 841 static void switchtec_ntb_deinit_db_msg_irq(struct switchtec_ntb *sndev) 842 { 843 free_irq(sndev->doorbell_irq, sndev); 844 free_irq(sndev->message_irq, sndev); 845 } 846 847 static int switchtec_ntb_add(struct device *dev, 848 struct class_interface *class_intf) 849 { 850 struct switchtec_dev *stdev = to_stdev(dev); 851 struct switchtec_ntb *sndev; 852 int rc; 853 854 stdev->sndev = NULL; 855 856 if (stdev->pdev->class != MICROSEMI_NTB_CLASSCODE) 857 return -ENODEV; 858 859 if (stdev->partition_count != 2) 860 dev_warn(dev, "ntb driver only supports 2 partitions"); 861 862 sndev = kzalloc_node(sizeof(*sndev), GFP_KERNEL, dev_to_node(dev)); 863 if (!sndev) 864 return -ENOMEM; 865 866 sndev->stdev = stdev; 867 switchtec_ntb_init_sndev(sndev); 868 switchtec_ntb_init_mw(sndev); 869 switchtec_ntb_init_db(sndev); 870 switchtec_ntb_init_msgs(sndev); 871 872 rc = switchtec_ntb_init_req_id_table(sndev); 873 if (rc) 874 goto free_and_exit; 875 876 rc = switchtec_ntb_init_shared_mw(sndev); 877 if (rc) 878 goto free_and_exit; 879 880 rc = switchtec_ntb_init_db_msg_irq(sndev); 881 if (rc) 882 goto deinit_shared_and_exit; 883 884 rc = ntb_register_device(&sndev->ntb); 885 if (rc) 886 goto deinit_and_exit; 887 888 stdev->sndev = sndev; 889 stdev->link_notifier = switchtec_ntb_link_notification; 890 dev_info(dev, "NTB device registered"); 891 892 return 0; 893 894 deinit_and_exit: 895 switchtec_ntb_deinit_db_msg_irq(sndev); 896 deinit_shared_and_exit: 897 switchtec_ntb_deinit_shared_mw(sndev); 898 free_and_exit: 899 kfree(sndev); 900 dev_err(dev, "failed to register ntb device: %d", rc); 901 return rc; 902 } 903 904 void switchtec_ntb_remove(struct device *dev, 905 struct class_interface *class_intf) 906 { 907 struct switchtec_dev *stdev = to_stdev(dev); 908 struct switchtec_ntb *sndev = stdev->sndev; 909 910 if (!sndev) 911 return; 912 913 stdev->link_notifier = NULL; 914 stdev->sndev = NULL; 915 ntb_unregister_device(&sndev->ntb); 916 switchtec_ntb_deinit_db_msg_irq(sndev); 917 switchtec_ntb_deinit_shared_mw(sndev); 918 kfree(sndev); 919 dev_info(dev, "ntb device unregistered"); 920 } 921 922 static struct class_interface switchtec_interface = { 923 .add_dev = switchtec_ntb_add, 924 .remove_dev = switchtec_ntb_remove, 925 }; 926 927 static int __init switchtec_ntb_init(void) 928 { 929 switchtec_interface.class = switchtec_class; 930 return class_interface_register(&switchtec_interface); 931 } 932 module_init(switchtec_ntb_init); 933 934 static void __exit switchtec_ntb_exit(void) 935 { 936 class_interface_unregister(&switchtec_interface); 937 } 938 module_exit(switchtec_ntb_exit); 939