1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2017 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * BSD LICENSE 14 * 15 * Copyright(c) 2017 Intel Corporation. All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 21 * * Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * * Redistributions in binary form must reproduce the above copy 24 * notice, this list of conditions and the following disclaimer in 25 * the documentation and/or other materials provided with the 26 * distribution. 27 * * Neither the name of Intel Corporation nor the names of its 28 * contributors may be used to endorse or promote products derived 29 * from this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * Intel PCIe GEN3 NTB Linux driver 44 * 45 */ 46 47 #include <linux/debugfs.h> 48 #include <linux/delay.h> 49 #include <linux/init.h> 50 #include <linux/interrupt.h> 51 #include <linux/module.h> 52 #include <linux/pci.h> 53 #include <linux/random.h> 54 #include <linux/slab.h> 55 #include <linux/ntb.h> 56 57 #include "ntb_hw_intel.h" 58 #include "ntb_hw_gen1.h" 59 #include "ntb_hw_gen3.h" 60 61 static int gen3_poll_link(struct intel_ntb_dev *ndev); 62 63 static const struct intel_ntb_reg gen3_reg = { 64 .poll_link = gen3_poll_link, 65 .link_is_up = xeon_link_is_up, 66 .db_ioread = gen3_db_ioread, 67 .db_iowrite = gen3_db_iowrite, 68 .db_size = sizeof(u32), 69 .ntb_ctl = GEN3_NTBCNTL_OFFSET, 70 .mw_bar = {2, 4}, 71 }; 72 73 static const struct intel_ntb_alt_reg gen3_pri_reg = { 74 .db_bell = GEN3_EM_DOORBELL_OFFSET, 75 .db_clear = GEN3_IM_INT_STATUS_OFFSET, 76 .db_mask = GEN3_IM_INT_DISABLE_OFFSET, 77 .spad = GEN3_IM_SPAD_OFFSET, 78 }; 79 80 static const struct intel_ntb_alt_reg gen3_b2b_reg = { 81 .db_bell = GEN3_IM_DOORBELL_OFFSET, 82 .db_clear = GEN3_EM_INT_STATUS_OFFSET, 83 .db_mask = GEN3_EM_INT_DISABLE_OFFSET, 84 .spad = GEN3_B2B_SPAD_OFFSET, 85 }; 86 87 static const struct intel_ntb_xlat_reg gen3_sec_xlat = { 88 /* .bar0_base = GEN3_EMBAR0_OFFSET, */ 89 .bar2_limit = GEN3_IMBAR1XLMT_OFFSET, 90 .bar2_xlat = GEN3_IMBAR1XBASE_OFFSET, 91 }; 92 93 static int gen3_poll_link(struct intel_ntb_dev *ndev) 94 { 95 u16 reg_val; 96 int rc; 97 98 ndev->reg->db_iowrite(ndev->db_link_mask, 99 ndev->self_mmio + 100 ndev->self_reg->db_clear); 101 102 rc = pci_read_config_word(ndev->ntb.pdev, 103 GEN3_LINK_STATUS_OFFSET, ®_val); 104 if (rc) 105 return 0; 106 107 if (reg_val == ndev->lnk_sta) 108 return 0; 109 110 ndev->lnk_sta = reg_val; 111 112 return 1; 113 } 114 115 static int gen3_init_isr(struct intel_ntb_dev *ndev) 116 { 117 int i; 118 119 /* 120 * The MSIX vectors and the interrupt status bits are not lined up 121 * on Skylake. By default the link status bit is bit 32, however it 122 * is by default MSIX vector0. We need to fixup to line them up. 123 * The vectors at reset is 1-32,0. We need to reprogram to 0-32. 124 */ 125 126 for (i = 0; i < GEN3_DB_MSIX_VECTOR_COUNT; i++) 127 iowrite8(i, ndev->self_mmio + GEN3_INTVEC_OFFSET + i); 128 129 /* move link status down one as workaround */ 130 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) { 131 iowrite8(GEN3_DB_MSIX_VECTOR_COUNT - 2, 132 ndev->self_mmio + GEN3_INTVEC_OFFSET + 133 (GEN3_DB_MSIX_VECTOR_COUNT - 1)); 134 } 135 136 return ndev_init_isr(ndev, GEN3_DB_MSIX_VECTOR_COUNT, 137 GEN3_DB_MSIX_VECTOR_COUNT, 138 GEN3_DB_MSIX_VECTOR_SHIFT, 139 GEN3_DB_TOTAL_SHIFT); 140 } 141 142 static int gen3_setup_b2b_mw(struct intel_ntb_dev *ndev, 143 const struct intel_b2b_addr *addr, 144 const struct intel_b2b_addr *peer_addr) 145 { 146 struct pci_dev *pdev; 147 void __iomem *mmio; 148 phys_addr_t bar_addr; 149 150 pdev = ndev->ntb.pdev; 151 mmio = ndev->self_mmio; 152 153 /* setup incoming bar limits == base addrs (zero length windows) */ 154 bar_addr = addr->bar2_addr64; 155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET); 156 bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET); 157 dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr); 158 159 bar_addr = addr->bar4_addr64; 160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET); 161 bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET); 162 dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr); 163 164 /* zero incoming translation addrs */ 165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET); 166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET); 167 168 ndev->peer_mmio = ndev->self_mmio; 169 170 return 0; 171 } 172 173 static int gen3_init_ntb(struct intel_ntb_dev *ndev) 174 { 175 int rc; 176 177 178 ndev->mw_count = XEON_MW_COUNT; 179 ndev->spad_count = GEN3_SPAD_COUNT; 180 ndev->db_count = GEN3_DB_COUNT; 181 ndev->db_link_mask = GEN3_DB_LINK_BIT; 182 183 /* DB fixup for using 31 right now */ 184 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) 185 ndev->db_link_mask |= BIT_ULL(31); 186 187 switch (ndev->ntb.topo) { 188 case NTB_TOPO_B2B_USD: 189 case NTB_TOPO_B2B_DSD: 190 ndev->self_reg = &gen3_pri_reg; 191 ndev->peer_reg = &gen3_b2b_reg; 192 ndev->xlat_reg = &gen3_sec_xlat; 193 194 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { 195 rc = gen3_setup_b2b_mw(ndev, 196 &xeon_b2b_dsd_addr, 197 &xeon_b2b_usd_addr); 198 } else { 199 rc = gen3_setup_b2b_mw(ndev, 200 &xeon_b2b_usd_addr, 201 &xeon_b2b_dsd_addr); 202 } 203 204 if (rc) 205 return rc; 206 207 /* Enable Bus Master and Memory Space on the secondary side */ 208 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, 209 ndev->self_mmio + GEN3_SPCICMD_OFFSET); 210 211 break; 212 213 default: 214 return -EINVAL; 215 } 216 217 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; 218 /* Make sure we are not using DB's used for link status */ 219 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) 220 ndev->db_valid_mask &= ~ndev->db_link_mask; 221 222 ndev->reg->db_iowrite(ndev->db_valid_mask, 223 ndev->self_mmio + 224 ndev->self_reg->db_mask); 225 226 return 0; 227 } 228 229 int gen3_init_dev(struct intel_ntb_dev *ndev) 230 { 231 struct pci_dev *pdev; 232 u8 ppd; 233 int rc; 234 235 pdev = ndev->ntb.pdev; 236 237 ndev->reg = &gen3_reg; 238 239 rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd); 240 if (rc) 241 return -EIO; 242 243 ndev->ntb.topo = xeon_ppd_topo(ndev, ppd); 244 dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd, 245 ntb_topo_string(ndev->ntb.topo)); 246 if (ndev->ntb.topo == NTB_TOPO_NONE) 247 return -EINVAL; 248 249 ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD; 250 251 rc = gen3_init_ntb(ndev); 252 if (rc) 253 return rc; 254 255 return gen3_init_isr(ndev); 256 } 257 258 ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf, 259 size_t count, loff_t *offp) 260 { 261 struct intel_ntb_dev *ndev; 262 void __iomem *mmio; 263 char *buf; 264 size_t buf_size; 265 ssize_t ret, off; 266 union { u64 v64; u32 v32; u16 v16; } u; 267 268 ndev = filp->private_data; 269 mmio = ndev->self_mmio; 270 271 buf_size = min(count, 0x800ul); 272 273 buf = kmalloc(buf_size, GFP_KERNEL); 274 if (!buf) 275 return -ENOMEM; 276 277 off = 0; 278 279 off += scnprintf(buf + off, buf_size - off, 280 "NTB Device Information:\n"); 281 282 off += scnprintf(buf + off, buf_size - off, 283 "Connection Topology -\t%s\n", 284 ntb_topo_string(ndev->ntb.topo)); 285 286 off += scnprintf(buf + off, buf_size - off, 287 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl); 288 off += scnprintf(buf + off, buf_size - off, 289 "LNK STA -\t\t%#06x\n", ndev->lnk_sta); 290 291 if (!ndev->reg->link_is_up(ndev)) 292 off += scnprintf(buf + off, buf_size - off, 293 "Link Status -\t\tDown\n"); 294 else { 295 off += scnprintf(buf + off, buf_size - off, 296 "Link Status -\t\tUp\n"); 297 off += scnprintf(buf + off, buf_size - off, 298 "Link Speed -\t\tPCI-E Gen %u\n", 299 NTB_LNK_STA_SPEED(ndev->lnk_sta)); 300 off += scnprintf(buf + off, buf_size - off, 301 "Link Width -\t\tx%u\n", 302 NTB_LNK_STA_WIDTH(ndev->lnk_sta)); 303 } 304 305 off += scnprintf(buf + off, buf_size - off, 306 "Memory Window Count -\t%u\n", ndev->mw_count); 307 off += scnprintf(buf + off, buf_size - off, 308 "Scratchpad Count -\t%u\n", ndev->spad_count); 309 off += scnprintf(buf + off, buf_size - off, 310 "Doorbell Count -\t%u\n", ndev->db_count); 311 off += scnprintf(buf + off, buf_size - off, 312 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count); 313 off += scnprintf(buf + off, buf_size - off, 314 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift); 315 316 off += scnprintf(buf + off, buf_size - off, 317 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask); 318 off += scnprintf(buf + off, buf_size - off, 319 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask); 320 off += scnprintf(buf + off, buf_size - off, 321 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); 322 323 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); 324 off += scnprintf(buf + off, buf_size - off, 325 "Doorbell Mask -\t\t%#llx\n", u.v64); 326 327 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell); 328 off += scnprintf(buf + off, buf_size - off, 329 "Doorbell Bell -\t\t%#llx\n", u.v64); 330 331 off += scnprintf(buf + off, buf_size - off, 332 "\nNTB Incoming XLAT:\n"); 333 334 u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET); 335 off += scnprintf(buf + off, buf_size - off, 336 "IMBAR1XBASE -\t\t%#018llx\n", u.v64); 337 338 u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET); 339 off += scnprintf(buf + off, buf_size - off, 340 "IMBAR2XBASE -\t\t%#018llx\n", u.v64); 341 342 u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET); 343 off += scnprintf(buf + off, buf_size - off, 344 "IMBAR1XLMT -\t\t\t%#018llx\n", u.v64); 345 346 u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET); 347 off += scnprintf(buf + off, buf_size - off, 348 "IMBAR2XLMT -\t\t\t%#018llx\n", u.v64); 349 350 if (ntb_topo_is_b2b(ndev->ntb.topo)) { 351 off += scnprintf(buf + off, buf_size - off, 352 "\nNTB Outgoing B2B XLAT:\n"); 353 354 u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET); 355 off += scnprintf(buf + off, buf_size - off, 356 "EMBAR1XBASE -\t\t%#018llx\n", u.v64); 357 358 u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET); 359 off += scnprintf(buf + off, buf_size - off, 360 "EMBAR2XBASE -\t\t%#018llx\n", u.v64); 361 362 u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET); 363 off += scnprintf(buf + off, buf_size - off, 364 "EMBAR1XLMT -\t\t%#018llx\n", u.v64); 365 366 u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET); 367 off += scnprintf(buf + off, buf_size - off, 368 "EMBAR2XLMT -\t\t%#018llx\n", u.v64); 369 370 off += scnprintf(buf + off, buf_size - off, 371 "\nNTB Secondary BAR:\n"); 372 373 u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET); 374 off += scnprintf(buf + off, buf_size - off, 375 "EMBAR0 -\t\t%#018llx\n", u.v64); 376 377 u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET); 378 off += scnprintf(buf + off, buf_size - off, 379 "EMBAR1 -\t\t%#018llx\n", u.v64); 380 381 u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET); 382 off += scnprintf(buf + off, buf_size - off, 383 "EMBAR2 -\t\t%#018llx\n", u.v64); 384 } 385 386 off += scnprintf(buf + off, buf_size - off, 387 "\nNTB Statistics:\n"); 388 389 u.v16 = ioread16(mmio + GEN3_USMEMMISS_OFFSET); 390 off += scnprintf(buf + off, buf_size - off, 391 "Upstream Memory Miss -\t%u\n", u.v16); 392 393 off += scnprintf(buf + off, buf_size - off, 394 "\nNTB Hardware Errors:\n"); 395 396 if (!pci_read_config_word(ndev->ntb.pdev, 397 GEN3_DEVSTS_OFFSET, &u.v16)) 398 off += scnprintf(buf + off, buf_size - off, 399 "DEVSTS -\t\t%#06x\n", u.v16); 400 401 if (!pci_read_config_word(ndev->ntb.pdev, 402 GEN3_LINK_STATUS_OFFSET, &u.v16)) 403 off += scnprintf(buf + off, buf_size - off, 404 "LNKSTS -\t\t%#06x\n", u.v16); 405 406 if (!pci_read_config_dword(ndev->ntb.pdev, 407 GEN3_UNCERRSTS_OFFSET, &u.v32)) 408 off += scnprintf(buf + off, buf_size - off, 409 "UNCERRSTS -\t\t%#06x\n", u.v32); 410 411 if (!pci_read_config_dword(ndev->ntb.pdev, 412 GEN3_CORERRSTS_OFFSET, &u.v32)) 413 off += scnprintf(buf + off, buf_size - off, 414 "CORERRSTS -\t\t%#06x\n", u.v32); 415 416 ret = simple_read_from_buffer(ubuf, count, offp, buf, off); 417 kfree(buf); 418 return ret; 419 } 420 421 int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed, 422 enum ntb_width max_width) 423 { 424 struct intel_ntb_dev *ndev; 425 u32 ntb_ctl; 426 427 ndev = container_of(ntb, struct intel_ntb_dev, ntb); 428 429 dev_dbg(&ntb->pdev->dev, 430 "Enabling link with max_speed %d max_width %d\n", 431 max_speed, max_width); 432 433 if (max_speed != NTB_SPEED_AUTO) 434 dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed); 435 if (max_width != NTB_WIDTH_AUTO) 436 dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width); 437 438 ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); 439 ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK); 440 ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP; 441 ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP; 442 iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); 443 444 return 0; 445 } 446 static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, 447 dma_addr_t addr, resource_size_t size) 448 { 449 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 450 unsigned long xlat_reg, limit_reg; 451 resource_size_t bar_size, mw_size; 452 void __iomem *mmio; 453 u64 base, limit, reg_val; 454 int bar; 455 456 if (pidx != NTB_DEF_PEER_IDX) 457 return -EINVAL; 458 459 if (idx >= ndev->b2b_idx && !ndev->b2b_off) 460 idx += 1; 461 462 bar = ndev_mw_to_bar(ndev, idx); 463 if (bar < 0) 464 return bar; 465 466 bar_size = pci_resource_len(ndev->ntb.pdev, bar); 467 468 if (idx == ndev->b2b_idx) 469 mw_size = bar_size - ndev->b2b_off; 470 else 471 mw_size = bar_size; 472 473 /* hardware requires that addr is aligned to bar size */ 474 if (addr & (bar_size - 1)) 475 return -EINVAL; 476 477 /* make sure the range fits in the usable mw size */ 478 if (size > mw_size) 479 return -EINVAL; 480 481 mmio = ndev->self_mmio; 482 xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10); 483 limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10); 484 base = pci_resource_start(ndev->ntb.pdev, bar); 485 486 /* Set the limit if supported, if size is not mw_size */ 487 if (limit_reg && size != mw_size) 488 limit = base + size; 489 else 490 limit = base + mw_size; 491 492 /* set and verify setting the translation address */ 493 iowrite64(addr, mmio + xlat_reg); 494 reg_val = ioread64(mmio + xlat_reg); 495 if (reg_val != addr) { 496 iowrite64(0, mmio + xlat_reg); 497 return -EIO; 498 } 499 500 dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val); 501 502 /* set and verify setting the limit */ 503 iowrite64(limit, mmio + limit_reg); 504 reg_val = ioread64(mmio + limit_reg); 505 if (reg_val != limit) { 506 iowrite64(base, mmio + limit_reg); 507 iowrite64(0, mmio + xlat_reg); 508 return -EIO; 509 } 510 511 dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val); 512 513 /* setup the EP */ 514 limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000; 515 base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx)); 516 base &= ~0xf; 517 518 if (limit_reg && size != mw_size) 519 limit = base + size; 520 else 521 limit = base + mw_size; 522 523 /* set and verify setting the limit */ 524 iowrite64(limit, mmio + limit_reg); 525 reg_val = ioread64(mmio + limit_reg); 526 if (reg_val != limit) { 527 iowrite64(base, mmio + limit_reg); 528 iowrite64(0, mmio + xlat_reg); 529 return -EIO; 530 } 531 532 dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val); 533 534 return 0; 535 } 536 537 int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, 538 resource_size_t *db_size, 539 u64 *db_data, int db_bit) 540 { 541 phys_addr_t db_addr_base; 542 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 543 544 if (unlikely(db_bit >= BITS_PER_LONG_LONG)) 545 return -EINVAL; 546 547 if (unlikely(BIT_ULL(db_bit) & ~ntb_ndev(ntb)->db_valid_mask)) 548 return -EINVAL; 549 550 ndev_db_addr(ndev, &db_addr_base, db_size, ndev->peer_addr, 551 ndev->peer_reg->db_bell); 552 553 if (db_addr) { 554 *db_addr = db_addr_base + (db_bit * 4); 555 dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx db bit %d\n", 556 *db_addr, db_bit); 557 } 558 559 if (db_data) { 560 *db_data = 1; 561 dev_dbg(&ndev->ntb.pdev->dev, "Peer db data %llx db bit %d\n", 562 *db_data, db_bit); 563 } 564 565 return 0; 566 } 567 568 int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 569 { 570 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 571 int bit; 572 573 if (db_bits & ~ndev->db_valid_mask) 574 return -EINVAL; 575 576 while (db_bits) { 577 bit = __ffs(db_bits); 578 iowrite32(1, ndev->peer_mmio + 579 ndev->peer_reg->db_bell + (bit * 4)); 580 db_bits &= db_bits - 1; 581 } 582 583 return 0; 584 } 585 586 u64 intel_ntb3_db_read(struct ntb_dev *ntb) 587 { 588 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 589 590 return ndev_db_read(ndev, 591 ndev->self_mmio + 592 ndev->self_reg->db_clear); 593 } 594 595 int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits) 596 { 597 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 598 599 return ndev_db_write(ndev, db_bits, 600 ndev->self_mmio + 601 ndev->self_reg->db_clear); 602 } 603 604 const struct ntb_dev_ops intel_ntb3_ops = { 605 .mw_count = intel_ntb_mw_count, 606 .mw_get_align = intel_ntb_mw_get_align, 607 .mw_set_trans = intel_ntb3_mw_set_trans, 608 .peer_mw_count = intel_ntb_peer_mw_count, 609 .peer_mw_get_addr = intel_ntb_peer_mw_get_addr, 610 .link_is_up = intel_ntb_link_is_up, 611 .link_enable = intel_ntb3_link_enable, 612 .link_disable = intel_ntb_link_disable, 613 .db_valid_mask = intel_ntb_db_valid_mask, 614 .db_vector_count = intel_ntb_db_vector_count, 615 .db_vector_mask = intel_ntb_db_vector_mask, 616 .db_read = intel_ntb3_db_read, 617 .db_clear = intel_ntb3_db_clear, 618 .db_set_mask = intel_ntb_db_set_mask, 619 .db_clear_mask = intel_ntb_db_clear_mask, 620 .peer_db_addr = intel_ntb3_peer_db_addr, 621 .peer_db_set = intel_ntb3_peer_db_set, 622 .spad_is_unsafe = intel_ntb_spad_is_unsafe, 623 .spad_count = intel_ntb_spad_count, 624 .spad_read = intel_ntb_spad_read, 625 .spad_write = intel_ntb_spad_write, 626 .peer_spad_addr = intel_ntb_peer_spad_addr, 627 .peer_spad_read = intel_ntb_peer_spad_read, 628 .peer_spad_write = intel_ntb_peer_spad_write, 629 }; 630 631