1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * I2C Link Layer for PN544 HCI based Driver 4 * 5 * Copyright (C) 2012 Intel Corporation. All rights reserved. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/crc-ccitt.h> 11 #include <linux/module.h> 12 #include <linux/i2c.h> 13 #include <linux/acpi.h> 14 #include <linux/interrupt.h> 15 #include <linux/delay.h> 16 #include <linux/nfc.h> 17 #include <linux/firmware.h> 18 #include <linux/gpio/consumer.h> 19 20 #include <linux/unaligned.h> 21 22 #include <net/nfc/hci.h> 23 #include <net/nfc/llc.h> 24 #include <net/nfc/nfc.h> 25 26 #include "pn544.h" 27 28 #define PN544_I2C_FRAME_HEADROOM 1 29 #define PN544_I2C_FRAME_TAILROOM 2 30 31 /* GPIO names */ 32 #define PN544_GPIO_NAME_IRQ "pn544_irq" 33 #define PN544_GPIO_NAME_FW "pn544_fw" 34 #define PN544_GPIO_NAME_EN "pn544_en" 35 36 /* framing in HCI mode */ 37 #define PN544_HCI_I2C_LLC_LEN 1 38 #define PN544_HCI_I2C_LLC_CRC 2 39 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ 40 PN544_HCI_I2C_LLC_CRC) 41 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) 42 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 43 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ 44 PN544_HCI_I2C_LLC_MAX_PAYLOAD) 45 46 static const struct i2c_device_id pn544_hci_i2c_id_table[] = { 47 { .name = "pn544" }, 48 { } 49 }; 50 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); 51 52 static const struct acpi_device_id pn544_hci_i2c_acpi_match[] = { 53 { .id = "NXP5440" }, 54 { } 55 }; 56 MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match); 57 58 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" 59 60 /* 61 * Exposed through the 4 most significant bytes 62 * from the HCI SW_VERSION first byte, a.k.a. 63 * SW RomLib. 64 */ 65 #define PN544_HW_VARIANT_C2 0xa 66 #define PN544_HW_VARIANT_C3 0xb 67 68 #define PN544_FW_CMD_RESET 0x01 69 #define PN544_FW_CMD_WRITE 0x08 70 #define PN544_FW_CMD_CHECK 0x06 71 #define PN544_FW_CMD_SECURE_WRITE 0x0C 72 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D 73 74 struct pn544_i2c_fw_frame_write { 75 u8 cmd; 76 u16 be_length; 77 u8 be_dest_addr[3]; 78 u16 be_datalen; 79 u8 data[]; 80 } __packed; 81 82 struct pn544_i2c_fw_frame_check { 83 u8 cmd; 84 u16 be_length; 85 u8 be_start_addr[3]; 86 u16 be_datalen; 87 u16 be_crc; 88 } __packed; 89 90 struct pn544_i2c_fw_frame_response { 91 u8 status; 92 u16 be_length; 93 } __packed; 94 95 struct pn544_i2c_fw_blob { 96 u32 be_size; 97 u32 be_destaddr; 98 u8 data[]; 99 }; 100 101 struct pn544_i2c_fw_secure_frame { 102 u8 cmd; 103 u16 be_datalen; 104 u8 data[]; 105 } __packed; 106 107 struct pn544_i2c_fw_secure_blob { 108 u64 header; 109 u8 data[]; 110 }; 111 112 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01 113 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02 114 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 115 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B 116 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 117 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 118 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 119 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 120 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D 121 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 122 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 123 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 124 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 125 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 126 127 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 128 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE 129 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 130 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ 131 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ 132 PN544_FW_WRITE_BUFFER_MAX_LEN) 133 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 134 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ 135 PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) 136 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3 137 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8 138 139 #define FW_WORK_STATE_IDLE 1 140 #define FW_WORK_STATE_START 2 141 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 142 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 143 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 144 145 struct pn544_i2c_phy { 146 struct i2c_client *i2c_dev; 147 struct nfc_hci_dev *hdev; 148 149 struct gpio_desc *gpiod_en; 150 struct gpio_desc *gpiod_fw; 151 152 unsigned int en_polarity; 153 154 u8 hw_variant; 155 156 struct work_struct fw_work; 157 int fw_work_state; 158 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; 159 const struct firmware *fw; 160 u32 fw_blob_dest_addr; 161 size_t fw_blob_size; 162 const u8 *fw_blob_data; 163 size_t fw_written; 164 size_t fw_size; 165 166 int fw_cmd_result; 167 168 int powered; 169 int run_mode; 170 171 int hard_fault; /* 172 * < 0 if hardware error occured (e.g. i2c err) 173 * and prevents normal operation. 174 */ 175 }; 176 177 #define I2C_DUMP_SKB(info, skb) \ 178 do { \ 179 pr_debug("%s:\n", info); \ 180 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ 181 16, 1, (skb)->data, (skb)->len, 0); \ 182 } while (0) 183 184 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) 185 { 186 int polarity, retry, ret; 187 static const char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; 188 int count = sizeof(rset_cmd); 189 190 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); 191 192 /* Disable fw download */ 193 gpiod_set_value_cansleep(phy->gpiod_fw, 0); 194 195 for (polarity = 0; polarity < 2; polarity++) { 196 phy->en_polarity = polarity; 197 retry = 3; 198 while (retry--) { 199 /* power off */ 200 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); 201 usleep_range(10000, 15000); 202 203 /* power on */ 204 gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity); 205 usleep_range(10000, 15000); 206 207 /* send reset */ 208 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); 209 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); 210 if (ret == count) { 211 nfc_info(&phy->i2c_dev->dev, 212 "nfc_en polarity : active %s\n", 213 (polarity == 0 ? "low" : "high")); 214 goto out; 215 } 216 } 217 } 218 219 nfc_err(&phy->i2c_dev->dev, 220 "Could not detect nfc_en polarity, fallback to active high\n"); 221 222 out: 223 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); 224 usleep_range(10000, 15000); 225 } 226 227 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) 228 { 229 gpiod_set_value_cansleep(phy->gpiod_fw, run_mode == PN544_FW_MODE ? 1 : 0); 230 gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity); 231 usleep_range(10000, 15000); 232 233 phy->run_mode = run_mode; 234 } 235 236 static int pn544_hci_i2c_enable(void *phy_id) 237 { 238 struct pn544_i2c_phy *phy = phy_id; 239 240 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); 241 242 phy->powered = 1; 243 244 return 0; 245 } 246 247 static void pn544_hci_i2c_disable(void *phy_id) 248 { 249 struct pn544_i2c_phy *phy = phy_id; 250 251 gpiod_set_value_cansleep(phy->gpiod_fw, 0); 252 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); 253 usleep_range(10000, 15000); 254 255 gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity); 256 usleep_range(10000, 15000); 257 258 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); 259 usleep_range(10000, 15000); 260 261 phy->powered = 0; 262 } 263 264 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) 265 { 266 u16 crc; 267 int len; 268 269 len = skb->len + 2; 270 *(u8 *)skb_push(skb, 1) = len; 271 272 crc = crc_ccitt(0xffff, skb->data, skb->len); 273 crc = ~crc; 274 skb_put_u8(skb, crc & 0xff); 275 skb_put_u8(skb, crc >> 8); 276 } 277 278 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) 279 { 280 skb_pull(skb, PN544_I2C_FRAME_HEADROOM); 281 skb_trim(skb, PN544_I2C_FRAME_TAILROOM); 282 } 283 284 /* 285 * Writing a frame must not return the number of written bytes. 286 * It must return either zero for success, or <0 for error. 287 * In addition, it must not alter the skb 288 */ 289 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) 290 { 291 int r; 292 struct pn544_i2c_phy *phy = phy_id; 293 struct i2c_client *client = phy->i2c_dev; 294 295 if (phy->hard_fault != 0) 296 return phy->hard_fault; 297 298 usleep_range(3000, 6000); 299 300 pn544_hci_i2c_add_len_crc(skb); 301 302 I2C_DUMP_SKB("i2c frame written", skb); 303 304 r = i2c_master_send(client, skb->data, skb->len); 305 306 if (r == -EREMOTEIO) { /* Retry, chip was in standby */ 307 usleep_range(6000, 10000); 308 r = i2c_master_send(client, skb->data, skb->len); 309 } 310 311 if (r >= 0) { 312 if (r != skb->len) 313 r = -EREMOTEIO; 314 else 315 r = 0; 316 } 317 318 pn544_hci_i2c_remove_len_crc(skb); 319 320 return r; 321 } 322 323 static int check_crc(u8 *buf, int buflen) 324 { 325 int len; 326 u16 crc; 327 328 len = buf[0] + 1; 329 crc = crc_ccitt(0xffff, buf, len - 2); 330 crc = ~crc; 331 332 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { 333 pr_err("CRC error 0x%x != 0x%x 0x%x\n", 334 crc, buf[len - 1], buf[len - 2]); 335 pr_info("%s: BAD CRC\n", __func__); 336 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, 337 16, 2, buf, buflen, false); 338 return -EPERM; 339 } 340 return 0; 341 } 342 343 /* 344 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees 345 * that i2c bus will be flushed and that next read will start on a new frame. 346 * returned skb contains only LLC header and payload. 347 * returns: 348 * -EREMOTEIO : i2c read error (fatal) 349 * -EBADMSG : frame was incorrect and discarded 350 * -ENOMEM : cannot allocate skb, frame dropped 351 */ 352 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) 353 { 354 int r; 355 u8 len; 356 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; 357 struct i2c_client *client = phy->i2c_dev; 358 359 r = i2c_master_recv(client, &len, 1); 360 if (r != 1) { 361 nfc_err(&client->dev, "cannot read len byte\n"); 362 return -EREMOTEIO; 363 } 364 365 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || 366 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { 367 nfc_err(&client->dev, "invalid len byte\n"); 368 r = -EBADMSG; 369 goto flush; 370 } 371 372 *skb = alloc_skb(1 + len, GFP_KERNEL); 373 if (*skb == NULL) { 374 r = -ENOMEM; 375 goto flush; 376 } 377 378 skb_put_u8(*skb, len); 379 380 r = i2c_master_recv(client, skb_put(*skb, len), len); 381 if (r != len) { 382 kfree_skb(*skb); 383 return -EREMOTEIO; 384 } 385 386 I2C_DUMP_SKB("i2c frame read", *skb); 387 388 r = check_crc((*skb)->data, (*skb)->len); 389 if (r != 0) { 390 kfree_skb(*skb); 391 r = -EBADMSG; 392 goto flush; 393 } 394 395 skb_pull(*skb, 1); 396 skb_trim(*skb, (*skb)->len - 2); 397 398 usleep_range(3000, 6000); 399 400 return 0; 401 402 flush: 403 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) 404 r = -EREMOTEIO; 405 406 usleep_range(3000, 6000); 407 408 return r; 409 } 410 411 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) 412 { 413 int r; 414 struct pn544_i2c_fw_frame_response response; 415 struct i2c_client *client = phy->i2c_dev; 416 417 r = i2c_master_recv(client, (char *) &response, sizeof(response)); 418 if (r != sizeof(response)) { 419 nfc_err(&client->dev, "cannot read fw status\n"); 420 return -EIO; 421 } 422 423 usleep_range(3000, 6000); 424 425 switch (response.status) { 426 case 0: 427 return 0; 428 case PN544_FW_CMD_RESULT_CHUNK_OK: 429 return response.status; 430 case PN544_FW_CMD_RESULT_TIMEOUT: 431 return -ETIMEDOUT; 432 case PN544_FW_CMD_RESULT_BAD_CRC: 433 return -ENODATA; 434 case PN544_FW_CMD_RESULT_ACCESS_DENIED: 435 return -EACCES; 436 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: 437 return -EPROTO; 438 case PN544_FW_CMD_RESULT_INVALID_PARAMETER: 439 return -EINVAL; 440 case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: 441 return -ENOTSUPP; 442 case PN544_FW_CMD_RESULT_INVALID_LENGTH: 443 return -EBADMSG; 444 case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: 445 return -ENOKEY; 446 case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: 447 return -EINVAL; 448 case PN544_FW_CMD_RESULT_MEMORY_ERROR: 449 return -ENOMEM; 450 case PN544_FW_CMD_RESULT_COMMAND_REJECTED: 451 return -EACCES; 452 case PN544_FW_CMD_RESULT_WRITE_FAILED: 453 case PN544_FW_CMD_RESULT_CHUNK_ERROR: 454 return -EIO; 455 default: 456 return -EIO; 457 } 458 } 459 460 /* 461 * Reads an shdlc frame from the chip. This is not as straightforward as it 462 * seems. There are cases where we could loose the frame start synchronization. 463 * The frame format is len-data-crc, and corruption can occur anywhere while 464 * transiting on i2c bus, such that we could read an invalid len. 465 * In order to recover synchronization with the next frame, we must be sure 466 * to read the real amount of data without using the len byte. We do this by 467 * assuming the following: 468 * - the chip will always present only one single complete frame on the bus 469 * before triggering the interrupt 470 * - the chip will not present a new frame until we have completely read 471 * the previous one (or until we have handled the interrupt). 472 * The tricky case is when we read a corrupted len that is less than the real 473 * len. We must detect this here in order to determine that we need to flush 474 * the bus. This is the reason why we check the crc here. 475 */ 476 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) 477 { 478 struct pn544_i2c_phy *phy = phy_id; 479 struct i2c_client *client; 480 struct sk_buff *skb = NULL; 481 int r; 482 483 if (!phy || irq != phy->i2c_dev->irq) { 484 WARN_ON_ONCE(1); 485 return IRQ_NONE; 486 } 487 488 client = phy->i2c_dev; 489 dev_dbg(&client->dev, "IRQ\n"); 490 491 if (phy->hard_fault != 0) 492 return IRQ_HANDLED; 493 494 if (phy->run_mode == PN544_FW_MODE) { 495 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); 496 schedule_work(&phy->fw_work); 497 } else { 498 r = pn544_hci_i2c_read(phy, &skb); 499 if (r == -EREMOTEIO) { 500 phy->hard_fault = r; 501 502 nfc_hci_recv_frame(phy->hdev, NULL); 503 504 return IRQ_HANDLED; 505 } else if ((r == -ENOMEM) || (r == -EBADMSG)) { 506 return IRQ_HANDLED; 507 } 508 509 nfc_hci_recv_frame(phy->hdev, skb); 510 } 511 return IRQ_HANDLED; 512 } 513 514 static const struct nfc_phy_ops i2c_phy_ops = { 515 .write = pn544_hci_i2c_write, 516 .enable = pn544_hci_i2c_enable, 517 .disable = pn544_hci_i2c_disable, 518 }; 519 520 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, 521 u8 hw_variant) 522 { 523 struct pn544_i2c_phy *phy = phy_id; 524 525 pr_info("Starting Firmware Download (%s)\n", firmware_name); 526 527 strscpy(phy->firmware_name, firmware_name); 528 529 phy->hw_variant = hw_variant; 530 phy->fw_work_state = FW_WORK_STATE_START; 531 532 schedule_work(&phy->fw_work); 533 534 return 0; 535 } 536 537 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, 538 int result) 539 { 540 pr_info("Firmware Download Complete, result=%d\n", result); 541 542 pn544_hci_i2c_disable(phy); 543 544 phy->fw_work_state = FW_WORK_STATE_IDLE; 545 546 if (phy->fw) { 547 release_firmware(phy->fw); 548 phy->fw = NULL; 549 } 550 551 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); 552 } 553 554 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, 555 const u8 *data, u16 datalen) 556 { 557 u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; 558 struct pn544_i2c_fw_frame_write *framep; 559 u16 params_len; 560 int framelen; 561 int r; 562 563 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) 564 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; 565 566 framep = (struct pn544_i2c_fw_frame_write *) frame; 567 568 params_len = sizeof(framep->be_dest_addr) + 569 sizeof(framep->be_datalen) + datalen; 570 framelen = params_len + sizeof(framep->cmd) + 571 sizeof(framep->be_length); 572 573 framep->cmd = PN544_FW_CMD_WRITE; 574 575 put_unaligned_be16(params_len, &framep->be_length); 576 577 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; 578 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; 579 framep->be_dest_addr[2] = dest_addr & 0xff; 580 581 put_unaligned_be16(datalen, &framep->be_datalen); 582 583 memcpy(framep->data, data, datalen); 584 585 r = i2c_master_send(client, frame, framelen); 586 587 if (r == framelen) 588 return datalen; 589 else if (r < 0) 590 return r; 591 else 592 return -EIO; 593 } 594 595 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, 596 const u8 *data, u16 datalen) 597 { 598 struct pn544_i2c_fw_frame_check frame; 599 int r; 600 u16 crc; 601 602 /* calculate local crc for the data we want to check */ 603 crc = crc_ccitt(0xffff, data, datalen); 604 605 frame.cmd = PN544_FW_CMD_CHECK; 606 607 put_unaligned_be16(sizeof(frame.be_start_addr) + 608 sizeof(frame.be_datalen) + sizeof(frame.be_crc), 609 &frame.be_length); 610 611 /* tell the chip the memory region to which our crc applies */ 612 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; 613 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; 614 frame.be_start_addr[2] = start_addr & 0xff; 615 616 put_unaligned_be16(datalen, &frame.be_datalen); 617 618 /* 619 * and give our local crc. Chip will calculate its own crc for the 620 * region and compare with ours. 621 */ 622 put_unaligned_be16(crc, &frame.be_crc); 623 624 r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); 625 626 if (r == sizeof(frame)) 627 return 0; 628 else if (r < 0) 629 return r; 630 else 631 return -EIO; 632 } 633 634 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) 635 { 636 int r; 637 638 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, 639 phy->fw_blob_dest_addr + phy->fw_written, 640 phy->fw_blob_data + phy->fw_written, 641 phy->fw_blob_size - phy->fw_written); 642 if (r < 0) 643 return r; 644 645 phy->fw_written += r; 646 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; 647 648 return 0; 649 } 650 651 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, 652 const u8 *data, u16 datalen) 653 { 654 u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; 655 struct pn544_i2c_fw_secure_frame *chunk; 656 int chunklen; 657 int r; 658 659 if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) 660 datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; 661 662 chunk = (struct pn544_i2c_fw_secure_frame *) buf; 663 664 chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; 665 666 put_unaligned_be16(datalen, &chunk->be_datalen); 667 668 memcpy(chunk->data, data, datalen); 669 670 chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; 671 672 r = i2c_master_send(phy->i2c_dev, buf, chunklen); 673 674 if (r == chunklen) 675 return datalen; 676 else if (r < 0) 677 return r; 678 else 679 return -EIO; 680 681 } 682 683 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) 684 { 685 struct pn544_i2c_fw_secure_frame *framep; 686 int r; 687 688 framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; 689 if (phy->fw_written == 0) 690 phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) 691 + PN544_FW_SECURE_FRAME_HEADER_LEN; 692 693 /* Only secure write command can be chunked*/ 694 if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && 695 framep->cmd != PN544_FW_CMD_SECURE_WRITE) 696 return -EINVAL; 697 698 /* The firmware also have other commands, we just send them directly */ 699 if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { 700 r = i2c_master_send(phy->i2c_dev, 701 (const char *) phy->fw_blob_data, phy->fw_blob_size); 702 703 if (r == phy->fw_blob_size) 704 goto exit; 705 else if (r < 0) 706 return r; 707 else 708 return -EIO; 709 } 710 711 r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, 712 phy->fw_blob_data + phy->fw_written, 713 phy->fw_blob_size - phy->fw_written); 714 if (r < 0) 715 return r; 716 717 exit: 718 phy->fw_written += r; 719 phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; 720 721 /* SW reset command will not trig any response from PN544 */ 722 if (framep->cmd == PN544_FW_CMD_RESET) { 723 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 724 phy->fw_cmd_result = 0; 725 schedule_work(&phy->fw_work); 726 } 727 728 return 0; 729 } 730 731 static void pn544_hci_i2c_fw_work(struct work_struct *work) 732 { 733 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, 734 fw_work); 735 int r; 736 struct pn544_i2c_fw_blob *blob; 737 struct pn544_i2c_fw_secure_blob *secure_blob; 738 739 switch (phy->fw_work_state) { 740 case FW_WORK_STATE_START: 741 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); 742 743 r = request_firmware(&phy->fw, phy->firmware_name, 744 &phy->i2c_dev->dev); 745 if (r < 0) 746 goto exit_state_start; 747 748 phy->fw_written = 0; 749 750 switch (phy->hw_variant) { 751 case PN544_HW_VARIANT_C2: 752 blob = (struct pn544_i2c_fw_blob *) phy->fw->data; 753 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 754 phy->fw_blob_dest_addr = get_unaligned_be32( 755 &blob->be_destaddr); 756 phy->fw_blob_data = blob->data; 757 758 r = pn544_hci_i2c_fw_write_chunk(phy); 759 break; 760 case PN544_HW_VARIANT_C3: 761 secure_blob = (struct pn544_i2c_fw_secure_blob *) 762 phy->fw->data; 763 phy->fw_blob_data = secure_blob->data; 764 phy->fw_size = phy->fw->size; 765 r = pn544_hci_i2c_fw_secure_write_frame(phy); 766 break; 767 default: 768 r = -ENOTSUPP; 769 break; 770 } 771 772 exit_state_start: 773 if (r < 0) 774 pn544_hci_i2c_fw_work_complete(phy, r); 775 break; 776 777 case FW_WORK_STATE_WAIT_WRITE_ANSWER: 778 r = phy->fw_cmd_result; 779 if (r < 0) 780 goto exit_state_wait_write_answer; 781 782 if (phy->fw_written == phy->fw_blob_size) { 783 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, 784 phy->fw_blob_dest_addr, 785 phy->fw_blob_data, 786 phy->fw_blob_size); 787 if (r < 0) 788 goto exit_state_wait_write_answer; 789 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; 790 break; 791 } 792 793 r = pn544_hci_i2c_fw_write_chunk(phy); 794 795 exit_state_wait_write_answer: 796 if (r < 0) 797 pn544_hci_i2c_fw_work_complete(phy, r); 798 break; 799 800 case FW_WORK_STATE_WAIT_CHECK_ANSWER: 801 r = phy->fw_cmd_result; 802 if (r < 0) 803 goto exit_state_wait_check_answer; 804 805 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + 806 phy->fw_blob_size); 807 phy->fw_blob_size = get_unaligned_be32(&blob->be_size); 808 if (phy->fw_blob_size != 0) { 809 phy->fw_blob_dest_addr = 810 get_unaligned_be32(&blob->be_destaddr); 811 phy->fw_blob_data = blob->data; 812 813 phy->fw_written = 0; 814 r = pn544_hci_i2c_fw_write_chunk(phy); 815 } 816 817 exit_state_wait_check_answer: 818 if (r < 0 || phy->fw_blob_size == 0) 819 pn544_hci_i2c_fw_work_complete(phy, r); 820 break; 821 822 case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: 823 r = phy->fw_cmd_result; 824 if (r < 0) 825 goto exit_state_wait_secure_write_answer; 826 827 if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { 828 r = pn544_hci_i2c_fw_secure_write_frame(phy); 829 goto exit_state_wait_secure_write_answer; 830 } 831 832 if (phy->fw_written == phy->fw_blob_size) { 833 secure_blob = (struct pn544_i2c_fw_secure_blob *) 834 (phy->fw_blob_data + phy->fw_blob_size); 835 phy->fw_size -= phy->fw_blob_size + 836 PN544_FW_SECURE_BLOB_HEADER_LEN; 837 if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN 838 + PN544_FW_SECURE_FRAME_HEADER_LEN) { 839 phy->fw_blob_data = secure_blob->data; 840 841 phy->fw_written = 0; 842 r = pn544_hci_i2c_fw_secure_write_frame(phy); 843 } 844 } 845 846 exit_state_wait_secure_write_answer: 847 if (r < 0 || phy->fw_size == 0) 848 pn544_hci_i2c_fw_work_complete(phy, r); 849 break; 850 851 default: 852 break; 853 } 854 } 855 856 static const struct acpi_gpio_params enable_gpios = { 1, 0, false }; 857 static const struct acpi_gpio_params firmware_gpios = { 2, 0, false }; 858 859 static const struct acpi_gpio_mapping acpi_pn544_gpios[] = { 860 { "enable-gpios", &enable_gpios, 1 }, 861 { "firmware-gpios", &firmware_gpios, 1 }, 862 { }, 863 }; 864 865 static int pn544_hci_i2c_probe(struct i2c_client *client) 866 { 867 struct device *dev = &client->dev; 868 struct pn544_i2c_phy *phy; 869 int r = 0; 870 871 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 872 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); 873 return -ENODEV; 874 } 875 876 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), 877 GFP_KERNEL); 878 if (!phy) 879 return -ENOMEM; 880 881 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); 882 phy->fw_work_state = FW_WORK_STATE_IDLE; 883 884 phy->i2c_dev = client; 885 i2c_set_clientdata(client, phy); 886 887 r = devm_acpi_dev_add_driver_gpios(dev, acpi_pn544_gpios); 888 if (r) 889 dev_dbg(dev, "Unable to add GPIO mapping table\n"); 890 891 /* Get EN GPIO */ 892 phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 893 if (IS_ERR(phy->gpiod_en)) { 894 nfc_err(dev, "Unable to get EN GPIO\n"); 895 return PTR_ERR(phy->gpiod_en); 896 } 897 898 /* Get FW GPIO */ 899 phy->gpiod_fw = devm_gpiod_get(dev, "firmware", GPIOD_OUT_LOW); 900 if (IS_ERR(phy->gpiod_fw)) { 901 nfc_err(dev, "Unable to get FW GPIO\n"); 902 return PTR_ERR(phy->gpiod_fw); 903 } 904 905 pn544_hci_i2c_platform_init(phy); 906 907 r = devm_request_threaded_irq(&client->dev, client->irq, NULL, 908 pn544_hci_i2c_irq_thread_fn, 909 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 910 PN544_HCI_I2C_DRIVER_NAME, phy); 911 if (r < 0) { 912 nfc_err(&client->dev, "Unable to register IRQ handler\n"); 913 return r; 914 } 915 916 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, 917 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, 918 PN544_HCI_I2C_LLC_MAX_PAYLOAD, 919 pn544_hci_i2c_fw_download, &phy->hdev); 920 if (r < 0) 921 return r; 922 923 return 0; 924 } 925 926 static void pn544_hci_i2c_remove(struct i2c_client *client) 927 { 928 struct pn544_i2c_phy *phy = i2c_get_clientdata(client); 929 930 cancel_work_sync(&phy->fw_work); 931 if (phy->fw_work_state != FW_WORK_STATE_IDLE) 932 pn544_hci_i2c_fw_work_complete(phy, -ENODEV); 933 934 pn544_hci_remove(phy->hdev); 935 936 if (phy->powered) 937 pn544_hci_i2c_disable(phy); 938 } 939 940 static const struct of_device_id of_pn544_i2c_match[] = { 941 { .compatible = "nxp,pn544-i2c" }, 942 { } 943 }; 944 MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); 945 946 static struct i2c_driver pn544_hci_i2c_driver = { 947 .driver = { 948 .name = PN544_HCI_I2C_DRIVER_NAME, 949 .of_match_table = of_match_ptr(of_pn544_i2c_match), 950 .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match), 951 }, 952 .probe = pn544_hci_i2c_probe, 953 .id_table = pn544_hci_i2c_id_table, 954 .remove = pn544_hci_i2c_remove, 955 }; 956 957 module_i2c_driver(pn544_hci_i2c_driver); 958 959 MODULE_LICENSE("GPL"); 960 MODULE_DESCRIPTION(DRIVER_DESC); 961