1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (c) 2021, MediaTek Inc. 4 * Copyright (c) 2021-2022, Intel Corporation. 5 * 6 * Authors: 7 * Haijun Liu <haijun.liu@mediatek.com> 8 * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> 9 * 10 * Contributors: 11 * Amir Hanania <amir.hanania@intel.com> 12 * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 13 * Eliot Lee <eliot.lee@intel.com> 14 * Moises Veleta <moises.veleta@intel.com> 15 * Ricardo Martinez <ricardo.martinez@linux.intel.com> 16 * Sreehari Kancharla <sreehari.kancharla@intel.com> 17 */ 18 19 #ifndef __T7XX_REG_H__ 20 #define __T7XX_REG_H__ 21 22 #include <linux/bits.h> 23 24 /* Device base address offset */ 25 #define MHCCIF_RC_DEV_BASE 0x10024000 26 27 #define REG_RC2EP_SW_BSY 0x04 28 #define REG_RC2EP_SW_INT_START 0x08 29 30 #define REG_RC2EP_SW_TCHNUM 0x0c 31 #define H2D_CH_EXCEPTION_ACK 1 32 #define H2D_CH_EXCEPTION_CLEARQ_ACK 2 33 #define H2D_CH_DS_LOCK 3 34 /* Channels 4-8 are reserved */ 35 #define H2D_CH_SUSPEND_REQ 9 36 #define H2D_CH_RESUME_REQ 10 37 #define H2D_CH_SUSPEND_REQ_AP 11 38 #define H2D_CH_RESUME_REQ_AP 12 39 #define H2D_CH_DEVICE_RESET 13 40 #define H2D_CH_DRM_DISABLE_AP 14 41 42 #define REG_EP2RC_SW_INT_STS 0x10 43 #define REG_EP2RC_SW_INT_ACK 0x14 44 #define REG_EP2RC_SW_INT_EAP_MASK 0x20 45 #define REG_EP2RC_SW_INT_EAP_MASK_SET 0x30 46 #define REG_EP2RC_SW_INT_EAP_MASK_CLR 0x40 47 48 #define D2H_INT_DS_LOCK_ACK BIT(0) 49 #define D2H_INT_EXCEPTION_INIT BIT(1) 50 #define D2H_INT_EXCEPTION_INIT_DONE BIT(2) 51 #define D2H_INT_EXCEPTION_CLEARQ_DONE BIT(3) 52 #define D2H_INT_EXCEPTION_ALLQ_RESET BIT(4) 53 #define D2H_INT_PORT_ENUM BIT(5) 54 /* Bits 6-10 are reserved */ 55 #define D2H_INT_SUSPEND_ACK BIT(11) 56 #define D2H_INT_RESUME_ACK BIT(12) 57 #define D2H_INT_SUSPEND_ACK_AP BIT(13) 58 #define D2H_INT_RESUME_ACK_AP BIT(14) 59 #define D2H_INT_ASYNC_AP_HK BIT(15) 60 #define D2H_INT_ASYNC_MD_HK BIT(16) 61 62 /* Register base */ 63 #define INFRACFG_AO_DEV_CHIP 0x10001000 64 65 /* ATR setting */ 66 #define T7XX_PCIE_REG_TRSL_ADDR_CHIP 0x10000000 67 #define T7XX_PCIE_REG_SIZE_CHIP 0x00400000 68 69 /* Reset Generic Unit (RGU) */ 70 #define TOPRGU_CH_PCIE_IRQ_STA 0x1000790c 71 72 #define ATR_PORT_OFFSET 0x100 73 #define ATR_TABLE_OFFSET 0x20 74 #define ATR_TABLE_NUM_PER_ATR 8 75 #define ATR_TRANSPARENT_SIZE 0x3f 76 77 /* PCIE_MAC_IREG Register Definition */ 78 79 #define ISTAT_HST_CTRL 0x01ac 80 #define ISTAT_HST_CTRL_DIS BIT(0) 81 82 #define T7XX_PCIE_MISC_CTRL 0x0348 83 #define T7XX_PCIE_MISC_MAC_SLEEP_DIS BIT(7) 84 85 #define T7XX_PCIE_CFG_MSIX 0x03ec 86 #define ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR 0x0600 87 #define ATR_PCIE_WIN0_T0_TRSL_ADDR 0x0608 88 #define ATR_PCIE_WIN0_T0_TRSL_PARAM 0x0610 89 #define ATR_PCIE_WIN0_ADDR_ALGMT GENMASK_ULL(63, 12) 90 91 #define ATR_SRC_ADDR_INVALID 0x007f 92 93 #define T7XX_PCIE_PM_RESUME_STATE 0x0d0c 94 95 enum t7xx_pm_resume_state { 96 PM_RESUME_REG_STATE_L3, 97 PM_RESUME_REG_STATE_L1, 98 PM_RESUME_REG_STATE_INIT, 99 PM_RESUME_REG_STATE_EXP, 100 PM_RESUME_REG_STATE_L2, 101 PM_RESUME_REG_STATE_L2_EXP, 102 }; 103 104 enum host_event_e { 105 HOST_EVENT_INIT = 0, 106 FASTBOOT_DL_NOTIFY = 0x3, 107 }; 108 109 #define T7XX_PCIE_MISC_DEV_STATUS 0x0d1c 110 #define MISC_STAGE_MASK GENMASK(2, 0) 111 #define MISC_RESET_TYPE_PLDR BIT(26) 112 #define MISC_RESET_TYPE_FLDR BIT(27) 113 #define MISC_RESET_TYPE_PLDR BIT(26) 114 #define MISC_LK_EVENT_MASK GENMASK(11, 8) 115 #define HOST_EVENT_MASK GENMASK(31, 28) 116 117 enum lk_event_id { 118 LK_EVENT_NORMAL = 0, 119 LK_EVENT_CREATE_PD_PORT = 1, 120 LK_EVENT_CREATE_POST_DL_PORT = 2, 121 LK_EVENT_RESET = 7, 122 }; 123 124 enum t7xx_device_stage { 125 T7XX_DEV_STAGE_INIT = 0, 126 T7XX_DEV_STAGE_BROM_PRE = 1, 127 T7XX_DEV_STAGE_BROM_POST = 2, 128 T7XX_DEV_STAGE_LK = 3, 129 T7XX_DEV_STAGE_LINUX = 4, 130 }; 131 132 #define T7XX_PCIE_RESOURCE_STATUS 0x0d28 133 #define T7XX_PCIE_RESOURCE_STS_MSK GENMASK(4, 0) 134 135 #define DISABLE_ASPM_LOWPWR 0x0e50 136 #define ENABLE_ASPM_LOWPWR 0x0e54 137 #define T7XX_L1_BIT(i) BIT((i) * 4 + 1) 138 #define T7XX_L1_1_BIT(i) BIT((i) * 4 + 2) 139 #define T7XX_L1_2_BIT(i) BIT((i) * 4 + 3) 140 141 #define MSIX_ISTAT_HST_GRP0_0 0x0f00 142 #define IMASK_HOST_MSIX_SET_GRP0_0 0x3000 143 #define IMASK_HOST_MSIX_CLR_GRP0_0 0x3080 144 #define EXT_INT_START 24 145 #define EXT_INT_NUM 8 146 #define MSIX_MSK_SET_ALL GENMASK(31, 24) 147 148 enum t7xx_int { 149 DPMAIF_INT, 150 CLDMA0_INT, 151 CLDMA1_INT, 152 CLDMA2_INT, 153 MHCCIF_INT, 154 DPMAIF2_INT, 155 SAP_RGU_INT, 156 CLDMA3_INT, 157 }; 158 159 /* DPMA definitions */ 160 161 #define DPMAIF_PD_BASE 0x1022d000 162 #define BASE_DPMAIF_UL DPMAIF_PD_BASE 163 #define BASE_DPMAIF_DL (DPMAIF_PD_BASE + 0x100) 164 #define BASE_DPMAIF_AP_MISC (DPMAIF_PD_BASE + 0x400) 165 #define BASE_DPMAIF_MMW_HPC (DPMAIF_PD_BASE + 0x600) 166 #define BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX (DPMAIF_PD_BASE + 0x900) 167 #define BASE_DPMAIF_PD_SRAM_DL (DPMAIF_PD_BASE + 0xc00) 168 #define BASE_DPMAIF_PD_SRAM_UL (DPMAIF_PD_BASE + 0xd00) 169 170 #define DPMAIF_AO_BASE 0x10014000 171 #define BASE_DPMAIF_AO_UL DPMAIF_AO_BASE 172 #define BASE_DPMAIF_AO_DL (DPMAIF_AO_BASE + 0x400) 173 174 #define DPMAIF_UL_ADD_DESC (BASE_DPMAIF_UL + 0x00) 175 #define DPMAIF_UL_CHK_BUSY (BASE_DPMAIF_UL + 0x88) 176 #define DPMAIF_UL_RESERVE_AO_RW (BASE_DPMAIF_UL + 0xac) 177 #define DPMAIF_UL_ADD_DESC_CH0 (BASE_DPMAIF_UL + 0xb0) 178 179 #define DPMAIF_DL_BAT_INIT (BASE_DPMAIF_DL + 0x00) 180 #define DPMAIF_DL_BAT_ADD (BASE_DPMAIF_DL + 0x04) 181 #define DPMAIF_DL_BAT_INIT_CON0 (BASE_DPMAIF_DL + 0x08) 182 #define DPMAIF_DL_BAT_INIT_CON1 (BASE_DPMAIF_DL + 0x0c) 183 #define DPMAIF_DL_BAT_INIT_CON2 (BASE_DPMAIF_DL + 0x10) 184 #define DPMAIF_DL_BAT_INIT_CON3 (BASE_DPMAIF_DL + 0x50) 185 #define DPMAIF_DL_CHK_BUSY (BASE_DPMAIF_DL + 0xb4) 186 187 #define DPMAIF_AP_L2TISAR0 (BASE_DPMAIF_AP_MISC + 0x00) 188 #define DPMAIF_AP_APDL_L2TISAR0 (BASE_DPMAIF_AP_MISC + 0x50) 189 #define DPMAIF_AP_IP_BUSY (BASE_DPMAIF_AP_MISC + 0x60) 190 #define DPMAIF_AP_CG_EN (BASE_DPMAIF_AP_MISC + 0x68) 191 #define DPMAIF_AP_OVERWRITE_CFG (BASE_DPMAIF_AP_MISC + 0x90) 192 #define DPMAIF_AP_MEM_CLR (BASE_DPMAIF_AP_MISC + 0x94) 193 #define DPMAIF_AP_ALL_L2TISAR0_MASK GENMASK(31, 0) 194 #define DPMAIF_AP_APDL_ALL_L2TISAR0_MASK GENMASK(31, 0) 195 #define DPMAIF_AP_IP_BUSY_MASK GENMASK(31, 0) 196 197 #define DPMAIF_AO_UL_INIT_SET (BASE_DPMAIF_AO_UL + 0x0) 198 #define DPMAIF_AO_UL_CHNL_ARB0 (BASE_DPMAIF_AO_UL + 0x1c) 199 #define DPMAIF_AO_UL_AP_L2TIMR0 (BASE_DPMAIF_AO_UL + 0x80) 200 #define DPMAIF_AO_UL_AP_L2TIMCR0 (BASE_DPMAIF_AO_UL + 0x84) 201 #define DPMAIF_AO_UL_AP_L2TIMSR0 (BASE_DPMAIF_AO_UL + 0x88) 202 #define DPMAIF_AO_UL_AP_L1TIMR0 (BASE_DPMAIF_AO_UL + 0x8c) 203 #define DPMAIF_AO_UL_APDL_L2TIMR0 (BASE_DPMAIF_AO_UL + 0x90) 204 #define DPMAIF_AO_UL_APDL_L2TIMCR0 (BASE_DPMAIF_AO_UL + 0x94) 205 #define DPMAIF_AO_UL_APDL_L2TIMSR0 (BASE_DPMAIF_AO_UL + 0x98) 206 #define DPMAIF_AO_AP_DLUL_IP_BUSY_MASK (BASE_DPMAIF_AO_UL + 0x9c) 207 208 #define DPMAIF_AO_UL_CHNL0_CON0 (BASE_DPMAIF_PD_SRAM_UL + 0x10) 209 #define DPMAIF_AO_UL_CHNL0_CON1 (BASE_DPMAIF_PD_SRAM_UL + 0x14) 210 #define DPMAIF_AO_UL_CHNL0_CON2 (BASE_DPMAIF_PD_SRAM_UL + 0x18) 211 #define DPMAIF_AO_UL_CH0_STA (BASE_DPMAIF_PD_SRAM_UL + 0x70) 212 213 #define DPMAIF_AO_DL_INIT_SET (BASE_DPMAIF_AO_DL + 0x00) 214 #define DPMAIF_AO_DL_IRQ_MASK (BASE_DPMAIF_AO_DL + 0x0c) 215 #define DPMAIF_AO_DL_DLQPIT_INIT_CON5 (BASE_DPMAIF_AO_DL + 0x28) 216 #define DPMAIF_AO_DL_DLQPIT_TRIG_THRES (BASE_DPMAIF_AO_DL + 0x34) 217 218 #define DPMAIF_AO_DL_PKTINFO_CON0 (BASE_DPMAIF_PD_SRAM_DL + 0x00) 219 #define DPMAIF_AO_DL_PKTINFO_CON1 (BASE_DPMAIF_PD_SRAM_DL + 0x04) 220 #define DPMAIF_AO_DL_PKTINFO_CON2 (BASE_DPMAIF_PD_SRAM_DL + 0x08) 221 #define DPMAIF_AO_DL_RDY_CHK_THRES (BASE_DPMAIF_PD_SRAM_DL + 0x0c) 222 #define DPMAIF_AO_DL_RDY_CHK_FRG_THRES (BASE_DPMAIF_PD_SRAM_DL + 0x10) 223 224 #define DPMAIF_AO_DL_DLQ_AGG_CFG (BASE_DPMAIF_PD_SRAM_DL + 0x20) 225 #define DPMAIF_AO_DL_DLQPIT_TIMEOUT0 (BASE_DPMAIF_PD_SRAM_DL + 0x24) 226 #define DPMAIF_AO_DL_DLQPIT_TIMEOUT1 (BASE_DPMAIF_PD_SRAM_DL + 0x28) 227 #define DPMAIF_AO_DL_HPC_CNTL (BASE_DPMAIF_PD_SRAM_DL + 0x38) 228 #define DPMAIF_AO_DL_PIT_SEQ_END (BASE_DPMAIF_PD_SRAM_DL + 0x40) 229 230 #define DPMAIF_AO_DL_BAT_RD_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xd8) 231 #define DPMAIF_AO_DL_BAT_WR_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xdc) 232 #define DPMAIF_AO_DL_PIT_RD_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xec) 233 #define DPMAIF_AO_DL_PIT_WR_IDX (BASE_DPMAIF_PD_SRAM_DL + 0x60) 234 #define DPMAIF_AO_DL_FRGBAT_RD_IDX (BASE_DPMAIF_PD_SRAM_DL + 0x78) 235 #define DPMAIF_AO_DL_DLQ_WR_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xa4) 236 237 #define DPMAIF_HPC_INTR_MASK (BASE_DPMAIF_MMW_HPC + 0x0f4) 238 #define DPMA_HPC_ALL_INT_MASK GENMASK(15, 0) 239 240 #define DPMAIF_HPC_DLQ_PATH_MODE 3 241 #define DPMAIF_HPC_ADD_MODE_DF 0 242 #define DPMAIF_HPC_TOTAL_NUM 8 243 #define DPMAIF_HPC_MAX_TOTAL_NUM 8 244 245 #define DPMAIF_DL_DLQPIT_INIT (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x00) 246 #define DPMAIF_DL_DLQPIT_ADD (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x10) 247 #define DPMAIF_DL_DLQPIT_INIT_CON0 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x14) 248 #define DPMAIF_DL_DLQPIT_INIT_CON1 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x18) 249 #define DPMAIF_DL_DLQPIT_INIT_CON2 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x1c) 250 #define DPMAIF_DL_DLQPIT_INIT_CON3 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x20) 251 #define DPMAIF_DL_DLQPIT_INIT_CON4 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x24) 252 #define DPMAIF_DL_DLQPIT_INIT_CON5 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x28) 253 #define DPMAIF_DL_DLQPIT_INIT_CON6 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x2c) 254 255 #define DPMAIF_ULQSAR_n(q) (DPMAIF_AO_UL_CHNL0_CON0 + 0x10 * (q)) 256 #define DPMAIF_UL_DRBSIZE_ADDRH_n(q) (DPMAIF_AO_UL_CHNL0_CON1 + 0x10 * (q)) 257 #define DPMAIF_UL_DRB_ADDRH_n(q) (DPMAIF_AO_UL_CHNL0_CON2 + 0x10 * (q)) 258 #define DPMAIF_ULQ_STA0_n(q) (DPMAIF_AO_UL_CH0_STA + 0x04 * (q)) 259 #define DPMAIF_ULQ_ADD_DESC_CH_n(q) (DPMAIF_UL_ADD_DESC_CH0 + 0x04 * (q)) 260 261 #define DPMAIF_UL_DRB_RIDX_MSK GENMASK(31, 16) 262 263 #define DPMAIF_AP_RGU_ASSERT 0x10001150 264 #define DPMAIF_AP_RGU_DEASSERT 0x10001154 265 #define DPMAIF_AP_RST_BIT BIT(2) 266 267 #define DPMAIF_AP_AO_RGU_ASSERT 0x10001140 268 #define DPMAIF_AP_AO_RGU_DEASSERT 0x10001144 269 #define DPMAIF_AP_AO_RST_BIT BIT(6) 270 271 /* DPMAIF init/restore */ 272 #define DPMAIF_UL_ADD_NOT_READY BIT(31) 273 #define DPMAIF_UL_ADD_UPDATE BIT(31) 274 #define DPMAIF_UL_ADD_COUNT_MASK GENMASK(15, 0) 275 #define DPMAIF_UL_ALL_QUE_ARB_EN GENMASK(11, 8) 276 277 #define DPMAIF_DL_ADD_UPDATE BIT(31) 278 #define DPMAIF_DL_ADD_NOT_READY BIT(31) 279 #define DPMAIF_DL_FRG_ADD_UPDATE BIT(16) 280 #define DPMAIF_DL_ADD_COUNT_MASK GENMASK(15, 0) 281 282 #define DPMAIF_DL_BAT_INIT_ALLSET BIT(0) 283 #define DPMAIF_DL_BAT_FRG_INIT BIT(16) 284 #define DPMAIF_DL_BAT_INIT_EN BIT(31) 285 #define DPMAIF_DL_BAT_INIT_NOT_READY BIT(31) 286 #define DPMAIF_DL_BAT_INIT_ONLY_ENABLE_BIT 0 287 288 #define DPMAIF_DL_PIT_INIT_ALLSET BIT(0) 289 #define DPMAIF_DL_PIT_INIT_EN BIT(31) 290 #define DPMAIF_DL_PIT_INIT_NOT_READY BIT(31) 291 292 #define DPMAIF_BAT_REMAIN_SZ_BASE 16 293 #define DPMAIF_BAT_BUFFER_SZ_BASE 128 294 #define DPMAIF_FRG_BUFFER_SZ_BASE 128 295 296 #define DLQ_PIT_IDX_SIZE 0x20 297 298 #define DPMAIF_PIT_SIZE_MSK GENMASK(17, 0) 299 300 #define DPMAIF_PIT_REM_CNT_MSK GENMASK(17, 0) 301 302 #define DPMAIF_BAT_EN_MSK BIT(16) 303 #define DPMAIF_FRG_EN_MSK BIT(28) 304 #define DPMAIF_BAT_SIZE_MSK GENMASK(15, 0) 305 306 #define DPMAIF_BAT_BID_MAXCNT_MSK GENMASK(31, 16) 307 #define DPMAIF_BAT_REMAIN_MINSZ_MSK GENMASK(15, 8) 308 #define DPMAIF_PIT_CHK_NUM_MSK GENMASK(31, 24) 309 #define DPMAIF_BAT_BUF_SZ_MSK GENMASK(16, 8) 310 #define DPMAIF_FRG_BUF_SZ_MSK GENMASK(16, 8) 311 #define DPMAIF_BAT_RSV_LEN_MSK GENMASK(7, 0) 312 #define DPMAIF_PKT_ALIGN_MSK GENMASK(23, 22) 313 314 #define DPMAIF_BAT_CHECK_THRES_MSK GENMASK(21, 16) 315 #define DPMAIF_FRG_CHECK_THRES_MSK GENMASK(7, 0) 316 317 #define DPMAIF_PKT_ALIGN_EN BIT(23) 318 319 #define DPMAIF_DRB_SIZE_MSK GENMASK(15, 0) 320 321 #define DPMAIF_DL_RD_WR_IDX_MSK GENMASK(17, 0) 322 323 /* DPMAIF_UL_CHK_BUSY */ 324 #define DPMAIF_UL_IDLE_STS BIT(11) 325 /* DPMAIF_DL_CHK_BUSY */ 326 #define DPMAIF_DL_IDLE_STS BIT(23) 327 /* DPMAIF_AO_DL_RDY_CHK_THRES */ 328 #define DPMAIF_DL_PKT_CHECKSUM_EN BIT(31) 329 #define DPMAIF_PORT_MODE_PCIE BIT(30) 330 #define DPMAIF_DL_BURST_PIT_EN BIT(13) 331 /* DPMAIF_DL_BAT_INIT_CON1 */ 332 #define DPMAIF_DL_BAT_CACHE_PRI BIT(22) 333 /* DPMAIF_AP_MEM_CLR */ 334 #define DPMAIF_MEM_CLR BIT(0) 335 /* DPMAIF_AP_OVERWRITE_CFG */ 336 #define DPMAIF_SRAM_SYNC BIT(0) 337 /* DPMAIF_AO_UL_INIT_SET */ 338 #define DPMAIF_UL_INIT_DONE BIT(0) 339 /* DPMAIF_AO_DL_INIT_SET */ 340 #define DPMAIF_DL_INIT_DONE BIT(0) 341 /* DPMAIF_AO_DL_PIT_SEQ_END */ 342 #define DPMAIF_DL_PIT_SEQ_MSK GENMASK(7, 0) 343 /* DPMAIF_UL_RESERVE_AO_RW */ 344 #define DPMAIF_PCIE_MODE_SET_VALUE 0x55 345 /* DPMAIF_AP_CG_EN */ 346 #define DPMAIF_CG_EN 0x7f 347 348 #define DPMAIF_UDL_IP_BUSY BIT(0) 349 #define DPMAIF_DL_INT_DLQ0_QDONE BIT(8) 350 #define DPMAIF_DL_INT_DLQ1_QDONE BIT(9) 351 #define DPMAIF_DL_INT_DLQ0_PITCNT_LEN BIT(10) 352 #define DPMAIF_DL_INT_DLQ1_PITCNT_LEN BIT(11) 353 #define DPMAIF_DL_INT_Q2TOQ1 BIT(24) 354 #define DPMAIF_DL_INT_Q2APTOP BIT(25) 355 356 #define DPMAIF_DLQ_LOW_TIMEOUT_THRES_MKS GENMASK(15, 0) 357 #define DPMAIF_DLQ_HIGH_TIMEOUT_THRES_MSK GENMASK(31, 16) 358 359 /* DPMAIF DLQ HW configure */ 360 #define DPMAIF_AGG_MAX_LEN_DF 65535 361 #define DPMAIF_AGG_TBL_ENT_NUM_DF 50 362 #define DPMAIF_HASH_PRIME_DF 13 363 #define DPMAIF_MID_TIMEOUT_THRES_DF 100 364 #define DPMAIF_DLQ_TIMEOUT_THRES_DF 100 365 #define DPMAIF_DLQ_PRS_THRES_DF 10 366 #define DPMAIF_DLQ_HASH_BIT_CHOOSE_DF 0 367 368 #define DPMAIF_DLQPIT_EN_MSK BIT(20) 369 #define DPMAIF_DLQPIT_CHAN_OFS 16 370 #define DPMAIF_ADD_DLQ_PIT_CHAN_OFS 20 371 372 #endif /* __T7XX_REG_H__ */ 373