1*d642b012SHaijun Liu /* SPDX-License-Identifier: GPL-2.0-only 2*d642b012SHaijun Liu * 3*d642b012SHaijun Liu * Copyright (c) 2021, MediaTek Inc. 4*d642b012SHaijun Liu * Copyright (c) 2021-2022, Intel Corporation. 5*d642b012SHaijun Liu * 6*d642b012SHaijun Liu * Authors: 7*d642b012SHaijun Liu * Haijun Liu <haijun.liu@mediatek.com> 8*d642b012SHaijun Liu * Eliot Lee <eliot.lee@intel.com> 9*d642b012SHaijun Liu * Ricardo Martinez <ricardo.martinez@linux.intel.com> 10*d642b012SHaijun Liu * 11*d642b012SHaijun Liu * Contributors: 12*d642b012SHaijun Liu * Amir Hanania <amir.hanania@intel.com> 13*d642b012SHaijun Liu * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> 14*d642b012SHaijun Liu * Moises Veleta <moises.veleta@intel.com> 15*d642b012SHaijun Liu * Sreehari Kancharla <sreehari.kancharla@intel.com> 16*d642b012SHaijun Liu */ 17*d642b012SHaijun Liu 18*d642b012SHaijun Liu #ifndef __T7XX_HIF_DPMA_TX_H__ 19*d642b012SHaijun Liu #define __T7XX_HIF_DPMA_TX_H__ 20*d642b012SHaijun Liu 21*d642b012SHaijun Liu #include <linux/bits.h> 22*d642b012SHaijun Liu #include <linux/skbuff.h> 23*d642b012SHaijun Liu #include <linux/types.h> 24*d642b012SHaijun Liu 25*d642b012SHaijun Liu #include "t7xx_hif_dpmaif.h" 26*d642b012SHaijun Liu 27*d642b012SHaijun Liu #define DPMAIF_TX_DEFAULT_QUEUE 0 28*d642b012SHaijun Liu 29*d642b012SHaijun Liu struct dpmaif_drb { 30*d642b012SHaijun Liu __le32 header; 31*d642b012SHaijun Liu union { 32*d642b012SHaijun Liu struct { 33*d642b012SHaijun Liu __le32 data_addr_l; 34*d642b012SHaijun Liu __le32 data_addr_h; 35*d642b012SHaijun Liu } pd; 36*d642b012SHaijun Liu struct { 37*d642b012SHaijun Liu __le32 msg_hdr; 38*d642b012SHaijun Liu __le32 reserved1; 39*d642b012SHaijun Liu } msg; 40*d642b012SHaijun Liu }; 41*d642b012SHaijun Liu __le32 reserved2; 42*d642b012SHaijun Liu }; 43*d642b012SHaijun Liu 44*d642b012SHaijun Liu /* Header fields */ 45*d642b012SHaijun Liu #define DRB_HDR_DATA_LEN GENMASK(31, 16) 46*d642b012SHaijun Liu #define DRB_HDR_RESERVED GENMASK(15, 3) 47*d642b012SHaijun Liu #define DRB_HDR_CONT BIT(2) 48*d642b012SHaijun Liu #define DRB_HDR_DTYP GENMASK(1, 0) 49*d642b012SHaijun Liu 50*d642b012SHaijun Liu #define DRB_MSG_DW2_RES GENMASK(31, 30) 51*d642b012SHaijun Liu #define DRB_MSG_L4_CHK BIT(29) 52*d642b012SHaijun Liu #define DRB_MSG_IP_CHK BIT(28) 53*d642b012SHaijun Liu #define DRB_MSG_RESERVED BIT(27) 54*d642b012SHaijun Liu #define DRB_MSG_NETWORK_TYPE GENMASK(26, 24) 55*d642b012SHaijun Liu #define DRB_MSG_CHANNEL_ID GENMASK(23, 16) 56*d642b012SHaijun Liu #define DRB_MSG_COUNT_L GENMASK(15, 0) 57*d642b012SHaijun Liu 58*d642b012SHaijun Liu struct dpmaif_drb_skb { 59*d642b012SHaijun Liu struct sk_buff *skb; 60*d642b012SHaijun Liu dma_addr_t bus_addr; 61*d642b012SHaijun Liu unsigned int data_len; 62*d642b012SHaijun Liu u16 index:13; 63*d642b012SHaijun Liu u16 is_msg:1; 64*d642b012SHaijun Liu u16 is_frag:1; 65*d642b012SHaijun Liu u16 is_last:1; 66*d642b012SHaijun Liu }; 67*d642b012SHaijun Liu 68*d642b012SHaijun Liu int t7xx_dpmaif_tx_send_skb(struct dpmaif_ctrl *dpmaif_ctrl, unsigned int txq_number, 69*d642b012SHaijun Liu struct sk_buff *skb); 70*d642b012SHaijun Liu void t7xx_dpmaif_tx_thread_rel(struct dpmaif_ctrl *dpmaif_ctrl); 71*d642b012SHaijun Liu int t7xx_dpmaif_tx_thread_init(struct dpmaif_ctrl *dpmaif_ctrl); 72*d642b012SHaijun Liu void t7xx_dpmaif_txq_free(struct dpmaif_tx_queue *txq); 73*d642b012SHaijun Liu void t7xx_dpmaif_irq_tx_done(struct dpmaif_ctrl *dpmaif_ctrl, unsigned int que_mask); 74*d642b012SHaijun Liu int t7xx_dpmaif_txq_init(struct dpmaif_tx_queue *txq); 75*d642b012SHaijun Liu void t7xx_dpmaif_tx_stop(struct dpmaif_ctrl *dpmaif_ctrl); 76*d642b012SHaijun Liu void t7xx_dpmaif_tx_clear(struct dpmaif_ctrl *dpmaif_ctrl); 77*d642b012SHaijun Liu 78*d642b012SHaijun Liu #endif /* __T7XX_HIF_DPMA_TX_H__ */ 79