1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (c) 2021, MediaTek Inc. 4 * Copyright (c) 2021-2022, Intel Corporation. 5 * 6 * Authors: 7 * Amir Hanania <amir.hanania@intel.com> 8 * Haijun Liu <haijun.liu@mediatek.com> 9 * Moises Veleta <moises.veleta@intel.com> 10 * Ricardo Martinez <ricardo.martinez@linux.intel.com> 11 * 12 * Contributors: 13 * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> 14 * Eliot Lee <eliot.lee@intel.com> 15 * Sreehari Kancharla <sreehari.kancharla@intel.com> 16 */ 17 18 #ifndef __T7XX_DPMAIF_H__ 19 #define __T7XX_DPMAIF_H__ 20 21 #include <linux/bits.h> 22 #include <linux/types.h> 23 24 #define DPMAIF_DL_PIT_SEQ_VALUE 251 25 #define DPMAIF_UL_DRB_SIZE_WORD 4 26 27 #define DPMAIF_MAX_CHECK_COUNT 1000000 28 #define DPMAIF_CHECK_TIMEOUT_US 10000 29 #define DPMAIF_CHECK_INIT_TIMEOUT_US 100000 30 #define DPMAIF_CHECK_DELAY_US 10 31 32 #define DPMAIF_RXQ_NUM 2 33 #define DPMAIF_TXQ_NUM 5 34 35 struct dpmaif_isr_en_mask { 36 unsigned int ap_ul_l2intr_en_msk; 37 unsigned int ap_dl_l2intr_en_msk; 38 unsigned int ap_udl_ip_busy_en_msk; 39 unsigned int ap_dl_l2intr_err_en_msk; 40 }; 41 42 struct dpmaif_ul { 43 bool que_started; 44 unsigned char reserved[3]; 45 dma_addr_t drb_base; 46 unsigned int drb_size_cnt; 47 }; 48 49 struct dpmaif_dl { 50 bool que_started; 51 unsigned char reserved[3]; 52 dma_addr_t pit_base; 53 unsigned int pit_size_cnt; 54 dma_addr_t bat_base; 55 unsigned int bat_size_cnt; 56 dma_addr_t frg_base; 57 unsigned int frg_size_cnt; 58 unsigned int pit_seq; 59 }; 60 61 struct dpmaif_hw_info { 62 struct device *dev; 63 void __iomem *pcie_base; 64 struct dpmaif_dl dl_que[DPMAIF_RXQ_NUM]; 65 struct dpmaif_ul ul_que[DPMAIF_TXQ_NUM]; 66 struct dpmaif_isr_en_mask isr_en_mask; 67 }; 68 69 /* DPMAIF HW Initialization parameter structure */ 70 struct dpmaif_hw_params { 71 /* UL part */ 72 dma_addr_t drb_base_addr[DPMAIF_TXQ_NUM]; 73 unsigned int drb_size_cnt[DPMAIF_TXQ_NUM]; 74 /* DL part */ 75 dma_addr_t pkt_bat_base_addr[DPMAIF_RXQ_NUM]; 76 unsigned int pkt_bat_size_cnt[DPMAIF_RXQ_NUM]; 77 dma_addr_t frg_bat_base_addr[DPMAIF_RXQ_NUM]; 78 unsigned int frg_bat_size_cnt[DPMAIF_RXQ_NUM]; 79 dma_addr_t pit_base_addr[DPMAIF_RXQ_NUM]; 80 unsigned int pit_size_cnt[DPMAIF_RXQ_NUM]; 81 }; 82 83 enum dpmaif_hw_intr_type { 84 DPF_INTR_INVALID_MIN, 85 DPF_INTR_UL_DONE, 86 DPF_INTR_UL_DRB_EMPTY, 87 DPF_INTR_UL_MD_NOTREADY, 88 DPF_INTR_UL_MD_PWR_NOTREADY, 89 DPF_INTR_UL_LEN_ERR, 90 DPF_INTR_DL_DONE, 91 DPF_INTR_DL_SKB_LEN_ERR, 92 DPF_INTR_DL_BATCNT_LEN_ERR, 93 DPF_INTR_DL_PITCNT_LEN_ERR, 94 DPF_INTR_DL_PKT_EMPTY_SET, 95 DPF_INTR_DL_FRG_EMPTY_SET, 96 DPF_INTR_DL_MTU_ERR, 97 DPF_INTR_DL_FRGCNT_LEN_ERR, 98 DPF_INTR_DL_Q0_PITCNT_LEN_ERR, 99 DPF_INTR_DL_Q1_PITCNT_LEN_ERR, 100 DPF_INTR_DL_HPC_ENT_TYPE_ERR, 101 DPF_INTR_DL_Q0_DONE, 102 DPF_INTR_DL_Q1_DONE, 103 DPF_INTR_INVALID_MAX 104 }; 105 106 #define DPF_RX_QNO0 0 107 #define DPF_RX_QNO1 1 108 #define DPF_RX_QNO_DFT DPF_RX_QNO0 109 110 struct dpmaif_hw_intr_st_para { 111 unsigned int intr_cnt; 112 enum dpmaif_hw_intr_type intr_types[DPF_INTR_INVALID_MAX - 1]; 113 unsigned int intr_queues[DPF_INTR_INVALID_MAX - 1]; 114 }; 115 116 #define DPMAIF_HW_BAT_REMAIN 64 117 #define DPMAIF_HW_BAT_PKTBUF (128 * 28) 118 #define DPMAIF_HW_FRG_PKTBUF 128 119 #define DPMAIF_HW_BAT_RSVLEN 64 120 #define DPMAIF_HW_PKT_BIDCNT 1 121 #define DPMAIF_HW_MTU_SIZE (3 * 1024 + 8) 122 #define DPMAIF_HW_CHK_BAT_NUM 62 123 #define DPMAIF_HW_CHK_FRG_NUM 3 124 #define DPMAIF_HW_CHK_PIT_NUM (2 * DPMAIF_HW_CHK_BAT_NUM) 125 126 #define DP_UL_INT_DONE_OFFSET 0 127 #define DP_UL_INT_QDONE_MSK GENMASK(4, 0) 128 #define DP_UL_INT_EMPTY_MSK GENMASK(9, 5) 129 #define DP_UL_INT_MD_NOTREADY_MSK GENMASK(14, 10) 130 #define DP_UL_INT_MD_PWR_NOTREADY_MSK GENMASK(19, 15) 131 #define DP_UL_INT_ERR_MSK GENMASK(24, 20) 132 133 #define DP_DL_INT_QDONE_MSK BIT(0) 134 #define DP_DL_INT_SKB_LEN_ERR BIT(1) 135 #define DP_DL_INT_BATCNT_LEN_ERR BIT(2) 136 #define DP_DL_INT_PITCNT_LEN_ERR BIT(3) 137 #define DP_DL_INT_PKT_EMPTY_MSK BIT(4) 138 #define DP_DL_INT_FRG_EMPTY_MSK BIT(5) 139 #define DP_DL_INT_MTU_ERR_MSK BIT(6) 140 #define DP_DL_INT_FRG_LEN_ERR_MSK BIT(7) 141 #define DP_DL_INT_Q0_PITCNT_LEN_ERR BIT(8) 142 #define DP_DL_INT_Q1_PITCNT_LEN_ERR BIT(9) 143 #define DP_DL_INT_HPC_ENT_TYPE_ERR BIT(10) 144 #define DP_DL_INT_Q0_DONE BIT(13) 145 #define DP_DL_INT_Q1_DONE BIT(14) 146 147 #define DP_DL_Q0_STATUS_MASK (DP_DL_INT_Q0_PITCNT_LEN_ERR | DP_DL_INT_Q0_DONE) 148 #define DP_DL_Q1_STATUS_MASK (DP_DL_INT_Q1_PITCNT_LEN_ERR | DP_DL_INT_Q1_DONE) 149 150 int t7xx_dpmaif_hw_init(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_params *init_param); 151 int t7xx_dpmaif_hw_stop_all_txq(struct dpmaif_hw_info *hw_info); 152 int t7xx_dpmaif_hw_stop_all_rxq(struct dpmaif_hw_info *hw_info); 153 void t7xx_dpmaif_start_hw(struct dpmaif_hw_info *hw_info); 154 int t7xx_dpmaif_hw_get_intr_cnt(struct dpmaif_hw_info *hw_info, 155 struct dpmaif_hw_intr_st_para *para, int qno); 156 void t7xx_dpmaif_unmask_ulq_intr(struct dpmaif_hw_info *hw_info, unsigned int q_num); 157 void t7xx_dpmaif_ul_update_hw_drb_cnt(struct dpmaif_hw_info *hw_info, unsigned int q_num, 158 unsigned int drb_entry_cnt); 159 int t7xx_dpmaif_dl_snd_hw_bat_cnt(struct dpmaif_hw_info *hw_info, unsigned int bat_entry_cnt); 160 int t7xx_dpmaif_dl_snd_hw_frg_cnt(struct dpmaif_hw_info *hw_info, unsigned int frg_entry_cnt); 161 int t7xx_dpmaif_dlq_add_pit_remain_cnt(struct dpmaif_hw_info *hw_info, unsigned int dlq_pit_idx, 162 unsigned int pit_remain_cnt); 163 void t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info, 164 unsigned int qno); 165 void t7xx_dpmaif_dlq_unmask_rx_done(struct dpmaif_hw_info *hw_info, unsigned int qno); 166 bool t7xx_dpmaif_ul_clr_done(struct dpmaif_hw_info *hw_info, unsigned int qno); 167 void t7xx_dpmaif_ul_clr_all_intr(struct dpmaif_hw_info *hw_info); 168 void t7xx_dpmaif_dl_clr_all_intr(struct dpmaif_hw_info *hw_info); 169 void t7xx_dpmaif_clr_ip_busy_sts(struct dpmaif_hw_info *hw_info); 170 void t7xx_dpmaif_dl_unmask_batcnt_len_err_intr(struct dpmaif_hw_info *hw_info); 171 void t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info); 172 unsigned int t7xx_dpmaif_ul_get_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num); 173 unsigned int t7xx_dpmaif_dl_get_bat_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num); 174 unsigned int t7xx_dpmaif_dl_get_bat_wr_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num); 175 unsigned int t7xx_dpmaif_dl_get_frg_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num); 176 unsigned int t7xx_dpmaif_dl_dlq_pit_get_wr_idx(struct dpmaif_hw_info *hw_info, 177 unsigned int dlq_pit_idx); 178 179 #endif /* __T7XX_DPMAIF_H__ */ 180