1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/device.h> 8 #include <linux/io.h> 9 #include <linux/io-64-nonatomic-lo-hi.h> 10 #include <linux/slab.h> 11 12 #include "iosm_ipc_mmio.h" 13 #include "iosm_ipc_mux.h" 14 15 /* Definition of MMIO offsets 16 * note that MMIO_CI offsets are relative to end of chip info structure 17 */ 18 19 /* MMIO chip info size in bytes */ 20 #define MMIO_CHIP_INFO_SIZE 60 21 22 /* CP execution stage */ 23 #define MMIO_OFFSET_EXECUTION_STAGE 0x00 24 25 /* Boot ROM Chip Info struct */ 26 #define MMIO_OFFSET_CHIP_INFO 0x04 27 28 #define MMIO_OFFSET_ROM_EXIT_CODE 0x40 29 30 #define MMIO_OFFSET_PSI_ADDRESS 0x54 31 32 #define MMIO_OFFSET_PSI_SIZE 0x5C 33 34 #define MMIO_OFFSET_IPC_STATUS 0x60 35 36 #define MMIO_OFFSET_CONTEXT_INFO 0x64 37 38 #define MMIO_OFFSET_BASE_ADDR 0x6C 39 40 #define MMIO_OFFSET_END_ADDR 0x74 41 42 #define MMIO_OFFSET_CP_VERSION 0xF0 43 44 #define MMIO_OFFSET_CP_CAPABILITIES 0xF4 45 46 /* Timeout in 50 msec to wait for the modem boot code to write a valid 47 * execution stage into mmio area 48 */ 49 #define IPC_MMIO_EXEC_STAGE_TIMEOUT 50 50 51 /* check if exec stage has one of the valid values */ 52 static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage) 53 { 54 switch (stage) { 55 case IPC_MEM_EXEC_STAGE_BOOT: 56 case IPC_MEM_EXEC_STAGE_PSI: 57 case IPC_MEM_EXEC_STAGE_EBL: 58 case IPC_MEM_EXEC_STAGE_RUN: 59 case IPC_MEM_EXEC_STAGE_CRASH: 60 case IPC_MEM_EXEC_STAGE_CD_READY: 61 return true; 62 default: 63 return false; 64 } 65 } 66 67 void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio) 68 { 69 u32 cp_cap; 70 unsigned int ver; 71 72 ver = ipc_mmio_get_cp_version(ipc_mmio); 73 cp_cap = ioread32(ipc_mmio->base + ipc_mmio->offset.cp_capability); 74 75 ipc_mmio->mux_protocol = ((ver >= IOSM_CP_VERSION) && (cp_cap & 76 (UL_AGGR | DL_AGGR))) ? MUX_AGGREGATION 77 : MUX_LITE; 78 79 ipc_mmio->has_ul_flow_credit = 80 (ver >= IOSM_CP_VERSION) && (cp_cap & UL_FLOW_CREDIT); 81 } 82 83 struct iosm_mmio *ipc_mmio_init(void __iomem *mmio, struct device *dev) 84 { 85 struct iosm_mmio *ipc_mmio = kzalloc(sizeof(*ipc_mmio), GFP_KERNEL); 86 int retries = IPC_MMIO_EXEC_STAGE_TIMEOUT; 87 enum ipc_mem_exec_stage stage; 88 89 if (!ipc_mmio) 90 return NULL; 91 92 ipc_mmio->dev = dev; 93 94 ipc_mmio->base = mmio; 95 96 ipc_mmio->offset.exec_stage = MMIO_OFFSET_EXECUTION_STAGE; 97 98 /* Check for a valid execution stage to make sure that the boot code 99 * has correctly initialized the MMIO area. 100 */ 101 do { 102 stage = ipc_mmio_get_exec_stage(ipc_mmio); 103 if (ipc_mmio_is_valid_exec_stage(stage)) 104 break; 105 106 msleep(20); 107 } while (retries-- > 0); 108 109 if (!retries) { 110 dev_err(ipc_mmio->dev, "invalid exec stage %X", stage); 111 goto init_fail; 112 } 113 114 ipc_mmio->offset.chip_info = MMIO_OFFSET_CHIP_INFO; 115 116 /* read chip info size and version from chip info structure */ 117 ipc_mmio->chip_info_version = 118 ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info); 119 120 /* Increment of 2 is needed as the size value in the chip info 121 * excludes the version and size field, which are always present 122 */ 123 ipc_mmio->chip_info_size = 124 ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info + 1) + 2; 125 126 if (ipc_mmio->chip_info_size != MMIO_CHIP_INFO_SIZE) { 127 dev_err(ipc_mmio->dev, "Unexpected Chip Info"); 128 goto init_fail; 129 } 130 131 ipc_mmio->offset.rom_exit_code = MMIO_OFFSET_ROM_EXIT_CODE; 132 133 ipc_mmio->offset.psi_address = MMIO_OFFSET_PSI_ADDRESS; 134 ipc_mmio->offset.psi_size = MMIO_OFFSET_PSI_SIZE; 135 ipc_mmio->offset.ipc_status = MMIO_OFFSET_IPC_STATUS; 136 ipc_mmio->offset.context_info = MMIO_OFFSET_CONTEXT_INFO; 137 ipc_mmio->offset.ap_win_base = MMIO_OFFSET_BASE_ADDR; 138 ipc_mmio->offset.ap_win_end = MMIO_OFFSET_END_ADDR; 139 140 ipc_mmio->offset.cp_version = MMIO_OFFSET_CP_VERSION; 141 ipc_mmio->offset.cp_capability = MMIO_OFFSET_CP_CAPABILITIES; 142 143 return ipc_mmio; 144 145 init_fail: 146 kfree(ipc_mmio); 147 return NULL; 148 } 149 150 enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio) 151 { 152 if (!ipc_mmio) 153 return IPC_MEM_EXEC_STAGE_INVALID; 154 155 return (enum ipc_mem_exec_stage)ioread32(ipc_mmio->base + 156 ipc_mmio->offset.exec_stage); 157 } 158 159 void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest, 160 size_t size) 161 { 162 if (ipc_mmio && dest) 163 memcpy_fromio(dest, ipc_mmio->base + ipc_mmio->offset.chip_info, 164 size); 165 } 166 167 enum ipc_mem_device_ipc_state ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio) 168 { 169 if (!ipc_mmio) 170 return IPC_MEM_DEVICE_IPC_INVALID; 171 172 return (enum ipc_mem_device_ipc_state)ioread32(ipc_mmio->base + 173 ipc_mmio->offset.ipc_status); 174 } 175 176 enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio) 177 { 178 if (!ipc_mmio) 179 return IMEM_ROM_EXIT_FAIL; 180 181 return (enum rom_exit_code)ioread32(ipc_mmio->base + 182 ipc_mmio->offset.rom_exit_code); 183 } 184 185 void ipc_mmio_config(struct iosm_mmio *ipc_mmio) 186 { 187 if (!ipc_mmio) 188 return; 189 190 /* AP memory window (full window is open and active so that modem checks 191 * each AP address) 0 means don't check on modem side. 192 */ 193 iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_base); 194 iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_end); 195 196 iowrite64(ipc_mmio->context_info_addr, 197 ipc_mmio->base + ipc_mmio->offset.context_info); 198 } 199 200 void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr, 201 u32 size) 202 { 203 if (!ipc_mmio) 204 return; 205 206 iowrite64(addr, ipc_mmio->base + ipc_mmio->offset.psi_address); 207 iowrite32(size, ipc_mmio->base + ipc_mmio->offset.psi_size); 208 } 209 210 void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, phys_addr_t addr) 211 { 212 if (!ipc_mmio) 213 return; 214 215 /* store context_info address. This will be stored in the mmio area 216 * during IPC_MEM_DEVICE_IPC_INIT state via ipc_mmio_config() 217 */ 218 ipc_mmio->context_info_addr = addr; 219 } 220 221 int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio) 222 { 223 if (ipc_mmio) 224 return ioread32(ipc_mmio->base + ipc_mmio->offset.cp_version); 225 226 return -EFAULT; 227 } 228