1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #ifndef IOSM_IPC_IMEM_H 7 #define IOSM_IPC_IMEM_H 8 9 #include <linux/skbuff.h> 10 11 #include "iosm_ipc_mmio.h" 12 #include "iosm_ipc_pcie.h" 13 #include "iosm_ipc_uevent.h" 14 #include "iosm_ipc_wwan.h" 15 #include "iosm_ipc_task_queue.h" 16 17 struct ipc_chnl_cfg; 18 19 /* IRQ moderation in usec */ 20 #define IRQ_MOD_OFF 0 21 #define IRQ_MOD_NET 1000 22 #define IRQ_MOD_TRC 4000 23 24 /* Either the PSI image is accepted by CP or the suspended flash tool is waken, 25 * informed that the CP ROM driver is not ready to process the PSI image. 26 * unit : milliseconds 27 */ 28 #define IPC_PSI_TRANSFER_TIMEOUT 3000 29 30 /* Timeout in 20 msec to wait for the modem to boot up to 31 * IPC_MEM_DEVICE_IPC_INIT state. 32 * unit : milliseconds (500 * ipc_util_msleep(20)) 33 */ 34 #define IPC_MODEM_BOOT_TIMEOUT 500 35 36 /* Wait timeout for ipc status reflects IPC_MEM_DEVICE_IPC_UNINIT 37 * unit : milliseconds 38 */ 39 #define IPC_MODEM_UNINIT_TIMEOUT_MS 30 40 41 /* Pending time for processing data. 42 * unit : milliseconds 43 */ 44 #define IPC_PEND_DATA_TIMEOUT 500 45 46 /* The timeout in milliseconds for application to wait for remote time. */ 47 #define IPC_REMOTE_TS_TIMEOUT_MS 10 48 49 /* Timeout for TD allocation retry. 50 * unit : milliseconds 51 */ 52 #define IPC_TD_ALLOC_TIMER_PERIOD_MS 100 53 54 /* Host sleep target is host */ 55 #define IPC_HOST_SLEEP_HOST 0 56 57 /* Host sleep target is device */ 58 #define IPC_HOST_SLEEP_DEVICE 1 59 60 /* Sleep message, target host: AP enters sleep / target device: CP is 61 * allowed to enter sleep and shall use the host sleep protocol 62 */ 63 #define IPC_HOST_SLEEP_ENTER_SLEEP 0 64 65 /* Sleep_message, target host: AP exits sleep / target device: CP is 66 * NOT allowed to enter sleep 67 */ 68 #define IPC_HOST_SLEEP_EXIT_SLEEP 1 69 70 #define IMEM_IRQ_DONT_CARE (-1) 71 72 #define IPC_MEM_MAX_CHANNELS 8 73 74 #define IPC_MEM_MUX_IP_SESSION_ENTRIES 8 75 76 #define IPC_MEM_MUX_IP_CH_IF_ID 0 77 78 #define TD_UPDATE_DEFAULT_TIMEOUT_USEC 1900 79 80 #define FORCE_UPDATE_DEFAULT_TIMEOUT_USEC 500 81 82 /* Sleep_message, target host: not applicable / target device: CP is 83 * allowed to enter sleep and shall NOT use the device sleep protocol 84 */ 85 #define IPC_HOST_SLEEP_ENTER_SLEEP_NO_PROTOCOL 2 86 87 /* in_band_crash_signal IPC_MEM_INBAND_CRASH_SIG 88 * Modem crash notification configuration. If this value is non-zero then 89 * FEATURE_SET message will be sent to the Modem as a result the Modem will 90 * signal Crash via Execution Stage register. If this value is zero then Modem 91 * will use out-of-band method to notify about it's Crash. 92 */ 93 #define IPC_MEM_INBAND_CRASH_SIG 1 94 95 /* Extra headroom to be allocated for DL SKBs to allow addition of Ethernet 96 * header 97 */ 98 #define IPC_MEM_DL_ETH_OFFSET 16 99 100 #define IPC_CB(skb) ((struct ipc_skb_cb *)((skb)->cb)) 101 #define IOSM_CHIP_INFO_SIZE_MAX 100 102 103 #define FULLY_FUNCTIONAL 0 104 #define IOSM_DEVLINK_INIT 1 105 106 /* List of the supported UL/DL pipes. */ 107 enum ipc_mem_pipes { 108 IPC_MEM_PIPE_0 = 0, 109 IPC_MEM_PIPE_1, 110 IPC_MEM_PIPE_2, 111 IPC_MEM_PIPE_3, 112 IPC_MEM_PIPE_4, 113 IPC_MEM_PIPE_5, 114 IPC_MEM_PIPE_6, 115 IPC_MEM_PIPE_7, 116 IPC_MEM_PIPE_8, 117 IPC_MEM_PIPE_9, 118 IPC_MEM_PIPE_10, 119 IPC_MEM_PIPE_11, 120 IPC_MEM_PIPE_12, 121 IPC_MEM_PIPE_13, 122 IPC_MEM_PIPE_14, 123 IPC_MEM_PIPE_15, 124 IPC_MEM_PIPE_16, 125 IPC_MEM_PIPE_17, 126 IPC_MEM_PIPE_18, 127 IPC_MEM_PIPE_19, 128 IPC_MEM_PIPE_20, 129 IPC_MEM_PIPE_21, 130 IPC_MEM_PIPE_22, 131 IPC_MEM_PIPE_23, 132 IPC_MEM_MAX_PIPES 133 }; 134 135 /* Enum defining channel states. */ 136 enum ipc_channel_state { 137 IMEM_CHANNEL_FREE, 138 IMEM_CHANNEL_RESERVED, 139 IMEM_CHANNEL_ACTIVE, 140 IMEM_CHANNEL_CLOSING, 141 }; 142 143 /** 144 * enum ipc_ctype - Enum defining supported channel type needed for control 145 * /IP traffic. 146 * @IPC_CTYPE_WWAN: Used for IP traffic 147 * @IPC_CTYPE_CTRL: Used for Control Communication 148 */ 149 enum ipc_ctype { 150 IPC_CTYPE_WWAN, 151 IPC_CTYPE_CTRL, 152 }; 153 154 /* Pipe direction. */ 155 enum ipc_mem_pipe_dir { 156 IPC_MEM_DIR_UL, 157 IPC_MEM_DIR_DL, 158 }; 159 160 /* HP update identifier. To be used as data for ipc_cp_irq_hpda_update() */ 161 enum ipc_hp_identifier { 162 IPC_HP_MR = 0, 163 IPC_HP_PM_TRIGGER, 164 IPC_HP_WAKEUP_SPEC_TMR, 165 IPC_HP_TD_UPD_TMR_START, 166 IPC_HP_TD_UPD_TMR, 167 IPC_HP_FAST_TD_UPD_TMR, 168 IPC_HP_UL_WRITE_TD, 169 IPC_HP_DL_PROCESS, 170 IPC_HP_NET_CHANNEL_INIT, 171 IPC_HP_CDEV_OPEN, 172 }; 173 174 /** 175 * struct ipc_pipe - Structure for Pipe. 176 * @tdr_start: Ipc private protocol Transfer Descriptor Ring 177 * @channel: Id of the sio device, set by imem_sio_open, 178 * needed to pass DL char to the user terminal 179 * @skbr_start: Circular buffer for skbuf and the buffer 180 * reference in a tdr_start entry. 181 * @phy_tdr_start: Transfer descriptor start address 182 * @old_head: last head pointer reported to CP. 183 * @old_tail: AP read position before CP moves the read 184 * position to write/head. If CP has consumed the 185 * buffers, AP has to freed the skbuf starting at 186 * tdr_start[old_tail]. 187 * @nr_of_entries: Number of elements of skb_start and tdr_start. 188 * @max_nr_of_queued_entries: Maximum number of queued entries in TDR 189 * @accumulation_backoff: Accumulation in usec for accumulation 190 * backoff (0 = no acc backoff) 191 * @irq_moderation: timer in usec for irq_moderation 192 * (0=no irq moderation) 193 * @pipe_nr: Pipe identification number 194 * @irq: Interrupt vector 195 * @dir: Direction of data stream in pipe 196 * @buf_size: Buffer size (in bytes) for preallocated 197 * buffers (for DL pipes) 198 * @nr_of_queued_entries: Aueued number of entries 199 * @is_open: Check for open pipe status 200 */ 201 struct ipc_pipe { 202 struct ipc_protocol_td *tdr_start; 203 struct ipc_mem_channel *channel; 204 struct sk_buff **skbr_start; 205 dma_addr_t phy_tdr_start; 206 u32 old_head; 207 u32 old_tail; 208 u32 nr_of_entries; 209 u32 max_nr_of_queued_entries; 210 u32 accumulation_backoff; 211 u32 irq_moderation; 212 u32 pipe_nr; 213 u32 irq; 214 enum ipc_mem_pipe_dir dir; 215 u32 buf_size; 216 u16 nr_of_queued_entries; 217 u8 is_open:1; 218 }; 219 220 /** 221 * struct ipc_mem_channel - Structure for Channel. 222 * @channel_id: Instance of the channel list and is return to the user 223 * at the end of the open operation. 224 * @ctype: Control or netif channel. 225 * @index: unique index per ctype 226 * @ul_pipe: pipe objects 227 * @dl_pipe: pipe objects 228 * @if_id: Interface ID 229 * @net_err_count: Number of downlink errors returned by ipc_wwan_receive 230 * interface at the entry point of the IP stack. 231 * @state: Free, reserved or busy (in use). 232 * @ul_sem: Needed for the blocking write or uplink transfer. 233 * @ul_list: Uplink accumulator which is filled by the uplink 234 * char app or IP stack. The socket buffer pointer are 235 * added to the descriptor list in the kthread context. 236 */ 237 struct ipc_mem_channel { 238 int channel_id; 239 enum ipc_ctype ctype; 240 int index; 241 struct ipc_pipe ul_pipe; 242 struct ipc_pipe dl_pipe; 243 int if_id; 244 u32 net_err_count; 245 enum ipc_channel_state state; 246 struct completion ul_sem; 247 struct sk_buff_head ul_list; 248 }; 249 250 /** 251 * enum ipc_phase - Different AP and CP phases. 252 * The enums defined after "IPC_P_ROM" and before 253 * "IPC_P_RUN" indicates the operating state where CP can 254 * respond to any requests. So while introducing new phase 255 * this shall be taken into consideration. 256 * @IPC_P_OFF: On host PC, the PCIe device link settings are known 257 * about the combined power on. PC is running, the driver 258 * is loaded and CP is in power off mode. The PCIe bus 259 * driver call the device power mode D3hot. In this phase 260 * the driver the polls the device, until the device is in 261 * the power on state and signals the power mode D0. 262 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts 263 * and ends. 264 * @IPC_P_CRASH: The phase indicating CP crash 265 * @IPC_P_CD_READY: The phase indicating CP core dump is ready 266 * @IPC_P_ROM: After power on, CP starts in ROM mode and the IPC ROM 267 * driver is waiting 150 ms for the AP active notification 268 * saved in the PCI link status register. 269 * @IPC_P_PSI: Primary signed image download phase 270 * @IPC_P_EBL: Extended bootloader pahse 271 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase. 272 */ 273 enum ipc_phase { 274 IPC_P_OFF, 275 IPC_P_OFF_REQ, 276 IPC_P_CRASH, 277 IPC_P_CD_READY, 278 IPC_P_ROM, 279 IPC_P_PSI, 280 IPC_P_EBL, 281 IPC_P_RUN, 282 }; 283 284 /** 285 * struct iosm_imem - Current state of the IPC shared memory. 286 * @mmio: mmio instance to access CP MMIO area / 287 * doorbell scratchpad. 288 * @ipc_protocol: IPC Protocol instance 289 * @ipc_task: Task for entry into ipc task queue 290 * @wwan: WWAN device pointer 291 * @mux: IP Data multiplexing state. 292 * @sio: IPC SIO data structure pointer 293 * @ipc_port: IPC PORT data structure pointer 294 * @pcie: IPC PCIe 295 * @trace: IPC trace data structure pointer 296 * @dev: Pointer to device structure 297 * @ipc_requested_state: Expected IPC state on CP. 298 * @channels: Channel list with UL/DL pipe pairs. 299 * @ipc_devlink: IPC Devlink data structure pointer 300 * @ipc_status: local ipc_status 301 * @nr_of_channels: number of configured channels 302 * @startup_timer: startup timer for NAND support. 303 * @hrtimer_period: Hr timer period 304 * @tdupdate_timer: Delay the TD update doorbell. 305 * @fast_update_timer: forced head pointer update delay timer. 306 * @td_alloc_timer: Timer for DL pipe TD allocation retry 307 * @adb_timer: Timer for finishing the ADB. 308 * @rom_exit_code: Mapped boot rom exit code. 309 * @enter_runtime: 1 means the transition to runtime phase was 310 * executed. 311 * @ul_pend_sem: Semaphore to wait/complete of UL TDs 312 * before closing pipe. 313 * @app_notify_ul_pend: Signal app if UL TD is pending 314 * @dl_pend_sem: Semaphore to wait/complete of DL TDs 315 * before closing pipe. 316 * @app_notify_dl_pend: Signal app if DL TD is pending 317 * @phase: Operating phase like runtime. 318 * @pci_device_id: Device ID 319 * @cp_version: CP version 320 * @device_sleep: Device sleep state 321 * @run_state_worker: Pointer to worker component for device 322 * setup operations to be called when modem 323 * reaches RUN state 324 * @ev_irq_pending: 0 means inform the IPC tasklet to 325 * process the irq actions. 326 * @flag: Flag to monitor the state of driver 327 * @td_update_timer_suspended: if true then td update timer suspend 328 * @ev_mux_net_transmit_pending:0 means inform the IPC tasklet to pass 329 * @reset_det_n: Reset detect flag 330 * @pcie_wake_n: Pcie wake flag 331 * @debugfs_wwan_dir: WWAN Debug FS directory entry 332 * @debugfs_dir: Debug FS directory for driver-specific entries 333 */ 334 struct iosm_imem { 335 struct iosm_mmio *mmio; 336 struct iosm_protocol *ipc_protocol; 337 struct ipc_task *ipc_task; 338 struct iosm_wwan *wwan; 339 struct iosm_mux *mux; 340 struct iosm_cdev *ipc_port[IPC_MEM_MAX_CHANNELS]; 341 struct iosm_pcie *pcie; 342 #ifdef CONFIG_WWAN_DEBUGFS 343 struct iosm_trace *trace; 344 #endif 345 struct device *dev; 346 enum ipc_mem_device_ipc_state ipc_requested_state; 347 struct ipc_mem_channel channels[IPC_MEM_MAX_CHANNELS]; 348 struct iosm_devlink *ipc_devlink; 349 u32 ipc_status; 350 u32 nr_of_channels; 351 struct hrtimer startup_timer; 352 ktime_t hrtimer_period; 353 struct hrtimer tdupdate_timer; 354 struct hrtimer fast_update_timer; 355 struct hrtimer td_alloc_timer; 356 struct hrtimer adb_timer; 357 enum rom_exit_code rom_exit_code; 358 u32 enter_runtime; 359 struct completion ul_pend_sem; 360 u32 app_notify_ul_pend; 361 struct completion dl_pend_sem; 362 u32 app_notify_dl_pend; 363 enum ipc_phase phase; 364 u16 pci_device_id; 365 int cp_version; 366 int device_sleep; 367 struct work_struct run_state_worker; 368 u8 ev_irq_pending[IPC_IRQ_VECTORS]; 369 unsigned long flag; 370 u8 td_update_timer_suspended:1, 371 ev_mux_net_transmit_pending:1, 372 reset_det_n:1, 373 pcie_wake_n:1; 374 #ifdef CONFIG_WWAN_DEBUGFS 375 struct dentry *debugfs_wwan_dir; 376 struct dentry *debugfs_dir; 377 #endif 378 }; 379 380 /** 381 * ipc_imem_init - Initialize the shared memory region 382 * @pcie: Pointer to core driver data-struct 383 * @device_id: PCI device ID 384 * @mmio: Pointer to the mmio area 385 * @dev: Pointer to device structure 386 * 387 * Returns: Initialized imem pointer on success else NULL 388 */ 389 struct iosm_imem *ipc_imem_init(struct iosm_pcie *pcie, unsigned int device_id, 390 void __iomem *mmio, struct device *dev); 391 392 /** 393 * ipc_imem_pm_s2idle_sleep - Set PM variables to sleep/active for 394 * s2idle sleep/active 395 * @ipc_imem: Pointer to imem data-struct 396 * @sleep: Set PM Variable to sleep/active 397 */ 398 void ipc_imem_pm_s2idle_sleep(struct iosm_imem *ipc_imem, bool sleep); 399 400 /** 401 * ipc_imem_pm_suspend - The HAL shall ask the shared memory layer 402 * whether D3 is allowed. 403 * @ipc_imem: Pointer to imem data-struct 404 */ 405 void ipc_imem_pm_suspend(struct iosm_imem *ipc_imem); 406 407 /** 408 * ipc_imem_pm_resume - The HAL shall inform the shared memory layer 409 * that the device is active. 410 * @ipc_imem: Pointer to imem data-struct 411 */ 412 void ipc_imem_pm_resume(struct iosm_imem *ipc_imem); 413 414 /** 415 * ipc_imem_cleanup - Inform CP and free the shared memory resources. 416 * @ipc_imem: Pointer to imem data-struct 417 */ 418 void ipc_imem_cleanup(struct iosm_imem *ipc_imem); 419 420 /** 421 * ipc_imem_irq_process - Shift the IRQ actions to the IPC thread. 422 * @ipc_imem: Pointer to imem data-struct 423 * @irq: Irq number 424 */ 425 void ipc_imem_irq_process(struct iosm_imem *ipc_imem, int irq); 426 427 /** 428 * imem_get_device_sleep_state - Get the device sleep state value. 429 * @ipc_imem: Pointer to imem instance 430 * 431 * Returns: device sleep state 432 */ 433 int imem_get_device_sleep_state(struct iosm_imem *ipc_imem); 434 435 /** 436 * ipc_imem_td_update_timer_suspend - Updates the TD Update Timer suspend flag. 437 * @ipc_imem: Pointer to imem data-struct 438 * @suspend: Flag to update. If TRUE then HP update doorbell is triggered to 439 * device without any wait. If FALSE then HP update doorbell is 440 * delayed until timeout. 441 */ 442 void ipc_imem_td_update_timer_suspend(struct iosm_imem *ipc_imem, bool suspend); 443 444 /** 445 * ipc_imem_channel_close - Release the channel resources. 446 * @ipc_imem: Pointer to imem data-struct 447 * @channel_id: Channel ID to be cleaned up. 448 */ 449 void ipc_imem_channel_close(struct iosm_imem *ipc_imem, int channel_id); 450 451 /** 452 * ipc_imem_channel_alloc - Reserves a channel 453 * @ipc_imem: Pointer to imem data-struct 454 * @index: ID to lookup from the preallocated list. 455 * @ctype: Channel type. 456 * 457 * Returns: Index on success and failure value on error 458 */ 459 int ipc_imem_channel_alloc(struct iosm_imem *ipc_imem, int index, 460 enum ipc_ctype ctype); 461 462 /** 463 * ipc_imem_channel_open - Establish the pipes. 464 * @ipc_imem: Pointer to imem data-struct 465 * @channel_id: Channel ID returned during alloc. 466 * @db_id: Doorbell ID for trigger identifier. 467 * 468 * Returns: Pointer of ipc_mem_channel on success and NULL on failure. 469 */ 470 struct ipc_mem_channel *ipc_imem_channel_open(struct iosm_imem *ipc_imem, 471 int channel_id, u32 db_id); 472 473 /** 474 * ipc_imem_td_update_timer_start - Starts the TD Update Timer if not running. 475 * @ipc_imem: Pointer to imem data-struct 476 */ 477 void ipc_imem_td_update_timer_start(struct iosm_imem *ipc_imem); 478 479 /** 480 * ipc_imem_ul_write_td - Pass the channel UL list to protocol layer for TD 481 * preparation and sending them to the device. 482 * @ipc_imem: Pointer to imem data-struct 483 * 484 * Returns: TRUE of HP Doorbell trigger is pending. FALSE otherwise. 485 */ 486 bool ipc_imem_ul_write_td(struct iosm_imem *ipc_imem); 487 488 /** 489 * ipc_imem_ul_send - Dequeue SKB from channel list and start with 490 * the uplink transfer.If HP Doorbell is pending to be 491 * triggered then starts the TD Update Timer. 492 * @ipc_imem: Pointer to imem data-struct 493 */ 494 void ipc_imem_ul_send(struct iosm_imem *ipc_imem); 495 496 /** 497 * ipc_imem_channel_update - Set or modify pipe config of an existing channel 498 * @ipc_imem: Pointer to imem data-struct 499 * @id: Channel config index 500 * @chnl_cfg: Channel config struct 501 * @irq_moderation: Timer in usec for irq_moderation 502 */ 503 void ipc_imem_channel_update(struct iosm_imem *ipc_imem, int id, 504 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 505 506 /** 507 * ipc_imem_channel_free -Free an IPC channel. 508 * @channel: Channel to be freed 509 */ 510 void ipc_imem_channel_free(struct ipc_mem_channel *channel); 511 512 /** 513 * ipc_imem_hrtimer_stop - Stop the hrtimer 514 * @hr_timer: Pointer to hrtimer instance 515 */ 516 void ipc_imem_hrtimer_stop(struct hrtimer *hr_timer); 517 518 /** 519 * ipc_imem_pipe_cleanup - Reset volatile pipe content for all channels 520 * @ipc_imem: Pointer to imem data-struct 521 * @pipe: Pipe to cleaned up 522 */ 523 void ipc_imem_pipe_cleanup(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 524 525 /** 526 * ipc_imem_pipe_close - Send msg to device to close pipe 527 * @ipc_imem: Pointer to imem data-struct 528 * @pipe: Pipe to be closed 529 */ 530 void ipc_imem_pipe_close(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 531 532 /** 533 * ipc_imem_phase_update - Get the CP execution state 534 * and map it to the AP phase. 535 * @ipc_imem: Pointer to imem data-struct 536 * 537 * Returns: Current ap updated phase 538 */ 539 enum ipc_phase ipc_imem_phase_update(struct iosm_imem *ipc_imem); 540 541 /** 542 * ipc_imem_phase_get_string - Return the current operation 543 * phase as string. 544 * @phase: AP phase 545 * 546 * Returns: AP phase string 547 */ 548 const char *ipc_imem_phase_get_string(enum ipc_phase phase); 549 550 /** 551 * ipc_imem_msg_send_feature_set - Send feature set message to modem 552 * @ipc_imem: Pointer to imem data-struct 553 * @reset_enable: 0 = out-of-band, 1 = in-band-crash notification 554 * @atomic_ctx: if disabled call in tasklet context 555 * 556 */ 557 void ipc_imem_msg_send_feature_set(struct iosm_imem *ipc_imem, 558 unsigned int reset_enable, bool atomic_ctx); 559 560 /** 561 * ipc_imem_ipc_init_check - Send the init event to CP, wait a certain time and 562 * set CP to runtime with the context information 563 * @ipc_imem: Pointer to imem data-struct 564 */ 565 void ipc_imem_ipc_init_check(struct iosm_imem *ipc_imem); 566 567 /** 568 * ipc_imem_channel_init - Initialize the channel list with UL/DL pipe pairs. 569 * @ipc_imem: Pointer to imem data-struct 570 * @ctype: Channel type 571 * @chnl_cfg: Channel configuration struct 572 * @irq_moderation: Timer in usec for irq_moderation 573 */ 574 void ipc_imem_channel_init(struct iosm_imem *ipc_imem, enum ipc_ctype ctype, 575 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 576 577 /** 578 * ipc_imem_devlink_trigger_chip_info - Inform devlink that the chip 579 * information are available if the 580 * flashing to RAM interworking shall be 581 * executed. 582 * @ipc_imem: Pointer to imem structure 583 * 584 * Returns: 0 on success, -1 on failure 585 */ 586 int ipc_imem_devlink_trigger_chip_info(struct iosm_imem *ipc_imem); 587 588 void ipc_imem_adb_timer_start(struct iosm_imem *ipc_imem); 589 590 #endif 591