1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright (C) 2020-21 Intel Corporation. 4 */ 5 6 #ifndef IOSM_IPC_IMEM_H 7 #define IOSM_IPC_IMEM_H 8 9 #include <linux/skbuff.h> 10 11 #include "iosm_ipc_mmio.h" 12 #include "iosm_ipc_pcie.h" 13 #include "iosm_ipc_uevent.h" 14 #include "iosm_ipc_wwan.h" 15 #include "iosm_ipc_task_queue.h" 16 17 struct ipc_chnl_cfg; 18 19 /* IRQ moderation in usec */ 20 #define IRQ_MOD_OFF 0 21 #define IRQ_MOD_NET 1000 22 #define IRQ_MOD_TRC 4000 23 24 /* Either the PSI image is accepted by CP or the suspended flash tool is waken, 25 * informed that the CP ROM driver is not ready to process the PSI image. 26 * unit : milliseconds 27 */ 28 #define IPC_PSI_TRANSFER_TIMEOUT 3000 29 30 /* Timeout in 20 msec to wait for the modem to boot up to 31 * IPC_MEM_DEVICE_IPC_INIT state. 32 * unit : milliseconds (500 * ipc_util_msleep(20)) 33 */ 34 #define IPC_MODEM_BOOT_TIMEOUT 500 35 36 /* Wait timeout for ipc status reflects IPC_MEM_DEVICE_IPC_UNINIT 37 * unit : milliseconds 38 */ 39 #define IPC_MODEM_UNINIT_TIMEOUT_MS 30 40 41 /* Pending time for processing data. 42 * unit : milliseconds 43 */ 44 #define IPC_PEND_DATA_TIMEOUT 500 45 46 /* The timeout in milliseconds for application to wait for remote time. */ 47 #define IPC_REMOTE_TS_TIMEOUT_MS 10 48 49 /* Timeout for TD allocation retry. 50 * unit : milliseconds 51 */ 52 #define IPC_TD_ALLOC_TIMER_PERIOD_MS 100 53 54 /* Host sleep target is host */ 55 #define IPC_HOST_SLEEP_HOST 0 56 57 /* Host sleep target is device */ 58 #define IPC_HOST_SLEEP_DEVICE 1 59 60 /* Sleep message, target host: AP enters sleep / target device: CP is 61 * allowed to enter sleep and shall use the host sleep protocol 62 */ 63 #define IPC_HOST_SLEEP_ENTER_SLEEP 0 64 65 /* Sleep_message, target host: AP exits sleep / target device: CP is 66 * NOT allowed to enter sleep 67 */ 68 #define IPC_HOST_SLEEP_EXIT_SLEEP 1 69 70 #define IMEM_IRQ_DONT_CARE (-1) 71 72 #define IPC_MEM_MAX_CHANNELS 8 73 74 #define IPC_MEM_MUX_IP_SESSION_ENTRIES 8 75 76 #define IPC_MEM_MUX_IP_CH_IF_ID 0 77 78 #define TD_UPDATE_DEFAULT_TIMEOUT_USEC 1900 79 80 #define FORCE_UPDATE_DEFAULT_TIMEOUT_USEC 500 81 82 /* Sleep_message, target host: not applicable / target device: CP is 83 * allowed to enter sleep and shall NOT use the device sleep protocol 84 */ 85 #define IPC_HOST_SLEEP_ENTER_SLEEP_NO_PROTOCOL 2 86 87 /* in_band_crash_signal IPC_MEM_INBAND_CRASH_SIG 88 * Modem crash notification configuration. If this value is non-zero then 89 * FEATURE_SET message will be sent to the Modem as a result the Modem will 90 * signal Crash via Execution Stage register. If this value is zero then Modem 91 * will use out-of-band method to notify about it's Crash. 92 */ 93 #define IPC_MEM_INBAND_CRASH_SIG 1 94 95 /* Extra headroom to be allocated for DL SKBs to allow addition of Ethernet 96 * header 97 */ 98 #define IPC_MEM_DL_ETH_OFFSET 16 99 100 #define IPC_CB(skb) ((struct ipc_skb_cb *)((skb)->cb)) 101 #define IOSM_CHIP_INFO_SIZE_MAX 100 102 103 #define FULLY_FUNCTIONAL 0 104 105 /* List of the supported UL/DL pipes. */ 106 enum ipc_mem_pipes { 107 IPC_MEM_PIPE_0 = 0, 108 IPC_MEM_PIPE_1, 109 IPC_MEM_PIPE_2, 110 IPC_MEM_PIPE_3, 111 IPC_MEM_PIPE_4, 112 IPC_MEM_PIPE_5, 113 IPC_MEM_PIPE_6, 114 IPC_MEM_PIPE_7, 115 IPC_MEM_PIPE_8, 116 IPC_MEM_PIPE_9, 117 IPC_MEM_PIPE_10, 118 IPC_MEM_PIPE_11, 119 IPC_MEM_PIPE_12, 120 IPC_MEM_PIPE_13, 121 IPC_MEM_PIPE_14, 122 IPC_MEM_PIPE_15, 123 IPC_MEM_PIPE_16, 124 IPC_MEM_PIPE_17, 125 IPC_MEM_PIPE_18, 126 IPC_MEM_PIPE_19, 127 IPC_MEM_PIPE_20, 128 IPC_MEM_PIPE_21, 129 IPC_MEM_PIPE_22, 130 IPC_MEM_PIPE_23, 131 IPC_MEM_MAX_PIPES 132 }; 133 134 /* Enum defining channel states. */ 135 enum ipc_channel_state { 136 IMEM_CHANNEL_FREE, 137 IMEM_CHANNEL_RESERVED, 138 IMEM_CHANNEL_ACTIVE, 139 IMEM_CHANNEL_CLOSING, 140 }; 141 142 /* Time Unit */ 143 enum ipc_time_unit { 144 IPC_SEC = 0, 145 IPC_MILLI_SEC = 1, 146 IPC_MICRO_SEC = 2, 147 IPC_NANO_SEC = 3, 148 IPC_PICO_SEC = 4, 149 IPC_FEMTO_SEC = 5, 150 IPC_ATTO_SEC = 6, 151 }; 152 153 /** 154 * enum ipc_ctype - Enum defining supported channel type needed for control 155 * /IP traffic. 156 * @IPC_CTYPE_WWAN: Used for IP traffic 157 * @IPC_CTYPE_CTRL: Used for Control Communication 158 */ 159 enum ipc_ctype { 160 IPC_CTYPE_WWAN, 161 IPC_CTYPE_CTRL, 162 }; 163 164 /* Pipe direction. */ 165 enum ipc_mem_pipe_dir { 166 IPC_MEM_DIR_UL, 167 IPC_MEM_DIR_DL, 168 }; 169 170 /* HP update identifier. To be used as data for ipc_cp_irq_hpda_update() */ 171 enum ipc_hp_identifier { 172 IPC_HP_MR = 0, 173 IPC_HP_PM_TRIGGER, 174 IPC_HP_WAKEUP_SPEC_TMR, 175 IPC_HP_TD_UPD_TMR_START, 176 IPC_HP_TD_UPD_TMR, 177 IPC_HP_FAST_TD_UPD_TMR, 178 IPC_HP_UL_WRITE_TD, 179 IPC_HP_DL_PROCESS, 180 IPC_HP_NET_CHANNEL_INIT, 181 IPC_HP_CDEV_OPEN, 182 }; 183 184 /** 185 * struct ipc_pipe - Structure for Pipe. 186 * @tdr_start: Ipc private protocol Transfer Descriptor Ring 187 * @channel: Id of the sio device, set by imem_sio_open, 188 * needed to pass DL char to the user terminal 189 * @skbr_start: Circular buffer for skbuf and the buffer 190 * reference in a tdr_start entry. 191 * @phy_tdr_start: Transfer descriptor start address 192 * @old_head: last head pointer reported to CP. 193 * @old_tail: AP read position before CP moves the read 194 * position to write/head. If CP has consumed the 195 * buffers, AP has to freed the skbuf starting at 196 * tdr_start[old_tail]. 197 * @nr_of_entries: Number of elements of skb_start and tdr_start. 198 * @max_nr_of_queued_entries: Maximum number of queued entries in TDR 199 * @accumulation_backoff: Accumulation in usec for accumulation 200 * backoff (0 = no acc backoff) 201 * @irq_moderation: timer in usec for irq_moderation 202 * (0=no irq moderation) 203 * @pipe_nr: Pipe identification number 204 * @irq: Interrupt vector 205 * @dir: Direction of data stream in pipe 206 * @td_tag: Unique tag of the buffer queued 207 * @buf_size: Buffer size (in bytes) for preallocated 208 * buffers (for DL pipes) 209 * @nr_of_queued_entries: Aueued number of entries 210 * @is_open: Check for open pipe status 211 */ 212 struct ipc_pipe { 213 struct ipc_protocol_td *tdr_start; 214 struct ipc_mem_channel *channel; 215 struct sk_buff **skbr_start; 216 dma_addr_t phy_tdr_start; 217 u32 old_head; 218 u32 old_tail; 219 u32 nr_of_entries; 220 u32 max_nr_of_queued_entries; 221 u32 accumulation_backoff; 222 u32 irq_moderation; 223 u32 pipe_nr; 224 u32 irq; 225 enum ipc_mem_pipe_dir dir; 226 u32 td_tag; 227 u32 buf_size; 228 u16 nr_of_queued_entries; 229 u8 is_open:1; 230 }; 231 232 /** 233 * struct ipc_mem_channel - Structure for Channel. 234 * @channel_id: Instance of the channel list and is return to the user 235 * at the end of the open operation. 236 * @ctype: Control or netif channel. 237 * @index: unique index per ctype 238 * @ul_pipe: pipe objects 239 * @dl_pipe: pipe objects 240 * @if_id: Interface ID 241 * @net_err_count: Number of downlink errors returned by ipc_wwan_receive 242 * interface at the entry point of the IP stack. 243 * @state: Free, reserved or busy (in use). 244 * @ul_sem: Needed for the blocking write or uplink transfer. 245 * @ul_list: Uplink accumulator which is filled by the uplink 246 * char app or IP stack. The socket buffer pointer are 247 * added to the descriptor list in the kthread context. 248 */ 249 struct ipc_mem_channel { 250 int channel_id; 251 enum ipc_ctype ctype; 252 int index; 253 struct ipc_pipe ul_pipe; 254 struct ipc_pipe dl_pipe; 255 int if_id; 256 u32 net_err_count; 257 enum ipc_channel_state state; 258 struct completion ul_sem; 259 struct sk_buff_head ul_list; 260 }; 261 262 /** 263 * enum ipc_phase - Different AP and CP phases. 264 * The enums defined after "IPC_P_ROM" and before 265 * "IPC_P_RUN" indicates the operating state where CP can 266 * respond to any requests. So while introducing new phase 267 * this shall be taken into consideration. 268 * @IPC_P_OFF: On host PC, the PCIe device link settings are known 269 * about the combined power on. PC is running, the driver 270 * is loaded and CP is in power off mode. The PCIe bus 271 * driver call the device power mode D3hot. In this phase 272 * the driver the polls the device, until the device is in 273 * the power on state and signals the power mode D0. 274 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts 275 * and ends. 276 * @IPC_P_CRASH: The phase indicating CP crash 277 * @IPC_P_CD_READY: The phase indicating CP core dump is ready 278 * @IPC_P_ROM: After power on, CP starts in ROM mode and the IPC ROM 279 * driver is waiting 150 ms for the AP active notification 280 * saved in the PCI link status register. 281 * @IPC_P_PSI: Primary signed image download phase 282 * @IPC_P_EBL: Extended bootloader pahse 283 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase. 284 */ 285 enum ipc_phase { 286 IPC_P_OFF, 287 IPC_P_OFF_REQ, 288 IPC_P_CRASH, 289 IPC_P_CD_READY, 290 IPC_P_ROM, 291 IPC_P_PSI, 292 IPC_P_EBL, 293 IPC_P_RUN, 294 }; 295 296 /** 297 * struct iosm_imem - Current state of the IPC shared memory. 298 * @mmio: mmio instance to access CP MMIO area / 299 * doorbell scratchpad. 300 * @ipc_protocol: IPC Protocol instance 301 * @ipc_task: Task for entry into ipc task queue 302 * @wwan: WWAN device pointer 303 * @mux: IP Data multiplexing state. 304 * @sio: IPC SIO data structure pointer 305 * @ipc_port: IPC PORT data structure pointer 306 * @pcie: IPC PCIe 307 * @trace: IPC trace data structure pointer 308 * @dev: Pointer to device structure 309 * @ipc_requested_state: Expected IPC state on CP. 310 * @channels: Channel list with UL/DL pipe pairs. 311 * @ipc_devlink: IPC Devlink data structure pointer 312 * @ipc_status: local ipc_status 313 * @nr_of_channels: number of configured channels 314 * @startup_timer: startup timer for NAND support. 315 * @hrtimer_period: Hr timer period 316 * @tdupdate_timer: Delay the TD update doorbell. 317 * @fast_update_timer: forced head pointer update delay timer. 318 * @td_alloc_timer: Timer for DL pipe TD allocation retry 319 * @rom_exit_code: Mapped boot rom exit code. 320 * @enter_runtime: 1 means the transition to runtime phase was 321 * executed. 322 * @ul_pend_sem: Semaphore to wait/complete of UL TDs 323 * before closing pipe. 324 * @app_notify_ul_pend: Signal app if UL TD is pending 325 * @dl_pend_sem: Semaphore to wait/complete of DL TDs 326 * before closing pipe. 327 * @app_notify_dl_pend: Signal app if DL TD is pending 328 * @phase: Operating phase like runtime. 329 * @pci_device_id: Device ID 330 * @cp_version: CP version 331 * @device_sleep: Device sleep state 332 * @run_state_worker: Pointer to worker component for device 333 * setup operations to be called when modem 334 * reaches RUN state 335 * @ev_irq_pending: 0 means inform the IPC tasklet to 336 * process the irq actions. 337 * @flag: Flag to monitor the state of driver 338 * @td_update_timer_suspended: if true then td update timer suspend 339 * @ev_cdev_write_pending: 0 means inform the IPC tasklet to pass 340 * the accumulated uplink buffers to CP. 341 * @ev_mux_net_transmit_pending:0 means inform the IPC tasklet to pass 342 * @reset_det_n: Reset detect flag 343 * @pcie_wake_n: Pcie wake flag 344 */ 345 struct iosm_imem { 346 struct iosm_mmio *mmio; 347 struct iosm_protocol *ipc_protocol; 348 struct ipc_task *ipc_task; 349 struct iosm_wwan *wwan; 350 struct iosm_mux *mux; 351 struct iosm_cdev *ipc_port[IPC_MEM_MAX_CHANNELS]; 352 struct iosm_pcie *pcie; 353 struct iosm_trace *trace; 354 struct device *dev; 355 enum ipc_mem_device_ipc_state ipc_requested_state; 356 struct ipc_mem_channel channels[IPC_MEM_MAX_CHANNELS]; 357 struct iosm_devlink *ipc_devlink; 358 u32 ipc_status; 359 u32 nr_of_channels; 360 struct hrtimer startup_timer; 361 ktime_t hrtimer_period; 362 struct hrtimer tdupdate_timer; 363 struct hrtimer fast_update_timer; 364 struct hrtimer td_alloc_timer; 365 enum rom_exit_code rom_exit_code; 366 u32 enter_runtime; 367 struct completion ul_pend_sem; 368 u32 app_notify_ul_pend; 369 struct completion dl_pend_sem; 370 u32 app_notify_dl_pend; 371 enum ipc_phase phase; 372 u16 pci_device_id; 373 int cp_version; 374 int device_sleep; 375 struct work_struct run_state_worker; 376 u8 ev_irq_pending[IPC_IRQ_VECTORS]; 377 unsigned long flag; 378 u8 td_update_timer_suspended:1, 379 ev_cdev_write_pending:1, 380 ev_mux_net_transmit_pending:1, 381 reset_det_n:1, 382 pcie_wake_n:1; 383 }; 384 385 /** 386 * ipc_imem_init - Initialize the shared memory region 387 * @pcie: Pointer to core driver data-struct 388 * @device_id: PCI device ID 389 * @mmio: Pointer to the mmio area 390 * @dev: Pointer to device structure 391 * 392 * Returns: Initialized imem pointer on success else NULL 393 */ 394 struct iosm_imem *ipc_imem_init(struct iosm_pcie *pcie, unsigned int device_id, 395 void __iomem *mmio, struct device *dev); 396 397 /** 398 * ipc_imem_pm_s2idle_sleep - Set PM variables to sleep/active for 399 * s2idle sleep/active 400 * @ipc_imem: Pointer to imem data-struct 401 * @sleep: Set PM Variable to sleep/active 402 */ 403 void ipc_imem_pm_s2idle_sleep(struct iosm_imem *ipc_imem, bool sleep); 404 405 /** 406 * ipc_imem_pm_suspend - The HAL shall ask the shared memory layer 407 * whether D3 is allowed. 408 * @ipc_imem: Pointer to imem data-struct 409 */ 410 void ipc_imem_pm_suspend(struct iosm_imem *ipc_imem); 411 412 /** 413 * ipc_imem_pm_resume - The HAL shall inform the shared memory layer 414 * that the device is active. 415 * @ipc_imem: Pointer to imem data-struct 416 */ 417 void ipc_imem_pm_resume(struct iosm_imem *ipc_imem); 418 419 /** 420 * ipc_imem_cleanup - Inform CP and free the shared memory resources. 421 * @ipc_imem: Pointer to imem data-struct 422 */ 423 void ipc_imem_cleanup(struct iosm_imem *ipc_imem); 424 425 /** 426 * ipc_imem_irq_process - Shift the IRQ actions to the IPC thread. 427 * @ipc_imem: Pointer to imem data-struct 428 * @irq: Irq number 429 */ 430 void ipc_imem_irq_process(struct iosm_imem *ipc_imem, int irq); 431 432 /** 433 * imem_get_device_sleep_state - Get the device sleep state value. 434 * @ipc_imem: Pointer to imem instance 435 * 436 * Returns: device sleep state 437 */ 438 int imem_get_device_sleep_state(struct iosm_imem *ipc_imem); 439 440 /** 441 * ipc_imem_td_update_timer_suspend - Updates the TD Update Timer suspend flag. 442 * @ipc_imem: Pointer to imem data-struct 443 * @suspend: Flag to update. If TRUE then HP update doorbell is triggered to 444 * device without any wait. If FALSE then HP update doorbell is 445 * delayed until timeout. 446 */ 447 void ipc_imem_td_update_timer_suspend(struct iosm_imem *ipc_imem, bool suspend); 448 449 /** 450 * ipc_imem_channel_close - Release the channel resources. 451 * @ipc_imem: Pointer to imem data-struct 452 * @channel_id: Channel ID to be cleaned up. 453 */ 454 void ipc_imem_channel_close(struct iosm_imem *ipc_imem, int channel_id); 455 456 /** 457 * ipc_imem_channel_alloc - Reserves a channel 458 * @ipc_imem: Pointer to imem data-struct 459 * @index: ID to lookup from the preallocated list. 460 * @ctype: Channel type. 461 * 462 * Returns: Index on success and failure value on error 463 */ 464 int ipc_imem_channel_alloc(struct iosm_imem *ipc_imem, int index, 465 enum ipc_ctype ctype); 466 467 /** 468 * ipc_imem_channel_open - Establish the pipes. 469 * @ipc_imem: Pointer to imem data-struct 470 * @channel_id: Channel ID returned during alloc. 471 * @db_id: Doorbell ID for trigger identifier. 472 * 473 * Returns: Pointer of ipc_mem_channel on success and NULL on failure. 474 */ 475 struct ipc_mem_channel *ipc_imem_channel_open(struct iosm_imem *ipc_imem, 476 int channel_id, u32 db_id); 477 478 /** 479 * ipc_imem_td_update_timer_start - Starts the TD Update Timer if not running. 480 * @ipc_imem: Pointer to imem data-struct 481 */ 482 void ipc_imem_td_update_timer_start(struct iosm_imem *ipc_imem); 483 484 /** 485 * ipc_imem_ul_write_td - Pass the channel UL list to protocol layer for TD 486 * preparation and sending them to the device. 487 * @ipc_imem: Pointer to imem data-struct 488 * 489 * Returns: TRUE of HP Doorbell trigger is pending. FALSE otherwise. 490 */ 491 bool ipc_imem_ul_write_td(struct iosm_imem *ipc_imem); 492 493 /** 494 * ipc_imem_ul_send - Dequeue SKB from channel list and start with 495 * the uplink transfer.If HP Doorbell is pending to be 496 * triggered then starts the TD Update Timer. 497 * @ipc_imem: Pointer to imem data-struct 498 */ 499 void ipc_imem_ul_send(struct iosm_imem *ipc_imem); 500 501 /** 502 * ipc_imem_channel_update - Set or modify pipe config of an existing channel 503 * @ipc_imem: Pointer to imem data-struct 504 * @id: Channel config index 505 * @chnl_cfg: Channel config struct 506 * @irq_moderation: Timer in usec for irq_moderation 507 */ 508 void ipc_imem_channel_update(struct iosm_imem *ipc_imem, int id, 509 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 510 511 /** 512 * ipc_imem_channel_free -Free an IPC channel. 513 * @channel: Channel to be freed 514 */ 515 void ipc_imem_channel_free(struct ipc_mem_channel *channel); 516 517 /** 518 * ipc_imem_hrtimer_stop - Stop the hrtimer 519 * @hr_timer: Pointer to hrtimer instance 520 */ 521 void ipc_imem_hrtimer_stop(struct hrtimer *hr_timer); 522 523 /** 524 * ipc_imem_pipe_cleanup - Reset volatile pipe content for all channels 525 * @ipc_imem: Pointer to imem data-struct 526 * @pipe: Pipe to cleaned up 527 */ 528 void ipc_imem_pipe_cleanup(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 529 530 /** 531 * ipc_imem_pipe_close - Send msg to device to close pipe 532 * @ipc_imem: Pointer to imem data-struct 533 * @pipe: Pipe to be closed 534 */ 535 void ipc_imem_pipe_close(struct iosm_imem *ipc_imem, struct ipc_pipe *pipe); 536 537 /** 538 * ipc_imem_phase_update - Get the CP execution state 539 * and map it to the AP phase. 540 * @ipc_imem: Pointer to imem data-struct 541 * 542 * Returns: Current ap updated phase 543 */ 544 enum ipc_phase ipc_imem_phase_update(struct iosm_imem *ipc_imem); 545 546 /** 547 * ipc_imem_phase_get_string - Return the current operation 548 * phase as string. 549 * @phase: AP phase 550 * 551 * Returns: AP phase string 552 */ 553 const char *ipc_imem_phase_get_string(enum ipc_phase phase); 554 555 /** 556 * ipc_imem_msg_send_feature_set - Send feature set message to modem 557 * @ipc_imem: Pointer to imem data-struct 558 * @reset_enable: 0 = out-of-band, 1 = in-band-crash notification 559 * @atomic_ctx: if disabled call in tasklet context 560 * 561 */ 562 void ipc_imem_msg_send_feature_set(struct iosm_imem *ipc_imem, 563 unsigned int reset_enable, bool atomic_ctx); 564 565 /** 566 * ipc_imem_ipc_init_check - Send the init event to CP, wait a certain time and 567 * set CP to runtime with the context information 568 * @ipc_imem: Pointer to imem data-struct 569 */ 570 void ipc_imem_ipc_init_check(struct iosm_imem *ipc_imem); 571 572 /** 573 * ipc_imem_channel_init - Initialize the channel list with UL/DL pipe pairs. 574 * @ipc_imem: Pointer to imem data-struct 575 * @ctype: Channel type 576 * @chnl_cfg: Channel configuration struct 577 * @irq_moderation: Timer in usec for irq_moderation 578 */ 579 void ipc_imem_channel_init(struct iosm_imem *ipc_imem, enum ipc_ctype ctype, 580 struct ipc_chnl_cfg chnl_cfg, u32 irq_moderation); 581 582 /** 583 * ipc_imem_devlink_trigger_chip_info - Inform devlink that the chip 584 * information are available if the 585 * flashing to RAM interworking shall be 586 * executed. 587 * @ipc_imem: Pointer to imem structure 588 * 589 * Returns: 0 on success, -1 on failure 590 */ 591 int ipc_imem_devlink_trigger_chip_info(struct iosm_imem *ipc_imem); 592 #endif 593