1 /* ZD1211 USB-WLAN driver for Linux 2 * 3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> 4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /* This file implements all the hardware specific functions for the ZD1211 21 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy 22 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/errno.h> 27 #include <linux/slab.h> 28 29 #include "zd_def.h" 30 #include "zd_chip.h" 31 #include "zd_mac.h" 32 #include "zd_rf.h" 33 34 void zd_chip_init(struct zd_chip *chip, 35 struct ieee80211_hw *hw, 36 struct usb_interface *intf) 37 { 38 memset(chip, 0, sizeof(*chip)); 39 mutex_init(&chip->mutex); 40 zd_usb_init(&chip->usb, hw, intf); 41 zd_rf_init(&chip->rf); 42 } 43 44 void zd_chip_clear(struct zd_chip *chip) 45 { 46 ZD_ASSERT(!mutex_is_locked(&chip->mutex)); 47 zd_usb_clear(&chip->usb); 48 zd_rf_clear(&chip->rf); 49 mutex_destroy(&chip->mutex); 50 ZD_MEMCLEAR(chip, sizeof(*chip)); 51 } 52 53 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size) 54 { 55 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip)); 56 return scnprintf(buffer, size, "%02x-%02x-%02x", 57 addr[0], addr[1], addr[2]); 58 } 59 60 /* Prints an identifier line, which will support debugging. */ 61 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) 62 { 63 int i = 0; 64 65 i = scnprintf(buffer, size, "zd1211%s chip ", 66 zd_chip_is_zd1211b(chip) ? "b" : ""); 67 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); 68 i += scnprintf(buffer+i, size-i, " "); 69 i += scnprint_mac_oui(chip, buffer+i, size-i); 70 i += scnprintf(buffer+i, size-i, " "); 71 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); 72 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, 73 chip->patch_cck_gain ? 'g' : '-', 74 chip->patch_cr157 ? '7' : '-', 75 chip->patch_6m_band_edge ? '6' : '-', 76 chip->new_phy_layout ? 'N' : '-', 77 chip->al2230s_bit ? 'S' : '-'); 78 return i; 79 } 80 81 static void print_id(struct zd_chip *chip) 82 { 83 char buffer[80]; 84 85 scnprint_id(chip, buffer, sizeof(buffer)); 86 buffer[sizeof(buffer)-1] = 0; 87 dev_info(zd_chip_dev(chip), "%s\n", buffer); 88 } 89 90 static zd_addr_t inc_addr(zd_addr_t addr) 91 { 92 u16 a = (u16)addr; 93 /* Control registers use byte addressing, but everything else uses word 94 * addressing. */ 95 if ((a & 0xf000) == CR_START) 96 a += 2; 97 else 98 a += 1; 99 return (zd_addr_t)a; 100 } 101 102 /* Read a variable number of 32-bit values. Parameter count is not allowed to 103 * exceed USB_MAX_IOREAD32_COUNT. 104 */ 105 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, 106 unsigned int count) 107 { 108 int r; 109 int i; 110 zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2]; 111 u16 v16[USB_MAX_IOREAD32_COUNT * 2]; 112 unsigned int count16; 113 114 if (count > USB_MAX_IOREAD32_COUNT) 115 return -EINVAL; 116 117 /* Use stack for values and addresses. */ 118 count16 = 2 * count; 119 BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16)); 120 BUG_ON(count16 * sizeof(u16) > sizeof(v16)); 121 122 for (i = 0; i < count; i++) { 123 int j = 2*i; 124 /* We read the high word always first. */ 125 a16[j] = inc_addr(addr[i]); 126 a16[j+1] = addr[i]; 127 } 128 129 r = zd_ioread16v_locked(chip, v16, a16, count16); 130 if (r) { 131 dev_dbg_f(zd_chip_dev(chip), 132 "error: %s. Error number %d\n", __func__, r); 133 return r; 134 } 135 136 for (i = 0; i < count; i++) { 137 int j = 2*i; 138 values[i] = (v16[j] << 16) | v16[j+1]; 139 } 140 141 return 0; 142 } 143 144 static int _zd_iowrite32v_async_locked(struct zd_chip *chip, 145 const struct zd_ioreq32 *ioreqs, 146 unsigned int count) 147 { 148 int i, j, r; 149 struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2]; 150 unsigned int count16; 151 152 /* Use stack for values and addresses. */ 153 154 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 155 156 if (count == 0) 157 return 0; 158 if (count > USB_MAX_IOWRITE32_COUNT) 159 return -EINVAL; 160 161 count16 = 2 * count; 162 BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16)); 163 164 for (i = 0; i < count; i++) { 165 j = 2*i; 166 /* We write the high word always first. */ 167 ioreqs16[j].value = ioreqs[i].value >> 16; 168 ioreqs16[j].addr = inc_addr(ioreqs[i].addr); 169 ioreqs16[j+1].value = ioreqs[i].value; 170 ioreqs16[j+1].addr = ioreqs[i].addr; 171 } 172 173 r = zd_usb_iowrite16v_async(&chip->usb, ioreqs16, count16); 174 #ifdef DEBUG 175 if (r) { 176 dev_dbg_f(zd_chip_dev(chip), 177 "error %d in zd_usb_write16v\n", r); 178 } 179 #endif /* DEBUG */ 180 return r; 181 } 182 183 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 184 unsigned int count) 185 { 186 int r; 187 188 zd_usb_iowrite16v_async_start(&chip->usb); 189 r = _zd_iowrite32v_async_locked(chip, ioreqs, count); 190 if (r) { 191 zd_usb_iowrite16v_async_end(&chip->usb, 0); 192 return r; 193 } 194 return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */); 195 } 196 197 int zd_iowrite16a_locked(struct zd_chip *chip, 198 const struct zd_ioreq16 *ioreqs, unsigned int count) 199 { 200 int r; 201 unsigned int i, j, t, max; 202 203 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 204 zd_usb_iowrite16v_async_start(&chip->usb); 205 206 for (i = 0; i < count; i += j + t) { 207 t = 0; 208 max = count-i; 209 if (max > USB_MAX_IOWRITE16_COUNT) 210 max = USB_MAX_IOWRITE16_COUNT; 211 for (j = 0; j < max; j++) { 212 if (!ioreqs[i+j].addr) { 213 t = 1; 214 break; 215 } 216 } 217 218 r = zd_usb_iowrite16v_async(&chip->usb, &ioreqs[i], j); 219 if (r) { 220 zd_usb_iowrite16v_async_end(&chip->usb, 0); 221 dev_dbg_f(zd_chip_dev(chip), 222 "error zd_usb_iowrite16v. Error number %d\n", 223 r); 224 return r; 225 } 226 } 227 228 return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */); 229 } 230 231 /* Writes a variable number of 32 bit registers. The functions will split 232 * that in several USB requests. A split can be forced by inserting an IO 233 * request with an zero address field. 234 */ 235 int zd_iowrite32a_locked(struct zd_chip *chip, 236 const struct zd_ioreq32 *ioreqs, unsigned int count) 237 { 238 int r; 239 unsigned int i, j, t, max; 240 241 zd_usb_iowrite16v_async_start(&chip->usb); 242 243 for (i = 0; i < count; i += j + t) { 244 t = 0; 245 max = count-i; 246 if (max > USB_MAX_IOWRITE32_COUNT) 247 max = USB_MAX_IOWRITE32_COUNT; 248 for (j = 0; j < max; j++) { 249 if (!ioreqs[i+j].addr) { 250 t = 1; 251 break; 252 } 253 } 254 255 r = _zd_iowrite32v_async_locked(chip, &ioreqs[i], j); 256 if (r) { 257 zd_usb_iowrite16v_async_end(&chip->usb, 0); 258 dev_dbg_f(zd_chip_dev(chip), 259 "error _%s. Error number %d\n", __func__, 260 r); 261 return r; 262 } 263 } 264 265 return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */); 266 } 267 268 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) 269 { 270 int r; 271 272 mutex_lock(&chip->mutex); 273 r = zd_ioread16_locked(chip, value, addr); 274 mutex_unlock(&chip->mutex); 275 return r; 276 } 277 278 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) 279 { 280 int r; 281 282 mutex_lock(&chip->mutex); 283 r = zd_ioread32_locked(chip, value, addr); 284 mutex_unlock(&chip->mutex); 285 return r; 286 } 287 288 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) 289 { 290 int r; 291 292 mutex_lock(&chip->mutex); 293 r = zd_iowrite16_locked(chip, value, addr); 294 mutex_unlock(&chip->mutex); 295 return r; 296 } 297 298 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) 299 { 300 int r; 301 302 mutex_lock(&chip->mutex); 303 r = zd_iowrite32_locked(chip, value, addr); 304 mutex_unlock(&chip->mutex); 305 return r; 306 } 307 308 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, 309 u32 *values, unsigned int count) 310 { 311 int r; 312 313 mutex_lock(&chip->mutex); 314 r = zd_ioread32v_locked(chip, values, addresses, count); 315 mutex_unlock(&chip->mutex); 316 return r; 317 } 318 319 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 320 unsigned int count) 321 { 322 int r; 323 324 mutex_lock(&chip->mutex); 325 r = zd_iowrite32a_locked(chip, ioreqs, count); 326 mutex_unlock(&chip->mutex); 327 return r; 328 } 329 330 static int read_pod(struct zd_chip *chip, u8 *rf_type) 331 { 332 int r; 333 u32 value; 334 335 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 336 r = zd_ioread32_locked(chip, &value, E2P_POD); 337 if (r) 338 goto error; 339 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); 340 341 /* FIXME: AL2230 handling (Bit 7 in POD) */ 342 *rf_type = value & 0x0f; 343 chip->pa_type = (value >> 16) & 0x0f; 344 chip->patch_cck_gain = (value >> 8) & 0x1; 345 chip->patch_cr157 = (value >> 13) & 0x1; 346 chip->patch_6m_band_edge = (value >> 21) & 0x1; 347 chip->new_phy_layout = (value >> 31) & 0x1; 348 chip->al2230s_bit = (value >> 7) & 0x1; 349 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; 350 chip->supports_tx_led = 1; 351 if (value & (1 << 24)) { /* LED scenario */ 352 if (value & (1 << 29)) 353 chip->supports_tx_led = 0; 354 } 355 356 dev_dbg_f(zd_chip_dev(chip), 357 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " 358 "patch 6M %d new PHY %d link LED%d tx led %d\n", 359 zd_rf_name(*rf_type), *rf_type, 360 chip->pa_type, chip->patch_cck_gain, 361 chip->patch_cr157, chip->patch_6m_band_edge, 362 chip->new_phy_layout, 363 chip->link_led == LED1 ? 1 : 2, 364 chip->supports_tx_led); 365 return 0; 366 error: 367 *rf_type = 0; 368 chip->pa_type = 0; 369 chip->patch_cck_gain = 0; 370 chip->patch_cr157 = 0; 371 chip->patch_6m_band_edge = 0; 372 chip->new_phy_layout = 0; 373 return r; 374 } 375 376 static int zd_write_mac_addr_common(struct zd_chip *chip, const u8 *mac_addr, 377 const struct zd_ioreq32 *in_reqs, 378 const char *type) 379 { 380 int r; 381 struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]}; 382 383 if (mac_addr) { 384 reqs[0].value = (mac_addr[3] << 24) 385 | (mac_addr[2] << 16) 386 | (mac_addr[1] << 8) 387 | mac_addr[0]; 388 reqs[1].value = (mac_addr[5] << 8) 389 | mac_addr[4]; 390 dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr); 391 } else { 392 dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type); 393 } 394 395 mutex_lock(&chip->mutex); 396 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); 397 mutex_unlock(&chip->mutex); 398 return r; 399 } 400 401 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and 402 * CR_MAC_ADDR_P2 must be overwritten 403 */ 404 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) 405 { 406 static const struct zd_ioreq32 reqs[2] = { 407 [0] = { .addr = CR_MAC_ADDR_P1 }, 408 [1] = { .addr = CR_MAC_ADDR_P2 }, 409 }; 410 411 return zd_write_mac_addr_common(chip, mac_addr, reqs, "mac"); 412 } 413 414 int zd_write_bssid(struct zd_chip *chip, const u8 *bssid) 415 { 416 static const struct zd_ioreq32 reqs[2] = { 417 [0] = { .addr = CR_BSSID_P1 }, 418 [1] = { .addr = CR_BSSID_P2 }, 419 }; 420 421 return zd_write_mac_addr_common(chip, bssid, reqs, "bssid"); 422 } 423 424 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) 425 { 426 int r; 427 u32 value; 428 429 mutex_lock(&chip->mutex); 430 r = zd_ioread32_locked(chip, &value, E2P_SUBID); 431 mutex_unlock(&chip->mutex); 432 if (r) 433 return r; 434 435 *regdomain = value >> 16; 436 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); 437 438 return 0; 439 } 440 441 static int read_values(struct zd_chip *chip, u8 *values, size_t count, 442 zd_addr_t e2p_addr, u32 guard) 443 { 444 int r; 445 int i; 446 u32 v; 447 448 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 449 for (i = 0;;) { 450 r = zd_ioread32_locked(chip, &v, 451 (zd_addr_t)((u16)e2p_addr+i/2)); 452 if (r) 453 return r; 454 v -= guard; 455 if (i+4 < count) { 456 values[i++] = v; 457 values[i++] = v >> 8; 458 values[i++] = v >> 16; 459 values[i++] = v >> 24; 460 continue; 461 } 462 for (;i < count; i++) 463 values[i] = v >> (8*(i%3)); 464 return 0; 465 } 466 } 467 468 static int read_pwr_cal_values(struct zd_chip *chip) 469 { 470 return read_values(chip, chip->pwr_cal_values, 471 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, 472 0); 473 } 474 475 static int read_pwr_int_values(struct zd_chip *chip) 476 { 477 return read_values(chip, chip->pwr_int_values, 478 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, 479 E2P_PWR_INT_GUARD); 480 } 481 482 static int read_ofdm_cal_values(struct zd_chip *chip) 483 { 484 int r; 485 int i; 486 static const zd_addr_t addresses[] = { 487 E2P_36M_CAL_VALUE1, 488 E2P_48M_CAL_VALUE1, 489 E2P_54M_CAL_VALUE1, 490 }; 491 492 for (i = 0; i < 3; i++) { 493 r = read_values(chip, chip->ofdm_cal_values[i], 494 E2P_CHANNEL_COUNT, addresses[i], 0); 495 if (r) 496 return r; 497 } 498 return 0; 499 } 500 501 static int read_cal_int_tables(struct zd_chip *chip) 502 { 503 int r; 504 505 r = read_pwr_cal_values(chip); 506 if (r) 507 return r; 508 r = read_pwr_int_values(chip); 509 if (r) 510 return r; 511 r = read_ofdm_cal_values(chip); 512 if (r) 513 return r; 514 return 0; 515 } 516 517 /* phy means physical registers */ 518 int zd_chip_lock_phy_regs(struct zd_chip *chip) 519 { 520 int r; 521 u32 tmp; 522 523 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 524 r = zd_ioread32_locked(chip, &tmp, CR_REG1); 525 if (r) { 526 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); 527 return r; 528 } 529 530 tmp &= ~UNLOCK_PHY_REGS; 531 532 r = zd_iowrite32_locked(chip, tmp, CR_REG1); 533 if (r) 534 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); 535 return r; 536 } 537 538 int zd_chip_unlock_phy_regs(struct zd_chip *chip) 539 { 540 int r; 541 u32 tmp; 542 543 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 544 r = zd_ioread32_locked(chip, &tmp, CR_REG1); 545 if (r) { 546 dev_err(zd_chip_dev(chip), 547 "error ioread32(CR_REG1): %d\n", r); 548 return r; 549 } 550 551 tmp |= UNLOCK_PHY_REGS; 552 553 r = zd_iowrite32_locked(chip, tmp, CR_REG1); 554 if (r) 555 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); 556 return r; 557 } 558 559 /* ZD_CR157 can be optionally patched by the EEPROM for original ZD1211 */ 560 static int patch_cr157(struct zd_chip *chip) 561 { 562 int r; 563 u16 value; 564 565 if (!chip->patch_cr157) 566 return 0; 567 568 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); 569 if (r) 570 return r; 571 572 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); 573 return zd_iowrite32_locked(chip, value >> 8, ZD_CR157); 574 } 575 576 /* 577 * 6M band edge can be optionally overwritten for certain RF's 578 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge 579 * bit (for AL2230, AL2230S) 580 */ 581 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) 582 { 583 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 584 if (!chip->patch_6m_band_edge) 585 return 0; 586 587 return zd_rf_patch_6m_band_edge(&chip->rf, channel); 588 } 589 590 /* Generic implementation of 6M band edge patching, used by most RFs via 591 * zd_rf_generic_patch_6m() */ 592 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) 593 { 594 struct zd_ioreq16 ioreqs[] = { 595 { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, 596 { ZD_CR47, 0x1e }, 597 }; 598 599 /* FIXME: Channel 11 is not the edge for all regulatory domains. */ 600 if (channel == 1 || channel == 11) 601 ioreqs[0].value = 0x12; 602 603 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); 604 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 605 } 606 607 static int zd1211_hw_reset_phy(struct zd_chip *chip) 608 { 609 static const struct zd_ioreq16 ioreqs[] = { 610 { ZD_CR0, 0x0a }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 }, 611 { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xa0 }, 612 { ZD_CR10, 0x81 }, { ZD_CR11, 0x00 }, { ZD_CR12, 0x7f }, 613 { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, { ZD_CR15, 0x3d }, 614 { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, { ZD_CR18, 0x0a }, 615 { ZD_CR19, 0x48 }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0c }, 616 { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, { ZD_CR24, 0x14 }, 617 { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, { ZD_CR27, 0x19 }, 618 { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, { ZD_CR30, 0x4b }, 619 { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 }, 620 { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 }, 621 { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c }, 622 { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 }, 623 { ZD_CR43, 0x10 }, { ZD_CR44, 0x12 }, { ZD_CR46, 0xff }, 624 { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b }, 625 { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 }, 626 { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 }, 627 { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff }, 628 { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 }, 629 { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 }, 630 { ZD_CR79, 0x68 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 }, 631 { ZD_CR82, 0x00 }, { ZD_CR83, 0x00 }, { ZD_CR84, 0x00 }, 632 { ZD_CR85, 0x02 }, { ZD_CR86, 0x00 }, { ZD_CR87, 0x00 }, 633 { ZD_CR88, 0xff }, { ZD_CR89, 0xfc }, { ZD_CR90, 0x00 }, 634 { ZD_CR91, 0x00 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x08 }, 635 { ZD_CR94, 0x00 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0xff }, 636 { ZD_CR97, 0xe7 }, { ZD_CR98, 0x00 }, { ZD_CR99, 0x00 }, 637 { ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 }, 638 { ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 }, 639 { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a }, 640 { ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 }, 641 { ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e }, 642 { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 }, 643 { }, 644 { ZD_CR5, 0x00 }, { ZD_CR6, 0x00 }, { ZD_CR7, 0x00 }, 645 { ZD_CR8, 0x00 }, { ZD_CR9, 0x20 }, { ZD_CR12, 0xf0 }, 646 { ZD_CR20, 0x0e }, { ZD_CR21, 0x0e }, { ZD_CR27, 0x10 }, 647 { ZD_CR44, 0x33 }, { ZD_CR47, 0x1E }, { ZD_CR83, 0x24 }, 648 { ZD_CR84, 0x04 }, { ZD_CR85, 0x00 }, { ZD_CR86, 0x0C }, 649 { ZD_CR87, 0x12 }, { ZD_CR88, 0x0C }, { ZD_CR89, 0x00 }, 650 { ZD_CR90, 0x10 }, { ZD_CR91, 0x08 }, { ZD_CR93, 0x00 }, 651 { ZD_CR94, 0x01 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0x50 }, 652 { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, { ZD_CR101, 0x13 }, 653 { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, 654 { ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 }, 655 { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, 656 { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 }, 657 { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f }, 658 { ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 }, 659 { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C }, 660 { ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 }, 661 { ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 }, 662 { ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c }, 663 { ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 }, 664 { ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe }, 665 { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa }, 666 { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe }, 667 { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba }, 668 { ZD_CR170, 0xba }, { ZD_CR171, 0xba }, 669 /* Note: ZD_CR204 must lead the ZD_CR203 */ 670 { ZD_CR204, 0x7d }, 671 { }, 672 { ZD_CR203, 0x30 }, 673 }; 674 675 int r, t; 676 677 dev_dbg_f(zd_chip_dev(chip), "\n"); 678 679 r = zd_chip_lock_phy_regs(chip); 680 if (r) 681 goto out; 682 683 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 684 if (r) 685 goto unlock; 686 687 r = patch_cr157(chip); 688 unlock: 689 t = zd_chip_unlock_phy_regs(chip); 690 if (t && !r) 691 r = t; 692 out: 693 return r; 694 } 695 696 static int zd1211b_hw_reset_phy(struct zd_chip *chip) 697 { 698 static const struct zd_ioreq16 ioreqs[] = { 699 { ZD_CR0, 0x14 }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 }, 700 { ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xe0 }, 701 { ZD_CR10, 0x81 }, 702 /* power control { { ZD_CR11, 1 << 6 }, */ 703 { ZD_CR11, 0x00 }, 704 { ZD_CR12, 0xf0 }, { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, 705 { ZD_CR15, 0x3d }, { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, 706 { ZD_CR18, 0x0a }, { ZD_CR19, 0x48 }, 707 { ZD_CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ 708 { ZD_CR21, 0x0e }, { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, 709 { ZD_CR24, 0x14 }, { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, 710 { ZD_CR27, 0x10 }, { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, 711 { ZD_CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ 712 { ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 }, 713 { ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 }, 714 { ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c }, 715 { ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 }, 716 { ZD_CR43, 0x10 }, { ZD_CR44, 0x33 }, { ZD_CR46, 0xff }, 717 { ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b }, 718 { ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 }, 719 { ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 }, 720 { ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff }, 721 { ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 }, 722 { ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 }, 723 { ZD_CR79, 0xf0 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 }, 724 { ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 }, 725 { ZD_CR85, 0x00 }, { ZD_CR86, 0x0c }, { ZD_CR87, 0x12 }, 726 { ZD_CR88, 0x0c }, { ZD_CR89, 0x00 }, { ZD_CR90, 0x58 }, 727 { ZD_CR91, 0x04 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x00 }, 728 { ZD_CR94, 0x01 }, 729 { ZD_CR95, 0x20 }, /* ZD1211B */ 730 { ZD_CR96, 0x50 }, { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, 731 { ZD_CR99, 0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 }, 732 { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, 733 { ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, 734 { ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 }, 735 { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, 736 { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 }, 737 { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e }, 738 { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 }, 739 { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, 740 { ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 }, 741 { ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 }, 742 { ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c }, 743 { ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 }, 744 { ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ 745 { ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ 746 { ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe }, 747 { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa }, 748 { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe }, 749 { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba }, 750 { ZD_CR170, 0xba }, { ZD_CR171, 0xba }, 751 /* Note: ZD_CR204 must lead the ZD_CR203 */ 752 { ZD_CR204, 0x7d }, 753 {}, 754 { ZD_CR203, 0x30 }, 755 }; 756 757 int r, t; 758 759 dev_dbg_f(zd_chip_dev(chip), "\n"); 760 761 r = zd_chip_lock_phy_regs(chip); 762 if (r) 763 goto out; 764 765 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 766 t = zd_chip_unlock_phy_regs(chip); 767 if (t && !r) 768 r = t; 769 out: 770 return r; 771 } 772 773 static int hw_reset_phy(struct zd_chip *chip) 774 { 775 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) : 776 zd1211_hw_reset_phy(chip); 777 } 778 779 static int zd1211_hw_init_hmac(struct zd_chip *chip) 780 { 781 static const struct zd_ioreq32 ioreqs[] = { 782 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT }, 783 { CR_RX_THRESHOLD, 0x000c0640 }, 784 }; 785 786 dev_dbg_f(zd_chip_dev(chip), "\n"); 787 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 788 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 789 } 790 791 static int zd1211b_hw_init_hmac(struct zd_chip *chip) 792 { 793 static const struct zd_ioreq32 ioreqs[] = { 794 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT }, 795 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f }, 796 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f }, 797 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f }, 798 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f }, 799 { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, 800 { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, 801 { CR_ZD1211B_TXOP, 0x01800824 }, 802 { CR_RX_THRESHOLD, 0x000c0eff, }, 803 }; 804 805 dev_dbg_f(zd_chip_dev(chip), "\n"); 806 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 807 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 808 } 809 810 static int hw_init_hmac(struct zd_chip *chip) 811 { 812 int r; 813 static const struct zd_ioreq32 ioreqs[] = { 814 { CR_ACK_TIMEOUT_EXT, 0x20 }, 815 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, 816 { CR_SNIFFER_ON, 0 }, 817 { CR_RX_FILTER, STA_RX_FILTER }, 818 { CR_GROUP_HASH_P1, 0x00 }, 819 { CR_GROUP_HASH_P2, 0x80000000 }, 820 { CR_REG1, 0xa4 }, 821 { CR_ADDA_PWR_DWN, 0x7f }, 822 { CR_BCN_PLCP_CFG, 0x00f00401 }, 823 { CR_PHY_DELAY, 0x00 }, 824 { CR_ACK_TIMEOUT_EXT, 0x80 }, 825 { CR_ADDA_PWR_DWN, 0x00 }, 826 { CR_ACK_TIME_80211, 0x100 }, 827 { CR_RX_PE_DELAY, 0x70 }, 828 { CR_PS_CTRL, 0x10000000 }, 829 { CR_RTS_CTS_RATE, 0x02030203 }, 830 { CR_AFTER_PNP, 0x1 }, 831 { CR_WEP_PROTECT, 0x114 }, 832 { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, 833 { CR_CAM_MODE, MODE_AP_WDS}, 834 }; 835 836 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 837 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 838 if (r) 839 return r; 840 841 return zd_chip_is_zd1211b(chip) ? 842 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); 843 } 844 845 struct aw_pt_bi { 846 u32 atim_wnd_period; 847 u32 pre_tbtt; 848 u32 beacon_interval; 849 }; 850 851 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) 852 { 853 int r; 854 static const zd_addr_t aw_pt_bi_addr[] = 855 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; 856 u32 values[3]; 857 858 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, 859 ARRAY_SIZE(aw_pt_bi_addr)); 860 if (r) { 861 memset(s, 0, sizeof(*s)); 862 return r; 863 } 864 865 s->atim_wnd_period = values[0]; 866 s->pre_tbtt = values[1]; 867 s->beacon_interval = values[2]; 868 return 0; 869 } 870 871 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) 872 { 873 struct zd_ioreq32 reqs[3]; 874 u16 b_interval = s->beacon_interval & 0xffff; 875 876 if (b_interval <= 5) 877 b_interval = 5; 878 if (s->pre_tbtt < 4 || s->pre_tbtt >= b_interval) 879 s->pre_tbtt = b_interval - 1; 880 if (s->atim_wnd_period >= s->pre_tbtt) 881 s->atim_wnd_period = s->pre_tbtt - 1; 882 883 reqs[0].addr = CR_ATIM_WND_PERIOD; 884 reqs[0].value = s->atim_wnd_period; 885 reqs[1].addr = CR_PRE_TBTT; 886 reqs[1].value = s->pre_tbtt; 887 reqs[2].addr = CR_BCN_INTERVAL; 888 reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval; 889 890 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); 891 } 892 893 894 static int set_beacon_interval(struct zd_chip *chip, u16 interval, 895 u8 dtim_period, int type) 896 { 897 int r; 898 struct aw_pt_bi s; 899 u32 b_interval, mode_flag; 900 901 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 902 903 if (interval > 0) { 904 switch (type) { 905 case NL80211_IFTYPE_ADHOC: 906 case NL80211_IFTYPE_MESH_POINT: 907 mode_flag = BCN_MODE_IBSS; 908 break; 909 case NL80211_IFTYPE_AP: 910 mode_flag = BCN_MODE_AP; 911 break; 912 default: 913 mode_flag = 0; 914 break; 915 } 916 } else { 917 dtim_period = 0; 918 mode_flag = 0; 919 } 920 921 b_interval = mode_flag | (dtim_period << 16) | interval; 922 923 r = zd_iowrite32_locked(chip, b_interval, CR_BCN_INTERVAL); 924 if (r) 925 return r; 926 r = get_aw_pt_bi(chip, &s); 927 if (r) 928 return r; 929 return set_aw_pt_bi(chip, &s); 930 } 931 932 int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period, 933 int type) 934 { 935 int r; 936 937 mutex_lock(&chip->mutex); 938 r = set_beacon_interval(chip, interval, dtim_period, type); 939 mutex_unlock(&chip->mutex); 940 return r; 941 } 942 943 static int hw_init(struct zd_chip *chip) 944 { 945 int r; 946 947 dev_dbg_f(zd_chip_dev(chip), "\n"); 948 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 949 r = hw_reset_phy(chip); 950 if (r) 951 return r; 952 953 r = hw_init_hmac(chip); 954 if (r) 955 return r; 956 957 return set_beacon_interval(chip, 100, 0, NL80211_IFTYPE_UNSPECIFIED); 958 } 959 960 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) 961 { 962 return (zd_addr_t)((u16)chip->fw_regs_base + offset); 963 } 964 965 #ifdef DEBUG 966 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, 967 const char *addr_string) 968 { 969 int r; 970 u32 value; 971 972 r = zd_ioread32_locked(chip, &value, addr); 973 if (r) { 974 dev_dbg_f(zd_chip_dev(chip), 975 "error reading %s. Error number %d\n", addr_string, r); 976 return r; 977 } 978 979 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", 980 addr_string, (unsigned int)value); 981 return 0; 982 } 983 984 static int test_init(struct zd_chip *chip) 985 { 986 int r; 987 988 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); 989 if (r) 990 return r; 991 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); 992 if (r) 993 return r; 994 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); 995 } 996 997 static void dump_fw_registers(struct zd_chip *chip) 998 { 999 const zd_addr_t addr[4] = { 1000 fw_reg_addr(chip, FW_REG_FIRMWARE_VER), 1001 fw_reg_addr(chip, FW_REG_USB_SPEED), 1002 fw_reg_addr(chip, FW_REG_FIX_TX_RATE), 1003 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), 1004 }; 1005 1006 int r; 1007 u16 values[4]; 1008 1009 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, 1010 ARRAY_SIZE(addr)); 1011 if (r) { 1012 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", 1013 r); 1014 return; 1015 } 1016 1017 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); 1018 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); 1019 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); 1020 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); 1021 } 1022 #endif /* DEBUG */ 1023 1024 static int print_fw_version(struct zd_chip *chip) 1025 { 1026 struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy; 1027 int r; 1028 u16 version; 1029 1030 r = zd_ioread16_locked(chip, &version, 1031 fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); 1032 if (r) 1033 return r; 1034 1035 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); 1036 1037 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), 1038 "%04hx", version); 1039 1040 return 0; 1041 } 1042 1043 static int set_mandatory_rates(struct zd_chip *chip, int gmode) 1044 { 1045 u32 rates; 1046 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1047 /* This sets the mandatory rates, which only depend from the standard 1048 * that the device is supporting. Until further notice we should try 1049 * to support 802.11g also for full speed USB. 1050 */ 1051 if (!gmode) 1052 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; 1053 else 1054 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| 1055 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; 1056 1057 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); 1058 } 1059 1060 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, 1061 int preamble) 1062 { 1063 u32 value = 0; 1064 1065 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble); 1066 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; 1067 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; 1068 1069 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */ 1070 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE; 1071 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE; 1072 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE; 1073 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; 1074 1075 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); 1076 } 1077 1078 int zd_chip_enable_hwint(struct zd_chip *chip) 1079 { 1080 int r; 1081 1082 mutex_lock(&chip->mutex); 1083 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); 1084 mutex_unlock(&chip->mutex); 1085 return r; 1086 } 1087 1088 static int disable_hwint(struct zd_chip *chip) 1089 { 1090 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); 1091 } 1092 1093 int zd_chip_disable_hwint(struct zd_chip *chip) 1094 { 1095 int r; 1096 1097 mutex_lock(&chip->mutex); 1098 r = disable_hwint(chip); 1099 mutex_unlock(&chip->mutex); 1100 return r; 1101 } 1102 1103 static int read_fw_regs_offset(struct zd_chip *chip) 1104 { 1105 int r; 1106 1107 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1108 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, 1109 FWRAW_REGS_ADDR); 1110 if (r) 1111 return r; 1112 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", 1113 (u16)chip->fw_regs_base); 1114 1115 return 0; 1116 } 1117 1118 /* Read mac address using pre-firmware interface */ 1119 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr) 1120 { 1121 dev_dbg_f(zd_chip_dev(chip), "\n"); 1122 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr, 1123 ETH_ALEN); 1124 } 1125 1126 int zd_chip_init_hw(struct zd_chip *chip) 1127 { 1128 int r; 1129 u8 rf_type; 1130 1131 dev_dbg_f(zd_chip_dev(chip), "\n"); 1132 1133 mutex_lock(&chip->mutex); 1134 1135 #ifdef DEBUG 1136 r = test_init(chip); 1137 if (r) 1138 goto out; 1139 #endif 1140 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); 1141 if (r) 1142 goto out; 1143 1144 r = read_fw_regs_offset(chip); 1145 if (r) 1146 goto out; 1147 1148 /* GPI is always disabled, also in the other driver. 1149 */ 1150 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); 1151 if (r) 1152 goto out; 1153 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); 1154 if (r) 1155 goto out; 1156 /* Currently we support IEEE 802.11g for full and high speed USB. 1157 * It might be discussed, whether we should support pure b mode for 1158 * full speed USB. 1159 */ 1160 r = set_mandatory_rates(chip, 1); 1161 if (r) 1162 goto out; 1163 /* Disabling interrupts is certainly a smart thing here. 1164 */ 1165 r = disable_hwint(chip); 1166 if (r) 1167 goto out; 1168 r = read_pod(chip, &rf_type); 1169 if (r) 1170 goto out; 1171 r = hw_init(chip); 1172 if (r) 1173 goto out; 1174 r = zd_rf_init_hw(&chip->rf, rf_type); 1175 if (r) 1176 goto out; 1177 1178 r = print_fw_version(chip); 1179 if (r) 1180 goto out; 1181 1182 #ifdef DEBUG 1183 dump_fw_registers(chip); 1184 r = test_init(chip); 1185 if (r) 1186 goto out; 1187 #endif /* DEBUG */ 1188 1189 r = read_cal_int_tables(chip); 1190 if (r) 1191 goto out; 1192 1193 print_id(chip); 1194 out: 1195 mutex_unlock(&chip->mutex); 1196 return r; 1197 } 1198 1199 static int update_pwr_int(struct zd_chip *chip, u8 channel) 1200 { 1201 u8 value = chip->pwr_int_values[channel - 1]; 1202 return zd_iowrite16_locked(chip, value, ZD_CR31); 1203 } 1204 1205 static int update_pwr_cal(struct zd_chip *chip, u8 channel) 1206 { 1207 u8 value = chip->pwr_cal_values[channel-1]; 1208 return zd_iowrite16_locked(chip, value, ZD_CR68); 1209 } 1210 1211 static int update_ofdm_cal(struct zd_chip *chip, u8 channel) 1212 { 1213 struct zd_ioreq16 ioreqs[3]; 1214 1215 ioreqs[0].addr = ZD_CR67; 1216 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; 1217 ioreqs[1].addr = ZD_CR66; 1218 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; 1219 ioreqs[2].addr = ZD_CR65; 1220 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; 1221 1222 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1223 } 1224 1225 static int update_channel_integration_and_calibration(struct zd_chip *chip, 1226 u8 channel) 1227 { 1228 int r; 1229 1230 if (!zd_rf_should_update_pwr_int(&chip->rf)) 1231 return 0; 1232 1233 r = update_pwr_int(chip, channel); 1234 if (r) 1235 return r; 1236 if (zd_chip_is_zd1211b(chip)) { 1237 static const struct zd_ioreq16 ioreqs[] = { 1238 { ZD_CR69, 0x28 }, 1239 {}, 1240 { ZD_CR69, 0x2a }, 1241 }; 1242 1243 r = update_ofdm_cal(chip, channel); 1244 if (r) 1245 return r; 1246 r = update_pwr_cal(chip, channel); 1247 if (r) 1248 return r; 1249 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1250 if (r) 1251 return r; 1252 } 1253 1254 return 0; 1255 } 1256 1257 /* The CCK baseband gain can be optionally patched by the EEPROM */ 1258 static int patch_cck_gain(struct zd_chip *chip) 1259 { 1260 int r; 1261 u32 value; 1262 1263 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) 1264 return 0; 1265 1266 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1267 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); 1268 if (r) 1269 return r; 1270 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); 1271 return zd_iowrite16_locked(chip, value & 0xff, ZD_CR47); 1272 } 1273 1274 int zd_chip_set_channel(struct zd_chip *chip, u8 channel) 1275 { 1276 int r, t; 1277 1278 mutex_lock(&chip->mutex); 1279 r = zd_chip_lock_phy_regs(chip); 1280 if (r) 1281 goto out; 1282 r = zd_rf_set_channel(&chip->rf, channel); 1283 if (r) 1284 goto unlock; 1285 r = update_channel_integration_and_calibration(chip, channel); 1286 if (r) 1287 goto unlock; 1288 r = patch_cck_gain(chip); 1289 if (r) 1290 goto unlock; 1291 r = patch_6m_band_edge(chip, channel); 1292 if (r) 1293 goto unlock; 1294 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); 1295 unlock: 1296 t = zd_chip_unlock_phy_regs(chip); 1297 if (t && !r) 1298 r = t; 1299 out: 1300 mutex_unlock(&chip->mutex); 1301 return r; 1302 } 1303 1304 u8 zd_chip_get_channel(struct zd_chip *chip) 1305 { 1306 u8 channel; 1307 1308 mutex_lock(&chip->mutex); 1309 channel = chip->rf.channel; 1310 mutex_unlock(&chip->mutex); 1311 return channel; 1312 } 1313 1314 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) 1315 { 1316 const zd_addr_t a[] = { 1317 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), 1318 CR_LED, 1319 }; 1320 1321 int r; 1322 u16 v[ARRAY_SIZE(a)]; 1323 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { 1324 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, 1325 [1] = { CR_LED }, 1326 }; 1327 u16 other_led; 1328 1329 mutex_lock(&chip->mutex); 1330 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); 1331 if (r) 1332 goto out; 1333 1334 other_led = chip->link_led == LED1 ? LED2 : LED1; 1335 1336 switch (status) { 1337 case ZD_LED_OFF: 1338 ioreqs[0].value = FW_LINK_OFF; 1339 ioreqs[1].value = v[1] & ~(LED1|LED2); 1340 break; 1341 case ZD_LED_SCANNING: 1342 ioreqs[0].value = FW_LINK_OFF; 1343 ioreqs[1].value = v[1] & ~other_led; 1344 if (get_seconds() % 3 == 0) { 1345 ioreqs[1].value &= ~chip->link_led; 1346 } else { 1347 ioreqs[1].value |= chip->link_led; 1348 } 1349 break; 1350 case ZD_LED_ASSOCIATED: 1351 ioreqs[0].value = FW_LINK_TX; 1352 ioreqs[1].value = v[1] & ~other_led; 1353 ioreqs[1].value |= chip->link_led; 1354 break; 1355 default: 1356 r = -EINVAL; 1357 goto out; 1358 } 1359 1360 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { 1361 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1362 if (r) 1363 goto out; 1364 } 1365 r = 0; 1366 out: 1367 mutex_unlock(&chip->mutex); 1368 return r; 1369 } 1370 1371 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) 1372 { 1373 int r; 1374 1375 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) 1376 return -EINVAL; 1377 1378 mutex_lock(&chip->mutex); 1379 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); 1380 mutex_unlock(&chip->mutex); 1381 return r; 1382 } 1383 1384 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame) 1385 { 1386 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame); 1387 } 1388 1389 /** 1390 * zd_rx_rate - report zd-rate 1391 * @rx_frame - received frame 1392 * @rx_status - rx_status as given by the device 1393 * 1394 * This function converts the rate as encoded in the received packet to the 1395 * zd-rate, we are using on other places in the driver. 1396 */ 1397 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status) 1398 { 1399 u8 zd_rate; 1400 if (status->frame_status & ZD_RX_OFDM) { 1401 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame); 1402 } else { 1403 switch (zd_cck_plcp_header_signal(rx_frame)) { 1404 case ZD_CCK_PLCP_SIGNAL_1M: 1405 zd_rate = ZD_CCK_RATE_1M; 1406 break; 1407 case ZD_CCK_PLCP_SIGNAL_2M: 1408 zd_rate = ZD_CCK_RATE_2M; 1409 break; 1410 case ZD_CCK_PLCP_SIGNAL_5M5: 1411 zd_rate = ZD_CCK_RATE_5_5M; 1412 break; 1413 case ZD_CCK_PLCP_SIGNAL_11M: 1414 zd_rate = ZD_CCK_RATE_11M; 1415 break; 1416 default: 1417 zd_rate = 0; 1418 } 1419 } 1420 1421 return zd_rate; 1422 } 1423 1424 int zd_chip_switch_radio_on(struct zd_chip *chip) 1425 { 1426 int r; 1427 1428 mutex_lock(&chip->mutex); 1429 r = zd_switch_radio_on(&chip->rf); 1430 mutex_unlock(&chip->mutex); 1431 return r; 1432 } 1433 1434 int zd_chip_switch_radio_off(struct zd_chip *chip) 1435 { 1436 int r; 1437 1438 mutex_lock(&chip->mutex); 1439 r = zd_switch_radio_off(&chip->rf); 1440 mutex_unlock(&chip->mutex); 1441 return r; 1442 } 1443 1444 int zd_chip_enable_int(struct zd_chip *chip) 1445 { 1446 int r; 1447 1448 mutex_lock(&chip->mutex); 1449 r = zd_usb_enable_int(&chip->usb); 1450 mutex_unlock(&chip->mutex); 1451 return r; 1452 } 1453 1454 void zd_chip_disable_int(struct zd_chip *chip) 1455 { 1456 mutex_lock(&chip->mutex); 1457 zd_usb_disable_int(&chip->usb); 1458 mutex_unlock(&chip->mutex); 1459 1460 /* cancel pending interrupt work */ 1461 cancel_work_sync(&zd_chip_to_mac(chip)->process_intr); 1462 } 1463 1464 int zd_chip_enable_rxtx(struct zd_chip *chip) 1465 { 1466 int r; 1467 1468 mutex_lock(&chip->mutex); 1469 zd_usb_enable_tx(&chip->usb); 1470 r = zd_usb_enable_rx(&chip->usb); 1471 zd_tx_watchdog_enable(&chip->usb); 1472 mutex_unlock(&chip->mutex); 1473 return r; 1474 } 1475 1476 void zd_chip_disable_rxtx(struct zd_chip *chip) 1477 { 1478 mutex_lock(&chip->mutex); 1479 zd_tx_watchdog_disable(&chip->usb); 1480 zd_usb_disable_rx(&chip->usb); 1481 zd_usb_disable_tx(&chip->usb); 1482 mutex_unlock(&chip->mutex); 1483 } 1484 1485 int zd_rfwritev_locked(struct zd_chip *chip, 1486 const u32* values, unsigned int count, u8 bits) 1487 { 1488 int r; 1489 unsigned int i; 1490 1491 for (i = 0; i < count; i++) { 1492 r = zd_rfwrite_locked(chip, values[i], bits); 1493 if (r) 1494 return r; 1495 } 1496 1497 return 0; 1498 } 1499 1500 /* 1501 * We can optionally program the RF directly through CR regs, if supported by 1502 * the hardware. This is much faster than the older method. 1503 */ 1504 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) 1505 { 1506 const struct zd_ioreq16 ioreqs[] = { 1507 { ZD_CR244, (value >> 16) & 0xff }, 1508 { ZD_CR243, (value >> 8) & 0xff }, 1509 { ZD_CR242, value & 0xff }, 1510 }; 1511 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 1512 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1513 } 1514 1515 int zd_rfwritev_cr_locked(struct zd_chip *chip, 1516 const u32 *values, unsigned int count) 1517 { 1518 int r; 1519 unsigned int i; 1520 1521 for (i = 0; i < count; i++) { 1522 r = zd_rfwrite_cr_locked(chip, values[i]); 1523 if (r) 1524 return r; 1525 } 1526 1527 return 0; 1528 } 1529 1530 int zd_chip_set_multicast_hash(struct zd_chip *chip, 1531 struct zd_mc_hash *hash) 1532 { 1533 const struct zd_ioreq32 ioreqs[] = { 1534 { CR_GROUP_HASH_P1, hash->low }, 1535 { CR_GROUP_HASH_P2, hash->high }, 1536 }; 1537 1538 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); 1539 } 1540 1541 u64 zd_chip_get_tsf(struct zd_chip *chip) 1542 { 1543 int r; 1544 static const zd_addr_t aw_pt_bi_addr[] = 1545 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART }; 1546 u32 values[2]; 1547 u64 tsf; 1548 1549 mutex_lock(&chip->mutex); 1550 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, 1551 ARRAY_SIZE(aw_pt_bi_addr)); 1552 mutex_unlock(&chip->mutex); 1553 if (r) 1554 return 0; 1555 1556 tsf = values[1]; 1557 tsf = (tsf << 32) | values[0]; 1558 1559 return tsf; 1560 } 1561