1 /* 2 * This file is part of wl18xx 3 * 4 * Copyright (C) 2011 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 25 #include "../wlcore/wlcore.h" 26 #include "../wlcore/debug.h" 27 #include "../wlcore/io.h" 28 #include "../wlcore/acx.h" 29 #include "../wlcore/tx.h" 30 #include "../wlcore/rx.h" 31 #include "../wlcore/io.h" 32 #include "../wlcore/boot.h" 33 34 #include "reg.h" 35 #include "conf.h" 36 #include "wl18xx.h" 37 38 #define WL18XX_TX_HW_BLOCK_SPARE 1 39 #define WL18XX_TX_HW_GEM_BLOCK_SPARE 2 40 #define WL18XX_TX_HW_BLOCK_SIZE 268 41 42 static const u8 wl18xx_rate_to_idx_2ghz[] = { 43 /* MCS rates are used only with 11n */ 44 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 45 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 46 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 47 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 48 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 49 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 50 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 51 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 52 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 53 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 54 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 55 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 56 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 57 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 58 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 59 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 60 61 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 62 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 63 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 64 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 65 66 /* TI-specific rate */ 67 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 68 69 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 70 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 71 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 72 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 73 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 74 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 75 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 76 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */ 77 }; 78 79 static const u8 wl18xx_rate_to_idx_5ghz[] = { 80 /* MCS rates are used only with 11n */ 81 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 82 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 83 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 84 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 85 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 86 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 87 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 88 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 89 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 90 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 91 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 92 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 93 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 94 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 95 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 96 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 97 98 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 99 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 100 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 101 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 102 103 /* TI-specific rate */ 104 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 105 106 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 107 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 108 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 109 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 110 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 111 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 112 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 113 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */ 114 }; 115 116 static const u8 *wl18xx_band_rate_to_idx[] = { 117 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz, 118 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz 119 }; 120 121 enum wl18xx_hw_rates { 122 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0, 123 WL18XX_CONF_HW_RXTX_RATE_MCS14, 124 WL18XX_CONF_HW_RXTX_RATE_MCS13, 125 WL18XX_CONF_HW_RXTX_RATE_MCS12, 126 WL18XX_CONF_HW_RXTX_RATE_MCS11, 127 WL18XX_CONF_HW_RXTX_RATE_MCS10, 128 WL18XX_CONF_HW_RXTX_RATE_MCS9, 129 WL18XX_CONF_HW_RXTX_RATE_MCS8, 130 WL18XX_CONF_HW_RXTX_RATE_MCS7, 131 WL18XX_CONF_HW_RXTX_RATE_MCS6, 132 WL18XX_CONF_HW_RXTX_RATE_MCS5, 133 WL18XX_CONF_HW_RXTX_RATE_MCS4, 134 WL18XX_CONF_HW_RXTX_RATE_MCS3, 135 WL18XX_CONF_HW_RXTX_RATE_MCS2, 136 WL18XX_CONF_HW_RXTX_RATE_MCS1, 137 WL18XX_CONF_HW_RXTX_RATE_MCS0, 138 WL18XX_CONF_HW_RXTX_RATE_54, 139 WL18XX_CONF_HW_RXTX_RATE_48, 140 WL18XX_CONF_HW_RXTX_RATE_36, 141 WL18XX_CONF_HW_RXTX_RATE_24, 142 WL18XX_CONF_HW_RXTX_RATE_22, 143 WL18XX_CONF_HW_RXTX_RATE_18, 144 WL18XX_CONF_HW_RXTX_RATE_12, 145 WL18XX_CONF_HW_RXTX_RATE_11, 146 WL18XX_CONF_HW_RXTX_RATE_9, 147 WL18XX_CONF_HW_RXTX_RATE_6, 148 WL18XX_CONF_HW_RXTX_RATE_5_5, 149 WL18XX_CONF_HW_RXTX_RATE_2, 150 WL18XX_CONF_HW_RXTX_RATE_1, 151 WL18XX_CONF_HW_RXTX_RATE_MAX, 152 }; 153 154 static struct wl18xx_conf wl18xx_default_conf = { 155 .phy = { 156 .phy_standalone = 0x00, 157 .primary_clock_setting_time = 0x05, 158 .clock_valid_on_wake_up = 0x00, 159 .secondary_clock_setting_time = 0x05, 160 .rdl = 0x01, 161 .auto_detect = 0x00, 162 .dedicated_fem = FEM_NONE, 163 .low_band_component = COMPONENT_2_WAY_SWITCH, 164 .low_band_component_type = 0x05, 165 .high_band_component = COMPONENT_2_WAY_SWITCH, 166 .high_band_component_type = 0x09, 167 .number_of_assembled_ant2_4 = 0x01, 168 .number_of_assembled_ant5 = 0x01, 169 .external_pa_dc2dc = 0x00, 170 .tcxo_ldo_voltage = 0x00, 171 .xtal_itrim_val = 0x04, 172 .srf_state = 0x00, 173 .io_configuration = 0x01, 174 .sdio_configuration = 0x00, 175 .settings = 0x00, 176 .enable_clpc = 0x00, 177 .enable_tx_low_pwr_on_siso_rdl = 0x00, 178 .rx_profile = 0x00, 179 }, 180 }; 181 182 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = { 183 [PART_TOP_PRCM_ELP_SOC] = { 184 .mem = { .start = 0x00A02000, .size = 0x00010000 }, 185 .reg = { .start = 0x00807000, .size = 0x00005000 }, 186 .mem2 = { .start = 0x00800000, .size = 0x0000B000 }, 187 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 188 }, 189 [PART_DOWN] = { 190 .mem = { .start = 0x00000000, .size = 0x00014000 }, 191 .reg = { .start = 0x00810000, .size = 0x0000BFFF }, 192 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 193 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 194 }, 195 [PART_BOOT] = { 196 .mem = { .start = 0x00700000, .size = 0x0000030c }, 197 .reg = { .start = 0x00802000, .size = 0x00014578 }, 198 .mem2 = { .start = 0x00B00404, .size = 0x00001000 }, 199 .mem3 = { .start = 0x00C00000, .size = 0x00000400 }, 200 }, 201 [PART_WORK] = { 202 .mem = { .start = 0x00800000, .size = 0x000050FC }, 203 .reg = { .start = 0x00B00404, .size = 0x00001000 }, 204 .mem2 = { .start = 0x00C00000, .size = 0x00000400 }, 205 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 206 }, 207 [PART_PHY_INIT] = { 208 /* TODO: use the phy_conf struct size here */ 209 .mem = { .start = 0x80926000, .size = 252 }, 210 .reg = { .start = 0x00000000, .size = 0x00000000 }, 211 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 212 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 213 }, 214 }; 215 216 static const int wl18xx_rtable[REG_TABLE_LEN] = { 217 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL, 218 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR, 219 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK, 220 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR, 221 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR, 222 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H, 223 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK, 224 [REG_PC_ON_RECOVERY] = 0, /* TODO: where is the PC? */ 225 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B, 226 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS, 227 228 /* data access memory addresses, used with partition translation */ 229 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA, 230 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA, 231 232 /* raw data access memory addresses */ 233 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR, 234 }; 235 236 /* TODO: maybe move to a new header file? */ 237 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin" 238 239 static int wl18xx_identify_chip(struct wl1271 *wl) 240 { 241 int ret = 0; 242 243 switch (wl->chip.id) { 244 case CHIP_ID_185x_PG10: 245 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)", 246 wl->chip.id); 247 wl->sr_fw_name = WL18XX_FW_NAME; 248 wl->quirks |= WLCORE_QUIRK_NO_ELP | 249 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN; 250 251 /* TODO: need to blocksize alignment for RX/TX separately? */ 252 break; 253 default: 254 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); 255 ret = -ENODEV; 256 goto out; 257 } 258 259 out: 260 return ret; 261 } 262 263 static void wl18xx_set_clk(struct wl1271 *wl) 264 { 265 /* 266 * TODO: this is hardcoded just for DVP/EVB, fix according to 267 * new unified_drv. 268 */ 269 wl1271_write32(wl, WL18XX_SCR_PAD2, 0xB3); 270 271 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 272 wl1271_write32(wl, 0x00A02360, 0xD0078); 273 wl1271_write32(wl, 0x00A0236c, 0x12); 274 wl1271_write32(wl, 0x00A02390, 0x20118); 275 } 276 277 static void wl18xx_boot_soft_reset(struct wl1271 *wl) 278 { 279 /* disable Rx/Tx */ 280 wl1271_write32(wl, WL18XX_ENABLE, 0x0); 281 282 /* disable auto calibration on start*/ 283 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff); 284 } 285 286 static int wl18xx_pre_boot(struct wl1271 *wl) 287 { 288 /* TODO: add hw_pg_ver reading */ 289 290 wl18xx_set_clk(wl); 291 292 /* Continue the ELP wake up sequence */ 293 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 294 udelay(500); 295 296 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 297 298 /* Disable interrupts */ 299 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 300 301 wl18xx_boot_soft_reset(wl); 302 303 return 0; 304 } 305 306 static void wl18xx_pre_upload(struct wl1271 *wl) 307 { 308 u32 tmp; 309 310 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 311 312 /* TODO: check if this is all needed */ 313 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); 314 315 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B); 316 317 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 318 319 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2); 320 } 321 322 static void wl18xx_set_mac_and_phy(struct wl1271 *wl) 323 { 324 struct wl18xx_mac_and_phy_params params; 325 326 memset(¶ms, 0, sizeof(params)); 327 328 params.phy_standalone = wl18xx_default_conf.phy.phy_standalone; 329 params.rdl = wl18xx_default_conf.phy.rdl; 330 params.enable_clpc = wl18xx_default_conf.phy.enable_clpc; 331 params.enable_tx_low_pwr_on_siso_rdl = 332 wl18xx_default_conf.phy.enable_tx_low_pwr_on_siso_rdl; 333 params.auto_detect = wl18xx_default_conf.phy.auto_detect; 334 params.dedicated_fem = wl18xx_default_conf.phy.dedicated_fem; 335 params.low_band_component = wl18xx_default_conf.phy.low_band_component; 336 params.low_band_component_type = 337 wl18xx_default_conf.phy.low_band_component_type; 338 params.high_band_component = 339 wl18xx_default_conf.phy.high_band_component; 340 params.high_band_component_type = 341 wl18xx_default_conf.phy.high_band_component_type; 342 params.number_of_assembled_ant2_4 = 343 wl18xx_default_conf.phy.number_of_assembled_ant2_4; 344 params.number_of_assembled_ant5 = 345 wl18xx_default_conf.phy.number_of_assembled_ant5; 346 params.external_pa_dc2dc = wl18xx_default_conf.phy.external_pa_dc2dc; 347 params.tcxo_ldo_voltage = wl18xx_default_conf.phy.tcxo_ldo_voltage; 348 params.xtal_itrim_val = wl18xx_default_conf.phy.xtal_itrim_val; 349 params.srf_state = wl18xx_default_conf.phy.srf_state; 350 params.io_configuration = wl18xx_default_conf.phy.io_configuration; 351 params.sdio_configuration = wl18xx_default_conf.phy.sdio_configuration; 352 params.settings = wl18xx_default_conf.phy.settings; 353 params.rx_profile = wl18xx_default_conf.phy.rx_profile; 354 params.primary_clock_setting_time = 355 wl18xx_default_conf.phy.primary_clock_setting_time; 356 params.clock_valid_on_wake_up = 357 wl18xx_default_conf.phy.clock_valid_on_wake_up; 358 params.secondary_clock_setting_time = 359 wl18xx_default_conf.phy.secondary_clock_setting_time; 360 361 /* TODO: hardcoded for now */ 362 params.board_type = BOARD_TYPE_DVP_EVB_18XX; 363 364 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); 365 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms, 366 sizeof(params), false); 367 } 368 369 static void wl18xx_enable_interrupts(struct wl1271 *wl) 370 { 371 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR); 372 373 wlcore_enable_interrupts(wl); 374 wlcore_write_reg(wl, REG_INTERRUPT_MASK, 375 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); 376 } 377 378 static int wl18xx_boot(struct wl1271 *wl) 379 { 380 int ret; 381 382 ret = wl18xx_pre_boot(wl); 383 if (ret < 0) 384 goto out; 385 386 ret = wlcore_boot_upload_nvs(wl); 387 if (ret < 0) 388 goto out; 389 390 wl18xx_pre_upload(wl); 391 392 ret = wlcore_boot_upload_firmware(wl); 393 if (ret < 0) 394 goto out; 395 396 wl18xx_set_mac_and_phy(wl); 397 398 ret = wlcore_boot_run_firmware(wl); 399 if (ret < 0) 400 goto out; 401 402 wl18xx_enable_interrupts(wl); 403 404 out: 405 return ret; 406 } 407 408 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, 409 void *buf, size_t len) 410 { 411 struct wl18xx_priv *priv = wl->priv; 412 413 memcpy(priv->cmd_buf, buf, len); 414 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len); 415 416 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE, 417 false); 418 } 419 420 static void wl18xx_ack_event(struct wl1271 *wl) 421 { 422 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK); 423 } 424 425 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) 426 { 427 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE; 428 return (len + blk_size - 1) / blk_size + spare_blks; 429 } 430 431 static void 432 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 433 u32 blks, u32 spare_blks) 434 { 435 desc->wl18xx_mem.total_mem_blocks = blks; 436 desc->wl18xx_mem.reserved = 0; 437 } 438 439 static void 440 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 441 struct sk_buff *skb) 442 { 443 desc->length = cpu_to_le16(skb->len); 444 445 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d " 446 "len: %d life: %d mem: %d", desc->hlid, 447 le16_to_cpu(desc->length), 448 le16_to_cpu(desc->life_time), 449 desc->wl18xx_mem.total_mem_blocks); 450 } 451 452 static enum wl_rx_buf_align 453 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc) 454 { 455 if (rx_desc & RX_BUF_PADDED_PAYLOAD) 456 return WLCORE_RX_BUF_PADDED; 457 458 return WLCORE_RX_BUF_ALIGNED; 459 } 460 461 462 static struct wlcore_ops wl18xx_ops = { 463 .identify_chip = wl18xx_identify_chip, 464 .boot = wl18xx_boot, 465 .trigger_cmd = wl18xx_trigger_cmd, 466 .ack_event = wl18xx_ack_event, 467 .calc_tx_blocks = wl18xx_calc_tx_blocks, 468 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks, 469 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len, 470 .get_rx_buf_align = wl18xx_get_rx_buf_align, 471 }; 472 473 int __devinit wl18xx_probe(struct platform_device *pdev) 474 { 475 struct wl1271 *wl; 476 struct ieee80211_hw *hw; 477 struct wl18xx_priv *priv; 478 479 hw = wlcore_alloc_hw(sizeof(*priv)); 480 if (IS_ERR(hw)) { 481 wl1271_error("can't allocate hw"); 482 return PTR_ERR(hw); 483 } 484 485 wl = hw->priv; 486 wl->ops = &wl18xx_ops; 487 wl->ptable = wl18xx_ptable; 488 wl->rtable = wl18xx_rtable; 489 wl->num_tx_desc = 32; 490 wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE; 491 wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE; 492 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; 493 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; 494 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; 495 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); 496 return wlcore_probe(wl, pdev); 497 } 498 499 static const struct platform_device_id wl18xx_id_table[] __devinitconst = { 500 { "wl18xx", 0 }, 501 { } /* Terminating Entry */ 502 }; 503 MODULE_DEVICE_TABLE(platform, wl18xx_id_table); 504 505 static struct platform_driver wl18xx_driver = { 506 .probe = wl18xx_probe, 507 .remove = __devexit_p(wlcore_remove), 508 .id_table = wl18xx_id_table, 509 .driver = { 510 .name = "wl18xx_driver", 511 .owner = THIS_MODULE, 512 } 513 }; 514 515 static int __init wl18xx_init(void) 516 { 517 return platform_driver_register(&wl18xx_driver); 518 } 519 module_init(wl18xx_init); 520 521 static void __exit wl18xx_exit(void) 522 { 523 platform_driver_unregister(&wl18xx_driver); 524 } 525 module_exit(wl18xx_exit); 526 527 MODULE_LICENSE("GPL v2"); 528 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>"); 529 MODULE_FIRMWARE(WL18XX_FW_NAME); 530