1 /* 2 * This file is part of wl18xx 3 * 4 * Copyright (C) 2011 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 25 #include "../wlcore/wlcore.h" 26 #include "../wlcore/debug.h" 27 #include "../wlcore/io.h" 28 #include "../wlcore/acx.h" 29 #include "../wlcore/tx.h" 30 #include "../wlcore/boot.h" 31 32 #include "reg.h" 33 #include "conf.h" 34 #include "wl18xx.h" 35 36 #define WL18XX_TX_HW_BLOCK_SPARE 1 37 #define WL18XX_TX_HW_GEM_BLOCK_SPARE 2 38 #define WL18XX_TX_HW_BLOCK_SIZE 268 39 40 static const u8 wl18xx_rate_to_idx_2ghz[] = { 41 /* MCS rates are used only with 11n */ 42 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 43 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 44 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 45 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 46 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 47 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 48 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 49 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 50 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 51 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 52 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 53 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 54 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 55 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 56 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 57 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 58 59 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 60 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 61 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 62 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 63 64 /* TI-specific rate */ 65 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 66 67 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 68 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 69 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 70 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 71 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 72 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 73 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 74 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */ 75 }; 76 77 static const u8 wl18xx_rate_to_idx_5ghz[] = { 78 /* MCS rates are used only with 11n */ 79 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 80 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 81 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 82 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 83 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 84 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 85 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 86 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 87 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 88 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 89 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 90 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 91 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 92 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 93 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 94 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 95 96 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 97 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 98 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 99 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 100 101 /* TI-specific rate */ 102 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 103 104 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 105 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 106 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 107 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 108 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 109 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 110 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 111 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */ 112 }; 113 114 static const u8 *wl18xx_band_rate_to_idx[] = { 115 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz, 116 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz 117 }; 118 119 enum wl18xx_hw_rates { 120 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0, 121 WL18XX_CONF_HW_RXTX_RATE_MCS14, 122 WL18XX_CONF_HW_RXTX_RATE_MCS13, 123 WL18XX_CONF_HW_RXTX_RATE_MCS12, 124 WL18XX_CONF_HW_RXTX_RATE_MCS11, 125 WL18XX_CONF_HW_RXTX_RATE_MCS10, 126 WL18XX_CONF_HW_RXTX_RATE_MCS9, 127 WL18XX_CONF_HW_RXTX_RATE_MCS8, 128 WL18XX_CONF_HW_RXTX_RATE_MCS7, 129 WL18XX_CONF_HW_RXTX_RATE_MCS6, 130 WL18XX_CONF_HW_RXTX_RATE_MCS5, 131 WL18XX_CONF_HW_RXTX_RATE_MCS4, 132 WL18XX_CONF_HW_RXTX_RATE_MCS3, 133 WL18XX_CONF_HW_RXTX_RATE_MCS2, 134 WL18XX_CONF_HW_RXTX_RATE_MCS1, 135 WL18XX_CONF_HW_RXTX_RATE_MCS0, 136 WL18XX_CONF_HW_RXTX_RATE_54, 137 WL18XX_CONF_HW_RXTX_RATE_48, 138 WL18XX_CONF_HW_RXTX_RATE_36, 139 WL18XX_CONF_HW_RXTX_RATE_24, 140 WL18XX_CONF_HW_RXTX_RATE_22, 141 WL18XX_CONF_HW_RXTX_RATE_18, 142 WL18XX_CONF_HW_RXTX_RATE_12, 143 WL18XX_CONF_HW_RXTX_RATE_11, 144 WL18XX_CONF_HW_RXTX_RATE_9, 145 WL18XX_CONF_HW_RXTX_RATE_6, 146 WL18XX_CONF_HW_RXTX_RATE_5_5, 147 WL18XX_CONF_HW_RXTX_RATE_2, 148 WL18XX_CONF_HW_RXTX_RATE_1, 149 WL18XX_CONF_HW_RXTX_RATE_MAX, 150 }; 151 152 static struct wl18xx_conf wl18xx_default_conf = { 153 .phy = { 154 .phy_standalone = 0x00, 155 .primary_clock_setting_time = 0x05, 156 .clock_valid_on_wake_up = 0x00, 157 .secondary_clock_setting_time = 0x05, 158 .rdl = 0x01, 159 .auto_detect = 0x00, 160 .dedicated_fem = FEM_NONE, 161 .low_band_component = COMPONENT_2_WAY_SWITCH, 162 .low_band_component_type = 0x05, 163 .high_band_component = COMPONENT_2_WAY_SWITCH, 164 .high_band_component_type = 0x09, 165 .number_of_assembled_ant2_4 = 0x01, 166 .number_of_assembled_ant5 = 0x01, 167 .external_pa_dc2dc = 0x00, 168 .tcxo_ldo_voltage = 0x00, 169 .xtal_itrim_val = 0x04, 170 .srf_state = 0x00, 171 .io_configuration = 0x01, 172 .sdio_configuration = 0x00, 173 .settings = 0x00, 174 .enable_clpc = 0x00, 175 .enable_tx_low_pwr_on_siso_rdl = 0x00, 176 .rx_profile = 0x00, 177 }, 178 }; 179 180 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = { 181 [PART_TOP_PRCM_ELP_SOC] = { 182 .mem = { .start = 0x00A02000, .size = 0x00010000 }, 183 .reg = { .start = 0x00807000, .size = 0x00005000 }, 184 .mem2 = { .start = 0x00800000, .size = 0x0000B000 }, 185 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 186 }, 187 [PART_DOWN] = { 188 .mem = { .start = 0x00000000, .size = 0x00014000 }, 189 .reg = { .start = 0x00810000, .size = 0x0000BFFF }, 190 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 191 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 192 }, 193 [PART_BOOT] = { 194 .mem = { .start = 0x00700000, .size = 0x0000030c }, 195 .reg = { .start = 0x00802000, .size = 0x00014578 }, 196 .mem2 = { .start = 0x00B00404, .size = 0x00001000 }, 197 .mem3 = { .start = 0x00C00000, .size = 0x00000400 }, 198 }, 199 [PART_WORK] = { 200 .mem = { .start = 0x00800000, .size = 0x000050FC }, 201 .reg = { .start = 0x00B00404, .size = 0x00001000 }, 202 .mem2 = { .start = 0x00C00000, .size = 0x00000400 }, 203 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 204 }, 205 [PART_PHY_INIT] = { 206 /* TODO: use the phy_conf struct size here */ 207 .mem = { .start = 0x80926000, .size = 252 }, 208 .reg = { .start = 0x00000000, .size = 0x00000000 }, 209 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 210 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 211 }, 212 }; 213 214 static const int wl18xx_rtable[REG_TABLE_LEN] = { 215 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL, 216 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR, 217 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK, 218 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR, 219 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR, 220 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H, 221 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK, 222 [REG_PC_ON_RECOVERY] = 0, /* TODO: where is the PC? */ 223 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B, 224 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS, 225 226 /* data access memory addresses, used with partition translation */ 227 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA, 228 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA, 229 230 /* raw data access memory addresses */ 231 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR, 232 }; 233 234 /* TODO: maybe move to a new header file? */ 235 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin" 236 237 static int wl18xx_identify_chip(struct wl1271 *wl) 238 { 239 int ret = 0; 240 241 switch (wl->chip.id) { 242 case CHIP_ID_185x_PG10: 243 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)", 244 wl->chip.id); 245 wl->sr_fw_name = WL18XX_FW_NAME; 246 wl->quirks |= WLCORE_QUIRK_NO_ELP | 247 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN; 248 249 /* TODO: need to blocksize alignment for RX/TX separately? */ 250 break; 251 default: 252 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); 253 ret = -ENODEV; 254 goto out; 255 } 256 257 out: 258 return ret; 259 } 260 261 static void wl18xx_set_clk(struct wl1271 *wl) 262 { 263 /* 264 * TODO: this is hardcoded just for DVP/EVB, fix according to 265 * new unified_drv. 266 */ 267 wl1271_write32(wl, WL18XX_SCR_PAD2, 0xB3); 268 269 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 270 wl1271_write32(wl, 0x00A02360, 0xD0078); 271 wl1271_write32(wl, 0x00A0236c, 0x12); 272 wl1271_write32(wl, 0x00A02390, 0x20118); 273 } 274 275 static void wl18xx_boot_soft_reset(struct wl1271 *wl) 276 { 277 /* disable Rx/Tx */ 278 wl1271_write32(wl, WL18XX_ENABLE, 0x0); 279 280 /* disable auto calibration on start*/ 281 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff); 282 } 283 284 static int wl18xx_pre_boot(struct wl1271 *wl) 285 { 286 /* TODO: add hw_pg_ver reading */ 287 288 wl18xx_set_clk(wl); 289 290 /* Continue the ELP wake up sequence */ 291 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 292 udelay(500); 293 294 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 295 296 /* Disable interrupts */ 297 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 298 299 wl18xx_boot_soft_reset(wl); 300 301 return 0; 302 } 303 304 static void wl18xx_pre_upload(struct wl1271 *wl) 305 { 306 u32 tmp; 307 308 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 309 310 /* TODO: check if this is all needed */ 311 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); 312 313 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B); 314 315 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 316 317 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2); 318 } 319 320 static void wl18xx_set_mac_and_phy(struct wl1271 *wl) 321 { 322 struct wl18xx_mac_and_phy_params params; 323 324 memset(¶ms, 0, sizeof(params)); 325 326 params.phy_standalone = wl18xx_default_conf.phy.phy_standalone; 327 params.rdl = wl18xx_default_conf.phy.rdl; 328 params.enable_clpc = wl18xx_default_conf.phy.enable_clpc; 329 params.enable_tx_low_pwr_on_siso_rdl = 330 wl18xx_default_conf.phy.enable_tx_low_pwr_on_siso_rdl; 331 params.auto_detect = wl18xx_default_conf.phy.auto_detect; 332 params.dedicated_fem = wl18xx_default_conf.phy.dedicated_fem; 333 params.low_band_component = wl18xx_default_conf.phy.low_band_component; 334 params.low_band_component_type = 335 wl18xx_default_conf.phy.low_band_component_type; 336 params.high_band_component = 337 wl18xx_default_conf.phy.high_band_component; 338 params.high_band_component_type = 339 wl18xx_default_conf.phy.high_band_component_type; 340 params.number_of_assembled_ant2_4 = 341 wl18xx_default_conf.phy.number_of_assembled_ant2_4; 342 params.number_of_assembled_ant5 = 343 wl18xx_default_conf.phy.number_of_assembled_ant5; 344 params.external_pa_dc2dc = wl18xx_default_conf.phy.external_pa_dc2dc; 345 params.tcxo_ldo_voltage = wl18xx_default_conf.phy.tcxo_ldo_voltage; 346 params.xtal_itrim_val = wl18xx_default_conf.phy.xtal_itrim_val; 347 params.srf_state = wl18xx_default_conf.phy.srf_state; 348 params.io_configuration = wl18xx_default_conf.phy.io_configuration; 349 params.sdio_configuration = wl18xx_default_conf.phy.sdio_configuration; 350 params.settings = wl18xx_default_conf.phy.settings; 351 params.rx_profile = wl18xx_default_conf.phy.rx_profile; 352 params.primary_clock_setting_time = 353 wl18xx_default_conf.phy.primary_clock_setting_time; 354 params.clock_valid_on_wake_up = 355 wl18xx_default_conf.phy.clock_valid_on_wake_up; 356 params.secondary_clock_setting_time = 357 wl18xx_default_conf.phy.secondary_clock_setting_time; 358 359 /* TODO: hardcoded for now */ 360 params.board_type = BOARD_TYPE_DVP_EVB_18XX; 361 362 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); 363 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms, 364 sizeof(params), false); 365 } 366 367 static void wl18xx_enable_interrupts(struct wl1271 *wl) 368 { 369 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR); 370 371 wlcore_enable_interrupts(wl); 372 wlcore_write_reg(wl, REG_INTERRUPT_MASK, 373 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); 374 } 375 376 static int wl18xx_boot(struct wl1271 *wl) 377 { 378 int ret; 379 380 ret = wl18xx_pre_boot(wl); 381 if (ret < 0) 382 goto out; 383 384 ret = wlcore_boot_upload_nvs(wl); 385 if (ret < 0) 386 goto out; 387 388 wl18xx_pre_upload(wl); 389 390 ret = wlcore_boot_upload_firmware(wl); 391 if (ret < 0) 392 goto out; 393 394 wl18xx_set_mac_and_phy(wl); 395 396 ret = wlcore_boot_run_firmware(wl); 397 if (ret < 0) 398 goto out; 399 400 wl18xx_enable_interrupts(wl); 401 402 out: 403 return ret; 404 } 405 406 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, 407 void *buf, size_t len) 408 { 409 struct wl18xx_priv *priv = wl->priv; 410 411 memcpy(priv->cmd_buf, buf, len); 412 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len); 413 414 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE, 415 false); 416 } 417 418 static void wl18xx_ack_event(struct wl1271 *wl) 419 { 420 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK); 421 } 422 423 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) 424 { 425 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE; 426 return (len + blk_size - 1) / blk_size + spare_blks; 427 } 428 429 static void 430 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 431 u32 blks, u32 spare_blks) 432 { 433 desc->wl18xx_mem.total_mem_blocks = blks; 434 desc->wl18xx_mem.reserved = 0; 435 } 436 437 static void 438 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 439 struct sk_buff *skb) 440 { 441 desc->length = cpu_to_le16(skb->len); 442 443 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d " 444 "len: %d life: %d mem: %d", desc->hlid, 445 le16_to_cpu(desc->length), 446 le16_to_cpu(desc->life_time), 447 desc->wl18xx_mem.total_mem_blocks); 448 } 449 450 static struct wlcore_ops wl18xx_ops = { 451 .identify_chip = wl18xx_identify_chip, 452 .boot = wl18xx_boot, 453 .trigger_cmd = wl18xx_trigger_cmd, 454 .ack_event = wl18xx_ack_event, 455 .calc_tx_blocks = wl18xx_calc_tx_blocks, 456 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks, 457 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len, 458 }; 459 460 int __devinit wl18xx_probe(struct platform_device *pdev) 461 { 462 struct wl1271 *wl; 463 struct ieee80211_hw *hw; 464 struct wl18xx_priv *priv; 465 466 hw = wlcore_alloc_hw(sizeof(*priv)); 467 if (IS_ERR(hw)) { 468 wl1271_error("can't allocate hw"); 469 return PTR_ERR(hw); 470 } 471 472 wl = hw->priv; 473 wl->ops = &wl18xx_ops; 474 wl->ptable = wl18xx_ptable; 475 wl->rtable = wl18xx_rtable; 476 wl->num_tx_desc = 32; 477 wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE; 478 wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE; 479 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; 480 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; 481 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; 482 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); 483 return wlcore_probe(wl, pdev); 484 } 485 486 static const struct platform_device_id wl18xx_id_table[] __devinitconst = { 487 { "wl18xx", 0 }, 488 { } /* Terminating Entry */ 489 }; 490 MODULE_DEVICE_TABLE(platform, wl18xx_id_table); 491 492 static struct platform_driver wl18xx_driver = { 493 .probe = wl18xx_probe, 494 .remove = __devexit_p(wlcore_remove), 495 .id_table = wl18xx_id_table, 496 .driver = { 497 .name = "wl18xx_driver", 498 .owner = THIS_MODULE, 499 } 500 }; 501 502 static int __init wl18xx_init(void) 503 { 504 return platform_driver_register(&wl18xx_driver); 505 } 506 module_init(wl18xx_init); 507 508 static void __exit wl18xx_exit(void) 509 { 510 platform_driver_unregister(&wl18xx_driver); 511 } 512 module_exit(wl18xx_exit); 513 514 MODULE_LICENSE("GPL v2"); 515 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>"); 516 MODULE_FIRMWARE(WL18XX_FW_NAME); 517