1 /* 2 * This file is part of wl18xx 3 * 4 * Copyright (C) 2011 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/ip.h> 25 #include <linux/firmware.h> 26 27 #include "../wlcore/wlcore.h" 28 #include "../wlcore/debug.h" 29 #include "../wlcore/io.h" 30 #include "../wlcore/acx.h" 31 #include "../wlcore/tx.h" 32 #include "../wlcore/rx.h" 33 #include "../wlcore/io.h" 34 #include "../wlcore/boot.h" 35 36 #include "reg.h" 37 #include "conf.h" 38 #include "acx.h" 39 #include "tx.h" 40 #include "wl18xx.h" 41 #include "io.h" 42 #include "debugfs.h" 43 44 #define WL18XX_RX_CHECKSUM_MASK 0x40 45 46 static char *ht_mode_param = NULL; 47 static char *board_type_param = NULL; 48 static bool checksum_param = false; 49 static bool enable_11a_param = true; 50 static int num_rx_desc_param = -1; 51 52 /* phy paramters */ 53 static int dc2dc_param = -1; 54 static int n_antennas_2_param = -1; 55 static int n_antennas_5_param = -1; 56 static int low_band_component_param = -1; 57 static int low_band_component_type_param = -1; 58 static int high_band_component_param = -1; 59 static int high_band_component_type_param = -1; 60 static int pwr_limit_reference_11_abg_param = -1; 61 62 static const u8 wl18xx_rate_to_idx_2ghz[] = { 63 /* MCS rates are used only with 11n */ 64 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 65 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 66 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 67 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 68 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 69 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 70 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 71 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 72 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 73 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 74 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 75 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 76 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 77 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 78 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 79 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 80 81 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 82 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 83 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 84 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 85 86 /* TI-specific rate */ 87 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 88 89 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 90 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 91 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 92 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 93 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 94 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 95 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 96 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */ 97 }; 98 99 static const u8 wl18xx_rate_to_idx_5ghz[] = { 100 /* MCS rates are used only with 11n */ 101 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */ 102 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */ 103 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */ 104 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */ 105 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */ 106 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */ 107 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */ 108 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */ 109 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */ 110 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */ 111 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */ 112 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */ 113 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */ 114 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */ 115 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */ 116 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */ 117 118 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */ 119 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */ 120 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */ 121 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */ 122 123 /* TI-specific rate */ 124 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */ 125 126 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */ 127 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */ 128 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */ 129 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */ 130 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */ 131 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */ 132 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */ 133 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */ 134 }; 135 136 static const u8 *wl18xx_band_rate_to_idx[] = { 137 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz, 138 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz 139 }; 140 141 enum wl18xx_hw_rates { 142 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0, 143 WL18XX_CONF_HW_RXTX_RATE_MCS14, 144 WL18XX_CONF_HW_RXTX_RATE_MCS13, 145 WL18XX_CONF_HW_RXTX_RATE_MCS12, 146 WL18XX_CONF_HW_RXTX_RATE_MCS11, 147 WL18XX_CONF_HW_RXTX_RATE_MCS10, 148 WL18XX_CONF_HW_RXTX_RATE_MCS9, 149 WL18XX_CONF_HW_RXTX_RATE_MCS8, 150 WL18XX_CONF_HW_RXTX_RATE_MCS7, 151 WL18XX_CONF_HW_RXTX_RATE_MCS6, 152 WL18XX_CONF_HW_RXTX_RATE_MCS5, 153 WL18XX_CONF_HW_RXTX_RATE_MCS4, 154 WL18XX_CONF_HW_RXTX_RATE_MCS3, 155 WL18XX_CONF_HW_RXTX_RATE_MCS2, 156 WL18XX_CONF_HW_RXTX_RATE_MCS1, 157 WL18XX_CONF_HW_RXTX_RATE_MCS0, 158 WL18XX_CONF_HW_RXTX_RATE_54, 159 WL18XX_CONF_HW_RXTX_RATE_48, 160 WL18XX_CONF_HW_RXTX_RATE_36, 161 WL18XX_CONF_HW_RXTX_RATE_24, 162 WL18XX_CONF_HW_RXTX_RATE_22, 163 WL18XX_CONF_HW_RXTX_RATE_18, 164 WL18XX_CONF_HW_RXTX_RATE_12, 165 WL18XX_CONF_HW_RXTX_RATE_11, 166 WL18XX_CONF_HW_RXTX_RATE_9, 167 WL18XX_CONF_HW_RXTX_RATE_6, 168 WL18XX_CONF_HW_RXTX_RATE_5_5, 169 WL18XX_CONF_HW_RXTX_RATE_2, 170 WL18XX_CONF_HW_RXTX_RATE_1, 171 WL18XX_CONF_HW_RXTX_RATE_MAX, 172 }; 173 174 static struct wlcore_conf wl18xx_conf = { 175 .sg = { 176 .params = { 177 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10, 178 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180, 179 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10, 180 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180, 181 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10, 182 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80, 183 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10, 184 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80, 185 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8, 186 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8, 187 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20, 188 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20, 189 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20, 190 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35, 191 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16, 192 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35, 193 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32, 194 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50, 195 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28, 196 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50, 197 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10, 198 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20, 199 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75, 200 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15, 201 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27, 202 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17, 203 /* active scan params */ 204 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170, 205 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50, 206 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100, 207 /* passive scan params */ 208 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800, 209 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200, 210 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200, 211 /* passive scan in dual antenna params */ 212 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0, 213 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0, 214 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0, 215 /* general params */ 216 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1, 217 [CONF_SG_ANTENNA_CONFIGURATION] = 0, 218 [CONF_SG_BEACON_MISS_PERCENT] = 60, 219 [CONF_SG_DHCP_TIME] = 5000, 220 [CONF_SG_RXT] = 1200, 221 [CONF_SG_TXT] = 1000, 222 [CONF_SG_ADAPTIVE_RXT_TXT] = 1, 223 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3, 224 [CONF_SG_HV3_MAX_SERVED] = 6, 225 [CONF_SG_PS_POLL_TIMEOUT] = 10, 226 [CONF_SG_UPSD_TIMEOUT] = 10, 227 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2, 228 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5, 229 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30, 230 /* AP params */ 231 [CONF_AP_BEACON_MISS_TX] = 3, 232 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10, 233 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2, 234 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0, 235 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25, 236 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25, 237 /* CTS Diluting params */ 238 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0, 239 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0, 240 }, 241 .state = CONF_SG_PROTECTIVE, 242 }, 243 .rx = { 244 .rx_msdu_life_time = 512000, 245 .packet_detection_threshold = 0, 246 .ps_poll_timeout = 15, 247 .upsd_timeout = 15, 248 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD, 249 .rx_cca_threshold = 0, 250 .irq_blk_threshold = 0xFFFF, 251 .irq_pkt_threshold = 0, 252 .irq_timeout = 600, 253 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY, 254 }, 255 .tx = { 256 .tx_energy_detection = 0, 257 .sta_rc_conf = { 258 .enabled_rates = 0, 259 .short_retry_limit = 10, 260 .long_retry_limit = 10, 261 .aflags = 0, 262 }, 263 .ac_conf_count = 4, 264 .ac_conf = { 265 [CONF_TX_AC_BE] = { 266 .ac = CONF_TX_AC_BE, 267 .cw_min = 15, 268 .cw_max = 63, 269 .aifsn = 3, 270 .tx_op_limit = 0, 271 }, 272 [CONF_TX_AC_BK] = { 273 .ac = CONF_TX_AC_BK, 274 .cw_min = 15, 275 .cw_max = 63, 276 .aifsn = 7, 277 .tx_op_limit = 0, 278 }, 279 [CONF_TX_AC_VI] = { 280 .ac = CONF_TX_AC_VI, 281 .cw_min = 15, 282 .cw_max = 63, 283 .aifsn = CONF_TX_AIFS_PIFS, 284 .tx_op_limit = 3008, 285 }, 286 [CONF_TX_AC_VO] = { 287 .ac = CONF_TX_AC_VO, 288 .cw_min = 15, 289 .cw_max = 63, 290 .aifsn = CONF_TX_AIFS_PIFS, 291 .tx_op_limit = 1504, 292 }, 293 }, 294 .max_tx_retries = 100, 295 .ap_aging_period = 300, 296 .tid_conf_count = 4, 297 .tid_conf = { 298 [CONF_TX_AC_BE] = { 299 .queue_id = CONF_TX_AC_BE, 300 .channel_type = CONF_CHANNEL_TYPE_EDCF, 301 .tsid = CONF_TX_AC_BE, 302 .ps_scheme = CONF_PS_SCHEME_LEGACY, 303 .ack_policy = CONF_ACK_POLICY_LEGACY, 304 .apsd_conf = {0, 0}, 305 }, 306 [CONF_TX_AC_BK] = { 307 .queue_id = CONF_TX_AC_BK, 308 .channel_type = CONF_CHANNEL_TYPE_EDCF, 309 .tsid = CONF_TX_AC_BK, 310 .ps_scheme = CONF_PS_SCHEME_LEGACY, 311 .ack_policy = CONF_ACK_POLICY_LEGACY, 312 .apsd_conf = {0, 0}, 313 }, 314 [CONF_TX_AC_VI] = { 315 .queue_id = CONF_TX_AC_VI, 316 .channel_type = CONF_CHANNEL_TYPE_EDCF, 317 .tsid = CONF_TX_AC_VI, 318 .ps_scheme = CONF_PS_SCHEME_LEGACY, 319 .ack_policy = CONF_ACK_POLICY_LEGACY, 320 .apsd_conf = {0, 0}, 321 }, 322 [CONF_TX_AC_VO] = { 323 .queue_id = CONF_TX_AC_VO, 324 .channel_type = CONF_CHANNEL_TYPE_EDCF, 325 .tsid = CONF_TX_AC_VO, 326 .ps_scheme = CONF_PS_SCHEME_LEGACY, 327 .ack_policy = CONF_ACK_POLICY_LEGACY, 328 .apsd_conf = {0, 0}, 329 }, 330 }, 331 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD, 332 .tx_compl_timeout = 350, 333 .tx_compl_threshold = 10, 334 .basic_rate = CONF_HW_BIT_RATE_1MBPS, 335 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS, 336 .tmpl_short_retry_limit = 10, 337 .tmpl_long_retry_limit = 10, 338 .tx_watchdog_timeout = 5000, 339 }, 340 .conn = { 341 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM, 342 .listen_interval = 1, 343 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM, 344 .suspend_listen_interval = 3, 345 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED, 346 .bcn_filt_ie_count = 3, 347 .bcn_filt_ie = { 348 [0] = { 349 .ie = WLAN_EID_CHANNEL_SWITCH, 350 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE, 351 }, 352 [1] = { 353 .ie = WLAN_EID_HT_OPERATION, 354 .rule = CONF_BCN_RULE_PASS_ON_CHANGE, 355 }, 356 [2] = { 357 .ie = WLAN_EID_ERP_INFO, 358 .rule = CONF_BCN_RULE_PASS_ON_CHANGE, 359 }, 360 }, 361 .synch_fail_thold = 12, 362 .bss_lose_timeout = 400, 363 .beacon_rx_timeout = 10000, 364 .broadcast_timeout = 20000, 365 .rx_broadcast_in_ps = 1, 366 .ps_poll_threshold = 10, 367 .bet_enable = CONF_BET_MODE_ENABLE, 368 .bet_max_consecutive = 50, 369 .psm_entry_retries = 8, 370 .psm_exit_retries = 16, 371 .psm_entry_nullfunc_retries = 3, 372 .dynamic_ps_timeout = 1500, 373 .forced_ps = false, 374 .keep_alive_interval = 55000, 375 .max_listen_interval = 20, 376 .sta_sleep_auth = WL1271_PSM_ILLEGAL, 377 }, 378 .itrim = { 379 .enable = false, 380 .timeout = 50000, 381 }, 382 .pm_config = { 383 .host_clk_settling_time = 5000, 384 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE, 385 }, 386 .roam_trigger = { 387 .trigger_pacing = 1, 388 .avg_weight_rssi_beacon = 20, 389 .avg_weight_rssi_data = 10, 390 .avg_weight_snr_beacon = 20, 391 .avg_weight_snr_data = 10, 392 }, 393 .scan = { 394 .min_dwell_time_active = 7500, 395 .max_dwell_time_active = 30000, 396 .min_dwell_time_passive = 100000, 397 .max_dwell_time_passive = 100000, 398 .num_probe_reqs = 2, 399 .split_scan_timeout = 50000, 400 }, 401 .sched_scan = { 402 /* 403 * Values are in TU/1000 but since sched scan FW command 404 * params are in TUs rounding up may occur. 405 */ 406 .base_dwell_time = 7500, 407 .max_dwell_time_delta = 22500, 408 /* based on 250bits per probe @1Mbps */ 409 .dwell_time_delta_per_probe = 2000, 410 /* based on 250bits per probe @6Mbps (plus a bit more) */ 411 .dwell_time_delta_per_probe_5 = 350, 412 .dwell_time_passive = 100000, 413 .dwell_time_dfs = 150000, 414 .num_probe_reqs = 2, 415 .rssi_threshold = -90, 416 .snr_threshold = 0, 417 }, 418 .ht = { 419 .rx_ba_win_size = 10, 420 .tx_ba_win_size = 64, 421 .inactivity_timeout = 10000, 422 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP, 423 }, 424 .mem = { 425 .num_stations = 1, 426 .ssid_profiles = 1, 427 .rx_block_num = 40, 428 .tx_min_block_num = 40, 429 .dynamic_memory = 1, 430 .min_req_tx_blocks = 45, 431 .min_req_rx_blocks = 22, 432 .tx_min = 27, 433 }, 434 .fm_coex = { 435 .enable = true, 436 .swallow_period = 5, 437 .n_divider_fref_set_1 = 0xff, /* default */ 438 .n_divider_fref_set_2 = 12, 439 .m_divider_fref_set_1 = 0xffff, 440 .m_divider_fref_set_2 = 148, /* default */ 441 .coex_pll_stabilization_time = 0xffffffff, /* default */ 442 .ldo_stabilization_time = 0xffff, /* default */ 443 .fm_disturbed_band_margin = 0xff, /* default */ 444 .swallow_clk_diff = 0xff, /* default */ 445 }, 446 .rx_streaming = { 447 .duration = 150, 448 .queues = 0x1, 449 .interval = 20, 450 .always = 0, 451 }, 452 .fwlog = { 453 .mode = WL12XX_FWLOG_ON_DEMAND, 454 .mem_blocks = 2, 455 .severity = 0, 456 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED, 457 .output = WL12XX_FWLOG_OUTPUT_HOST, 458 .threshold = 0, 459 }, 460 .rate = { 461 .rate_retry_score = 32000, 462 .per_add = 8192, 463 .per_th1 = 2048, 464 .per_th2 = 4096, 465 .max_per = 8100, 466 .inverse_curiosity_factor = 5, 467 .tx_fail_low_th = 4, 468 .tx_fail_high_th = 10, 469 .per_alpha_shift = 4, 470 .per_add_shift = 13, 471 .per_beta1_shift = 10, 472 .per_beta2_shift = 8, 473 .rate_check_up = 2, 474 .rate_check_down = 12, 475 .rate_retry_policy = { 476 0x00, 0x00, 0x00, 0x00, 0x00, 477 0x00, 0x00, 0x00, 0x00, 0x00, 478 0x00, 0x00, 0x00, 479 }, 480 }, 481 .hangover = { 482 .recover_time = 0, 483 .hangover_period = 20, 484 .dynamic_mode = 1, 485 .early_termination_mode = 1, 486 .max_period = 20, 487 .min_period = 1, 488 .increase_delta = 1, 489 .decrease_delta = 2, 490 .quiet_time = 4, 491 .increase_time = 1, 492 .window_size = 16, 493 }, 494 }; 495 496 static struct wl18xx_priv_conf wl18xx_default_priv_conf = { 497 .ht = { 498 .mode = HT_MODE_DEFAULT, 499 }, 500 .phy = { 501 .phy_standalone = 0x00, 502 .primary_clock_setting_time = 0x05, 503 .clock_valid_on_wake_up = 0x00, 504 .secondary_clock_setting_time = 0x05, 505 .board_type = BOARD_TYPE_HDK_18XX, 506 .rdl = 0x01, 507 .auto_detect = 0x00, 508 .dedicated_fem = FEM_NONE, 509 .low_band_component = COMPONENT_2_WAY_SWITCH, 510 .low_band_component_type = 0x06, 511 .high_band_component = COMPONENT_2_WAY_SWITCH, 512 .high_band_component_type = 0x09, 513 .tcxo_ldo_voltage = 0x00, 514 .xtal_itrim_val = 0x04, 515 .srf_state = 0x00, 516 .io_configuration = 0x01, 517 .sdio_configuration = 0x00, 518 .settings = 0x00, 519 .enable_clpc = 0x00, 520 .enable_tx_low_pwr_on_siso_rdl = 0x00, 521 .rx_profile = 0x00, 522 .pwr_limit_reference_11_abg = 0xc8, 523 .psat = 0, 524 .low_power_val = 0x00, 525 .med_power_val = 0x0a, 526 .high_power_val = 0x1e, 527 .external_pa_dc2dc = 0, 528 .number_of_assembled_ant2_4 = 1, 529 .number_of_assembled_ant5 = 1, 530 }, 531 }; 532 533 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = { 534 [PART_TOP_PRCM_ELP_SOC] = { 535 .mem = { .start = 0x00A02000, .size = 0x00010000 }, 536 .reg = { .start = 0x00807000, .size = 0x00005000 }, 537 .mem2 = { .start = 0x00800000, .size = 0x0000B000 }, 538 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 539 }, 540 [PART_DOWN] = { 541 .mem = { .start = 0x00000000, .size = 0x00014000 }, 542 .reg = { .start = 0x00810000, .size = 0x0000BFFF }, 543 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 544 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 545 }, 546 [PART_BOOT] = { 547 .mem = { .start = 0x00700000, .size = 0x0000030c }, 548 .reg = { .start = 0x00802000, .size = 0x00014578 }, 549 .mem2 = { .start = 0x00B00404, .size = 0x00001000 }, 550 .mem3 = { .start = 0x00C00000, .size = 0x00000400 }, 551 }, 552 [PART_WORK] = { 553 .mem = { .start = 0x00800000, .size = 0x000050FC }, 554 .reg = { .start = 0x00B00404, .size = 0x00001000 }, 555 .mem2 = { .start = 0x00C00000, .size = 0x00000400 }, 556 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 557 }, 558 [PART_PHY_INIT] = { 559 .mem = { .start = 0x80926000, 560 .size = sizeof(struct wl18xx_mac_and_phy_params) }, 561 .reg = { .start = 0x00000000, .size = 0x00000000 }, 562 .mem2 = { .start = 0x00000000, .size = 0x00000000 }, 563 .mem3 = { .start = 0x00000000, .size = 0x00000000 }, 564 }, 565 }; 566 567 static const int wl18xx_rtable[REG_TABLE_LEN] = { 568 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL, 569 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR, 570 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK, 571 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR, 572 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR, 573 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H, 574 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK, 575 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4, 576 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B, 577 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS, 578 579 /* data access memory addresses, used with partition translation */ 580 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA, 581 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA, 582 583 /* raw data access memory addresses */ 584 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR, 585 }; 586 587 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = { 588 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true }, 589 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true }, 590 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false }, 591 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false }, 592 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false }, 593 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true }, 594 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false }, 595 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false }, 596 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false }, 597 }; 598 599 /* TODO: maybe move to a new header file? */ 600 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin" 601 602 static int wl18xx_identify_chip(struct wl1271 *wl) 603 { 604 int ret = 0; 605 606 switch (wl->chip.id) { 607 case CHIP_ID_185x_PG20: 608 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)", 609 wl->chip.id); 610 wl->sr_fw_name = WL18XX_FW_NAME; 611 /* wl18xx uses the same firmware for PLT */ 612 wl->plt_fw_name = WL18XX_FW_NAME; 613 wl->quirks |= WLCORE_QUIRK_NO_ELP | 614 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN | 615 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN | 616 WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN | 617 WLCORE_QUIRK_TX_PAD_LAST_FRAME; 618 619 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER, WL18XX_IFTYPE_VER, 620 WL18XX_MAJOR_VER, WL18XX_SUBTYPE_VER, 621 WL18XX_MINOR_VER); 622 break; 623 case CHIP_ID_185x_PG10: 624 wl1271_warning("chip id 0x%x (185x PG10) is deprecated", 625 wl->chip.id); 626 ret = -ENODEV; 627 goto out; 628 629 default: 630 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); 631 ret = -ENODEV; 632 goto out; 633 } 634 635 out: 636 return ret; 637 } 638 639 static int wl18xx_set_clk(struct wl1271 *wl) 640 { 641 u16 clk_freq; 642 int ret; 643 644 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 645 if (ret < 0) 646 goto out; 647 648 /* TODO: PG2: apparently we need to read the clk type */ 649 650 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq); 651 if (ret < 0) 652 goto out; 653 654 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq, 655 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m, 656 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q, 657 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit"); 658 659 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, 660 wl18xx_clk_table[clk_freq].n); 661 if (ret < 0) 662 goto out; 663 664 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, 665 wl18xx_clk_table[clk_freq].m); 666 if (ret < 0) 667 goto out; 668 669 if (wl18xx_clk_table[clk_freq].swallow) { 670 /* first the 16 lower bits */ 671 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1, 672 wl18xx_clk_table[clk_freq].q & 673 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK); 674 if (ret < 0) 675 goto out; 676 677 /* then the 16 higher bits, masked out */ 678 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2, 679 (wl18xx_clk_table[clk_freq].q >> 16) & 680 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK); 681 if (ret < 0) 682 goto out; 683 684 /* first the 16 lower bits */ 685 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1, 686 wl18xx_clk_table[clk_freq].p & 687 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK); 688 if (ret < 0) 689 goto out; 690 691 /* then the 16 higher bits, masked out */ 692 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2, 693 (wl18xx_clk_table[clk_freq].p >> 16) & 694 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK); 695 } else { 696 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN, 697 PLLSH_WCS_PLL_SWALLOW_EN_VAL2); 698 } 699 700 out: 701 return ret; 702 } 703 704 static int wl18xx_boot_soft_reset(struct wl1271 *wl) 705 { 706 int ret; 707 708 /* disable Rx/Tx */ 709 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0); 710 if (ret < 0) 711 goto out; 712 713 /* disable auto calibration on start*/ 714 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff); 715 716 out: 717 return ret; 718 } 719 720 static int wl18xx_pre_boot(struct wl1271 *wl) 721 { 722 int ret; 723 724 ret = wl18xx_set_clk(wl); 725 if (ret < 0) 726 goto out; 727 728 /* Continue the ELP wake up sequence */ 729 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 730 if (ret < 0) 731 goto out; 732 733 udelay(500); 734 735 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 736 if (ret < 0) 737 goto out; 738 739 /* Disable interrupts */ 740 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 741 if (ret < 0) 742 goto out; 743 744 ret = wl18xx_boot_soft_reset(wl); 745 746 out: 747 return ret; 748 } 749 750 static int wl18xx_pre_upload(struct wl1271 *wl) 751 { 752 u32 tmp; 753 int ret; 754 755 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 756 if (ret < 0) 757 goto out; 758 759 /* TODO: check if this is all needed */ 760 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND); 761 if (ret < 0) 762 goto out; 763 764 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp); 765 if (ret < 0) 766 goto out; 767 768 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 769 770 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp); 771 772 out: 773 return ret; 774 } 775 776 static int wl18xx_set_mac_and_phy(struct wl1271 *wl) 777 { 778 struct wl18xx_priv *priv = wl->priv; 779 struct wl18xx_mac_and_phy_params *params; 780 int ret; 781 782 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL); 783 if (!params) { 784 ret = -ENOMEM; 785 goto out; 786 } 787 788 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); 789 if (ret < 0) 790 goto out; 791 792 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params, 793 sizeof(*params), false); 794 795 out: 796 kfree(params); 797 return ret; 798 } 799 800 static int wl18xx_enable_interrupts(struct wl1271 *wl) 801 { 802 u32 event_mask, intr_mask; 803 int ret; 804 805 event_mask = WL18XX_ACX_EVENTS_VECTOR; 806 intr_mask = WL18XX_INTR_MASK; 807 808 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask); 809 if (ret < 0) 810 goto out; 811 812 wlcore_enable_interrupts(wl); 813 814 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, 815 WL1271_ACX_INTR_ALL & ~intr_mask); 816 817 out: 818 return ret; 819 } 820 821 static int wl18xx_boot(struct wl1271 *wl) 822 { 823 int ret; 824 825 ret = wl18xx_pre_boot(wl); 826 if (ret < 0) 827 goto out; 828 829 ret = wl18xx_pre_upload(wl); 830 if (ret < 0) 831 goto out; 832 833 ret = wlcore_boot_upload_firmware(wl); 834 if (ret < 0) 835 goto out; 836 837 ret = wl18xx_set_mac_and_phy(wl); 838 if (ret < 0) 839 goto out; 840 841 ret = wlcore_boot_run_firmware(wl); 842 if (ret < 0) 843 goto out; 844 845 ret = wl18xx_enable_interrupts(wl); 846 847 out: 848 return ret; 849 } 850 851 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr, 852 void *buf, size_t len) 853 { 854 struct wl18xx_priv *priv = wl->priv; 855 856 memcpy(priv->cmd_buf, buf, len); 857 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len); 858 859 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf, 860 WL18XX_CMD_MAX_SIZE, false); 861 } 862 863 static int wl18xx_ack_event(struct wl1271 *wl) 864 { 865 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG, 866 WL18XX_INTR_TRIG_EVENT_ACK); 867 } 868 869 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks) 870 { 871 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE; 872 return (len + blk_size - 1) / blk_size + spare_blks; 873 } 874 875 static void 876 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 877 u32 blks, u32 spare_blks) 878 { 879 desc->wl18xx_mem.total_mem_blocks = blks; 880 } 881 882 static void 883 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc, 884 struct sk_buff *skb) 885 { 886 desc->length = cpu_to_le16(skb->len); 887 888 /* if only the last frame is to be padded, we unset this bit on Tx */ 889 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) 890 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED; 891 else 892 desc->wl18xx_mem.ctrl = 0; 893 894 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d " 895 "len: %d life: %d mem: %d", desc->hlid, 896 le16_to_cpu(desc->length), 897 le16_to_cpu(desc->life_time), 898 desc->wl18xx_mem.total_mem_blocks); 899 } 900 901 static enum wl_rx_buf_align 902 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc) 903 { 904 if (rx_desc & RX_BUF_PADDED_PAYLOAD) 905 return WLCORE_RX_BUF_PADDED; 906 907 return WLCORE_RX_BUF_ALIGNED; 908 } 909 910 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data, 911 u32 data_len) 912 { 913 struct wl1271_rx_descriptor *desc = rx_data; 914 915 /* invalid packet */ 916 if (data_len < sizeof(*desc)) 917 return 0; 918 919 return data_len - sizeof(*desc); 920 } 921 922 static void wl18xx_tx_immediate_completion(struct wl1271 *wl) 923 { 924 wl18xx_tx_immediate_complete(wl); 925 } 926 927 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk) 928 { 929 int ret; 930 u32 sdio_align_size = 0; 931 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE | 932 HOST_IF_CFG_ADD_RX_ALIGNMENT; 933 934 /* Enable Tx SDIO padding */ 935 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) { 936 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK; 937 sdio_align_size = WL12XX_BUS_BLOCK_SIZE; 938 } 939 940 /* Enable Rx SDIO padding */ 941 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) { 942 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK; 943 sdio_align_size = WL12XX_BUS_BLOCK_SIZE; 944 } 945 946 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap, 947 sdio_align_size, extra_mem_blk, 948 WL18XX_HOST_IF_LEN_SIZE_FIELD); 949 if (ret < 0) 950 return ret; 951 952 return 0; 953 } 954 955 static int wl18xx_hw_init(struct wl1271 *wl) 956 { 957 int ret; 958 struct wl18xx_priv *priv = wl->priv; 959 960 /* (re)init private structures. Relevant on recovery as well. */ 961 priv->last_fw_rls_idx = 0; 962 priv->extra_spare_vif_count = 0; 963 964 /* set the default amount of spare blocks in the bitmap */ 965 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE); 966 if (ret < 0) 967 return ret; 968 969 if (checksum_param) { 970 ret = wl18xx_acx_set_checksum_state(wl); 971 if (ret != 0) 972 return ret; 973 } 974 975 return ret; 976 } 977 978 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl, 979 struct wl1271_tx_hw_descr *desc, 980 struct sk_buff *skb) 981 { 982 u32 ip_hdr_offset; 983 struct iphdr *ip_hdr; 984 985 if (!checksum_param) { 986 desc->wl18xx_checksum_data = 0; 987 return; 988 } 989 990 if (skb->ip_summed != CHECKSUM_PARTIAL) { 991 desc->wl18xx_checksum_data = 0; 992 return; 993 } 994 995 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb); 996 if (WARN_ON(ip_hdr_offset >= (1<<7))) { 997 desc->wl18xx_checksum_data = 0; 998 return; 999 } 1000 1001 desc->wl18xx_checksum_data = ip_hdr_offset << 1; 1002 1003 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */ 1004 ip_hdr = (void *)skb_network_header(skb); 1005 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01); 1006 } 1007 1008 static void wl18xx_set_rx_csum(struct wl1271 *wl, 1009 struct wl1271_rx_descriptor *desc, 1010 struct sk_buff *skb) 1011 { 1012 if (desc->status & WL18XX_RX_CHECKSUM_MASK) 1013 skb->ip_summed = CHECKSUM_UNNECESSARY; 1014 } 1015 1016 static bool wl18xx_is_mimo_supported(struct wl1271 *wl) 1017 { 1018 struct wl18xx_priv *priv = wl->priv; 1019 1020 return priv->conf.phy.number_of_assembled_ant2_4 >= 2; 1021 } 1022 1023 /* 1024 * TODO: instead of having these two functions to get the rate mask, 1025 * we should modify the wlvif->rate_set instead 1026 */ 1027 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl, 1028 struct wl12xx_vif *wlvif) 1029 { 1030 u32 hw_rate_set = wlvif->rate_set; 1031 1032 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS || 1033 wlvif->channel_type == NL80211_CHAN_HT40PLUS) { 1034 wl1271_debug(DEBUG_ACX, "using wide channel rate mask"); 1035 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN; 1036 1037 /* we don't support MIMO in wide-channel mode */ 1038 hw_rate_set &= ~CONF_TX_MIMO_RATES; 1039 } else if (wl18xx_is_mimo_supported(wl)) { 1040 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask"); 1041 hw_rate_set |= CONF_TX_MIMO_RATES; 1042 } 1043 1044 return hw_rate_set; 1045 } 1046 1047 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl, 1048 struct wl12xx_vif *wlvif) 1049 { 1050 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS || 1051 wlvif->channel_type == NL80211_CHAN_HT40PLUS) { 1052 wl1271_debug(DEBUG_ACX, "using wide channel rate mask"); 1053 1054 /* sanity check - we don't support this */ 1055 if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ)) 1056 return 0; 1057 1058 return CONF_TX_RATE_USE_WIDE_CHAN; 1059 } else if (wl18xx_is_mimo_supported(wl) && 1060 wlvif->band == IEEE80211_BAND_2GHZ) { 1061 wl1271_debug(DEBUG_ACX, "using MIMO rate mask"); 1062 /* 1063 * we don't care about HT channel here - if a peer doesn't 1064 * support MIMO, we won't enable it in its rates 1065 */ 1066 return CONF_TX_MIMO_RATES; 1067 } else { 1068 return 0; 1069 } 1070 } 1071 1072 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) 1073 { 1074 u32 fuse; 1075 int ret; 1076 1077 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 1078 if (ret < 0) 1079 goto out; 1080 1081 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse); 1082 if (ret < 0) 1083 goto out; 1084 1085 if (ver) 1086 *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; 1087 1088 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); 1089 1090 out: 1091 return ret; 1092 } 1093 1094 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin" 1095 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev) 1096 { 1097 struct wl18xx_priv *priv = wl->priv; 1098 struct wlcore_conf_file *conf_file; 1099 const struct firmware *fw; 1100 int ret; 1101 1102 ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev); 1103 if (ret < 0) { 1104 wl1271_error("could not get configuration binary %s: %d", 1105 WL18XX_CONF_FILE_NAME, ret); 1106 goto out_fallback; 1107 } 1108 1109 if (fw->size != WL18XX_CONF_SIZE) { 1110 wl1271_error("configuration binary file size is wrong, expected %zu got %zu", 1111 WL18XX_CONF_SIZE, fw->size); 1112 ret = -EINVAL; 1113 goto out; 1114 } 1115 1116 conf_file = (struct wlcore_conf_file *) fw->data; 1117 1118 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) { 1119 wl1271_error("configuration binary file magic number mismatch, " 1120 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC, 1121 conf_file->header.magic); 1122 ret = -EINVAL; 1123 goto out; 1124 } 1125 1126 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) { 1127 wl1271_error("configuration binary file version not supported, " 1128 "expected 0x%08x got 0x%08x", 1129 WL18XX_CONF_VERSION, conf_file->header.version); 1130 ret = -EINVAL; 1131 goto out; 1132 } 1133 1134 memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf)); 1135 memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf)); 1136 1137 goto out; 1138 1139 out_fallback: 1140 wl1271_warning("falling back to default config"); 1141 1142 /* apply driver default configuration */ 1143 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf)); 1144 /* apply default private configuration */ 1145 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf)); 1146 1147 /* For now we just fallback */ 1148 return 0; 1149 1150 out: 1151 release_firmware(fw); 1152 return ret; 1153 } 1154 1155 static int wl18xx_plt_init(struct wl1271 *wl) 1156 { 1157 int ret; 1158 1159 /* calibrator based auto/fem detect not supported for 18xx */ 1160 if (wl->plt_mode == PLT_FEM_DETECT) { 1161 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported"); 1162 return -EINVAL; 1163 } 1164 1165 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT); 1166 if (ret < 0) 1167 return ret; 1168 1169 return wl->ops->boot(wl); 1170 } 1171 1172 static int wl18xx_get_mac(struct wl1271 *wl) 1173 { 1174 u32 mac1, mac2; 1175 int ret; 1176 1177 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); 1178 if (ret < 0) 1179 goto out; 1180 1181 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1); 1182 if (ret < 0) 1183 goto out; 1184 1185 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2); 1186 if (ret < 0) 1187 goto out; 1188 1189 /* these are the two parts of the BD_ADDR */ 1190 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + 1191 ((mac1 & 0xff000000) >> 24); 1192 wl->fuse_nic_addr = (mac1 & 0xffffff); 1193 1194 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); 1195 1196 out: 1197 return ret; 1198 } 1199 1200 static int wl18xx_handle_static_data(struct wl1271 *wl, 1201 struct wl1271_static_data *static_data) 1202 { 1203 struct wl18xx_static_data_priv *static_data_priv = 1204 (struct wl18xx_static_data_priv *) static_data->priv; 1205 1206 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version); 1207 1208 return 0; 1209 } 1210 1211 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem) 1212 { 1213 struct wl18xx_priv *priv = wl->priv; 1214 1215 /* If we have VIFs requiring extra spare, indulge them */ 1216 if (priv->extra_spare_vif_count) 1217 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE; 1218 1219 return WL18XX_TX_HW_BLOCK_SPARE; 1220 } 1221 1222 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd, 1223 struct ieee80211_vif *vif, 1224 struct ieee80211_sta *sta, 1225 struct ieee80211_key_conf *key_conf) 1226 { 1227 struct wl18xx_priv *priv = wl->priv; 1228 bool change_spare = false; 1229 int ret; 1230 1231 /* 1232 * when adding the first or removing the last GEM/TKIP interface, 1233 * we have to adjust the number of spare blocks. 1234 */ 1235 change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM || 1236 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) && 1237 ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) || 1238 (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY)); 1239 1240 /* no need to change spare - just regular set_key */ 1241 if (!change_spare) 1242 return wlcore_set_key(wl, cmd, vif, sta, key_conf); 1243 1244 /* 1245 * stop the queues and flush to ensure the next packets are 1246 * in sync with FW spare block accounting 1247 */ 1248 wlcore_stop_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK); 1249 wl1271_tx_flush(wl); 1250 1251 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf); 1252 if (ret < 0) 1253 goto out; 1254 1255 /* key is now set, change the spare blocks */ 1256 if (cmd == SET_KEY) { 1257 ret = wl18xx_set_host_cfg_bitmap(wl, 1258 WL18XX_TX_HW_EXTRA_BLOCK_SPARE); 1259 if (ret < 0) 1260 goto out; 1261 1262 priv->extra_spare_vif_count++; 1263 } else { 1264 ret = wl18xx_set_host_cfg_bitmap(wl, 1265 WL18XX_TX_HW_BLOCK_SPARE); 1266 if (ret < 0) 1267 goto out; 1268 1269 priv->extra_spare_vif_count--; 1270 } 1271 1272 out: 1273 wlcore_wake_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK); 1274 return ret; 1275 } 1276 1277 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl, 1278 u32 buf_offset, u32 last_len) 1279 { 1280 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) { 1281 struct wl1271_tx_hw_descr *last_desc; 1282 1283 /* get the last TX HW descriptor written to the aggr buf */ 1284 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf + 1285 buf_offset - last_len); 1286 1287 /* the last frame is padded up to an SDIO block */ 1288 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED; 1289 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE); 1290 } 1291 1292 /* no modifications */ 1293 return buf_offset; 1294 } 1295 1296 static struct wlcore_ops wl18xx_ops = { 1297 .identify_chip = wl18xx_identify_chip, 1298 .boot = wl18xx_boot, 1299 .plt_init = wl18xx_plt_init, 1300 .trigger_cmd = wl18xx_trigger_cmd, 1301 .ack_event = wl18xx_ack_event, 1302 .calc_tx_blocks = wl18xx_calc_tx_blocks, 1303 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks, 1304 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len, 1305 .get_rx_buf_align = wl18xx_get_rx_buf_align, 1306 .get_rx_packet_len = wl18xx_get_rx_packet_len, 1307 .tx_immediate_compl = wl18xx_tx_immediate_completion, 1308 .tx_delayed_compl = NULL, 1309 .hw_init = wl18xx_hw_init, 1310 .set_tx_desc_csum = wl18xx_set_tx_desc_csum, 1311 .get_pg_ver = wl18xx_get_pg_ver, 1312 .set_rx_csum = wl18xx_set_rx_csum, 1313 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask, 1314 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask, 1315 .get_mac = wl18xx_get_mac, 1316 .debugfs_init = wl18xx_debugfs_add_files, 1317 .handle_static_data = wl18xx_handle_static_data, 1318 .get_spare_blocks = wl18xx_get_spare_blocks, 1319 .set_key = wl18xx_set_key, 1320 .pre_pkt_send = wl18xx_pre_pkt_send, 1321 }; 1322 1323 /* HT cap appropriate for wide channels in 2Ghz */ 1324 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = { 1325 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | 1326 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40, 1327 .ht_supported = true, 1328 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1329 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1330 .mcs = { 1331 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1332 .rx_highest = cpu_to_le16(150), 1333 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1334 }, 1335 }; 1336 1337 /* HT cap appropriate for wide channels in 5Ghz */ 1338 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = { 1339 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | 1340 IEEE80211_HT_CAP_SUP_WIDTH_20_40, 1341 .ht_supported = true, 1342 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1343 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1344 .mcs = { 1345 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1346 .rx_highest = cpu_to_le16(150), 1347 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1348 }, 1349 }; 1350 1351 /* HT cap appropriate for SISO 20 */ 1352 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = { 1353 .cap = IEEE80211_HT_CAP_SGI_20, 1354 .ht_supported = true, 1355 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1356 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1357 .mcs = { 1358 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 1359 .rx_highest = cpu_to_le16(72), 1360 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1361 }, 1362 }; 1363 1364 /* HT cap appropriate for MIMO rates in 20mhz channel */ 1365 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = { 1366 .cap = IEEE80211_HT_CAP_SGI_20, 1367 .ht_supported = true, 1368 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K, 1369 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1370 .mcs = { 1371 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, }, 1372 .rx_highest = cpu_to_le16(144), 1373 .tx_params = IEEE80211_HT_MCS_TX_DEFINED, 1374 }, 1375 }; 1376 1377 static int __devinit wl18xx_probe(struct platform_device *pdev) 1378 { 1379 struct wl1271 *wl; 1380 struct ieee80211_hw *hw; 1381 struct wl18xx_priv *priv; 1382 int ret; 1383 1384 hw = wlcore_alloc_hw(sizeof(*priv)); 1385 if (IS_ERR(hw)) { 1386 wl1271_error("can't allocate hw"); 1387 ret = PTR_ERR(hw); 1388 goto out; 1389 } 1390 1391 wl = hw->priv; 1392 priv = wl->priv; 1393 wl->ops = &wl18xx_ops; 1394 wl->ptable = wl18xx_ptable; 1395 wl->rtable = wl18xx_rtable; 1396 wl->num_tx_desc = 32; 1397 wl->num_rx_desc = 32; 1398 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; 1399 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; 1400 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; 1401 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); 1402 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics); 1403 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv); 1404 1405 if (num_rx_desc_param != -1) 1406 wl->num_rx_desc = num_rx_desc_param; 1407 1408 ret = wl18xx_conf_init(wl, &pdev->dev); 1409 if (ret < 0) 1410 goto out_free; 1411 1412 /* If the module param is set, update it in conf */ 1413 if (board_type_param) { 1414 if (!strcmp(board_type_param, "fpga")) { 1415 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX; 1416 } else if (!strcmp(board_type_param, "hdk")) { 1417 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX; 1418 } else if (!strcmp(board_type_param, "dvp")) { 1419 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX; 1420 } else if (!strcmp(board_type_param, "evb")) { 1421 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX; 1422 } else if (!strcmp(board_type_param, "com8")) { 1423 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX; 1424 } else { 1425 wl1271_error("invalid board type '%s'", 1426 board_type_param); 1427 ret = -EINVAL; 1428 goto out_free; 1429 } 1430 } 1431 1432 /* HACK! Just for now we hardcode COM8 and HDK to 0x06 */ 1433 switch (priv->conf.phy.board_type) { 1434 case BOARD_TYPE_HDK_18XX: 1435 case BOARD_TYPE_COM8_18XX: 1436 priv->conf.phy.low_band_component_type = 0x06; 1437 break; 1438 case BOARD_TYPE_FPGA_18XX: 1439 case BOARD_TYPE_DVP_18XX: 1440 case BOARD_TYPE_EVB_18XX: 1441 priv->conf.phy.low_band_component_type = 0x05; 1442 break; 1443 default: 1444 wl1271_error("invalid board type '%d'", 1445 priv->conf.phy.board_type); 1446 ret = -EINVAL; 1447 goto out_free; 1448 } 1449 1450 if (low_band_component_param != -1) 1451 priv->conf.phy.low_band_component = low_band_component_param; 1452 if (low_band_component_type_param != -1) 1453 priv->conf.phy.low_band_component_type = 1454 low_band_component_type_param; 1455 if (high_band_component_param != -1) 1456 priv->conf.phy.high_band_component = high_band_component_param; 1457 if (high_band_component_type_param != -1) 1458 priv->conf.phy.high_band_component_type = 1459 high_band_component_type_param; 1460 if (pwr_limit_reference_11_abg_param != -1) 1461 priv->conf.phy.pwr_limit_reference_11_abg = 1462 pwr_limit_reference_11_abg_param; 1463 if (n_antennas_2_param != -1) 1464 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param; 1465 if (n_antennas_5_param != -1) 1466 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param; 1467 if (dc2dc_param != -1) 1468 priv->conf.phy.external_pa_dc2dc = dc2dc_param; 1469 1470 if (ht_mode_param) { 1471 if (!strcmp(ht_mode_param, "default")) 1472 priv->conf.ht.mode = HT_MODE_DEFAULT; 1473 else if (!strcmp(ht_mode_param, "wide")) 1474 priv->conf.ht.mode = HT_MODE_WIDE; 1475 else if (!strcmp(ht_mode_param, "siso20")) 1476 priv->conf.ht.mode = HT_MODE_SISO20; 1477 else { 1478 wl1271_error("invalid ht_mode '%s'", ht_mode_param); 1479 ret = -EINVAL; 1480 goto out_free; 1481 } 1482 } 1483 1484 if (priv->conf.ht.mode == HT_MODE_DEFAULT) { 1485 /* 1486 * Only support mimo with multiple antennas. Fall back to 1487 * siso20. 1488 */ 1489 if (wl18xx_is_mimo_supported(wl)) 1490 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, 1491 &wl18xx_mimo_ht_cap_2ghz); 1492 else 1493 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, 1494 &wl18xx_siso20_ht_cap); 1495 1496 /* 5Ghz is always wide */ 1497 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, 1498 &wl18xx_siso40_ht_cap_5ghz); 1499 } else if (priv->conf.ht.mode == HT_MODE_WIDE) { 1500 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, 1501 &wl18xx_siso40_ht_cap_2ghz); 1502 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, 1503 &wl18xx_siso40_ht_cap_5ghz); 1504 } else if (priv->conf.ht.mode == HT_MODE_SISO20) { 1505 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, 1506 &wl18xx_siso20_ht_cap); 1507 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, 1508 &wl18xx_siso20_ht_cap); 1509 } 1510 1511 if (!checksum_param) { 1512 wl18xx_ops.set_rx_csum = NULL; 1513 wl18xx_ops.init_vif = NULL; 1514 } 1515 1516 wl->enable_11a = enable_11a_param; 1517 1518 return wlcore_probe(wl, pdev); 1519 1520 out_free: 1521 wlcore_free_hw(wl); 1522 out: 1523 return ret; 1524 } 1525 1526 static const struct platform_device_id wl18xx_id_table[] __devinitconst = { 1527 { "wl18xx", 0 }, 1528 { } /* Terminating Entry */ 1529 }; 1530 MODULE_DEVICE_TABLE(platform, wl18xx_id_table); 1531 1532 static struct platform_driver wl18xx_driver = { 1533 .probe = wl18xx_probe, 1534 .remove = __devexit_p(wlcore_remove), 1535 .id_table = wl18xx_id_table, 1536 .driver = { 1537 .name = "wl18xx_driver", 1538 .owner = THIS_MODULE, 1539 } 1540 }; 1541 1542 static int __init wl18xx_init(void) 1543 { 1544 return platform_driver_register(&wl18xx_driver); 1545 } 1546 module_init(wl18xx_init); 1547 1548 static void __exit wl18xx_exit(void) 1549 { 1550 platform_driver_unregister(&wl18xx_driver); 1551 } 1552 module_exit(wl18xx_exit); 1553 1554 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR); 1555 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20"); 1556 1557 module_param_named(board_type, board_type_param, charp, S_IRUSR); 1558 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or " 1559 "dvp"); 1560 1561 module_param_named(checksum, checksum_param, bool, S_IRUSR); 1562 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)"); 1563 1564 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR); 1565 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)"); 1566 1567 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR); 1568 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)"); 1569 1570 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR); 1571 MODULE_PARM_DESC(n_antennas_2, 1572 "Number of installed 2.4GHz antennas: 1 (default) or 2"); 1573 1574 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR); 1575 MODULE_PARM_DESC(n_antennas_5, 1576 "Number of installed 5GHz antennas: 1 (default) or 2"); 1577 1578 module_param_named(low_band_component, low_band_component_param, int, 1579 S_IRUSR); 1580 MODULE_PARM_DESC(low_band_component, "Low band component: u8 " 1581 "(default is 0x01)"); 1582 1583 module_param_named(low_band_component_type, low_band_component_type_param, 1584 int, S_IRUSR); 1585 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 " 1586 "(default is 0x05 or 0x06 depending on the board_type)"); 1587 1588 module_param_named(high_band_component, high_band_component_param, int, 1589 S_IRUSR); 1590 MODULE_PARM_DESC(high_band_component, "High band component: u8, " 1591 "(default is 0x01)"); 1592 1593 module_param_named(high_band_component_type, high_band_component_type_param, 1594 int, S_IRUSR); 1595 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 " 1596 "(default is 0x09)"); 1597 1598 module_param_named(pwr_limit_reference_11_abg, 1599 pwr_limit_reference_11_abg_param, int, S_IRUSR); 1600 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 " 1601 "(default is 0xc8)"); 1602 1603 module_param_named(num_rx_desc, 1604 num_rx_desc_param, int, S_IRUSR); 1605 MODULE_PARM_DESC(num_rx_desc_param, 1606 "Number of Rx descriptors: u8 (default is 32)"); 1607 1608 MODULE_LICENSE("GPL v2"); 1609 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>"); 1610 MODULE_FIRMWARE(WL18XX_FW_NAME); 1611