1 /* 2 * This file is part of wl18xx 3 * 4 * Copyright (C) 2011 Texas Instruments. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #ifndef __WL18XX_ACX_H__ 23 #define __WL18XX_ACX_H__ 24 25 #include "../wlcore/wlcore.h" 26 #include "../wlcore/acx.h" 27 28 enum { 29 ACX_NS_IPV6_FILTER = 0x0050, 30 ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051, 31 ACX_CSUM_CONFIG = 0x0052, 32 ACX_SIM_CONFIG = 0x0053, 33 ACX_CLEAR_STATISTICS = 0x0054, 34 ACX_AUTO_RX_STREAMING = 0x0055, 35 ACX_PEER_CAP = 0x0056, 36 ACX_INTERRUPT_NOTIFY = 0x0057, 37 ACX_RX_BA_FILTER = 0x0058, 38 ACX_AP_SLEEP_CFG = 0x0059 39 }; 40 41 /* numbers of bits the length field takes (add 1 for the actual number) */ 42 #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15 43 44 #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ 45 WL1271_ACX_INTR_INIT_COMPLETE | \ 46 WL1271_ACX_INTR_EVENT_A | \ 47 WL1271_ACX_INTR_EVENT_B | \ 48 WL1271_ACX_INTR_CMD_COMPLETE | \ 49 WL1271_ACX_INTR_HW_AVAILABLE | \ 50 WL1271_ACX_INTR_DATA | \ 51 WL1271_ACX_SW_INTR_WATCHDOG) 52 53 #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ 54 WL1271_ACX_INTR_EVENT_A | \ 55 WL1271_ACX_INTR_EVENT_B | \ 56 WL1271_ACX_INTR_HW_AVAILABLE | \ 57 WL1271_ACX_INTR_DATA | \ 58 WL1271_ACX_SW_INTR_WATCHDOG) 59 60 struct wl18xx_acx_host_config_bitmap { 61 struct acx_header header; 62 63 __le32 host_cfg_bitmap; 64 65 __le32 host_sdio_block_size; 66 67 /* extra mem blocks per frame in TX. */ 68 __le32 extra_mem_blocks; 69 70 /* 71 * number of bits of the length field in the first TX word 72 * (up to 15 - for using the entire 16 bits). 73 */ 74 __le32 length_field_size; 75 76 } __packed; 77 78 enum { 79 CHECKSUM_OFFLOAD_DISABLED = 0, 80 CHECKSUM_OFFLOAD_ENABLED = 1, 81 CHECKSUM_OFFLOAD_FAKE_RX = 2, 82 CHECKSUM_OFFLOAD_INVALID = 0xFF 83 }; 84 85 struct wl18xx_acx_checksum_state { 86 struct acx_header header; 87 88 /* enum acx_checksum_state */ 89 u8 checksum_state; 90 u8 pad[3]; 91 } __packed; 92 93 94 struct wl18xx_acx_error_stats { 95 u32 error_frame; 96 u32 error_null_Frame_tx_start; 97 u32 error_numll_frame_cts_start; 98 u32 error_bar_retry; 99 u32 error_frame_cts_nul_flid; 100 } __packed; 101 102 struct wl18xx_acx_debug_stats { 103 u32 debug1; 104 u32 debug2; 105 u32 debug3; 106 u32 debug4; 107 u32 debug5; 108 u32 debug6; 109 } __packed; 110 111 struct wl18xx_acx_ring_stats { 112 u32 prepared_descs; 113 u32 tx_cmplt; 114 } __packed; 115 116 struct wl18xx_acx_tx_stats { 117 u32 tx_prepared_descs; 118 u32 tx_cmplt; 119 u32 tx_template_prepared; 120 u32 tx_data_prepared; 121 u32 tx_template_programmed; 122 u32 tx_data_programmed; 123 u32 tx_burst_programmed; 124 u32 tx_starts; 125 u32 tx_imm_resp; 126 u32 tx_start_templates; 127 u32 tx_start_int_templates; 128 u32 tx_start_fw_gen; 129 u32 tx_start_data; 130 u32 tx_start_null_frame; 131 u32 tx_exch; 132 u32 tx_retry_template; 133 u32 tx_retry_data; 134 u32 tx_exch_pending; 135 u32 tx_exch_expiry; 136 u32 tx_done_template; 137 u32 tx_done_data; 138 u32 tx_done_int_template; 139 u32 tx_frame_checksum; 140 u32 tx_checksum_result; 141 u32 frag_called; 142 u32 frag_mpdu_alloc_failed; 143 u32 frag_init_called; 144 u32 frag_in_process_called; 145 u32 frag_tkip_called; 146 u32 frag_key_not_found; 147 u32 frag_need_fragmentation; 148 u32 frag_bad_mblk_num; 149 u32 frag_failed; 150 u32 frag_cache_hit; 151 u32 frag_cache_miss; 152 } __packed; 153 154 struct wl18xx_acx_rx_stats { 155 u32 rx_beacon_early_term; 156 u32 rx_out_of_mpdu_nodes; 157 u32 rx_hdr_overflow; 158 u32 rx_dropped_frame; 159 u32 rx_done_stage; 160 u32 rx_done; 161 u32 rx_defrag; 162 u32 rx_defrag_end; 163 u32 rx_cmplt; 164 u32 rx_pre_complt; 165 u32 rx_cmplt_task; 166 u32 rx_phy_hdr; 167 u32 rx_timeout; 168 u32 rx_timeout_wa; 169 u32 rx_wa_density_dropped_frame; 170 u32 rx_wa_ba_not_expected; 171 u32 rx_frame_checksum; 172 u32 rx_checksum_result; 173 u32 defrag_called; 174 u32 defrag_init_called; 175 u32 defrag_in_process_called; 176 u32 defrag_tkip_called; 177 u32 defrag_need_defrag; 178 u32 defrag_decrypt_failed; 179 u32 decrypt_key_not_found; 180 u32 defrag_need_decrypt; 181 u32 rx_tkip_replays; 182 } __packed; 183 184 struct wl18xx_acx_isr_stats { 185 u32 irqs; 186 } __packed; 187 188 #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10 189 190 struct wl18xx_acx_pwr_stats { 191 u32 missing_bcns_cnt; 192 u32 rcvd_bcns_cnt; 193 u32 connection_out_of_sync; 194 u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD]; 195 u32 rcvd_awake_bcns_cnt; 196 } __packed; 197 198 struct wl18xx_acx_event_stats { 199 u32 calibration; 200 u32 rx_mismatch; 201 u32 rx_mem_empty; 202 } __packed; 203 204 struct wl18xx_acx_ps_poll_stats { 205 u32 ps_poll_timeouts; 206 u32 upsd_timeouts; 207 u32 upsd_max_ap_turn; 208 u32 ps_poll_max_ap_turn; 209 u32 ps_poll_utilization; 210 u32 upsd_utilization; 211 } __packed; 212 213 struct wl18xx_acx_rx_filter_stats { 214 u32 beacon_filter; 215 u32 arp_filter; 216 u32 mc_filter; 217 u32 dup_filter; 218 u32 data_filter; 219 u32 ibss_filter; 220 u32 protection_filter; 221 u32 accum_arp_pend_requests; 222 u32 max_arp_queue_dep; 223 } __packed; 224 225 struct wl18xx_acx_rx_rate_stats { 226 u32 rx_frames_per_rates[50]; 227 } __packed; 228 229 #define AGGR_STATS_TX_AGG 16 230 #define AGGR_STATS_TX_RATE 16 231 #define AGGR_STATS_RX_SIZE_LEN 16 232 233 struct wl18xx_acx_aggr_stats { 234 u32 tx_agg_vs_rate[AGGR_STATS_TX_AGG * AGGR_STATS_TX_RATE]; 235 u32 rx_size[AGGR_STATS_RX_SIZE_LEN]; 236 } __packed; 237 238 #define PIPE_STATS_HW_FIFO 11 239 240 struct wl18xx_acx_pipeline_stats { 241 u32 hs_tx_stat_fifo_int; 242 u32 hs_rx_stat_fifo_int; 243 u32 tcp_tx_stat_fifo_int; 244 u32 tcp_rx_stat_fifo_int; 245 u32 enc_tx_stat_fifo_int; 246 u32 enc_rx_stat_fifo_int; 247 u32 rx_complete_stat_fifo_int; 248 u32 pre_proc_swi; 249 u32 post_proc_swi; 250 u32 sec_frag_swi; 251 u32 pre_to_defrag_swi; 252 u32 defrag_to_csum_swi; 253 u32 csum_to_rx_xfer_swi; 254 u32 dec_packet_in; 255 u32 dec_packet_in_fifo_full; 256 u32 dec_packet_out; 257 u32 cs_rx_packet_in; 258 u32 cs_rx_packet_out; 259 u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO]; 260 } __packed; 261 262 struct wl18xx_acx_mem_stats { 263 u32 rx_free_mem_blks; 264 u32 tx_free_mem_blks; 265 u32 fwlog_free_mem_blks; 266 u32 fw_gen_free_mem_blks; 267 } __packed; 268 269 struct wl18xx_acx_statistics { 270 struct acx_header header; 271 272 struct wl18xx_acx_error_stats error; 273 struct wl18xx_acx_debug_stats debug; 274 struct wl18xx_acx_tx_stats tx; 275 struct wl18xx_acx_rx_stats rx; 276 struct wl18xx_acx_isr_stats isr; 277 struct wl18xx_acx_pwr_stats pwr; 278 struct wl18xx_acx_ps_poll_stats ps_poll; 279 struct wl18xx_acx_rx_filter_stats rx_filter; 280 struct wl18xx_acx_rx_rate_stats rx_rate; 281 struct wl18xx_acx_aggr_stats aggr_size; 282 struct wl18xx_acx_pipeline_stats pipeline; 283 struct wl18xx_acx_mem_stats mem; 284 } __packed; 285 286 struct wl18xx_acx_clear_statistics { 287 struct acx_header header; 288 }; 289 290 enum wlcore_bandwidth { 291 WLCORE_BANDWIDTH_20MHZ, 292 WLCORE_BANDWIDTH_40MHZ, 293 }; 294 295 struct wlcore_peer_ht_operation_mode { 296 struct acx_header header; 297 298 u8 hlid; 299 u8 bandwidth; /* enum wlcore_bandwidth */ 300 u8 padding[2]; 301 }; 302 303 /* 304 * ACX_PEER_CAP 305 * this struct is very similar to wl1271_acx_ht_capabilities, with the 306 * addition of supported rates 307 */ 308 struct wlcore_acx_peer_cap { 309 struct acx_header header; 310 311 /* bitmask of capability bits supported by the peer */ 312 __le32 ht_capabilites; 313 314 /* rates supported by the remote peer */ 315 __le32 supported_rates; 316 317 /* Indicates to which link these capabilities apply. */ 318 u8 hlid; 319 320 /* 321 * This the maximum A-MPDU length supported by the AP. The FW may not 322 * exceed this length when sending A-MPDUs 323 */ 324 u8 ampdu_max_length; 325 326 /* This is the minimal spacing required when sending A-MPDUs to the AP*/ 327 u8 ampdu_min_spacing; 328 329 u8 padding; 330 } __packed; 331 332 /* 333 * ACX_INTERRUPT_NOTIFY 334 * enable/disable fast-link/PSM notification from FW 335 */ 336 struct wl18xx_acx_interrupt_notify { 337 struct acx_header header; 338 u32 enable; 339 }; 340 341 /* 342 * ACX_RX_BA_FILTER 343 * enable/disable RX BA filtering in FW 344 */ 345 struct wl18xx_acx_rx_ba_filter { 346 struct acx_header header; 347 u32 enable; 348 }; 349 350 struct acx_ap_sleep_cfg { 351 struct acx_header header; 352 /* Duty Cycle (20-80% of staying Awake) for IDLE AP 353 * (0: disable) 354 */ 355 u8 idle_duty_cycle; 356 /* Duty Cycle (20-80% of staying Awake) for Connected AP 357 * (0: disable) 358 */ 359 u8 connected_duty_cycle; 360 /* Maximum stations that are allowed to be connected to AP 361 * (255: no limit) 362 */ 363 u8 max_stations_thresh; 364 /* Timeout till enabling the Sleep Mechanism after data stops 365 * [unit: 100 msec] 366 */ 367 u8 idle_conn_thresh; 368 } __packed; 369 370 int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap, 371 u32 sdio_blk_size, u32 extra_mem_blks, 372 u32 len_field_size); 373 int wl18xx_acx_set_checksum_state(struct wl1271 *wl); 374 int wl18xx_acx_clear_statistics(struct wl1271 *wl); 375 int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide); 376 int wl18xx_acx_set_peer_cap(struct wl1271 *wl, 377 struct ieee80211_sta_ht_cap *ht_cap, 378 bool allow_ht_operation, 379 u32 rate_set, u8 hlid); 380 int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action); 381 int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action); 382 int wl18xx_acx_ap_sleep(struct wl1271 *wl); 383 384 #endif /* __WL18XX_ACX_H__ */ 385