1 /** 2 * Copyright (c) 2014 Redpine Signals Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __RSI_MGMT_H__ 18 #define __RSI_MGMT_H__ 19 20 #include <linux/sort.h> 21 #include "rsi_boot_params.h" 22 #include "rsi_main.h" 23 24 #define MAX_MGMT_PKT_SIZE 512 25 #define RSI_NEEDED_HEADROOM 80 26 #define RSI_RCV_BUFFER_LEN 2000 27 28 #define RSI_11B_MODE 0 29 #define RSI_11G_MODE BIT(7) 30 #define RETRY_COUNT 8 31 #define RETRY_LONG 4 32 #define RETRY_SHORT 7 33 #define WMM_SHORT_SLOT_TIME 9 34 #define SIFS_DURATION 16 35 36 #define KEY_TYPE_CLEAR 0 37 #define RSI_PAIRWISE_KEY 1 38 #define RSI_GROUP_KEY 2 39 40 /* EPPROM_READ_ADDRESS */ 41 #define WLAN_MAC_EEPROM_ADDR 40 42 #define WLAN_MAC_MAGIC_WORD_LEN 0x01 43 #define WLAN_HOST_MODE_LEN 0x04 44 #define WLAN_FW_VERSION_LEN 0x08 45 #define MAGIC_WORD 0x5A 46 47 /* Receive Frame Types */ 48 #define TA_CONFIRM_TYPE 0x01 49 #define RX_DOT11_MGMT 0x02 50 #define TX_STATUS_IND 0x04 51 #define PROBEREQ_CONFIRM 2 52 #define CARD_READY_IND 0x00 53 54 #define RSI_DELETE_PEER 0x0 55 #define RSI_ADD_PEER 0x1 56 #define START_AMPDU_AGGR 0x1 57 #define STOP_AMPDU_AGGR 0x0 58 #define INTERNAL_MGMT_PKT 0x99 59 60 #define PUT_BBP_RESET 0 61 #define BBP_REG_WRITE 0 62 #define RF_RESET_ENABLE BIT(3) 63 #define RATE_INFO_ENABLE BIT(0) 64 #define RSI_BROADCAST_PKT BIT(9) 65 66 #define UPPER_20_ENABLE (0x2 << 12) 67 #define LOWER_20_ENABLE (0x4 << 12) 68 #define FULL40M_ENABLE 0x6 69 70 #define RSI_LMAC_CLOCK_80MHZ 0x1 71 #define RSI_ENABLE_40MHZ (0x1 << 3) 72 73 #define RX_BA_INDICATION 1 74 #define RSI_TBL_SZ 40 75 #define MAX_RETRIES 8 76 77 #define STD_RATE_MCS7 0x07 78 #define STD_RATE_MCS6 0x06 79 #define STD_RATE_MCS5 0x05 80 #define STD_RATE_MCS4 0x04 81 #define STD_RATE_MCS3 0x03 82 #define STD_RATE_MCS2 0x02 83 #define STD_RATE_MCS1 0x01 84 #define STD_RATE_MCS0 0x00 85 #define STD_RATE_54 0x6c 86 #define STD_RATE_48 0x60 87 #define STD_RATE_36 0x48 88 #define STD_RATE_24 0x30 89 #define STD_RATE_18 0x24 90 #define STD_RATE_12 0x18 91 #define STD_RATE_11 0x16 92 #define STD_RATE_09 0x12 93 #define STD_RATE_06 0x0C 94 #define STD_RATE_5_5 0x0B 95 #define STD_RATE_02 0x04 96 #define STD_RATE_01 0x02 97 98 #define RSI_RF_TYPE 1 99 #define RSI_RATE_00 0x00 100 #define RSI_RATE_1 0x0 101 #define RSI_RATE_2 0x2 102 #define RSI_RATE_5_5 0x4 103 #define RSI_RATE_11 0x6 104 #define RSI_RATE_6 0x8b 105 #define RSI_RATE_9 0x8f 106 #define RSI_RATE_12 0x8a 107 #define RSI_RATE_18 0x8e 108 #define RSI_RATE_24 0x89 109 #define RSI_RATE_36 0x8d 110 #define RSI_RATE_48 0x88 111 #define RSI_RATE_54 0x8c 112 #define RSI_RATE_MCS0 0x100 113 #define RSI_RATE_MCS1 0x101 114 #define RSI_RATE_MCS2 0x102 115 #define RSI_RATE_MCS3 0x103 116 #define RSI_RATE_MCS4 0x104 117 #define RSI_RATE_MCS5 0x105 118 #define RSI_RATE_MCS6 0x106 119 #define RSI_RATE_MCS7 0x107 120 #define RSI_RATE_MCS7_SG 0x307 121 122 #define BW_20MHZ 0 123 #define BW_40MHZ 1 124 125 #define RSI_SUPP_FILTERS (FIF_ALLMULTI | FIF_PROBE_REQ |\ 126 FIF_BCN_PRBRESP_PROMISC) 127 enum opmode { 128 STA_OPMODE = 1, 129 AP_OPMODE = 2 130 }; 131 132 extern struct ieee80211_rate rsi_rates[12]; 133 extern const u16 rsi_mcsrates[8]; 134 135 enum sta_notify_events { 136 STA_CONNECTED = 0, 137 STA_DISCONNECTED, 138 STA_TX_ADDBA_DONE, 139 STA_TX_DELBA, 140 STA_RX_ADDBA_DONE, 141 STA_RX_DELBA 142 }; 143 144 /* Send Frames Types */ 145 enum cmd_frame_type { 146 TX_DOT11_MGMT, 147 RESET_MAC_REQ, 148 RADIO_CAPABILITIES, 149 BB_PROG_VALUES_REQUEST, 150 RF_PROG_VALUES_REQUEST, 151 WAKEUP_SLEEP_REQUEST, 152 SCAN_REQUEST, 153 TSF_UPDATE, 154 PEER_NOTIFY, 155 BLOCK_UNBLOCK, 156 SET_KEY_REQ, 157 AUTO_RATE_IND, 158 BOOTUP_PARAMS_REQUEST, 159 VAP_CAPABILITIES, 160 EEPROM_READ_TYPE , 161 EEPROM_WRITE, 162 GPIO_PIN_CONFIG , 163 SET_RX_FILTER, 164 AMPDU_IND, 165 STATS_REQUEST_FRAME, 166 BB_BUF_PROG_VALUES_REQ, 167 BBP_PROG_IN_TA, 168 BG_SCAN_PARAMS, 169 BG_SCAN_PROBE_REQ, 170 CW_MODE_REQ, 171 PER_CMD_PKT 172 }; 173 174 struct rsi_mac_frame { 175 __le16 desc_word[8]; 176 } __packed; 177 178 struct rsi_boot_params { 179 __le16 desc_word[8]; 180 struct bootup_params bootup_params; 181 } __packed; 182 183 struct rsi_peer_notify { 184 __le16 desc_word[8]; 185 u8 mac_addr[6]; 186 __le16 command; 187 __le16 mpdu_density; 188 __le16 reserved; 189 __le32 sta_flags; 190 } __packed; 191 192 struct rsi_vap_caps { 193 __le16 desc_word[8]; 194 u8 mac_addr[6]; 195 __le16 keep_alive_period; 196 u8 bssid[6]; 197 __le16 reserved; 198 __le32 flags; 199 __le16 frag_threshold; 200 __le16 rts_threshold; 201 __le32 default_mgmt_rate; 202 __le32 default_ctrl_rate; 203 __le32 default_data_rate; 204 __le16 beacon_interval; 205 __le16 dtim_period; 206 } __packed; 207 208 struct rsi_set_key { 209 __le16 desc_word[8]; 210 u8 key[4][32]; 211 u8 tx_mic_key[8]; 212 u8 rx_mic_key[8]; 213 } __packed; 214 215 struct rsi_auto_rate { 216 __le16 desc_word[8]; 217 __le16 failure_limit; 218 __le16 initial_boundary; 219 __le16 max_threshold_limt; 220 __le16 num_supported_rates; 221 __le16 aarf_rssi; 222 __le16 moderate_rate_inx; 223 __le16 collision_tolerance; 224 __le16 supported_rates[40]; 225 } __packed; 226 227 struct qos_params { 228 __le16 cont_win_min_q; 229 __le16 cont_win_max_q; 230 __le16 aifsn_val_q; 231 __le16 txop_q; 232 } __packed; 233 234 struct rsi_radio_caps { 235 __le16 desc_word[8]; 236 struct qos_params qos_params[MAX_HW_QUEUES]; 237 u8 num_11n_rates; 238 u8 num_11ac_rates; 239 __le16 gcpd_per_rate[20]; 240 } __packed; 241 242 static inline u32 rsi_get_queueno(u8 *addr, u16 offset) 243 { 244 return (le16_to_cpu(*(__le16 *)&addr[offset]) & 0x7000) >> 12; 245 } 246 247 static inline u32 rsi_get_length(u8 *addr, u16 offset) 248 { 249 return (le16_to_cpu(*(__le16 *)&addr[offset])) & 0x0fff; 250 } 251 252 static inline u8 rsi_get_extended_desc(u8 *addr, u16 offset) 253 { 254 return le16_to_cpu(*((__le16 *)&addr[offset + 4])) & 0x00ff; 255 } 256 257 static inline u8 rsi_get_rssi(u8 *addr) 258 { 259 return *(u8 *)(addr + FRAME_DESC_SZ); 260 } 261 262 static inline u8 rsi_get_channel(u8 *addr) 263 { 264 return *(char *)(addr + 15); 265 } 266 267 int rsi_mgmt_pkt_recv(struct rsi_common *common, u8 *msg); 268 int rsi_set_vap_capabilities(struct rsi_common *common, enum opmode mode); 269 int rsi_send_aggregation_params_frame(struct rsi_common *common, u16 tid, 270 u16 ssn, u8 buf_size, u8 event); 271 int rsi_hal_load_key(struct rsi_common *common, u8 *data, u16 key_len, 272 u8 key_type, u8 key_id, u32 cipher); 273 int rsi_set_channel(struct rsi_common *common, u16 chno); 274 void rsi_inform_bss_status(struct rsi_common *common, u8 status, 275 const u8 *bssid, u8 qos_enable, u16 aid); 276 void rsi_indicate_pkt_to_os(struct rsi_common *common, struct sk_buff *skb); 277 int rsi_mac80211_attach(struct rsi_common *common); 278 void rsi_indicate_tx_status(struct rsi_hw *common, struct sk_buff *skb, 279 int status); 280 bool rsi_is_cipher_wep(struct rsi_common *common); 281 void rsi_core_qos_processor(struct rsi_common *common); 282 void rsi_core_xmit(struct rsi_common *common, struct sk_buff *skb); 283 int rsi_send_mgmt_pkt(struct rsi_common *common, struct sk_buff *skb); 284 int rsi_send_data_pkt(struct rsi_common *common, struct sk_buff *skb); 285 #endif 286