1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_TXRX_H__ 6 #define __RTW89_TXRX_H__ 7 8 #include "debug.h" 9 10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 12 #define DATA_RATE_MODE_NON_HT 0x0 13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 14 #define DATA_RATE_MODE_HT 0x1 15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 17 #define DATA_RATE_MODE_VHT 0x2 18 #define DATA_RATE_MODE_HE 0x3 19 #define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) 20 #define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) 21 #define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) 22 #define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) 23 #define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) 24 25 /* TX WD BODY DWORD 0 */ 26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 27 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 28 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 29 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 30 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 31 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 32 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 33 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 34 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2) 35 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0) 36 37 /* TX WD BODY DWORD 1 */ 38 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 39 40 /* TX WD BODY DWORD 2 */ 41 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 42 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 43 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 44 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 45 46 /* TX WD BODY DWORD 3 */ 47 #define RTW89_TXWD_BODY3_BK BIT(13) 48 #define RTW89_TXWD_BODY3_AGG_EN BIT(12) 49 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 50 51 /* TX WD BODY DWORD 4 */ 52 53 /* TX WD BODY DWORD 5 */ 54 55 /* TX WD INFO DWORD 0 */ 56 #define RTW89_TXWD_INFO0_USE_RATE BIT(30) 57 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 58 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 59 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 60 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 61 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4) 62 63 /* TX WD INFO DWORD 1 */ 64 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 65 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 66 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 67 68 /* TX WD INFO DWORD 2 */ 69 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 70 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 71 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 72 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 73 74 /* TX WD INFO DWORD 3 */ 75 76 /* TX WD INFO DWORD 4 */ 77 #define RTW89_TXWD_INFO4_RTS_EN BIT(27) 78 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 79 80 /* TX WD INFO DWORD 5 */ 81 82 /* RX DESC helpers */ 83 /* Short Descriptor */ 84 #define RTW89_GET_RXWD_LONG_RXD(rxdesc) \ 85 le32_get_bits((rxdesc)->dword0, BIT(31)) 86 #define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \ 87 le32_get_bits((rxdesc)->dword0, GENMASK(30, 28)) 88 #define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \ 89 le32_get_bits((rxdesc)->dword0, GENMASK(27, 24)) 90 #define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \ 91 le32_get_bits((rxdesc)->dword0, BIT(23)) 92 #define RTW89_GET_RXWD_BB_SEL(rxdesc) \ 93 le32_get_bits((rxdesc)->dword0, BIT(22)) 94 #define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \ 95 le32_get_bits((rxdesc)->dword0, GENMASK(21, 16)) 96 #define RTW89_GET_RXWD_SHIFT(rxdesc) \ 97 le32_get_bits((rxdesc)->dword0, GENMASK(15, 14)) 98 #define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \ 99 le32_get_bits((rxdesc)->dword0, GENMASK(13, 0)) 100 #define RTW89_GET_RXWD_BW(rxdesc) \ 101 le32_get_bits((rxdesc)->dword1, GENMASK(31, 30)) 102 #define RTW89_GET_RXWD_GI_LTF(rxdesc) \ 103 le32_get_bits((rxdesc)->dword1, GENMASK(27, 25)) 104 #define RTW89_GET_RXWD_DATA_RATE(rxdesc) \ 105 le32_get_bits((rxdesc)->dword1, GENMASK(24, 16)) 106 #define RTW89_GET_RXWD_USER_ID(rxdesc) \ 107 le32_get_bits((rxdesc)->dword1, GENMASK(15, 8)) 108 #define RTW89_GET_RXWD_SR_EN(rxdesc) \ 109 le32_get_bits((rxdesc)->dword1, BIT(7)) 110 #define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \ 111 le32_get_bits((rxdesc)->dword1, GENMASK(6, 4)) 112 #define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \ 113 le32_get_bits((rxdesc)->dword1, GENMASK(3, 0)) 114 #define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \ 115 le32_get_bits((rxdesc)->dword2, GENMASK(31, 0)) 116 #define RTW89_GET_RXWD_ICV_ERR(rxdesc) \ 117 le32_get_bits((rxdesc)->dword3, BIT(10)) 118 #define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \ 119 le32_get_bits((rxdesc)->dword3, BIT(9)) 120 #define RTW89_GET_RXWD_HW_DEC(rxdesc) \ 121 le32_get_bits((rxdesc)->dword3, BIT(2)) 122 #define RTW89_GET_RXWD_SW_DEC(rxdesc) \ 123 le32_get_bits((rxdesc)->dword3, BIT(1)) 124 #define RTW89_GET_RXWD_A1_MATCH(rxdesc) \ 125 le32_get_bits((rxdesc)->dword3, BIT(0)) 126 127 /* Long Descriptor */ 128 #define RTW89_GET_RXWD_FRAG(rxdesc) \ 129 le32_get_bits((rxdesc)->dword4, GENMASK(31, 28)) 130 #define RTW89_GET_RXWD_SEQ(rxdesc) \ 131 le32_get_bits((rxdesc)->dword4, GENMASK(27, 16)) 132 #define RTW89_GET_RXWD_TYPE(rxdesc) \ 133 le32_get_bits((rxdesc)->dword4, GENMASK(1, 0)) 134 #define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \ 135 le32_get_bits((rxdesc)->dword5, BIT(28)) 136 #define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \ 137 le32_get_bits((rxdesc)->dword5, GENMASK(27, 24)) 138 #define RTW89_GET_RXWD_MAC_ID(rxdesc) \ 139 le32_get_bits((rxdesc)->dword5, GENMASK(23, 16)) 140 #define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \ 141 le32_get_bits((rxdesc)->dword5, GENMASK(15, 8)) 142 #define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \ 143 le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) 144 145 #define RTW89_GET_RXINFO_USR_NUM(rpt) \ 146 le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0)) 147 #define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ 148 le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8)) 149 #define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ 150 le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16)) 151 #define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ 152 le32_get_bits(*((const __le32 *)rpt), BIT(28)) 153 #define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ 154 le32_get_bits(*((const __le32 *)rpt), BIT(29)) 155 #define RTW89_GET_RXINFO_LONG_RXD(rpt) \ 156 le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30)) 157 #define RTW89_GET_RXINFO_SERVICE(rpt) \ 158 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0)) 159 #define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ 160 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16)) 161 #define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ 162 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0)) 163 #define RTW89_GET_RXINFO_DATA(rpt, usr) \ 164 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1)) 165 #define RTW89_GET_RXINFO_CTRL(rpt, usr) \ 166 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2)) 167 #define RTW89_GET_RXINFO_MGMT(rpt, usr) \ 168 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3)) 169 #define RTW89_GET_RXINFO_BCM(rpt, usr) \ 170 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4)) 171 #define RTW89_GET_RXINFO_MACID(rpt, usr) \ 172 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) 173 174 #define RTW89_GET_PHY_STS_IE_MAP(sts) \ 175 le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0)) 176 #define RTW89_GET_PHY_STS_RSSI_A(sts) \ 177 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0)) 178 #define RTW89_GET_PHY_STS_RSSI_B(sts) \ 179 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8)) 180 #define RTW89_GET_PHY_STS_RSSI_C(sts) \ 181 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16)) 182 #define RTW89_GET_PHY_STS_RSSI_D(sts) \ 183 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24)) 184 #define RTW89_GET_PHY_STS_LEN(sts) \ 185 le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8)) 186 #define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ 187 le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24)) 188 #define RTW89_GET_PHY_STS_IE_TYPE(ie) \ 189 le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0)) 190 #define RTW89_GET_PHY_STS_IE_LEN(ie) \ 191 le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5)) 192 #define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \ 193 le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16)) 194 #define RTW89_GET_PHY_STS_IE01_CFO(ie) \ 195 le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20)) 196 197 enum rtw89_tx_channel { 198 RTW89_TXCH_ACH0 = 0, 199 RTW89_TXCH_ACH1 = 1, 200 RTW89_TXCH_ACH2 = 2, 201 RTW89_TXCH_ACH3 = 3, 202 RTW89_TXCH_ACH4 = 4, 203 RTW89_TXCH_ACH5 = 5, 204 RTW89_TXCH_ACH6 = 6, 205 RTW89_TXCH_ACH7 = 7, 206 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 207 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 208 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 209 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 210 RTW89_TXCH_CH12 = 12, /* FW CMD */ 211 212 /* keep last */ 213 RTW89_TXCH_NUM, 214 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 215 }; 216 217 enum rtw89_rx_channel { 218 RTW89_RXCH_RXQ = 0, 219 RTW89_RXCH_RPQ = 1, 220 221 /* keep last */ 222 RTW89_RXCH_NUM, 223 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 224 }; 225 226 enum rtw89_tx_qsel { 227 RTW89_TX_QSEL_BE_0 = 0x00, 228 RTW89_TX_QSEL_BK_0 = 0x01, 229 RTW89_TX_QSEL_VI_0 = 0x02, 230 RTW89_TX_QSEL_VO_0 = 0x03, 231 RTW89_TX_QSEL_BE_1 = 0x04, 232 RTW89_TX_QSEL_BK_1 = 0x05, 233 RTW89_TX_QSEL_VI_1 = 0x06, 234 RTW89_TX_QSEL_VO_1 = 0x07, 235 RTW89_TX_QSEL_BE_2 = 0x08, 236 RTW89_TX_QSEL_BK_2 = 0x09, 237 RTW89_TX_QSEL_VI_2 = 0x0a, 238 RTW89_TX_QSEL_VO_2 = 0x0b, 239 RTW89_TX_QSEL_BE_3 = 0x0c, 240 RTW89_TX_QSEL_BK_3 = 0x0d, 241 RTW89_TX_QSEL_VI_3 = 0x0e, 242 RTW89_TX_QSEL_VO_3 = 0x0f, 243 RTW89_TX_QSEL_B0_BCN = 0x10, 244 RTW89_TX_QSEL_B0_HI = 0x11, 245 RTW89_TX_QSEL_B0_MGMT = 0x12, 246 RTW89_TX_QSEL_B0_NOPS = 0x13, 247 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 248 /* reserved */ 249 /* reserved */ 250 /* reserved */ 251 RTW89_TX_QSEL_B1_BCN = 0x18, 252 RTW89_TX_QSEL_B1_HI = 0x19, 253 RTW89_TX_QSEL_B1_MGMT = 0x1a, 254 RTW89_TX_QSEL_B1_NOPS = 0x1b, 255 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 256 /* reserved */ 257 /* reserved */ 258 /* reserved */ 259 }; 260 261 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 262 { 263 switch (tid) { 264 default: 265 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 266 fallthrough; 267 case 0: 268 case 3: 269 return RTW89_TX_QSEL_BE_0; 270 case 1: 271 case 2: 272 return RTW89_TX_QSEL_BK_0; 273 case 4: 274 case 5: 275 return RTW89_TX_QSEL_VI_0; 276 case 6: 277 case 7: 278 return RTW89_TX_QSEL_VO_0; 279 } 280 } 281 282 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 283 { 284 switch (qsel) { 285 default: 286 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 287 fallthrough; 288 case RTW89_TX_QSEL_BE_0: 289 return RTW89_TXCH_ACH0; 290 case RTW89_TX_QSEL_BK_0: 291 return RTW89_TXCH_ACH1; 292 case RTW89_TX_QSEL_VI_0: 293 return RTW89_TXCH_ACH2; 294 case RTW89_TX_QSEL_VO_0: 295 return RTW89_TXCH_ACH3; 296 case RTW89_TX_QSEL_B0_MGMT: 297 return RTW89_TXCH_CH8; 298 case RTW89_TX_QSEL_B0_HI: 299 return RTW89_TXCH_CH9; 300 case RTW89_TX_QSEL_B1_MGMT: 301 return RTW89_TXCH_CH10; 302 case RTW89_TX_QSEL_B1_HI: 303 return RTW89_TXCH_CH11; 304 } 305 } 306 307 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 308 { 309 switch (tid) { 310 case 3: 311 case 2: 312 case 5: 313 case 7: 314 return 1; 315 default: 316 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 317 fallthrough; 318 case 0: 319 case 1: 320 case 4: 321 case 6: 322 return 0; 323 } 324 } 325 326 #endif 327