1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_TXRX_H__ 6 #define __RTW89_TXRX_H__ 7 8 #include "debug.h" 9 10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 12 #define DATA_RATE_MODE_NON_HT 0x0 13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 14 #define DATA_RATE_MODE_HT 0x1 15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 17 #define DATA_RATE_MODE_VHT 0x2 18 #define DATA_RATE_MODE_HE 0x3 19 #define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) 20 #define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) 21 #define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) 22 #define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) 23 #define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) 24 25 /* TX WD BODY DWORD 0 */ 26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 27 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24) 28 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 29 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 30 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 31 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 32 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 33 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 34 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 35 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2) 36 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0) 37 38 /* TX WD BODY DWORD 1 */ 39 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 40 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 41 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4) 42 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0) 43 44 /* TX WD BODY DWORD 2 */ 45 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 46 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 47 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 48 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 49 50 /* TX WD BODY DWORD 3 */ 51 #define RTW89_TXWD_BODY3_BK BIT(13) 52 #define RTW89_TXWD_BODY3_AGG_EN BIT(12) 53 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 54 55 /* TX WD BODY DWORD 4 */ 56 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24) 57 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16) 58 59 /* TX WD BODY DWORD 5 */ 60 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24) 61 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16) 62 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8) 63 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0) 64 65 /* TX WD BODY DWORD 6 (V1) */ 66 67 /* TX WD BODY DWORD 7 (V1) */ 68 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31) 69 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28) 70 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25) 71 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16) 72 73 /* TX WD INFO DWORD 0 */ 74 #define RTW89_TXWD_INFO0_USE_RATE BIT(30) 75 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 76 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 77 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 78 #define RTW89_TXWD_INFO0_DATA_ER BIT(15) 79 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 80 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8) 81 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4) 82 83 /* TX WD INFO DWORD 1 */ 84 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 85 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 86 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 87 88 /* TX WD INFO DWORD 2 */ 89 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 90 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 91 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 92 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8) 93 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 94 95 /* TX WD INFO DWORD 3 */ 96 97 /* TX WD INFO DWORD 4 */ 98 #define RTW89_TXWD_INFO4_RTS_EN BIT(27) 99 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 100 101 /* TX WD INFO DWORD 5 */ 102 103 /* RX WD dword0 */ 104 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0) 105 #define AX_RXD_SHIFT_MASK GENMASK(15, 14) 106 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16) 107 #define AX_RXD_BB_SEL BIT(22) 108 #define AX_RXD_MAC_INFO_VLD BIT(23) 109 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24) 110 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28) 111 #define AX_RXD_LONG_RXD BIT(31) 112 113 /* RX WD dword1 */ 114 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0) 115 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4) 116 #define AX_RXD_SR_EN BIT(7) 117 #define AX_RXD_USER_ID_MASK GENMASK(15, 8) 118 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8) 119 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16) 120 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25) 121 #define AX_RXD_NON_SRG_PPDU BIT(28) 122 #define AX_RXD_INTER_PPDU BIT(29) 123 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14) 124 #define AX_RXD_INTER_PPDU_v1 BIT(15) 125 #define AX_RXD_BW_MASK GENMASK(31, 30) 126 #define AX_RXD_BW_v1_MASK GENMASK(31, 29) 127 128 /* RX WD dword2 */ 129 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 130 131 /* RX WD dword3 */ 132 #define AX_RXD_A1_MATCH BIT(0) 133 #define AX_RXD_SW_DEC BIT(1) 134 #define AX_RXD_HW_DEC BIT(2) 135 #define AX_RXD_AMPDU BIT(3) 136 #define AX_RXD_AMPDU_END_PKT BIT(4) 137 #define AX_RXD_AMSDU BIT(5) 138 #define AX_RXD_AMSDU_CUT BIT(6) 139 #define AX_RXD_LAST_MSDU BIT(7) 140 #define AX_RXD_BYPASS BIT(8) 141 #define AX_RXD_CRC32_ERR BIT(9) 142 #define AX_RXD_ICV_ERR BIT(10) 143 #define AX_RXD_MAGIC_WAKE BIT(11) 144 #define AX_RXD_UNICAST_WAKE BIT(12) 145 #define AX_RXD_PATTERN_WAKE BIT(13) 146 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14) 147 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16) 148 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21) 149 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) 150 #define AX_RXD_WITH_LLC BIT(25) 151 #define AX_RXD_RX_STATISTICS BIT(26) 152 153 /* RX WD dword4 */ 154 #define AX_RXD_TYPE_MASK GENMASK(1, 0) 155 #define AX_RXD_MC BIT(2) 156 #define AX_RXD_BC BIT(3) 157 #define AX_RXD_MD BIT(4) 158 #define AX_RXD_MF BIT(5) 159 #define AX_RXD_PWR BIT(6) 160 #define AX_RXD_QOS BIT(7) 161 #define AX_RXD_TID_MASK GENMASK(11, 8) 162 #define AX_RXD_EOSP BIT(12) 163 #define AX_RXD_HTC BIT(13) 164 #define AX_RXD_QNULL BIT(14) 165 #define AX_RXD_SEQ_MASK GENMASK(27, 16) 166 #define AX_RXD_FRAG_MASK GENMASK(31, 28) 167 168 /* RX WD dword5 */ 169 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0) 170 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8) 171 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16) 172 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24) 173 #define AX_RXD_ADDR_CAM_VLD BIT(28) 174 #define AX_RXD_ADDR_FWD_EN BIT(29) 175 #define AX_RXD_RX_PL_MATCH BIT(30) 176 177 /* RX WD dword6 */ 178 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0) 179 180 /* RX WD dword7 */ 181 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 182 #define AX_RXD_SMART_ANT BIT(16) 183 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17) 184 #define AX_RXD_HDR_CNV BIT(21) 185 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22) 186 #define AX_RXD_BIP_KEYID BIT(27) 187 #define AX_RXD_BIP_ENC BIT(28) 188 189 /* RX DESC helpers */ 190 /* Short Descriptor */ 191 #define RTW89_GET_RXWD_LONG_RXD(rxdesc) \ 192 le32_get_bits((rxdesc)->dword0, BIT(31)) 193 #define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \ 194 le32_get_bits((rxdesc)->dword0, GENMASK(30, 28)) 195 #define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \ 196 le32_get_bits((rxdesc)->dword0, GENMASK(27, 24)) 197 #define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \ 198 le32_get_bits((rxdesc)->dword0, BIT(23)) 199 #define RTW89_GET_RXWD_BB_SEL(rxdesc) \ 200 le32_get_bits((rxdesc)->dword0, BIT(22)) 201 #define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \ 202 le32_get_bits((rxdesc)->dword0, GENMASK(21, 16)) 203 #define RTW89_GET_RXWD_SHIFT(rxdesc) \ 204 le32_get_bits((rxdesc)->dword0, GENMASK(15, 14)) 205 #define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \ 206 le32_get_bits((rxdesc)->dword0, GENMASK(13, 0)) 207 #define RTW89_GET_RXWD_BW(rxdesc) \ 208 le32_get_bits((rxdesc)->dword1, GENMASK(31, 30)) 209 #define RTW89_GET_RXWD_BW_V1(rxdesc) \ 210 le32_get_bits((rxdesc)->dword1, GENMASK(31, 29)) 211 #define RTW89_GET_RXWD_GI_LTF(rxdesc) \ 212 le32_get_bits((rxdesc)->dword1, GENMASK(27, 25)) 213 #define RTW89_GET_RXWD_DATA_RATE(rxdesc) \ 214 le32_get_bits((rxdesc)->dword1, GENMASK(24, 16)) 215 #define RTW89_GET_RXWD_USER_ID(rxdesc) \ 216 le32_get_bits((rxdesc)->dword1, GENMASK(15, 8)) 217 #define RTW89_GET_RXWD_SR_EN(rxdesc) \ 218 le32_get_bits((rxdesc)->dword1, BIT(7)) 219 #define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \ 220 le32_get_bits((rxdesc)->dword1, GENMASK(6, 4)) 221 #define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \ 222 le32_get_bits((rxdesc)->dword1, GENMASK(3, 0)) 223 #define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \ 224 le32_get_bits((rxdesc)->dword2, GENMASK(31, 0)) 225 #define RTW89_GET_RXWD_ICV_ERR(rxdesc) \ 226 le32_get_bits((rxdesc)->dword3, BIT(10)) 227 #define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \ 228 le32_get_bits((rxdesc)->dword3, BIT(9)) 229 #define RTW89_GET_RXWD_HW_DEC(rxdesc) \ 230 le32_get_bits((rxdesc)->dword3, BIT(2)) 231 #define RTW89_GET_RXWD_SW_DEC(rxdesc) \ 232 le32_get_bits((rxdesc)->dword3, BIT(1)) 233 #define RTW89_GET_RXWD_A1_MATCH(rxdesc) \ 234 le32_get_bits((rxdesc)->dword3, BIT(0)) 235 236 /* Long Descriptor */ 237 #define RTW89_GET_RXWD_FRAG(rxdesc) \ 238 le32_get_bits((rxdesc)->dword4, GENMASK(31, 28)) 239 #define RTW89_GET_RXWD_SEQ(rxdesc) \ 240 le32_get_bits((rxdesc)->dword4, GENMASK(27, 16)) 241 #define RTW89_GET_RXWD_TYPE(rxdesc) \ 242 le32_get_bits((rxdesc)->dword4, GENMASK(1, 0)) 243 #define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \ 244 le32_get_bits((rxdesc)->dword5, BIT(28)) 245 #define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \ 246 le32_get_bits((rxdesc)->dword5, GENMASK(27, 24)) 247 #define RTW89_GET_RXWD_MAC_ID(rxdesc) \ 248 le32_get_bits((rxdesc)->dword5, GENMASK(23, 16)) 249 #define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \ 250 le32_get_bits((rxdesc)->dword5, GENMASK(15, 8)) 251 #define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \ 252 le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) 253 254 #define RTW89_GET_RXINFO_USR_NUM(rpt) \ 255 le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0)) 256 #define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ 257 le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8)) 258 #define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ 259 le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16)) 260 #define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ 261 le32_get_bits(*((const __le32 *)rpt), BIT(28)) 262 #define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ 263 le32_get_bits(*((const __le32 *)rpt), BIT(29)) 264 #define RTW89_GET_RXINFO_LONG_RXD(rpt) \ 265 le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30)) 266 #define RTW89_GET_RXINFO_SERVICE(rpt) \ 267 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0)) 268 #define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ 269 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16)) 270 #define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ 271 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0)) 272 #define RTW89_GET_RXINFO_DATA(rpt, usr) \ 273 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1)) 274 #define RTW89_GET_RXINFO_CTRL(rpt, usr) \ 275 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2)) 276 #define RTW89_GET_RXINFO_MGMT(rpt, usr) \ 277 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3)) 278 #define RTW89_GET_RXINFO_BCM(rpt, usr) \ 279 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4)) 280 #define RTW89_GET_RXINFO_MACID(rpt, usr) \ 281 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) 282 283 #define RTW89_GET_PHY_STS_IE_MAP(sts) \ 284 le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0)) 285 #define RTW89_GET_PHY_STS_RSSI_A(sts) \ 286 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0)) 287 #define RTW89_GET_PHY_STS_RSSI_B(sts) \ 288 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8)) 289 #define RTW89_GET_PHY_STS_RSSI_C(sts) \ 290 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16)) 291 #define RTW89_GET_PHY_STS_RSSI_D(sts) \ 292 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24)) 293 #define RTW89_GET_PHY_STS_LEN(sts) \ 294 le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8)) 295 #define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ 296 le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24)) 297 #define RTW89_GET_PHY_STS_IE_TYPE(ie) \ 298 le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0)) 299 #define RTW89_GET_PHY_STS_IE_LEN(ie) \ 300 le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5)) 301 #define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \ 302 le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16)) 303 #define RTW89_GET_PHY_STS_IE01_FD_CFO(ie) \ 304 le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(19, 8)) 305 #define RTW89_GET_PHY_STS_IE01_PREMB_CFO(ie) \ 306 le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20)) 307 308 enum rtw89_tx_channel { 309 RTW89_TXCH_ACH0 = 0, 310 RTW89_TXCH_ACH1 = 1, 311 RTW89_TXCH_ACH2 = 2, 312 RTW89_TXCH_ACH3 = 3, 313 RTW89_TXCH_ACH4 = 4, 314 RTW89_TXCH_ACH5 = 5, 315 RTW89_TXCH_ACH6 = 6, 316 RTW89_TXCH_ACH7 = 7, 317 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 318 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 319 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 320 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 321 RTW89_TXCH_CH12 = 12, /* FW CMD */ 322 323 /* keep last */ 324 RTW89_TXCH_NUM, 325 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 326 }; 327 328 enum rtw89_rx_channel { 329 RTW89_RXCH_RXQ = 0, 330 RTW89_RXCH_RPQ = 1, 331 332 /* keep last */ 333 RTW89_RXCH_NUM, 334 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 335 }; 336 337 enum rtw89_tx_qsel { 338 RTW89_TX_QSEL_BE_0 = 0x00, 339 RTW89_TX_QSEL_BK_0 = 0x01, 340 RTW89_TX_QSEL_VI_0 = 0x02, 341 RTW89_TX_QSEL_VO_0 = 0x03, 342 RTW89_TX_QSEL_BE_1 = 0x04, 343 RTW89_TX_QSEL_BK_1 = 0x05, 344 RTW89_TX_QSEL_VI_1 = 0x06, 345 RTW89_TX_QSEL_VO_1 = 0x07, 346 RTW89_TX_QSEL_BE_2 = 0x08, 347 RTW89_TX_QSEL_BK_2 = 0x09, 348 RTW89_TX_QSEL_VI_2 = 0x0a, 349 RTW89_TX_QSEL_VO_2 = 0x0b, 350 RTW89_TX_QSEL_BE_3 = 0x0c, 351 RTW89_TX_QSEL_BK_3 = 0x0d, 352 RTW89_TX_QSEL_VI_3 = 0x0e, 353 RTW89_TX_QSEL_VO_3 = 0x0f, 354 RTW89_TX_QSEL_B0_BCN = 0x10, 355 RTW89_TX_QSEL_B0_HI = 0x11, 356 RTW89_TX_QSEL_B0_MGMT = 0x12, 357 RTW89_TX_QSEL_B0_NOPS = 0x13, 358 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 359 /* reserved */ 360 /* reserved */ 361 /* reserved */ 362 RTW89_TX_QSEL_B1_BCN = 0x18, 363 RTW89_TX_QSEL_B1_HI = 0x19, 364 RTW89_TX_QSEL_B1_MGMT = 0x1a, 365 RTW89_TX_QSEL_B1_NOPS = 0x1b, 366 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 367 /* reserved */ 368 /* reserved */ 369 /* reserved */ 370 }; 371 372 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 373 { 374 switch (tid) { 375 default: 376 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 377 fallthrough; 378 case 0: 379 case 3: 380 return RTW89_TX_QSEL_BE_0; 381 case 1: 382 case 2: 383 return RTW89_TX_QSEL_BK_0; 384 case 4: 385 case 5: 386 return RTW89_TX_QSEL_VI_0; 387 case 6: 388 case 7: 389 return RTW89_TX_QSEL_VO_0; 390 } 391 } 392 393 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 394 { 395 switch (qsel) { 396 default: 397 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 398 fallthrough; 399 case RTW89_TX_QSEL_BE_0: 400 return RTW89_TXCH_ACH0; 401 case RTW89_TX_QSEL_BK_0: 402 return RTW89_TXCH_ACH1; 403 case RTW89_TX_QSEL_VI_0: 404 return RTW89_TXCH_ACH2; 405 case RTW89_TX_QSEL_VO_0: 406 return RTW89_TXCH_ACH3; 407 case RTW89_TX_QSEL_B0_MGMT: 408 return RTW89_TXCH_CH8; 409 case RTW89_TX_QSEL_B0_HI: 410 return RTW89_TXCH_CH9; 411 case RTW89_TX_QSEL_B1_MGMT: 412 return RTW89_TXCH_CH10; 413 case RTW89_TX_QSEL_B1_HI: 414 return RTW89_TXCH_CH11; 415 } 416 } 417 418 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 419 { 420 switch (tid) { 421 case 3: 422 case 2: 423 case 5: 424 case 7: 425 return 1; 426 default: 427 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 428 fallthrough; 429 case 0: 430 case 1: 431 case 4: 432 case 6: 433 return 0; 434 } 435 } 436 437 #endif 438