1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "debug.h" 10 #include "fw.h" 11 #include "mac.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "ser.h" 15 #include "util.h" 16 17 #define SER_RECFG_TIMEOUT 1000 18 19 enum ser_evt { 20 SER_EV_NONE, 21 SER_EV_STATE_IN, 22 SER_EV_STATE_OUT, 23 SER_EV_L1_RESET_PREPARE, /* pre-M0 */ 24 SER_EV_L1_RESET, /* M1 */ 25 SER_EV_DO_RECOVERY, /* M3 */ 26 SER_EV_MAC_RESET_DONE, /* M5 */ 27 SER_EV_L2_RESET, 28 SER_EV_L2_RECFG_DONE, 29 SER_EV_L2_RECFG_TIMEOUT, 30 SER_EV_M1_TIMEOUT, 31 SER_EV_M3_TIMEOUT, 32 SER_EV_FW_M5_TIMEOUT, 33 SER_EV_L0_RESET, 34 SER_EV_MAXX 35 }; 36 37 enum ser_state { 38 SER_IDLE_ST, 39 SER_L1_RESET_PRE_ST, 40 SER_RESET_TRX_ST, 41 SER_DO_HCI_ST, 42 SER_L2_RESET_ST, 43 SER_ST_MAX_ST 44 }; 45 46 struct ser_msg { 47 struct list_head list; 48 u8 event; 49 }; 50 51 struct state_ent { 52 u8 state; 53 char *name; 54 void (*st_func)(struct rtw89_ser *ser, u8 event); 55 }; 56 57 struct event_ent { 58 u8 event; 59 char *name; 60 }; 61 62 static char *ser_ev_name(struct rtw89_ser *ser, u8 event) 63 { 64 if (event < SER_EV_MAXX) 65 return ser->ev_tbl[event].name; 66 67 return "err_ev_name"; 68 } 69 70 static char *ser_st_name(struct rtw89_ser *ser) 71 { 72 if (ser->state < SER_ST_MAX_ST) 73 return ser->st_tbl[ser->state].name; 74 75 return "err_st_name"; 76 } 77 78 #define RTW89_DEF_SER_CD_TYPE(_name, _type, _size) \ 79 struct ser_cd_ ## _name { \ 80 u32 type; \ 81 u32 type_size; \ 82 u64 padding; \ 83 u8 data[_size]; \ 84 } __packed; \ 85 static void ser_cd_ ## _name ## _init(struct ser_cd_ ## _name *p) \ 86 { \ 87 p->type = _type; \ 88 p->type_size = sizeof(p->data); \ 89 p->padding = 0x0123456789abcdef; \ 90 } 91 92 enum rtw89_ser_cd_type { 93 RTW89_SER_CD_FW_RSVD_PLE = 0, 94 RTW89_SER_CD_FW_BACKTRACE = 1, 95 }; 96 97 RTW89_DEF_SER_CD_TYPE(fw_rsvd_ple, 98 RTW89_SER_CD_FW_RSVD_PLE, 99 RTW89_FW_RSVD_PLE_SIZE); 100 101 RTW89_DEF_SER_CD_TYPE(fw_backtrace, 102 RTW89_SER_CD_FW_BACKTRACE, 103 RTW89_FW_BACKTRACE_MAX_SIZE); 104 105 struct rtw89_ser_cd_buffer { 106 struct ser_cd_fw_rsvd_ple fwple; 107 struct ser_cd_fw_backtrace fwbt; 108 } __packed; 109 110 static struct rtw89_ser_cd_buffer *rtw89_ser_cd_prep(struct rtw89_dev *rtwdev) 111 { 112 struct rtw89_ser_cd_buffer *buf; 113 114 buf = vzalloc(sizeof(*buf)); 115 if (!buf) 116 return NULL; 117 118 ser_cd_fw_rsvd_ple_init(&buf->fwple); 119 ser_cd_fw_backtrace_init(&buf->fwbt); 120 121 return buf; 122 } 123 124 static void rtw89_ser_cd_send(struct rtw89_dev *rtwdev, 125 struct rtw89_ser_cd_buffer *buf) 126 { 127 rtw89_debug(rtwdev, RTW89_DBG_SER, "SER sends core dump\n"); 128 129 /* After calling dev_coredump, buf's lifetime is supposed to be 130 * handled by the device coredump framework. Note that a new dump 131 * will be discarded if a previous one hasn't been released by 132 * framework yet. 133 */ 134 dev_coredumpv(rtwdev->dev, buf, sizeof(*buf), GFP_KERNEL); 135 } 136 137 static void rtw89_ser_cd_free(struct rtw89_dev *rtwdev, 138 struct rtw89_ser_cd_buffer *buf, bool free_self) 139 { 140 if (!free_self) 141 return; 142 143 rtw89_debug(rtwdev, RTW89_DBG_SER, "SER frees core dump by self\n"); 144 145 /* When some problems happen during filling data of core dump, 146 * we won't send it to device coredump framework. Instead, we 147 * free buf by ourselves. 148 */ 149 vfree(buf); 150 } 151 152 static void ser_state_run(struct rtw89_ser *ser, u8 evt) 153 { 154 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 155 156 rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s receive %s\n", 157 ser_st_name(ser), ser_ev_name(ser, evt)); 158 159 mutex_lock(&rtwdev->mutex); 160 rtw89_leave_lps(rtwdev); 161 mutex_unlock(&rtwdev->mutex); 162 163 ser->st_tbl[ser->state].st_func(ser, evt); 164 } 165 166 static void ser_state_goto(struct rtw89_ser *ser, u8 new_state) 167 { 168 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 169 170 if (ser->state == new_state || new_state >= SER_ST_MAX_ST) 171 return; 172 ser_state_run(ser, SER_EV_STATE_OUT); 173 174 rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s goto -> %s\n", 175 ser_st_name(ser), ser->st_tbl[new_state].name); 176 177 ser->state = new_state; 178 ser_state_run(ser, SER_EV_STATE_IN); 179 } 180 181 static struct ser_msg *__rtw89_ser_dequeue_msg(struct rtw89_ser *ser) 182 { 183 struct ser_msg *msg; 184 185 spin_lock_irq(&ser->msg_q_lock); 186 msg = list_first_entry_or_null(&ser->msg_q, struct ser_msg, list); 187 if (msg) 188 list_del(&msg->list); 189 spin_unlock_irq(&ser->msg_q_lock); 190 191 return msg; 192 } 193 194 static void rtw89_ser_hdl_work(struct work_struct *work) 195 { 196 struct ser_msg *msg; 197 struct rtw89_ser *ser = container_of(work, struct rtw89_ser, 198 ser_hdl_work); 199 200 while ((msg = __rtw89_ser_dequeue_msg(ser))) { 201 ser_state_run(ser, msg->event); 202 kfree(msg); 203 } 204 } 205 206 static int ser_send_msg(struct rtw89_ser *ser, u8 event) 207 { 208 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 209 struct ser_msg *msg = NULL; 210 211 if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) 212 return -EIO; 213 214 msg = kmalloc(sizeof(*msg), GFP_ATOMIC); 215 if (!msg) 216 return -ENOMEM; 217 218 msg->event = event; 219 220 spin_lock_irq(&ser->msg_q_lock); 221 list_add(&msg->list, &ser->msg_q); 222 spin_unlock_irq(&ser->msg_q_lock); 223 224 ieee80211_queue_work(rtwdev->hw, &ser->ser_hdl_work); 225 return 0; 226 } 227 228 static void rtw89_ser_alarm_work(struct work_struct *work) 229 { 230 struct rtw89_ser *ser = container_of(work, struct rtw89_ser, 231 ser_alarm_work.work); 232 233 ser_send_msg(ser, ser->alarm_event); 234 ser->alarm_event = SER_EV_NONE; 235 } 236 237 static void ser_set_alarm(struct rtw89_ser *ser, u32 ms, u8 event) 238 { 239 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 240 241 if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) 242 return; 243 244 ser->alarm_event = event; 245 ieee80211_queue_delayed_work(rtwdev->hw, &ser->ser_alarm_work, 246 msecs_to_jiffies(ms)); 247 } 248 249 static void ser_del_alarm(struct rtw89_ser *ser) 250 { 251 cancel_delayed_work(&ser->ser_alarm_work); 252 ser->alarm_event = SER_EV_NONE; 253 } 254 255 /* driver function */ 256 static void drv_stop_tx(struct rtw89_ser *ser) 257 { 258 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 259 260 ieee80211_stop_queues(rtwdev->hw); 261 set_bit(RTW89_SER_DRV_STOP_TX, ser->flags); 262 } 263 264 static void drv_stop_rx(struct rtw89_ser *ser) 265 { 266 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 267 268 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 269 set_bit(RTW89_SER_DRV_STOP_RX, ser->flags); 270 } 271 272 static void drv_trx_reset(struct rtw89_ser *ser) 273 { 274 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 275 276 rtw89_hci_reset(rtwdev); 277 } 278 279 static void drv_resume_tx(struct rtw89_ser *ser) 280 { 281 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 282 283 if (!test_bit(RTW89_SER_DRV_STOP_TX, ser->flags)) 284 return; 285 286 ieee80211_wake_queues(rtwdev->hw); 287 clear_bit(RTW89_SER_DRV_STOP_TX, ser->flags); 288 } 289 290 static void drv_resume_rx(struct rtw89_ser *ser) 291 { 292 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 293 294 if (!test_bit(RTW89_SER_DRV_STOP_RX, ser->flags)) 295 return; 296 297 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 298 clear_bit(RTW89_SER_DRV_STOP_RX, ser->flags); 299 } 300 301 static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 302 { 303 struct rtw89_vif_link *rtwvif_link; 304 unsigned int link_id; 305 306 rtwvif->tdls_peer = 0; 307 308 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { 309 rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif_link->port); 310 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 311 rtwvif_link->trigger = false; 312 } 313 } 314 315 static void ser_sta_deinit_cam_iter(void *data, struct ieee80211_sta *sta) 316 { 317 struct rtw89_vif *target_rtwvif = (struct rtw89_vif *)data; 318 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 319 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 320 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 321 struct rtw89_vif_link *rtwvif_link; 322 struct rtw89_sta_link *rtwsta_link; 323 unsigned int link_id; 324 325 if (rtwvif != target_rtwvif) 326 return; 327 328 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 329 rtwvif_link = rtwsta_link->rtwvif_link; 330 331 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 332 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 333 if (sta->tdls) 334 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 335 336 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 337 } 338 } 339 340 static void ser_deinit_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 341 { 342 struct rtw89_vif_link *rtwvif_link; 343 unsigned int link_id; 344 345 ieee80211_iterate_stations_atomic(rtwdev->hw, 346 ser_sta_deinit_cam_iter, 347 rtwvif); 348 349 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 350 rtw89_cam_deinit(rtwdev, rtwvif_link); 351 352 bitmap_zero(rtwdev->cam_info.ba_cam_map, RTW89_MAX_BA_CAM_NUM); 353 } 354 355 static void ser_reset_mac_binding(struct rtw89_dev *rtwdev) 356 { 357 struct rtw89_vif *rtwvif; 358 359 rtw89_cam_reset_keys(rtwdev); 360 rtw89_for_each_rtwvif(rtwdev, rtwvif) 361 ser_deinit_cam(rtwdev, rtwvif); 362 363 rtw89_core_release_all_bits_map(rtwdev->mac_id_map, RTW89_MAX_MAC_ID_NUM); 364 rtw89_for_each_rtwvif(rtwdev, rtwvif) 365 ser_reset_vif(rtwdev, rtwvif); 366 367 rtwdev->total_sta_assoc = 0; 368 } 369 370 /* hal function */ 371 static int hal_enable_dma(struct rtw89_ser *ser) 372 { 373 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 374 int ret; 375 376 if (!test_bit(RTW89_SER_HAL_STOP_DMA, ser->flags)) 377 return 0; 378 379 if (!rtwdev->hci.ops->mac_lv1_rcvy) 380 return -EIO; 381 382 ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_2); 383 if (!ret) 384 clear_bit(RTW89_SER_HAL_STOP_DMA, ser->flags); 385 else 386 rtw89_debug(rtwdev, RTW89_DBG_SER, 387 "lv1 rcvy fail to start dma: %d\n", ret); 388 389 return ret; 390 } 391 392 static int hal_stop_dma(struct rtw89_ser *ser) 393 { 394 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 395 int ret; 396 397 if (!rtwdev->hci.ops->mac_lv1_rcvy) 398 return -EIO; 399 400 ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_1); 401 if (!ret) 402 set_bit(RTW89_SER_HAL_STOP_DMA, ser->flags); 403 else 404 rtw89_debug(rtwdev, RTW89_DBG_SER, 405 "lv1 rcvy fail to stop dma: %d\n", ret); 406 407 return ret; 408 } 409 410 static void hal_send_post_m0_event(struct rtw89_ser *ser) 411 { 412 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 413 414 rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_START_DMAC); 415 } 416 417 static void hal_send_m2_event(struct rtw89_ser *ser) 418 { 419 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 420 421 rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_DISABLE_EN); 422 } 423 424 static void hal_send_m4_event(struct rtw89_ser *ser) 425 { 426 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 427 428 rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RCVY_EN); 429 } 430 431 /* state handler */ 432 static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt) 433 { 434 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 435 436 switch (evt) { 437 case SER_EV_STATE_IN: 438 rtw89_hci_recovery_complete(rtwdev); 439 clear_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags); 440 clear_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 441 break; 442 case SER_EV_L1_RESET_PREPARE: 443 ser_state_goto(ser, SER_L1_RESET_PRE_ST); 444 break; 445 case SER_EV_L1_RESET: 446 ser_state_goto(ser, SER_RESET_TRX_ST); 447 break; 448 case SER_EV_L2_RESET: 449 ser_state_goto(ser, SER_L2_RESET_ST); 450 break; 451 case SER_EV_STATE_OUT: 452 set_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags); 453 rtw89_hci_recovery_start(rtwdev); 454 break; 455 default: 456 break; 457 } 458 } 459 460 static void ser_l1_reset_pre_st_hdl(struct rtw89_ser *ser, u8 evt) 461 { 462 switch (evt) { 463 case SER_EV_STATE_IN: 464 ser->prehandle_l1 = true; 465 hal_send_post_m0_event(ser); 466 ser_set_alarm(ser, 1000, SER_EV_M1_TIMEOUT); 467 break; 468 case SER_EV_L1_RESET: 469 ser_state_goto(ser, SER_RESET_TRX_ST); 470 break; 471 case SER_EV_M1_TIMEOUT: 472 ser_state_goto(ser, SER_L2_RESET_ST); 473 break; 474 case SER_EV_STATE_OUT: 475 ser_del_alarm(ser); 476 break; 477 default: 478 break; 479 } 480 } 481 482 static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt) 483 { 484 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 485 486 switch (evt) { 487 case SER_EV_STATE_IN: 488 cancel_delayed_work_sync(&rtwdev->track_work); 489 drv_stop_tx(ser); 490 491 if (hal_stop_dma(ser)) { 492 ser_state_goto(ser, SER_L2_RESET_ST); 493 break; 494 } 495 496 drv_stop_rx(ser); 497 drv_trx_reset(ser); 498 499 /* wait m3 */ 500 hal_send_m2_event(ser); 501 502 /* set alarm to prevent FW response timeout */ 503 ser_set_alarm(ser, 1000, SER_EV_M3_TIMEOUT); 504 break; 505 506 case SER_EV_DO_RECOVERY: 507 ser_state_goto(ser, SER_DO_HCI_ST); 508 break; 509 510 case SER_EV_M3_TIMEOUT: 511 ser_state_goto(ser, SER_L2_RESET_ST); 512 break; 513 514 case SER_EV_STATE_OUT: 515 ser_del_alarm(ser); 516 hal_enable_dma(ser); 517 drv_resume_rx(ser); 518 drv_resume_tx(ser); 519 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 520 RTW89_TRACK_WORK_PERIOD); 521 break; 522 523 default: 524 break; 525 } 526 } 527 528 static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt) 529 { 530 switch (evt) { 531 case SER_EV_STATE_IN: 532 /* wait m5 */ 533 hal_send_m4_event(ser); 534 535 /* prevent FW response timeout */ 536 ser_set_alarm(ser, 1000, SER_EV_FW_M5_TIMEOUT); 537 break; 538 539 case SER_EV_FW_M5_TIMEOUT: 540 ser_state_goto(ser, SER_L2_RESET_ST); 541 break; 542 543 case SER_EV_MAC_RESET_DONE: 544 ser_state_goto(ser, SER_IDLE_ST); 545 break; 546 547 case SER_EV_STATE_OUT: 548 ser_del_alarm(ser); 549 break; 550 551 default: 552 break; 553 } 554 } 555 556 static void ser_mac_mem_dump(struct rtw89_dev *rtwdev, u8 *buf, 557 u8 sel, u32 start_addr, u32 len) 558 { 559 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 560 u32 filter_model_addr = mac->filter_model_addr; 561 u32 indir_access_addr = mac->indir_access_addr; 562 u32 *ptr = (u32 *)buf; 563 u32 base_addr, start_page, residue; 564 u32 cnt = 0; 565 u32 i; 566 567 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 568 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 569 base_addr = mac->mem_base_addrs[sel]; 570 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 571 572 while (cnt < len) { 573 rtw89_write32(rtwdev, filter_model_addr, base_addr); 574 575 for (i = indir_access_addr + residue; 576 i < indir_access_addr + MAC_MEM_DUMP_PAGE_SIZE; 577 i += 4, ptr++) { 578 *ptr = rtw89_read32(rtwdev, i); 579 cnt += 4; 580 if (cnt >= len) 581 break; 582 } 583 584 residue = 0; 585 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 586 } 587 } 588 589 static void rtw89_ser_fw_rsvd_ple_dump(struct rtw89_dev *rtwdev, u8 *buf) 590 { 591 u32 start_addr = rtwdev->chip->rsvd_ple_ofst; 592 593 rtw89_debug(rtwdev, RTW89_DBG_SER, 594 "dump mem for fw rsvd payload engine (start addr: 0x%x)\n", 595 start_addr); 596 ser_mac_mem_dump(rtwdev, buf, RTW89_MAC_MEM_SHARED_BUF, start_addr, 597 RTW89_FW_RSVD_PLE_SIZE); 598 } 599 600 struct __fw_backtrace_entry { 601 u32 wcpu_addr; 602 u32 size; 603 u32 key; 604 } __packed; 605 606 struct __fw_backtrace_info { 607 u32 ra; 608 u32 sp; 609 } __packed; 610 611 static_assert(RTW89_FW_BACKTRACE_INFO_SIZE == 612 sizeof(struct __fw_backtrace_info)); 613 614 static u32 convert_addr_from_wcpu(u32 wcpu_addr) 615 { 616 if (wcpu_addr < 0x30000000) 617 return wcpu_addr; 618 619 return wcpu_addr & GENMASK(28, 0); 620 } 621 622 static int rtw89_ser_fw_backtrace_dump(struct rtw89_dev *rtwdev, u8 *buf, 623 const struct __fw_backtrace_entry *ent) 624 { 625 struct __fw_backtrace_info *ptr = (struct __fw_backtrace_info *)buf; 626 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 627 u32 filter_model_addr = mac->filter_model_addr; 628 u32 indir_access_addr = mac->indir_access_addr; 629 u32 fwbt_addr = convert_addr_from_wcpu(ent->wcpu_addr); 630 u32 fwbt_size = ent->size; 631 u32 fwbt_key = ent->key; 632 u32 i; 633 634 if (fwbt_addr == 0) { 635 rtw89_warn(rtwdev, "FW backtrace invalid address: 0x%x\n", 636 fwbt_addr); 637 return -EINVAL; 638 } 639 640 if (fwbt_key != RTW89_FW_BACKTRACE_KEY) { 641 rtw89_warn(rtwdev, "FW backtrace invalid key: 0x%x\n", 642 fwbt_key); 643 return -EINVAL; 644 } 645 646 if (fwbt_size == 0 || !RTW89_VALID_FW_BACKTRACE_SIZE(fwbt_size) || 647 fwbt_size > RTW89_FW_BACKTRACE_MAX_SIZE) { 648 rtw89_warn(rtwdev, "FW backtrace invalid size: 0x%x\n", 649 fwbt_size); 650 return -EINVAL; 651 } 652 653 rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace start\n"); 654 rtw89_write32(rtwdev, filter_model_addr, fwbt_addr); 655 656 for (i = indir_access_addr; 657 i < indir_access_addr + fwbt_size; 658 i += RTW89_FW_BACKTRACE_INFO_SIZE, ptr++) { 659 *ptr = (struct __fw_backtrace_info){ 660 .ra = rtw89_read32(rtwdev, i), 661 .sp = rtw89_read32(rtwdev, i + 4), 662 }; 663 rtw89_debug(rtwdev, RTW89_DBG_SER, 664 "next sp: 0x%x, next ra: 0x%x\n", 665 ptr->sp, ptr->ra); 666 } 667 668 rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace end\n"); 669 return 0; 670 } 671 672 static void ser_l2_reset_st_pre_hdl(struct rtw89_ser *ser) 673 { 674 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 675 struct rtw89_ser_cd_buffer *buf; 676 struct __fw_backtrace_entry fwbt_ent; 677 int ret = 0; 678 679 buf = rtw89_ser_cd_prep(rtwdev); 680 if (!buf) { 681 ret = -ENOMEM; 682 goto bottom; 683 } 684 685 rtw89_ser_fw_rsvd_ple_dump(rtwdev, buf->fwple.data); 686 687 fwbt_ent = *(struct __fw_backtrace_entry *)buf->fwple.data; 688 ret = rtw89_ser_fw_backtrace_dump(rtwdev, buf->fwbt.data, &fwbt_ent); 689 if (ret) 690 goto bottom; 691 692 rtw89_ser_cd_send(rtwdev, buf); 693 694 bottom: 695 rtw89_ser_cd_free(rtwdev, buf, !!ret); 696 697 ser_reset_mac_binding(rtwdev); 698 rtw89_core_stop(rtwdev); 699 rtw89_entity_init(rtwdev); 700 rtw89_fw_release_general_pkt_list(rtwdev, false); 701 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 702 } 703 704 static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt) 705 { 706 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 707 708 switch (evt) { 709 case SER_EV_STATE_IN: 710 mutex_lock(&rtwdev->mutex); 711 ser_l2_reset_st_pre_hdl(ser); 712 mutex_unlock(&rtwdev->mutex); 713 714 ieee80211_restart_hw(rtwdev->hw); 715 ser_set_alarm(ser, SER_RECFG_TIMEOUT, SER_EV_L2_RECFG_TIMEOUT); 716 break; 717 718 case SER_EV_L2_RECFG_TIMEOUT: 719 rtw89_info(rtwdev, "Err: ser L2 re-config timeout\n"); 720 fallthrough; 721 case SER_EV_L2_RECFG_DONE: 722 ser_state_goto(ser, SER_IDLE_ST); 723 break; 724 725 case SER_EV_STATE_OUT: 726 ser_del_alarm(ser); 727 break; 728 729 default: 730 break; 731 } 732 } 733 734 static const struct event_ent ser_ev_tbl[] = { 735 {SER_EV_NONE, "SER_EV_NONE"}, 736 {SER_EV_STATE_IN, "SER_EV_STATE_IN"}, 737 {SER_EV_STATE_OUT, "SER_EV_STATE_OUT"}, 738 {SER_EV_L1_RESET_PREPARE, "SER_EV_L1_RESET_PREPARE pre-m0"}, 739 {SER_EV_L1_RESET, "SER_EV_L1_RESET m1"}, 740 {SER_EV_DO_RECOVERY, "SER_EV_DO_RECOVERY m3"}, 741 {SER_EV_MAC_RESET_DONE, "SER_EV_MAC_RESET_DONE m5"}, 742 {SER_EV_L2_RESET, "SER_EV_L2_RESET"}, 743 {SER_EV_L2_RECFG_DONE, "SER_EV_L2_RECFG_DONE"}, 744 {SER_EV_L2_RECFG_TIMEOUT, "SER_EV_L2_RECFG_TIMEOUT"}, 745 {SER_EV_M1_TIMEOUT, "SER_EV_M1_TIMEOUT"}, 746 {SER_EV_M3_TIMEOUT, "SER_EV_M3_TIMEOUT"}, 747 {SER_EV_FW_M5_TIMEOUT, "SER_EV_FW_M5_TIMEOUT"}, 748 {SER_EV_L0_RESET, "SER_EV_L0_RESET"}, 749 {SER_EV_MAXX, "SER_EV_MAX"} 750 }; 751 752 static const struct state_ent ser_st_tbl[] = { 753 {SER_IDLE_ST, "SER_IDLE_ST", ser_idle_st_hdl}, 754 {SER_L1_RESET_PRE_ST, "SER_L1_RESET_PRE_ST", ser_l1_reset_pre_st_hdl}, 755 {SER_RESET_TRX_ST, "SER_RESET_TRX_ST", ser_reset_trx_st_hdl}, 756 {SER_DO_HCI_ST, "SER_DO_HCI_ST", ser_do_hci_st_hdl}, 757 {SER_L2_RESET_ST, "SER_L2_RESET_ST", ser_l2_reset_st_hdl} 758 }; 759 760 int rtw89_ser_init(struct rtw89_dev *rtwdev) 761 { 762 struct rtw89_ser *ser = &rtwdev->ser; 763 764 memset(ser, 0, sizeof(*ser)); 765 INIT_LIST_HEAD(&ser->msg_q); 766 ser->state = SER_IDLE_ST; 767 ser->st_tbl = ser_st_tbl; 768 ser->ev_tbl = ser_ev_tbl; 769 770 bitmap_zero(ser->flags, RTW89_NUM_OF_SER_FLAGS); 771 spin_lock_init(&ser->msg_q_lock); 772 INIT_WORK(&ser->ser_hdl_work, rtw89_ser_hdl_work); 773 INIT_DELAYED_WORK(&ser->ser_alarm_work, rtw89_ser_alarm_work); 774 return 0; 775 } 776 777 int rtw89_ser_deinit(struct rtw89_dev *rtwdev) 778 { 779 struct rtw89_ser *ser = (struct rtw89_ser *)&rtwdev->ser; 780 781 set_bit(RTW89_SER_DRV_STOP_RUN, ser->flags); 782 cancel_delayed_work_sync(&ser->ser_alarm_work); 783 cancel_work_sync(&ser->ser_hdl_work); 784 clear_bit(RTW89_SER_DRV_STOP_RUN, ser->flags); 785 return 0; 786 } 787 788 void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev) 789 { 790 ser_send_msg(&rtwdev->ser, SER_EV_L2_RECFG_DONE); 791 } 792 793 int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err) 794 { 795 u8 event = SER_EV_NONE; 796 797 rtw89_info(rtwdev, "SER catches error: 0x%x\n", err); 798 799 switch (err) { 800 case MAC_AX_ERR_L1_PREERR_DMAC: /* pre-M0 */ 801 event = SER_EV_L1_RESET_PREPARE; 802 break; 803 case MAC_AX_ERR_L1_ERR_DMAC: 804 case MAC_AX_ERR_L0_PROMOTE_TO_L1: 805 event = SER_EV_L1_RESET; /* M1 */ 806 break; 807 case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE: 808 event = SER_EV_DO_RECOVERY; /* M3 */ 809 break; 810 case MAC_AX_ERR_L1_RESET_RECOVERY_DONE: 811 event = SER_EV_MAC_RESET_DONE; /* M5 */ 812 break; 813 case MAC_AX_ERR_L0_ERR_CMAC0: 814 case MAC_AX_ERR_L0_ERR_CMAC1: 815 case MAC_AX_ERR_L0_RESET_DONE: 816 event = SER_EV_L0_RESET; 817 break; 818 default: 819 if (err == MAC_AX_ERR_L1_PROMOTE_TO_L2 || 820 (err >= MAC_AX_ERR_L2_ERR_AH_DMA && 821 err <= MAC_AX_GET_ERR_MAX)) 822 event = SER_EV_L2_RESET; 823 break; 824 } 825 826 if (event == SER_EV_NONE) { 827 rtw89_warn(rtwdev, "SER cannot recognize error: 0x%x\n", err); 828 return -EINVAL; 829 } 830 831 ser_send_msg(&rtwdev->ser, event); 832 return 0; 833 } 834 EXPORT_SYMBOL(rtw89_ser_notify); 835