1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "acpi.h" 6 #include "debug.h" 7 #include "phy.h" 8 #include "reg.h" 9 #include "sar.h" 10 #include "util.h" 11 12 #define RTW89_TAS_FACTOR 2 /* unit: 0.25 dBm */ 13 #define RTW89_TAS_SAR_GAP (1 << RTW89_TAS_FACTOR) 14 #define RTW89_TAS_DPR_GAP (1 << RTW89_TAS_FACTOR) 15 #define RTW89_TAS_DELTA (2 << RTW89_TAS_FACTOR) 16 #define RTW89_TAS_TX_RATIO_THRESHOLD 70 17 #define RTW89_TAS_DFLT_TX_RATIO 80 18 #define RTW89_TAS_DPR_ON_OFFSET (RTW89_TAS_DELTA + RTW89_TAS_SAR_GAP) 19 #define RTW89_TAS_DPR_OFF_OFFSET (4 << RTW89_TAS_FACTOR) 20 21 static enum rtw89_sar_subband rtw89_sar_get_subband(struct rtw89_dev *rtwdev, 22 u32 center_freq) 23 { 24 switch (center_freq) { 25 default: 26 rtw89_debug(rtwdev, RTW89_DBG_SAR, 27 "center freq: %u to SAR subband is unhandled\n", 28 center_freq); 29 fallthrough; 30 case 2412 ... 2484: 31 return RTW89_SAR_2GHZ_SUBBAND; 32 case 5180 ... 5320: 33 return RTW89_SAR_5GHZ_SUBBAND_1_2; 34 case 5500 ... 5720: 35 return RTW89_SAR_5GHZ_SUBBAND_2_E; 36 case 5745 ... 5885: 37 return RTW89_SAR_5GHZ_SUBBAND_3_4; 38 case 5955 ... 6155: 39 return RTW89_SAR_6GHZ_SUBBAND_5_L; 40 case 6175 ... 6415: 41 return RTW89_SAR_6GHZ_SUBBAND_5_H; 42 case 6435 ... 6515: 43 return RTW89_SAR_6GHZ_SUBBAND_6; 44 case 6535 ... 6695: 45 return RTW89_SAR_6GHZ_SUBBAND_7_L; 46 case 6715 ... 6855: 47 return RTW89_SAR_6GHZ_SUBBAND_7_H; 48 49 /* freq 6875 (ch 185, 20MHz) spans RTW89_SAR_6GHZ_SUBBAND_7_H 50 * and RTW89_SAR_6GHZ_SUBBAND_8, so directly describe it with 51 * struct rtw89_6ghz_span. 52 */ 53 54 case 6895 ... 7115: 55 return RTW89_SAR_6GHZ_SUBBAND_8; 56 } 57 } 58 59 static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, 60 const struct rtw89_sar_parm *sar_parm, 61 s32 *cfg) 62 { 63 struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common; 64 enum rtw89_sar_subband subband_l, subband_h; 65 u32 center_freq = sar_parm->center_freq; 66 const struct rtw89_6ghz_span *span; 67 68 span = rtw89_get_6ghz_span(rtwdev, center_freq); 69 70 if (span && RTW89_SAR_SPAN_VALID(span)) { 71 subband_l = span->sar_subband_low; 72 subband_h = span->sar_subband_high; 73 } else { 74 subband_l = rtw89_sar_get_subband(rtwdev, center_freq); 75 subband_h = subband_l; 76 } 77 78 rtw89_debug(rtwdev, RTW89_DBG_SAR, 79 "center_freq %u: SAR subband {%u, %u}\n", 80 center_freq, subband_l, subband_h); 81 82 if (!rtwsar->set[subband_l] && !rtwsar->set[subband_h]) 83 return -ENODATA; 84 85 if (!rtwsar->set[subband_l]) 86 *cfg = rtwsar->cfg[subband_h]; 87 else if (!rtwsar->set[subband_h]) 88 *cfg = rtwsar->cfg[subband_l]; 89 else 90 *cfg = min(rtwsar->cfg[subband_l], rtwsar->cfg[subband_h]); 91 92 return 0; 93 } 94 95 static const struct rtw89_sar_entry_from_acpi * 96 rtw89_sar_cfg_acpi_get_ent(const struct rtw89_sar_cfg_acpi *rtwsar, 97 enum rtw89_rf_path path, 98 enum rtw89_regulation_type regd) 99 { 100 const struct rtw89_sar_indicator_from_acpi *ind = &rtwsar->indicator; 101 const struct rtw89_sar_table_from_acpi *tbl; 102 u8 sel; 103 104 sel = ind->tblsel[path]; 105 tbl = &rtwsar->tables[sel]; 106 107 return &tbl->entries[regd]; 108 } 109 110 static 111 s32 rtw89_sar_cfg_acpi_get_min(const struct rtw89_sar_entry_from_acpi *ent, 112 enum rtw89_rf_path path, 113 enum rtw89_acpi_sar_subband subband_low, 114 enum rtw89_acpi_sar_subband subband_high) 115 { 116 return min(ent->v[subband_low][path], ent->v[subband_high][path]); 117 } 118 119 static int rtw89_query_sar_config_acpi(struct rtw89_dev *rtwdev, 120 const struct rtw89_sar_parm *sar_parm, 121 s32 *cfg) 122 { 123 const struct rtw89_chip_info *chip = rtwdev->chip; 124 const struct rtw89_sar_cfg_acpi *rtwsar = &rtwdev->sar.cfg_acpi; 125 const struct rtw89_sar_entry_from_acpi *ent_a, *ent_b; 126 enum rtw89_acpi_sar_subband subband_l, subband_h; 127 u32 center_freq = sar_parm->center_freq; 128 const struct rtw89_6ghz_span *span; 129 enum rtw89_regulation_type regd; 130 enum rtw89_band band; 131 s32 cfg_a, cfg_b; 132 133 span = rtw89_get_6ghz_span(rtwdev, center_freq); 134 135 if (span && RTW89_ACPI_SAR_SPAN_VALID(span)) { 136 subband_l = span->acpi_sar_subband_low; 137 subband_h = span->acpi_sar_subband_high; 138 } else { 139 subband_l = rtw89_acpi_sar_get_subband(rtwdev, center_freq); 140 subband_h = subband_l; 141 } 142 143 band = rtw89_acpi_sar_subband_to_band(rtwdev, subband_l); 144 regd = rtw89_regd_get(rtwdev, band); 145 146 ent_a = rtw89_sar_cfg_acpi_get_ent(rtwsar, RF_PATH_A, regd); 147 ent_b = rtw89_sar_cfg_acpi_get_ent(rtwsar, RF_PATH_B, regd); 148 149 cfg_a = rtw89_sar_cfg_acpi_get_min(ent_a, RF_PATH_A, subband_l, subband_h); 150 cfg_b = rtw89_sar_cfg_acpi_get_min(ent_b, RF_PATH_B, subband_l, subband_h); 151 152 if (chip->support_sar_by_ant) { 153 /* With declaration of support_sar_by_ant, relax the general 154 * SAR querying to return the maximum between paths. However, 155 * expect chip has dealt with the corresponding SAR settings 156 * by path. (To get SAR for a given path, chip can then query 157 * with force_path.) 158 */ 159 if (sar_parm->force_path) { 160 switch (sar_parm->path) { 161 default: 162 case RF_PATH_A: 163 *cfg = cfg_a; 164 break; 165 case RF_PATH_B: 166 *cfg = cfg_b; 167 break; 168 } 169 } else { 170 *cfg = max(cfg_a, cfg_b); 171 } 172 } else { 173 *cfg = min(cfg_a, cfg_b); 174 } 175 176 if (sar_parm->ntx == RTW89_2TX) 177 *cfg -= rtwsar->downgrade_2tx; 178 179 return 0; 180 } 181 182 static const 183 struct rtw89_sar_handler rtw89_sar_handlers[RTW89_SAR_SOURCE_NR] = { 184 [RTW89_SAR_SOURCE_COMMON] = { 185 .descr_sar_source = "RTW89_SAR_SOURCE_COMMON", 186 .txpwr_factor_sar = 2, 187 .query_sar_config = rtw89_query_sar_config_common, 188 }, 189 [RTW89_SAR_SOURCE_ACPI] = { 190 .descr_sar_source = "RTW89_SAR_SOURCE_ACPI", 191 .txpwr_factor_sar = TXPWR_FACTOR_OF_RTW89_ACPI_SAR, 192 .query_sar_config = rtw89_query_sar_config_acpi, 193 }, 194 }; 195 196 #define rtw89_sar_set_src(_dev, _src, _cfg_name, _cfg_data) \ 197 do { \ 198 typeof(_src) _s = (_src); \ 199 typeof(_dev) _d = (_dev); \ 200 BUILD_BUG_ON(!rtw89_sar_handlers[_s].descr_sar_source); \ 201 BUILD_BUG_ON(!rtw89_sar_handlers[_s].query_sar_config); \ 202 lockdep_assert_wiphy(_d->hw->wiphy); \ 203 _d->sar._cfg_name = *(_cfg_data); \ 204 _d->sar.src = _s; \ 205 } while (0) 206 207 static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg) 208 { 209 const u8 fct_mac = rtwdev->chip->txpwr_factor_mac; 210 s32 cfg_mac; 211 212 cfg_mac = fct > fct_mac ? 213 cfg >> (fct - fct_mac) : cfg << (fct_mac - fct); 214 215 return (s8)clamp_t(s32, cfg_mac, 216 RTW89_SAR_TXPWR_MAC_MIN, 217 RTW89_SAR_TXPWR_MAC_MAX); 218 } 219 220 static s32 rtw89_txpwr_tas_to_sar(const struct rtw89_sar_handler *sar_hdl, 221 s32 cfg) 222 { 223 const u8 fct = sar_hdl->txpwr_factor_sar; 224 225 if (fct > RTW89_TAS_FACTOR) 226 return cfg << (fct - RTW89_TAS_FACTOR); 227 else 228 return cfg >> (RTW89_TAS_FACTOR - fct); 229 } 230 231 static s32 rtw89_txpwr_sar_to_tas(const struct rtw89_sar_handler *sar_hdl, 232 s32 cfg) 233 { 234 const u8 fct = sar_hdl->txpwr_factor_sar; 235 236 if (fct > RTW89_TAS_FACTOR) 237 return cfg >> (fct - RTW89_TAS_FACTOR); 238 else 239 return cfg << (RTW89_TAS_FACTOR - fct); 240 } 241 242 static bool rtw89_tas_is_active(struct rtw89_dev *rtwdev) 243 { 244 struct rtw89_tas_info *tas = &rtwdev->tas; 245 struct rtw89_vif *rtwvif; 246 247 if (!tas->enable) 248 return false; 249 250 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 251 if (ieee80211_vif_is_mld(rtwvif_to_vif(rtwvif))) 252 return false; 253 } 254 255 return true; 256 } 257 258 static const char *rtw89_tas_state_str(enum rtw89_tas_state state) 259 { 260 switch (state) { 261 case RTW89_TAS_STATE_DPR_OFF: 262 return "DPR OFF"; 263 case RTW89_TAS_STATE_DPR_ON: 264 return "DPR ON"; 265 case RTW89_TAS_STATE_STATIC_SAR: 266 return "STATIC SAR"; 267 default: 268 return NULL; 269 } 270 } 271 272 s8 rtw89_query_sar(struct rtw89_dev *rtwdev, const struct rtw89_sar_parm *sar_parm) 273 { 274 const enum rtw89_sar_sources src = rtwdev->sar.src; 275 /* its members are protected by rtw89_sar_set_src() */ 276 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; 277 struct rtw89_tas_info *tas = &rtwdev->tas; 278 s32 offset; 279 int ret; 280 s32 cfg; 281 u8 fct; 282 283 lockdep_assert_wiphy(rtwdev->hw->wiphy); 284 285 if (src == RTW89_SAR_SOURCE_NONE) 286 return RTW89_SAR_TXPWR_MAC_MAX; 287 288 ret = sar_hdl->query_sar_config(rtwdev, sar_parm, &cfg); 289 if (ret) 290 return RTW89_SAR_TXPWR_MAC_MAX; 291 292 if (rtw89_tas_is_active(rtwdev)) { 293 switch (tas->state) { 294 case RTW89_TAS_STATE_DPR_OFF: 295 offset = rtw89_txpwr_tas_to_sar(sar_hdl, RTW89_TAS_DPR_OFF_OFFSET); 296 cfg += offset; 297 break; 298 case RTW89_TAS_STATE_DPR_ON: 299 offset = rtw89_txpwr_tas_to_sar(sar_hdl, RTW89_TAS_DPR_ON_OFFSET); 300 cfg -= offset; 301 break; 302 case RTW89_TAS_STATE_STATIC_SAR: 303 default: 304 break; 305 } 306 } 307 308 fct = sar_hdl->txpwr_factor_sar; 309 310 return rtw89_txpwr_sar_to_mac(rtwdev, fct, cfg); 311 } 312 EXPORT_SYMBOL(rtw89_query_sar); 313 314 int rtw89_print_sar(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 315 const struct rtw89_sar_parm *sar_parm) 316 { 317 const enum rtw89_sar_sources src = rtwdev->sar.src; 318 /* its members are protected by rtw89_sar_set_src() */ 319 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; 320 const u8 fct_mac = rtwdev->chip->txpwr_factor_mac; 321 char *p = buf, *end = buf + bufsz; 322 int ret; 323 s32 cfg; 324 u8 fct; 325 326 lockdep_assert_wiphy(rtwdev->hw->wiphy); 327 328 if (src == RTW89_SAR_SOURCE_NONE) { 329 p += scnprintf(p, end - p, "no SAR is applied\n"); 330 goto out; 331 } 332 333 p += scnprintf(p, end - p, "source: %d (%s)\n", src, 334 sar_hdl->descr_sar_source); 335 336 ret = sar_hdl->query_sar_config(rtwdev, sar_parm, &cfg); 337 if (ret) { 338 p += scnprintf(p, end - p, "config: return code: %d\n", ret); 339 p += scnprintf(p, end - p, 340 "assign: max setting: %d (unit: 1/%lu dBm)\n", 341 RTW89_SAR_TXPWR_MAC_MAX, BIT(fct_mac)); 342 goto out; 343 } 344 345 fct = sar_hdl->txpwr_factor_sar; 346 347 p += scnprintf(p, end - p, "config: %d (unit: 1/%lu dBm)\n", cfg, 348 BIT(fct)); 349 350 p += scnprintf(p, end - p, "support different configs by antenna: %s\n", 351 str_yes_no(rtwdev->chip->support_sar_by_ant)); 352 out: 353 return p - buf; 354 } 355 356 int rtw89_print_tas(struct rtw89_dev *rtwdev, char *buf, size_t bufsz) 357 { 358 struct rtw89_tas_info *tas = &rtwdev->tas; 359 char *p = buf, *end = buf + bufsz; 360 361 if (!rtw89_tas_is_active(rtwdev)) { 362 p += scnprintf(p, end - p, "no TAS is applied\n"); 363 goto out; 364 } 365 366 p += scnprintf(p, end - p, "State: %s\n", 367 rtw89_tas_state_str(tas->state)); 368 p += scnprintf(p, end - p, "Average time: %d\n", 369 tas->window_size * 2); 370 p += scnprintf(p, end - p, "SAR gap: %d dBm\n", 371 RTW89_TAS_SAR_GAP >> RTW89_TAS_FACTOR); 372 p += scnprintf(p, end - p, "DPR gap: %d dBm\n", 373 RTW89_TAS_DPR_GAP >> RTW89_TAS_FACTOR); 374 p += scnprintf(p, end - p, "DPR ON offset: %d dBm\n", 375 RTW89_TAS_DPR_ON_OFFSET >> RTW89_TAS_FACTOR); 376 p += scnprintf(p, end - p, "DPR OFF offset: %d dBm\n", 377 RTW89_TAS_DPR_OFF_OFFSET >> RTW89_TAS_FACTOR); 378 379 out: 380 return p - buf; 381 } 382 383 static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev, 384 const struct rtw89_sar_cfg_common *sar) 385 { 386 /* let common SAR have the highest priority; always apply it */ 387 rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_COMMON, cfg_common, sar); 388 rtw89_core_set_chip_txpwr(rtwdev); 389 rtw89_tas_reset(rtwdev, false); 390 391 return 0; 392 } 393 394 static const struct cfg80211_sar_freq_ranges rtw89_common_sar_freq_ranges[] = { 395 { .start_freq = 2412, .end_freq = 2484, }, 396 { .start_freq = 5180, .end_freq = 5320, }, 397 { .start_freq = 5500, .end_freq = 5720, }, 398 { .start_freq = 5745, .end_freq = 5885, }, 399 { .start_freq = 5955, .end_freq = 6155, }, 400 { .start_freq = 6175, .end_freq = 6415, }, 401 { .start_freq = 6435, .end_freq = 6515, }, 402 { .start_freq = 6535, .end_freq = 6695, }, 403 { .start_freq = 6715, .end_freq = 6875, }, 404 { .start_freq = 6875, .end_freq = 7115, }, 405 }; 406 407 static_assert(RTW89_SAR_SUBBAND_NR == 408 ARRAY_SIZE(rtw89_common_sar_freq_ranges)); 409 410 const struct cfg80211_sar_capa rtw89_sar_capa = { 411 .type = NL80211_SAR_TYPE_POWER, 412 .num_freq_ranges = ARRAY_SIZE(rtw89_common_sar_freq_ranges), 413 .freq_ranges = rtw89_common_sar_freq_ranges, 414 }; 415 416 int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, 417 const struct cfg80211_sar_specs *sar) 418 { 419 struct rtw89_dev *rtwdev = hw->priv; 420 struct rtw89_sar_cfg_common sar_common = {0}; 421 u8 fct; 422 u32 freq_start; 423 u32 freq_end; 424 s32 power; 425 u32 i, idx; 426 427 lockdep_assert_wiphy(rtwdev->hw->wiphy); 428 429 if (sar->type != NL80211_SAR_TYPE_POWER) 430 return -EINVAL; 431 432 fct = rtw89_sar_handlers[RTW89_SAR_SOURCE_COMMON].txpwr_factor_sar; 433 434 for (i = 0; i < sar->num_sub_specs; i++) { 435 idx = sar->sub_specs[i].freq_range_index; 436 if (idx >= ARRAY_SIZE(rtw89_common_sar_freq_ranges)) 437 return -EINVAL; 438 439 freq_start = rtw89_common_sar_freq_ranges[idx].start_freq; 440 freq_end = rtw89_common_sar_freq_ranges[idx].end_freq; 441 power = sar->sub_specs[i].power; 442 443 rtw89_debug(rtwdev, RTW89_DBG_SAR, 444 "On freq %u to %u, set SAR limit %d (unit: 1/%lu dBm)\n", 445 freq_start, freq_end, power, BIT(fct)); 446 447 sar_common.set[idx] = true; 448 sar_common.cfg[idx] = power; 449 } 450 451 return rtw89_apply_sar_common(rtwdev, &sar_common); 452 } 453 454 static void rtw89_apply_sar_acpi(struct rtw89_dev *rtwdev, 455 const struct rtw89_sar_cfg_acpi *sar) 456 { 457 const struct rtw89_sar_table_from_acpi *tbl; 458 const struct rtw89_sar_entry_from_acpi *ent; 459 enum rtw89_sar_sources src; 460 unsigned int i, j, k; 461 462 src = rtwdev->sar.src; 463 if (src != RTW89_SAR_SOURCE_NONE) { 464 rtw89_warn(rtwdev, "SAR source: %d is in use", src); 465 return; 466 } 467 468 rtw89_debug(rtwdev, RTW89_DBG_SAR, 469 "SAR-ACPI downgrade 2TX: %u (unit: 1/%lu dBm)\n", 470 sar->downgrade_2tx, BIT(TXPWR_FACTOR_OF_RTW89_ACPI_SAR)); 471 472 for (i = 0; i < sar->valid_num; i++) { 473 tbl = &sar->tables[i]; 474 475 for (j = 0; j < RTW89_REGD_NUM; j++) { 476 ent = &tbl->entries[j]; 477 478 rtw89_debug(rtwdev, RTW89_DBG_SAR, 479 "SAR-ACPI-[%u] REGD-%s (unit: 1/%lu dBm)\n", 480 i, rtw89_regd_get_string(j), 481 BIT(TXPWR_FACTOR_OF_RTW89_ACPI_SAR)); 482 483 for (k = 0; k < NUM_OF_RTW89_ACPI_SAR_SUBBAND; k++) 484 rtw89_debug(rtwdev, RTW89_DBG_SAR, 485 "On subband %u, { %d, %d }\n", k, 486 ent->v[k][RF_PATH_A], ent->v[k][RF_PATH_B]); 487 } 488 } 489 490 rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_ACPI, cfg_acpi, sar); 491 492 /* SAR via ACPI is only configured in the early initial phase, so 493 * it does not seem necessary to reset txpwr related things here. 494 */ 495 } 496 497 static void rtw89_set_sar_from_acpi(struct rtw89_dev *rtwdev) 498 { 499 struct rtw89_sar_cfg_acpi *cfg; 500 int ret; 501 502 lockdep_assert_wiphy(rtwdev->hw->wiphy); 503 504 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 505 if (!cfg) 506 return; 507 508 ret = rtw89_acpi_evaluate_sar(rtwdev, cfg); 509 if (ret) { 510 rtw89_debug(rtwdev, RTW89_DBG_SAR, 511 "evaluating ACPI SAR returns %d\n", ret); 512 goto out; 513 } 514 515 if (unlikely(!cfg->valid_num)) { 516 rtw89_debug(rtwdev, RTW89_DBG_SAR, "no valid SAR table from ACPI\n"); 517 goto out; 518 } 519 520 rtw89_apply_sar_acpi(rtwdev, cfg); 521 522 out: 523 kfree(cfg); 524 } 525 526 static bool rtw89_tas_query_sar_config(struct rtw89_dev *rtwdev, s32 *cfg) 527 { 528 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 529 const enum rtw89_sar_sources src = rtwdev->sar.src; 530 /* its members are protected by rtw89_sar_set_src() */ 531 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; 532 struct rtw89_sar_parm sar_parm = {}; 533 int ret; 534 535 if (src == RTW89_SAR_SOURCE_NONE) 536 return false; 537 538 sar_parm.center_freq = chan->freq; 539 ret = sar_hdl->query_sar_config(rtwdev, &sar_parm, cfg); 540 if (ret) 541 return false; 542 543 *cfg = rtw89_txpwr_sar_to_tas(sar_hdl, *cfg); 544 545 return true; 546 } 547 548 static bool __rtw89_tas_state_update(struct rtw89_dev *rtwdev, 549 enum rtw89_tas_state state) 550 { 551 struct rtw89_tas_info *tas = &rtwdev->tas; 552 553 if (tas->state == state) 554 return false; 555 556 rtw89_debug(rtwdev, RTW89_DBG_SAR, "tas: switch state: %s -> %s\n", 557 rtw89_tas_state_str(tas->state), rtw89_tas_state_str(state)); 558 559 tas->state = state; 560 return true; 561 } 562 563 static void rtw89_tas_state_update(struct rtw89_dev *rtwdev, 564 enum rtw89_tas_state state) 565 { 566 if (!__rtw89_tas_state_update(rtwdev, state)) 567 return; 568 569 rtw89_core_set_chip_txpwr(rtwdev); 570 } 571 572 static u32 rtw89_tas_get_window_size(struct rtw89_dev *rtwdev) 573 { 574 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 575 u8 band = chan->band_type; 576 u8 regd = rtw89_regd_get(rtwdev, band); 577 578 switch (regd) { 579 default: 580 rtw89_debug(rtwdev, RTW89_DBG_SAR, 581 "tas: regd: %u is unhandled\n", regd); 582 fallthrough; 583 case RTW89_IC: 584 case RTW89_KCC: 585 return 180; 586 case RTW89_FCC: 587 switch (band) { 588 case RTW89_BAND_2G: 589 return 50; 590 case RTW89_BAND_5G: 591 return 30; 592 case RTW89_BAND_6G: 593 default: 594 return 15; 595 } 596 break; 597 } 598 } 599 600 static void rtw89_tas_window_update(struct rtw89_dev *rtwdev) 601 { 602 u32 window_size = rtw89_tas_get_window_size(rtwdev); 603 struct rtw89_tas_info *tas = &rtwdev->tas; 604 u64 total_txpwr = 0; 605 u8 head_idx; 606 u32 i, j; 607 608 WARN_ON_ONCE(tas->window_size > RTW89_TAS_TXPWR_WINDOW); 609 610 if (tas->window_size == window_size) 611 return; 612 613 rtw89_debug(rtwdev, RTW89_DBG_SAR, "tas: window update: %u -> %u\n", 614 tas->window_size, window_size); 615 616 head_idx = (tas->txpwr_tail_idx - window_size + 1 + RTW89_TAS_TXPWR_WINDOW) % 617 RTW89_TAS_TXPWR_WINDOW; 618 for (i = 0; i < window_size; i++) { 619 j = (head_idx + i) % RTW89_TAS_TXPWR_WINDOW; 620 total_txpwr += tas->txpwr_history[j]; 621 } 622 623 tas->window_size = window_size; 624 tas->total_txpwr = total_txpwr; 625 tas->txpwr_head_idx = head_idx; 626 } 627 628 static void rtw89_tas_history_update(struct rtw89_dev *rtwdev) 629 { 630 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, RTW89_PHY_0); 631 struct rtw89_env_monitor_info *env = &bb->env_monitor; 632 struct rtw89_tas_info *tas = &rtwdev->tas; 633 u8 tx_ratio = env->ifs_clm_tx_ratio; 634 u64 instant_txpwr, txpwr; 635 636 /* txpwr in unit of linear(mW) multiply by percentage */ 637 if (tx_ratio == 0) { 638 /* special case: idle tx power 639 * use -40 dBm * 100 tx ratio 640 */ 641 instant_txpwr = rtw89_db_to_linear(-40); 642 txpwr = instant_txpwr * 100; 643 } else { 644 instant_txpwr = tas->instant_txpwr; 645 txpwr = instant_txpwr * tx_ratio; 646 } 647 648 tas->total_txpwr += txpwr - tas->txpwr_history[tas->txpwr_head_idx]; 649 tas->total_tx_ratio += tx_ratio - tas->tx_ratio_history[tas->tx_ratio_idx]; 650 tas->tx_ratio_history[tas->tx_ratio_idx] = tx_ratio; 651 652 tas->txpwr_head_idx = (tas->txpwr_head_idx + 1) % RTW89_TAS_TXPWR_WINDOW; 653 tas->txpwr_tail_idx = (tas->txpwr_tail_idx + 1) % RTW89_TAS_TXPWR_WINDOW; 654 tas->tx_ratio_idx = (tas->tx_ratio_idx + 1) % RTW89_TAS_TX_RATIO_WINDOW; 655 tas->txpwr_history[tas->txpwr_tail_idx] = txpwr; 656 657 rtw89_debug(rtwdev, RTW89_DBG_SAR, 658 "tas: instant_txpwr: %d, tx_ratio: %u, txpwr: %d\n", 659 rtw89_linear_to_db_quarter(instant_txpwr), tx_ratio, 660 rtw89_linear_to_db_quarter(div_u64(txpwr, PERCENT))); 661 } 662 663 static bool rtw89_tas_rolling_average(struct rtw89_dev *rtwdev) 664 { 665 struct rtw89_tas_info *tas = &rtwdev->tas; 666 s32 dpr_on_threshold, dpr_off_threshold; 667 enum rtw89_tas_state state; 668 u16 tx_ratio_avg; 669 s32 txpwr_avg; 670 u64 linear; 671 672 linear = DIV_ROUND_DOWN_ULL(tas->total_txpwr, tas->window_size * PERCENT); 673 txpwr_avg = rtw89_linear_to_db_quarter(linear); 674 tx_ratio_avg = tas->total_tx_ratio / RTW89_TAS_TX_RATIO_WINDOW; 675 dpr_on_threshold = tas->dpr_on_threshold; 676 dpr_off_threshold = tas->dpr_off_threshold; 677 678 rtw89_debug(rtwdev, RTW89_DBG_SAR, 679 "tas: DPR_ON: %d, DPR_OFF: %d, txpwr_avg: %d, tx_ratio_avg: %u\n", 680 dpr_on_threshold, dpr_off_threshold, txpwr_avg, tx_ratio_avg); 681 682 if (tx_ratio_avg >= RTW89_TAS_TX_RATIO_THRESHOLD) 683 state = RTW89_TAS_STATE_STATIC_SAR; 684 else if (txpwr_avg >= dpr_on_threshold) 685 state = RTW89_TAS_STATE_DPR_ON; 686 else if (txpwr_avg < dpr_off_threshold) 687 state = RTW89_TAS_STATE_DPR_OFF; 688 else 689 return false; 690 691 return __rtw89_tas_state_update(rtwdev, state); 692 } 693 694 static void rtw89_tas_init(struct rtw89_dev *rtwdev) 695 { 696 const struct rtw89_chip_info *chip = rtwdev->chip; 697 struct rtw89_tas_info *tas = &rtwdev->tas; 698 const struct rtw89_acpi_policy_tas *ptr; 699 struct rtw89_acpi_dsm_result res = {}; 700 int ret; 701 702 if (!chip->support_tas) 703 return; 704 705 ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_TAS_EN, &res); 706 if (ret) { 707 rtw89_debug(rtwdev, RTW89_DBG_SAR, 708 "acpi: cannot get TAS: %d\n", ret); 709 return; 710 } 711 712 ptr = res.u.policy_tas; 713 714 switch (ptr->enable) { 715 case 0: 716 tas->enable = false; 717 break; 718 case 1: 719 tas->enable = true; 720 break; 721 default: 722 break; 723 } 724 725 if (!tas->enable) { 726 rtw89_debug(rtwdev, RTW89_DBG_SAR, "TAS not enable\n"); 727 goto out; 728 } 729 730 tas->enabled_countries = ptr->enabled_countries; 731 732 out: 733 kfree(ptr); 734 } 735 736 void rtw89_tas_reset(struct rtw89_dev *rtwdev, bool force) 737 { 738 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 739 struct rtw89_tas_info *tas = &rtwdev->tas; 740 u64 linear; 741 s32 cfg; 742 int i; 743 744 if (!rtw89_tas_is_active(rtwdev)) 745 return; 746 747 if (!rtw89_tas_query_sar_config(rtwdev, &cfg)) 748 return; 749 750 tas->dpr_on_threshold = cfg - RTW89_TAS_SAR_GAP; 751 tas->dpr_off_threshold = cfg - RTW89_TAS_SAR_GAP - RTW89_TAS_DPR_GAP; 752 753 /* avoid history reset after new SAR apply */ 754 if (!force && tas->keep_history) 755 return; 756 757 linear = rtw89_db_quarter_to_linear(cfg) * RTW89_TAS_DFLT_TX_RATIO; 758 for (i = 0; i < RTW89_TAS_TXPWR_WINDOW; i++) 759 tas->txpwr_history[i] = linear; 760 761 for (i = 0; i < RTW89_TAS_TX_RATIO_WINDOW; i++) 762 tas->tx_ratio_history[i] = RTW89_TAS_DFLT_TX_RATIO; 763 764 tas->total_tx_ratio = RTW89_TAS_DFLT_TX_RATIO * RTW89_TAS_TX_RATIO_WINDOW; 765 tas->total_txpwr = linear * RTW89_TAS_TXPWR_WINDOW; 766 tas->window_size = RTW89_TAS_TXPWR_WINDOW; 767 tas->txpwr_head_idx = 0; 768 tas->txpwr_tail_idx = RTW89_TAS_TXPWR_WINDOW - 1; 769 tas->tx_ratio_idx = 0; 770 tas->state = RTW89_TAS_STATE_DPR_OFF; 771 tas->backup_state = RTW89_TAS_STATE_DPR_OFF; 772 tas->keep_history = true; 773 774 rtw89_debug(rtwdev, RTW89_DBG_SAR, 775 "tas: band: %u, freq: %u\n", chan->band_type, chan->freq); 776 } 777 778 static bool rtw89_tas_track(struct rtw89_dev *rtwdev) 779 { 780 struct rtw89_tas_info *tas = &rtwdev->tas; 781 struct rtw89_hal *hal = &rtwdev->hal; 782 s32 cfg; 783 784 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_TAS)) 785 return false; 786 787 if (!rtw89_tas_is_active(rtwdev)) 788 return false; 789 790 if (!rtw89_tas_query_sar_config(rtwdev, &cfg) || tas->block_regd) 791 return __rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR); 792 793 if (tas->pause) 794 return false; 795 796 rtw89_tas_window_update(rtwdev); 797 rtw89_tas_history_update(rtwdev); 798 799 return rtw89_tas_rolling_average(rtwdev); 800 } 801 802 void rtw89_tas_scan(struct rtw89_dev *rtwdev, bool start) 803 { 804 struct rtw89_tas_info *tas = &rtwdev->tas; 805 s32 cfg; 806 807 if (!rtw89_tas_is_active(rtwdev)) 808 return; 809 810 if (!rtw89_tas_query_sar_config(rtwdev, &cfg)) 811 return; 812 813 if (start) { 814 tas->backup_state = tas->state; 815 rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR); 816 } else { 817 rtw89_tas_state_update(rtwdev, tas->backup_state); 818 } 819 } 820 821 void rtw89_tas_chanctx_cb(struct rtw89_dev *rtwdev, 822 enum rtw89_chanctx_state state) 823 { 824 struct rtw89_tas_info *tas = &rtwdev->tas; 825 s32 cfg; 826 827 if (!rtw89_tas_is_active(rtwdev)) 828 return; 829 830 if (!rtw89_tas_query_sar_config(rtwdev, &cfg)) 831 return; 832 833 switch (state) { 834 case RTW89_CHANCTX_STATE_MCC_START: 835 tas->pause = true; 836 rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR); 837 break; 838 case RTW89_CHANCTX_STATE_MCC_STOP: 839 tas->pause = false; 840 break; 841 default: 842 break; 843 } 844 } 845 EXPORT_SYMBOL(rtw89_tas_chanctx_cb); 846 847 void rtw89_sar_init(struct rtw89_dev *rtwdev) 848 { 849 rtw89_set_sar_from_acpi(rtwdev); 850 rtw89_tas_init(rtwdev); 851 } 852 853 static bool rtw89_sar_track_acpi(struct rtw89_dev *rtwdev) 854 { 855 struct rtw89_sar_cfg_acpi *cfg = &rtwdev->sar.cfg_acpi; 856 struct rtw89_sar_indicator_from_acpi *ind = &cfg->indicator; 857 const enum rtw89_sar_sources src = rtwdev->sar.src; 858 bool changed; 859 int ret; 860 861 lockdep_assert_wiphy(rtwdev->hw->wiphy); 862 863 if (src != RTW89_SAR_SOURCE_ACPI) 864 return false; 865 866 if (!ind->enable_sync) 867 return false; 868 869 ret = rtw89_acpi_evaluate_dynamic_sar_indicator(rtwdev, cfg, &changed); 870 if (likely(!ret)) 871 return changed; 872 873 rtw89_debug(rtwdev, RTW89_DBG_SAR, 874 "%s: failed to track indicator: %d; reset and disable\n", 875 __func__, ret); 876 877 memset(ind->tblsel, 0, sizeof(ind->tblsel)); 878 ind->enable_sync = false; 879 return true; 880 } 881 882 void rtw89_sar_track(struct rtw89_dev *rtwdev) 883 { 884 unsigned int changes = 0; 885 886 changes += rtw89_sar_track_acpi(rtwdev); 887 changes += rtw89_tas_track(rtwdev); 888 889 if (!changes) 890 return; 891 892 rtw89_core_set_chip_txpwr(rtwdev); 893 } 894