1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "phy.h" 8 #include "reg.h" 9 #include "rtw8852c.h" 10 #include "rtw8852c_rfk.h" 11 #include "rtw8852c_rfk_table.h" 12 #include "rtw8852c_table.h" 13 14 struct rxck_def { 15 u32 ctl; 16 u32 en; 17 u32 bw0; 18 u32 bw1; 19 u32 mul; 20 u32 lp; 21 }; 22 23 #define _TSSI_DE_MASK GENMASK(21, 12) 24 static const u32 _tssi_de_cck_long[RF_PATH_NUM_8852C] = {0x5858, 0x7858}; 25 static const u32 _tssi_de_cck_short[RF_PATH_NUM_8852C] = {0x5860, 0x7860}; 26 static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8852C] = {0x5838, 0x7838}; 27 static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8852C] = {0x5840, 0x7840}; 28 static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8852C] = {0x5848, 0x7848}; 29 static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8852C] = {0x5850, 0x7850}; 30 static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852C] = {0x5828, 0x7828}; 31 static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852C] = {0x5830, 0x7830}; 32 33 static const u32 rtw8852c_backup_bb_regs[] = { 34 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x8220, 0xc1d4, 0xc1d8, 0xc1e8 35 }; 36 37 static const u32 rtw8852c_backup_rf_regs[] = { 38 0xdf, 0x5f, 0x8f, 0x97, 0xa3, 0x5, 0x10005 39 }; 40 41 #define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852c_backup_bb_regs) 42 #define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852c_backup_rf_regs) 43 44 #define RXK_GROUP_NR 4 45 static const u32 _rxk_a6_idxrxgain[RXK_GROUP_NR] = {0x190, 0x196, 0x290, 0x316}; 46 static const u32 _rxk_a6_idxattc2[RXK_GROUP_NR] = {0x00, 0x0, 0x00, 0x00}; 47 static const u32 _rxk_a_idxrxgain[RXK_GROUP_NR] = {0x190, 0x198, 0x310, 0x318}; 48 static const u32 _rxk_a_idxattc2[RXK_GROUP_NR] = {0x00, 0x00, 0x00, 0x00}; 49 static const u32 _rxk_g_idxrxgain[RXK_GROUP_NR] = {0x252, 0x26c, 0x350, 0x360}; 50 static const u32 _rxk_g_idxattc2[RXK_GROUP_NR] = {0x00, 0x07, 0x00, 0x3}; 51 52 #define TXK_GROUP_NR 3 53 static const u32 _txk_a6_power_range[TXK_GROUP_NR] = {0x0, 0x0, 0x0}; 54 static const u32 _txk_a6_track_range[TXK_GROUP_NR] = {0x6, 0x7, 0x7}; 55 static const u32 _txk_a6_gain_bb[TXK_GROUP_NR] = {0x12, 0x09, 0x0e}; 56 static const u32 _txk_a6_itqt[TXK_GROUP_NR] = {0x12, 0x12, 0x12}; 57 static const u32 _txk_a_power_range[TXK_GROUP_NR] = {0x0, 0x0, 0x0}; 58 static const u32 _txk_a_track_range[TXK_GROUP_NR] = {0x5, 0x6, 0x7}; 59 static const u32 _txk_a_gain_bb[TXK_GROUP_NR] = {0x12, 0x09, 0x0e}; 60 static const u32 _txk_a_itqt[TXK_GROUP_NR] = {0x12, 0x12, 0x12}; 61 static const u32 _txk_g_power_range[TXK_GROUP_NR] = {0x0, 0x0, 0x0}; 62 static const u32 _txk_g_track_range[TXK_GROUP_NR] = {0x5, 0x6, 0x6}; 63 static const u32 _txk_g_gain_bb[TXK_GROUP_NR] = {0x0e, 0x0a, 0x0e}; 64 static const u32 _txk_g_itqt[TXK_GROUP_NR] = { 0x12, 0x12, 0x12}; 65 66 static const u32 dpk_par_regs[RTW89_DPK_RF_PATH][4] = { 67 {0x8190, 0x8194, 0x8198, 0x81a4}, 68 {0x81a8, 0x81c4, 0x81c8, 0x81e8}, 69 }; 70 71 static const u8 _dck_addr_bs[RF_PATH_NUM_8852C] = {0x0, 0x10}; 72 static const u8 _dck_addr[RF_PATH_NUM_8852C] = {0xc, 0x1c}; 73 74 static const struct rxck_def _ck480M = {0x8, 0x2, 0x3, 0xf, 0x0, 0x9}; 75 static const struct rxck_def _ck960M = {0x8, 0x2, 0x2, 0x8, 0x0, 0x9}; 76 static const struct rxck_def _ck1920M = {0x8, 0x0, 0x2, 0x4, 0x6, 0x9}; 77 78 static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 79 { 80 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n", 81 rtwdev->dbcc_en, phy_idx); 82 83 if (!rtwdev->dbcc_en) 84 return RF_AB; 85 86 if (phy_idx == RTW89_PHY_0) 87 return RF_A; 88 else 89 return RF_B; 90 } 91 92 static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[]) 93 { 94 u32 i; 95 96 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { 97 backup_bb_reg_val[i] = 98 rtw89_phy_read32_mask(rtwdev, rtw8852c_backup_bb_regs[i], 99 MASKDWORD); 100 rtw89_debug(rtwdev, RTW89_DBG_RFK, 101 "[IQK]backup bb reg : %x, value =%x\n", 102 rtw8852c_backup_bb_regs[i], backup_bb_reg_val[i]); 103 } 104 } 105 106 static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[], 107 u8 rf_path) 108 { 109 u32 i; 110 111 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { 112 backup_rf_reg_val[i] = 113 rtw89_read_rf(rtwdev, rf_path, 114 rtw8852c_backup_rf_regs[i], RFREG_MASK); 115 rtw89_debug(rtwdev, RTW89_DBG_RFK, 116 "[IQK]backup rf S%d reg : %x, value =%x\n", rf_path, 117 rtw8852c_backup_rf_regs[i], backup_rf_reg_val[i]); 118 } 119 } 120 121 static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[]) 122 { 123 u32 i; 124 125 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { 126 rtw89_phy_write32_mask(rtwdev, rtw8852c_backup_bb_regs[i], 127 MASKDWORD, backup_bb_reg_val[i]); 128 rtw89_debug(rtwdev, RTW89_DBG_RFK, 129 "[IQK]restore bb reg : %x, value =%x\n", 130 rtw8852c_backup_bb_regs[i], backup_bb_reg_val[i]); 131 } 132 } 133 134 static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[], 135 u8 rf_path) 136 { 137 u32 i; 138 139 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { 140 rtw89_write_rf(rtwdev, rf_path, rtw8852c_backup_rf_regs[i], 141 RFREG_MASK, backup_rf_reg_val[i]); 142 143 rtw89_debug(rtwdev, RTW89_DBG_RFK, 144 "[IQK]restore rf S%d reg: %x, value =%x\n", rf_path, 145 rtw8852c_backup_rf_regs[i], backup_rf_reg_val[i]); 146 } 147 } 148 149 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath) 150 { 151 u8 path; 152 u32 rf_mode; 153 int ret; 154 155 for (path = 0; path < RF_PATH_MAX; path++) { 156 if (!(kpath & BIT(path))) 157 continue; 158 159 ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2, 160 2, 5000, false, rtwdev, path, 0x00, 161 RR_MOD_MASK); 162 rtw89_debug(rtwdev, RTW89_DBG_RFK, 163 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", 164 path, ret); 165 } 166 } 167 168 static void _dack_dump(struct rtw89_dev *rtwdev) 169 { 170 struct rtw89_dack_info *dack = &rtwdev->dack; 171 u8 i; 172 u8 t; 173 174 rtw89_debug(rtwdev, RTW89_DBG_RFK, 175 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", 176 dack->addck_d[0][0], dack->addck_d[0][1]); 177 rtw89_debug(rtwdev, RTW89_DBG_RFK, 178 "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", 179 dack->addck_d[1][0], dack->addck_d[1][1]); 180 rtw89_debug(rtwdev, RTW89_DBG_RFK, 181 "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 182 dack->dadck_d[0][0], dack->dadck_d[0][1]); 183 rtw89_debug(rtwdev, RTW89_DBG_RFK, 184 "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 185 dack->dadck_d[1][0], dack->dadck_d[1][1]); 186 187 rtw89_debug(rtwdev, RTW89_DBG_RFK, 188 "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", 189 dack->biask_d[0][0], dack->biask_d[0][1]); 190 rtw89_debug(rtwdev, RTW89_DBG_RFK, 191 "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", 192 dack->biask_d[1][0], dack->biask_d[1][1]); 193 194 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n"); 195 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { 196 t = dack->msbk_d[0][0][i]; 197 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); 198 } 199 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n"); 200 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { 201 t = dack->msbk_d[0][1][i]; 202 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); 203 } 204 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n"); 205 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { 206 t = dack->msbk_d[1][0][i]; 207 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); 208 } 209 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n"); 210 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { 211 t = dack->msbk_d[1][1][i]; 212 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); 213 } 214 } 215 216 static void _addck_backup(struct rtw89_dev *rtwdev) 217 { 218 struct rtw89_dack_info *dack = &rtwdev->dack; 219 220 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0); 221 dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, 222 B_ADDCKR0_A0); 223 dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, 224 B_ADDCKR0_A1); 225 226 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x0); 227 dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, 228 B_ADDCKR1_A0); 229 dack->addck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, 230 B_ADDCKR1_A1); 231 } 232 233 static void _addck_reload(struct rtw89_dev *rtwdev) 234 { 235 struct rtw89_dack_info *dack = &rtwdev->dack; 236 237 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL1, 238 dack->addck_d[0][0]); 239 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL0, 240 dack->addck_d[0][1]); 241 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RLS, 0x3); 242 rtw89_phy_write32_mask(rtwdev, R_ADDCK1_RL, B_ADDCK1_RL1, 243 dack->addck_d[1][0]); 244 rtw89_phy_write32_mask(rtwdev, R_ADDCK1_RL, B_ADDCK1_RL0, 245 dack->addck_d[1][1]); 246 rtw89_phy_write32_mask(rtwdev, R_ADDCK1_RL, B_ADDCK1_RLS, 0x3); 247 } 248 249 static void _dack_backup_s0(struct rtw89_dev *rtwdev) 250 { 251 struct rtw89_dack_info *dack = &rtwdev->dack; 252 u8 i; 253 254 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); 255 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { 256 rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_V, i); 257 dack->msbk_d[0][0][i] = rtw89_phy_read32_mask(rtwdev, 258 R_DACK_S0P2, 259 B_DACK_S0M0); 260 rtw89_phy_write32_mask(rtwdev, R_DCOF8, B_DCOF8_V, i); 261 dack->msbk_d[0][1][i] = rtw89_phy_read32_mask(rtwdev, 262 R_DACK_S0P3, 263 B_DACK_S0M1); 264 } 265 dack->biask_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00, 266 B_DACK_BIAS00); 267 dack->biask_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01, 268 B_DACK_BIAS01); 269 dack->dadck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00, 270 B_DACK_DADCK00); 271 dack->dadck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01, 272 B_DACK_DADCK01); 273 } 274 275 static void _dack_backup_s1(struct rtw89_dev *rtwdev) 276 { 277 struct rtw89_dack_info *dack = &rtwdev->dack; 278 u8 i; 279 280 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); 281 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { 282 rtw89_phy_write32_mask(rtwdev, R_DACK10, B_DACK10, i); 283 dack->msbk_d[1][0][i] = rtw89_phy_read32_mask(rtwdev, 284 R_DACK10S, 285 B_DACK10S); 286 rtw89_phy_write32_mask(rtwdev, R_DACK11, B_DACK11, i); 287 dack->msbk_d[1][1][i] = rtw89_phy_read32_mask(rtwdev, 288 R_DACK11S, 289 B_DACK11S); 290 } 291 dack->biask_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS10, 292 B_DACK_BIAS10); 293 dack->biask_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS11, 294 B_DACK_BIAS11); 295 dack->dadck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK10, 296 B_DACK_DADCK10); 297 dack->dadck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK11, 298 B_DACK_DADCK11); 299 } 300 301 static void _dack_reload_by_path(struct rtw89_dev *rtwdev, 302 enum rtw89_rf_path path, u8 index) 303 { 304 struct rtw89_dack_info *dack = &rtwdev->dack; 305 u32 idx_offset, path_offset; 306 u32 val32, offset, addr; 307 u8 i; 308 309 idx_offset = (index == 0 ? 0 : 0x14); 310 path_offset = (path == RF_PATH_A ? 0 : 0x28); 311 offset = idx_offset + path_offset; 312 313 rtw89_rfk_parser(rtwdev, &rtw8852c_dack_reload_defs_tbl); 314 315 /* msbk_d: 15/14/13/12 */ 316 val32 = 0x0; 317 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) 318 val32 |= dack->msbk_d[path][index][i + 12] << (i * 8); 319 addr = 0xc200 + offset; 320 rtw89_phy_write32(rtwdev, addr, val32); 321 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", addr, 322 rtw89_phy_read32_mask(rtwdev, addr, MASKDWORD)); 323 324 /* msbk_d: 11/10/9/8 */ 325 val32 = 0x0; 326 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) 327 val32 |= dack->msbk_d[path][index][i + 8] << (i * 8); 328 addr = 0xc204 + offset; 329 rtw89_phy_write32(rtwdev, addr, val32); 330 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", addr, 331 rtw89_phy_read32_mask(rtwdev, addr, MASKDWORD)); 332 333 /* msbk_d: 7/6/5/4 */ 334 val32 = 0x0; 335 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) 336 val32 |= dack->msbk_d[path][index][i + 4] << (i * 8); 337 addr = 0xc208 + offset; 338 rtw89_phy_write32(rtwdev, addr, val32); 339 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", addr, 340 rtw89_phy_read32_mask(rtwdev, addr, MASKDWORD)); 341 342 /* msbk_d: 3/2/1/0 */ 343 val32 = 0x0; 344 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) 345 val32 |= dack->msbk_d[path][index][i] << (i * 8); 346 addr = 0xc20c + offset; 347 rtw89_phy_write32(rtwdev, addr, val32); 348 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", addr, 349 rtw89_phy_read32_mask(rtwdev, addr, MASKDWORD)); 350 351 /* dadak_d/biask_d */ 352 val32 = (dack->biask_d[path][index] << 22) | 353 (dack->dadck_d[path][index] << 14); 354 addr = 0xc210 + offset; 355 rtw89_phy_write32(rtwdev, addr, val32); 356 rtw89_phy_write32_set(rtwdev, addr, BIT(0)); 357 } 358 359 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) 360 { 361 u8 i; 362 363 for (i = 0; i < 2; i++) 364 _dack_reload_by_path(rtwdev, path, i); 365 } 366 367 static void _addck(struct rtw89_dev *rtwdev) 368 { 369 struct rtw89_dack_info *dack = &rtwdev->dack; 370 u32 val; 371 int ret; 372 373 /* S0 */ 374 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_RST, 0x1); 375 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_EN, 0x1); 376 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_EN, 0x0); 377 fsleep(1); 378 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1); 379 380 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 381 1, 10000, false, rtwdev, 0xc0fc, BIT(0)); 382 if (ret) { 383 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n"); 384 dack->addck_timeout[0] = true; 385 } 386 387 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_RST, 0x0); 388 389 /* S1 */ 390 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_RST, 0x1); 391 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_EN, 0x1); 392 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_EN, 0x0); 393 udelay(1); 394 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x1); 395 396 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 397 1, 10000, false, rtwdev, 0xc1fc, BIT(0)); 398 if (ret) { 399 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n"); 400 dack->addck_timeout[0] = true; 401 } 402 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_RST, 0x0); 403 } 404 405 static void _dack_reset(struct rtw89_dev *rtwdev, u8 path) 406 { 407 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 408 &rtw8852c_dack_reset_defs_a_tbl, 409 &rtw8852c_dack_reset_defs_b_tbl); 410 } 411 412 enum adc_ck { 413 ADC_NA = 0, 414 ADC_480M = 1, 415 ADC_960M = 2, 416 ADC_1920M = 3, 417 }; 418 419 enum dac_ck { 420 DAC_40M = 0, 421 DAC_80M = 1, 422 DAC_120M = 2, 423 DAC_160M = 3, 424 DAC_240M = 4, 425 DAC_320M = 5, 426 DAC_480M = 6, 427 DAC_960M = 7, 428 }; 429 430 enum rf_mode { 431 RF_SHUT_DOWN = 0x0, 432 RF_STANDBY = 0x1, 433 RF_TX = 0x2, 434 RF_RX = 0x3, 435 RF_TXIQK = 0x4, 436 RF_DPK = 0x5, 437 RF_RXK1 = 0x6, 438 RF_RXK2 = 0x7, 439 }; 440 441 static void rtw8852c_txck_force(struct rtw89_dev *rtwdev, u8 path, bool force, 442 enum dac_ck ck) 443 { 444 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0); 445 446 if (!force) 447 return; 448 449 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck); 450 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1); 451 } 452 453 static void rtw8852c_rxck_force(struct rtw89_dev *rtwdev, u8 path, bool force, 454 enum adc_ck ck) 455 { 456 const struct rxck_def *def; 457 458 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0); 459 460 if (!force) 461 return; 462 463 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck); 464 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1); 465 466 switch (ck) { 467 case ADC_480M: 468 def = &_ck480M; 469 break; 470 case ADC_960M: 471 def = &_ck960M; 472 break; 473 case ADC_1920M: 474 default: 475 def = &_ck1920M; 476 break; 477 } 478 479 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_CTL, def->ctl); 480 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_EN, def->en); 481 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, def->bw0); 482 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, def->bw1); 483 rtw89_phy_write32_mask(rtwdev, R_DRCK | (path << 8), B_DRCK_MUL, def->mul); 484 rtw89_phy_write32_mask(rtwdev, R_ADCMOD | (path << 8), B_ADCMOD_LP, def->lp); 485 } 486 487 static bool _check_dack_done(struct rtw89_dev *rtwdev, bool s0) 488 { 489 if (s0) { 490 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 || 491 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0 || 492 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 || 493 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0) 494 return false; 495 } else { 496 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S1P0, B_DACK_S1P0_OK) == 0 || 497 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P1, B_DACK_S1P1_OK) == 0 || 498 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P2, B_DACK_S1P2_OK) == 0 || 499 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P3, B_DACK_S1P3_OK) == 0) 500 return false; 501 } 502 503 return true; 504 } 505 506 static void _dack_s0(struct rtw89_dev *rtwdev) 507 { 508 struct rtw89_dack_info *dack = &rtwdev->dack; 509 bool done; 510 int ret; 511 512 rtw8852c_txck_force(rtwdev, RF_PATH_A, true, DAC_160M); 513 rtw89_rfk_parser(rtwdev, &rtw8852c_dack_defs_s0_tbl); 514 515 _dack_reset(rtwdev, RF_PATH_A); 516 517 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_S, 0x1); 518 ret = read_poll_timeout_atomic(_check_dack_done, done, done, 519 1, 10000, false, rtwdev, true); 520 if (ret) { 521 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DACK timeout\n"); 522 dack->msbk_timeout[0] = true; 523 } 524 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_S, 0x0); 525 rtw8852c_txck_force(rtwdev, RF_PATH_A, false, DAC_960M); 526 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n"); 527 528 _dack_backup_s0(rtwdev); 529 _dack_reload(rtwdev, RF_PATH_A); 530 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); 531 } 532 533 static void _dack_s1(struct rtw89_dev *rtwdev) 534 { 535 struct rtw89_dack_info *dack = &rtwdev->dack; 536 bool done; 537 int ret; 538 539 rtw8852c_txck_force(rtwdev, RF_PATH_B, true, DAC_160M); 540 rtw89_rfk_parser(rtwdev, &rtw8852c_dack_defs_s1_tbl); 541 542 _dack_reset(rtwdev, RF_PATH_B); 543 544 rtw89_phy_write32_mask(rtwdev, R_DACK1_K, B_DACK1_EN, 0x1); 545 ret = read_poll_timeout_atomic(_check_dack_done, done, done, 546 1, 10000, false, rtwdev, false); 547 if (ret) { 548 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DACK timeout\n"); 549 dack->msbk_timeout[0] = true; 550 } 551 rtw89_phy_write32_mask(rtwdev, R_DACK1_K, B_DACK1_EN, 0x0); 552 rtw8852c_txck_force(rtwdev, RF_PATH_B, false, DAC_960M); 553 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n"); 554 555 _dack_backup_s1(rtwdev); 556 _dack_reload(rtwdev, RF_PATH_B); 557 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); 558 } 559 560 static void _dack(struct rtw89_dev *rtwdev) 561 { 562 _dack_s0(rtwdev); 563 _dack_s1(rtwdev); 564 } 565 566 static void _drck(struct rtw89_dev *rtwdev) 567 { 568 u32 val; 569 int ret; 570 571 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x1); 572 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 573 1, 10000, false, rtwdev, 0xc0c8, BIT(3)); 574 if (ret) 575 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n"); 576 577 rtw89_rfk_parser(rtwdev, &rtw8852c_drck_defs_tbl); 578 579 val = rtw89_phy_read32_mask(rtwdev, R_DRCK_RES, B_DRCK_RES); 580 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_IDLE, 0x0); 581 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_VAL, val); 582 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0c4 = 0x%x\n", 583 rtw89_phy_read32_mask(rtwdev, R_DRCK, MASKDWORD)); 584 } 585 586 static void _dac_cal(struct rtw89_dev *rtwdev, bool force) 587 { 588 struct rtw89_dack_info *dack = &rtwdev->dack; 589 u32 rf0_0, rf1_0; 590 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, RF_AB); 591 592 dack->dack_done = false; 593 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK b\n"); 594 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n"); 595 rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK); 596 rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK); 597 _drck(rtwdev); 598 599 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0); 600 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0); 601 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1); 602 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x337e1); 603 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START); 604 _addck(rtwdev); 605 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP); 606 607 _addck_backup(rtwdev); 608 _addck_reload(rtwdev); 609 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0); 610 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0); 611 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START); 612 _dack(rtwdev); 613 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP); 614 615 _dack_dump(rtwdev); 616 dack->dack_done = true; 617 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0); 618 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0); 619 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1); 620 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1); 621 dack->dack_cnt++; 622 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n"); 623 } 624 625 #define RTW8852C_NCTL_VER 0xd 626 #define RTW8852C_IQK_VER 0x2a 627 #define RTW8852C_IQK_SS 2 628 #define RTW8852C_IQK_THR_REK 8 629 #define RTW8852C_IQK_CFIR_GROUP_NR 4 630 631 enum rtw8852c_iqk_type { 632 ID_TXAGC, 633 ID_G_FLOK_COARSE, 634 ID_A_FLOK_COARSE, 635 ID_G_FLOK_FINE, 636 ID_A_FLOK_FINE, 637 ID_FLOK_VBUFFER, 638 ID_TXK, 639 ID_RXAGC, 640 ID_RXK, 641 ID_NBTXK, 642 ID_NBRXK, 643 }; 644 645 static void rtw8852c_disable_rxagc(struct rtw89_dev *rtwdev, u8 path, u8 en_rxgac) 646 { 647 if (path == RF_PATH_A) 648 rtw89_phy_write32_mask(rtwdev, R_P0_AGC_CTL, B_P0_AGC_EN, en_rxgac); 649 else 650 rtw89_phy_write32_mask(rtwdev, R_P1_AGC_CTL, B_P1_AGC_EN, en_rxgac); 651 } 652 653 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) 654 { 655 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 656 657 if (path == RF_PATH_A) 658 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101); 659 else 660 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0202); 661 662 switch (iqk_info->iqk_bw[path]) { 663 case RTW89_CHANNEL_WIDTH_20: 664 case RTW89_CHANNEL_WIDTH_40: 665 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1); 666 rtw8852c_rxck_force(rtwdev, path, true, ADC_480M); 667 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x0); 668 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1); 669 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1); 670 break; 671 case RTW89_CHANNEL_WIDTH_80: 672 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1); 673 rtw8852c_rxck_force(rtwdev, path, true, ADC_960M); 674 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x1); 675 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1); 676 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1); 677 break; 678 case RTW89_CHANNEL_WIDTH_160: 679 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1); 680 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M); 681 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x2); 682 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1); 683 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1); 684 break; 685 default: 686 break; 687 } 688 689 rtw89_rfk_parser(rtwdev, &rtw8852c_iqk_rxk_cfg_defs_tbl); 690 691 if (path == RF_PATH_A) 692 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x1101); 693 else 694 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x2202); 695 } 696 697 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype) 698 { 699 u32 tmp; 700 u32 val; 701 int ret; 702 703 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 704 1, 8200, false, rtwdev, 0xbff8, MASKBYTE0); 705 if (ret) 706 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n"); 707 708 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); 709 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); 710 tmp = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD); 711 rtw89_debug(rtwdev, RTW89_DBG_RFK, 712 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp); 713 714 return false; 715 } 716 717 static bool _iqk_one_shot(struct rtw89_dev *rtwdev, 718 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype) 719 { 720 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 721 u32 addr_rfc_ctl = R_UPD_CLK + (path << 13); 722 u32 iqk_cmd; 723 bool fail; 724 725 switch (ktype) { 726 case ID_TXAGC: 727 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); 728 break; 729 case ID_A_FLOK_COARSE: 730 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 731 iqk_cmd = 0x008 | (1 << (4 + path)); 732 break; 733 case ID_G_FLOK_COARSE: 734 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 735 iqk_cmd = 0x108 | (1 << (4 + path)); 736 break; 737 case ID_A_FLOK_FINE: 738 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 739 iqk_cmd = 0x508 | (1 << (4 + path)); 740 break; 741 case ID_G_FLOK_FINE: 742 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 743 iqk_cmd = 0x208 | (1 << (4 + path)); 744 break; 745 case ID_FLOK_VBUFFER: 746 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 747 iqk_cmd = 0x308 | (1 << (4 + path)); 748 break; 749 case ID_TXK: 750 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x0); 751 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0x8 + iqk_info->iqk_bw[path]) << 8); 752 break; 753 case ID_RXAGC: 754 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); 755 break; 756 case ID_RXK: 757 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 758 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0xc + iqk_info->iqk_bw[path]) << 8); 759 break; 760 case ID_NBTXK: 761 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x0); 762 iqk_cmd = 0x408 | (1 << (4 + path)); 763 break; 764 case ID_NBRXK: 765 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x1); 766 iqk_cmd = 0x608 | (1 << (4 + path)); 767 break; 768 default: 769 return false; 770 } 771 772 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1); 773 fsleep(15); 774 fail = _iqk_check_cal(rtwdev, path, ktype); 775 rtw89_phy_write32_mask(rtwdev, addr_rfc_ctl, 0x00000002, 0x0); 776 777 return fail; 778 } 779 780 static bool _rxk_group_sel(struct rtw89_dev *rtwdev, 781 enum rtw89_phy_idx phy_idx, u8 path) 782 { 783 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 784 bool fail; 785 u32 tmp; 786 u32 bkrf0; 787 u8 gp; 788 789 bkrf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_NBW); 790 if (path == RF_PATH_B) { 791 rtw89_write_rf(rtwdev, RF_PATH_B, RR_IQKPLL, RR_IQKPLL_MOD, 0x3); 792 tmp = rtw89_read_rf(rtwdev, RF_PATH_B, RR_CHTR, RR_CHTR_MOD); 793 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV4, RR_RSV4_AGH, tmp); 794 tmp = rtw89_read_rf(rtwdev, RF_PATH_B, RR_CHTR, RR_CHTR_TXRX); 795 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV4, RR_RSV4_PLLCH, tmp); 796 } 797 798 switch (iqk_info->iqk_band[path]) { 799 case RTW89_BAND_2G: 800 default: 801 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); 802 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0); 803 rtw89_write_rf(rtwdev, path, RR_RXG, RR_RXG_IQKMOD, 0x9); 804 break; 805 case RTW89_BAND_5G: 806 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); 807 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0); 808 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x8); 809 break; 810 case RTW89_BAND_6G: 811 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); 812 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0); 813 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x9); 814 break; 815 } 816 817 fsleep(10); 818 819 for (gp = 0; gp < RXK_GROUP_NR; gp++) { 820 switch (iqk_info->iqk_band[path]) { 821 case RTW89_BAND_2G: 822 default: 823 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, 824 _rxk_g_idxrxgain[gp]); 825 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_VOBUF, 826 _rxk_g_idxattc2[gp]); 827 break; 828 case RTW89_BAND_5G: 829 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, 830 _rxk_a_idxrxgain[gp]); 831 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, 832 _rxk_a_idxattc2[gp]); 833 break; 834 case RTW89_BAND_6G: 835 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, 836 _rxk_a6_idxrxgain[gp]); 837 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, 838 _rxk_a6_idxattc2[gp]); 839 break; 840 } 841 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 842 B_CFIR_LUT_SEL, 0x1); 843 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 844 B_CFIR_LUT_SET, 0x0); 845 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 846 B_CFIR_LUT_GP_V1, gp); 847 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); 848 } 849 850 if (path == RF_PATH_B) 851 rtw89_write_rf(rtwdev, path, RR_IQKPLL, RR_IQKPLL_MOD, 0x0); 852 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, bkrf0); 853 854 if (fail) { 855 iqk_info->nb_rxcfir[path] = 0x40000002; 856 iqk_info->is_wb_rxiqk[path] = false; 857 } else { 858 iqk_info->nb_rxcfir[path] = 0x40000000; 859 iqk_info->is_wb_rxiqk[path] = true; 860 } 861 862 return false; 863 } 864 865 static bool _iqk_nbrxk(struct rtw89_dev *rtwdev, 866 enum rtw89_phy_idx phy_idx, u8 path) 867 { 868 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 869 bool fail; 870 u32 tmp; 871 u32 bkrf0; 872 u8 gp = 0x2; 873 874 bkrf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_NBW); 875 if (path == RF_PATH_B) { 876 rtw89_write_rf(rtwdev, RF_PATH_B, RR_IQKPLL, RR_IQKPLL_MOD, 0x3); 877 tmp = rtw89_read_rf(rtwdev, RF_PATH_B, RR_CHTR, RR_CHTR_MOD); 878 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV4, RR_RSV4_AGH, tmp); 879 tmp = rtw89_read_rf(rtwdev, RF_PATH_B, RR_CHTR, RR_CHTR_TXRX); 880 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV4, RR_RSV4_PLLCH, tmp); 881 } 882 883 switch (iqk_info->iqk_band[path]) { 884 case RTW89_BAND_2G: 885 default: 886 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); 887 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0); 888 rtw89_write_rf(rtwdev, path, RR_RXG, RR_RXG_IQKMOD, 0x9); 889 break; 890 case RTW89_BAND_5G: 891 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); 892 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0); 893 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x8); 894 break; 895 case RTW89_BAND_6G: 896 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); 897 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0); 898 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x9); 899 break; 900 } 901 902 fsleep(10); 903 904 switch (iqk_info->iqk_band[path]) { 905 case RTW89_BAND_2G: 906 default: 907 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_g_idxrxgain[gp]); 908 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_VOBUF, _rxk_g_idxattc2[gp]); 909 break; 910 case RTW89_BAND_5G: 911 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_a_idxrxgain[gp]); 912 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, _rxk_a_idxattc2[gp]); 913 break; 914 case RTW89_BAND_6G: 915 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_a6_idxrxgain[gp]); 916 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, _rxk_a6_idxattc2[gp]); 917 break; 918 } 919 920 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); 921 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0); 922 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp); 923 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); 924 925 if (path == RF_PATH_B) 926 rtw89_write_rf(rtwdev, path, RR_IQKPLL, RR_IQKPLL_MOD, 0x0); 927 928 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, bkrf0); 929 930 if (fail) 931 iqk_info->nb_rxcfir[path] = 932 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), 933 MASKDWORD) | 0x2; 934 else 935 iqk_info->nb_rxcfir[path] = 0x40000002; 936 937 iqk_info->is_wb_rxiqk[path] = false; 938 return fail; 939 } 940 941 static bool _txk_group_sel(struct rtw89_dev *rtwdev, 942 enum rtw89_phy_idx phy_idx, u8 path) 943 { 944 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 945 bool fail; 946 u8 gp; 947 948 for (gp = 0; gp < TXK_GROUP_NR; gp++) { 949 switch (iqk_info->iqk_band[path]) { 950 case RTW89_BAND_2G: 951 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 952 _txk_g_power_range[gp]); 953 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 954 _txk_g_track_range[gp]); 955 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 956 _txk_g_gain_bb[gp]); 957 rtw89_phy_write32_mask(rtwdev, 958 R_KIP_IQP + (path << 8), 959 MASKDWORD, _txk_g_itqt[gp]); 960 break; 961 case RTW89_BAND_5G: 962 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 963 _txk_a_power_range[gp]); 964 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 965 _txk_a_track_range[gp]); 966 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 967 _txk_a_gain_bb[gp]); 968 rtw89_phy_write32_mask(rtwdev, 969 R_KIP_IQP + (path << 8), 970 MASKDWORD, _txk_a_itqt[gp]); 971 break; 972 case RTW89_BAND_6G: 973 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 974 _txk_a6_power_range[gp]); 975 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 976 _txk_a6_track_range[gp]); 977 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 978 _txk_a6_gain_bb[gp]); 979 rtw89_phy_write32_mask(rtwdev, 980 R_KIP_IQP + (path << 8), 981 MASKDWORD, _txk_a6_itqt[gp]); 982 break; 983 default: 984 break; 985 } 986 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 987 B_CFIR_LUT_SEL, 0x1); 988 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 989 B_CFIR_LUT_SET, 0x1); 990 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 991 B_CFIR_LUT_G2, 0x0); 992 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 993 B_CFIR_LUT_GP, gp + 1); 994 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x00b); 995 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); 996 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); 997 } 998 999 if (fail) { 1000 iqk_info->nb_txcfir[path] = 0x40000002; 1001 iqk_info->is_wb_txiqk[path] = false; 1002 } else { 1003 iqk_info->nb_txcfir[path] = 0x40000000; 1004 iqk_info->is_wb_txiqk[path] = true; 1005 } 1006 1007 return fail; 1008 } 1009 1010 static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, 1011 enum rtw89_phy_idx phy_idx, u8 path) 1012 { 1013 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1014 bool fail; 1015 u8 gp = 0x2; 1016 1017 switch (iqk_info->iqk_band[path]) { 1018 case RTW89_BAND_2G: 1019 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_g_power_range[gp]); 1020 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_g_track_range[gp]); 1021 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_g_gain_bb[gp]); 1022 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1023 MASKDWORD, _txk_g_itqt[gp]); 1024 break; 1025 case RTW89_BAND_5G: 1026 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_a_power_range[gp]); 1027 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_a_track_range[gp]); 1028 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_a_gain_bb[gp]); 1029 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1030 MASKDWORD, _txk_a_itqt[gp]); 1031 break; 1032 case RTW89_BAND_6G: 1033 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_a6_power_range[gp]); 1034 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_a6_track_range[gp]); 1035 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_a6_gain_bb[gp]); 1036 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1037 MASKDWORD, _txk_a6_itqt[gp]); 1038 break; 1039 default: 1040 break; 1041 } 1042 1043 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); 1044 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1); 1045 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0); 1046 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp + 1); 1047 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x00b); 1048 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); 1049 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); 1050 1051 if (!fail) 1052 iqk_info->nb_txcfir[path] = 1053 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), 1054 MASKDWORD) | 0x2; 1055 else 1056 iqk_info->nb_txcfir[path] = 0x40000002; 1057 1058 iqk_info->is_wb_txiqk[path] = false; 1059 1060 return fail; 1061 } 1062 1063 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) 1064 { 1065 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1066 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1067 u8 idx = rfk_mcc->table_idx; 1068 bool is_fail1, is_fail2; 1069 u32 val; 1070 u32 core_i; 1071 u32 core_q; 1072 u32 vbuff_i; 1073 u32 vbuff_q; 1074 1075 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1076 val = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); 1077 core_i = FIELD_GET(RR_TXMO_COI, val); 1078 core_q = FIELD_GET(RR_TXMO_COQ, val); 1079 1080 if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) 1081 is_fail1 = true; 1082 else 1083 is_fail1 = false; 1084 1085 iqk_info->lok_idac[idx][path] = val; 1086 1087 val = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK); 1088 vbuff_i = FIELD_GET(RR_LOKVB_COI, val); 1089 vbuff_q = FIELD_GET(RR_LOKVB_COQ, val); 1090 1091 if (vbuff_i < 0x2 || vbuff_i > 0x3d || vbuff_q < 0x2 || vbuff_q > 0x3d) 1092 is_fail2 = true; 1093 else 1094 is_fail2 = false; 1095 1096 iqk_info->lok_vbuf[idx][path] = val; 1097 1098 return is_fail1 || is_fail2; 1099 } 1100 1101 static bool _iqk_lok(struct rtw89_dev *rtwdev, 1102 enum rtw89_phy_idx phy_idx, u8 path) 1103 { 1104 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1105 u8 tmp_id = 0x0; 1106 bool fail = false; 1107 bool tmp = false; 1108 1109 /* Step 0: Init RF gain & tone idx= 8.25Mhz */ 1110 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, IQK_DF4_TXT_8_25MHZ); 1111 1112 /* Step 1 START: _lok_coarse_fine_wi_swap */ 1113 switch (iqk_info->iqk_band[path]) { 1114 case RTW89_BAND_2G: 1115 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6); 1116 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1117 B_KIP_IQP_IQSW, 0x9); 1118 tmp_id = ID_G_FLOK_COARSE; 1119 break; 1120 case RTW89_BAND_5G: 1121 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6); 1122 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1123 B_KIP_IQP_IQSW, 0x9); 1124 tmp_id = ID_A_FLOK_COARSE; 1125 break; 1126 case RTW89_BAND_6G: 1127 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6); 1128 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1129 B_KIP_IQP_IQSW, 0x9); 1130 tmp_id = ID_A_FLOK_COARSE; 1131 break; 1132 default: 1133 break; 1134 } 1135 tmp = _iqk_one_shot(rtwdev, phy_idx, path, tmp_id); 1136 iqk_info->lok_cor_fail[0][path] = tmp; 1137 1138 /* Step 2 */ 1139 switch (iqk_info->iqk_band[path]) { 1140 case RTW89_BAND_2G: 1141 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); 1142 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1143 B_KIP_IQP_IQSW, 0x1b); 1144 break; 1145 case RTW89_BAND_5G: 1146 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); 1147 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1148 B_KIP_IQP_IQSW, 0x1b); 1149 break; 1150 case RTW89_BAND_6G: 1151 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); 1152 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1153 B_KIP_IQP_IQSW, 0x1b); 1154 break; 1155 default: 1156 break; 1157 } 1158 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER); 1159 1160 /* Step 3 */ 1161 switch (iqk_info->iqk_band[path]) { 1162 case RTW89_BAND_2G: 1163 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6); 1164 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1165 B_KIP_IQP_IQSW, 0x9); 1166 tmp_id = ID_G_FLOK_FINE; 1167 break; 1168 case RTW89_BAND_5G: 1169 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6); 1170 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1171 B_KIP_IQP_IQSW, 0x9); 1172 tmp_id = ID_A_FLOK_FINE; 1173 break; 1174 case RTW89_BAND_6G: 1175 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6); 1176 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1177 B_KIP_IQP_IQSW, 0x9); 1178 tmp_id = ID_A_FLOK_FINE; 1179 break; 1180 default: 1181 break; 1182 } 1183 tmp = _iqk_one_shot(rtwdev, phy_idx, path, tmp_id); 1184 iqk_info->lok_fin_fail[0][path] = tmp; 1185 1186 /* Step 4 large rf gain */ 1187 switch (iqk_info->iqk_band[path]) { 1188 case RTW89_BAND_2G: 1189 default: 1190 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); 1191 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1192 B_KIP_IQP_IQSW, 0x1b); 1193 break; 1194 case RTW89_BAND_5G: 1195 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); 1196 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1197 B_KIP_IQP_IQSW, 0x1b); 1198 break; 1199 case RTW89_BAND_6G: 1200 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); 1201 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), 1202 B_KIP_IQP_IQSW, 0x1b); 1203 break; 1204 } 1205 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER); 1206 fail = _lok_finetune_check(rtwdev, path); 1207 1208 return fail; 1209 } 1210 1211 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) 1212 { 1213 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1214 1215 switch (iqk_info->iqk_band[path]) { 1216 case RTW89_BAND_2G: 1217 default: 1218 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); 1219 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0); 1220 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); 1221 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf); 1222 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); 1223 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); 1224 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 1225 0x403e0 | iqk_info->syn1to2); 1226 fsleep(10); 1227 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); 1228 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6); 1229 break; 1230 case RTW89_BAND_5G: 1231 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW2, 0x0); 1232 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXAS, 0x1); 1233 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf); 1234 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); 1235 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); 1236 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 1237 0x403e0 | iqk_info->syn1to2); 1238 fsleep(10); 1239 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); 1240 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6); 1241 break; 1242 case RTW89_BAND_6G: 1243 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW2, 0x0); 1244 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXAS, 0x1); 1245 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf); 1246 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); 1247 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); 1248 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 1249 0x403e0 | iqk_info->syn1to2); 1250 fsleep(10); 1251 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); 1252 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6); 1253 break; 1254 } 1255 } 1256 1257 static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 1258 u8 path) 1259 { 1260 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1261 u32 tmp; 1262 bool flag; 1263 1264 iqk_info->thermal[path] = 1265 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); 1266 iqk_info->thermal_rek_en = false; 1267 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %d\n", path, 1268 iqk_info->thermal[path]); 1269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path, 1270 iqk_info->lok_cor_fail[0][path]); 1271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path, 1272 iqk_info->lok_fin_fail[0][path]); 1273 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path, 1274 iqk_info->iqk_tx_fail[0][path]); 1275 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path, 1276 iqk_info->iqk_rx_fail[0][path]); 1277 1278 flag = iqk_info->lok_cor_fail[0][path]; 1279 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag); 1280 flag = iqk_info->lok_fin_fail[0][path]; 1281 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag); 1282 flag = iqk_info->iqk_tx_fail[0][path]; 1283 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag); 1284 flag = iqk_info->iqk_rx_fail[0][path]; 1285 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag); 1286 1287 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); 1288 iqk_info->bp_iqkenable[path] = tmp; 1289 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); 1290 iqk_info->bp_txkresult[path] = tmp; 1291 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); 1292 iqk_info->bp_rxkresult[path] = tmp; 1293 1294 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, 1295 iqk_info->iqk_times); 1296 1297 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4)); 1298 if (tmp != 0x0) 1299 iqk_info->iqk_fail_cnt++; 1300 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4), 1301 iqk_info->iqk_fail_cnt); 1302 } 1303 1304 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) 1305 { 1306 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1307 1308 _iqk_txk_setting(rtwdev, path); 1309 iqk_info->lok_fail[path] = _iqk_lok(rtwdev, phy_idx, path); 1310 1311 if (iqk_info->is_nbiqk) 1312 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); 1313 else 1314 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); 1315 1316 _iqk_rxk_setting(rtwdev, path); 1317 if (iqk_info->is_nbiqk) 1318 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); 1319 else 1320 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); 1321 1322 _iqk_info_iqk(rtwdev, phy_idx, path); 1323 } 1324 1325 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, 1326 enum rtw89_phy_idx phy, u8 path) 1327 { 1328 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1329 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1330 1331 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1332 1333 iqk_info->iqk_band[path] = chan->band_type; 1334 iqk_info->iqk_bw[path] = chan->band_width; 1335 iqk_info->iqk_ch[path] = chan->channel; 1336 1337 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1338 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, 1339 iqk_info->iqk_band[path]); 1340 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n", 1341 path, iqk_info->iqk_bw[path]); 1342 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n", 1343 path, iqk_info->iqk_ch[path]); 1344 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1345 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy, 1346 rtwdev->dbcc_en ? "on" : "off", 1347 iqk_info->iqk_band[path] == 0 ? "2G" : 1348 iqk_info->iqk_band[path] == 1 ? "5G" : "6G", 1349 iqk_info->iqk_ch[path], 1350 iqk_info->iqk_bw[path] == 0 ? "20M" : 1351 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M"); 1352 if (!rtwdev->dbcc_en) 1353 iqk_info->syn1to2 = 0x1; 1354 else 1355 iqk_info->syn1to2 = 0x3; 1356 1357 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852C_IQK_VER); 1358 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16), 1359 iqk_info->iqk_band[path]); 1360 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16), 1361 iqk_info->iqk_bw[path]); 1362 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16), 1363 iqk_info->iqk_ch[path]); 1364 1365 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_NCTLV, RTW8852C_NCTL_VER); 1366 } 1367 1368 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 1369 u8 path) 1370 { 1371 _iqk_by_path(rtwdev, phy_idx, path); 1372 } 1373 1374 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) 1375 { 1376 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1377 bool fail; 1378 1379 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 1380 iqk_info->nb_txcfir[path]); 1381 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 1382 iqk_info->nb_rxcfir[path]); 1383 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 1384 0x00001219 + (path << 4)); 1385 fsleep(200); 1386 fail = _iqk_check_cal(rtwdev, path, 0x12); 1387 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] restore fail = %x\n", fail); 1388 1389 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); 1390 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000); 1391 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); 1392 1393 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); 1394 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); 1395 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); 1396 } 1397 1398 static void _iqk_afebb_restore(struct rtw89_dev *rtwdev, 1399 enum rtw89_phy_idx phy_idx, u8 path) 1400 { 1401 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 1402 &rtw8852c_iqk_afebb_restore_defs_a_tbl, 1403 &rtw8852c_iqk_afebb_restore_defs_b_tbl); 1404 1405 rtw8852c_disable_rxagc(rtwdev, path, 0x1); 1406 } 1407 1408 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) 1409 { 1410 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1411 u8 idx = 0; 1412 1413 idx = rfk_mcc->table_idx; 1414 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx); 1415 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx); 1416 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); 1417 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); 1418 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a); 1419 } 1420 1421 static void _iqk_macbb_setting(struct rtw89_dev *rtwdev, 1422 enum rtw89_phy_idx phy_idx, u8 path) 1423 { 1424 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===> %s\n", __func__); 1425 1426 /* 01_BB_AFE_for DPK_S0_20210820 */ 1427 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); 1428 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1); 1429 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0); 1430 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1); 1431 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0); 1432 1433 /* disable rxgac */ 1434 rtw8852c_disable_rxagc(rtwdev, path, 0x0); 1435 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), MASKDWORD, 0xf801fffd); 1436 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DPD_DIS, 0x1); 1437 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DAC_VAL, 0x1); 1438 1439 rtw8852c_txck_force(rtwdev, path, true, DAC_960M); 1440 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DPD_GDIS, 0x1); 1441 1442 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M); 1443 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_ACK_VAL, 0x2); 1444 1445 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW | (path << 13), B_P0_NRBW_DBG, 0x1); 1446 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f); 1447 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13); 1448 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001); 1449 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041); 1450 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x1); 1451 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x1); 1452 } 1453 1454 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) 1455 { 1456 u32 rf_reg5, rck_val = 0; 1457 u32 val; 1458 int ret; 1459 1460 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); 1461 1462 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); 1463 1464 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); 1465 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); 1466 1467 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n", 1468 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); 1469 1470 /* RCK trigger */ 1471 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); 1472 1473 ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 20, 1474 false, rtwdev, path, 0x1c, BIT(3)); 1475 if (ret) 1476 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RCK timeout\n"); 1477 1478 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); 1479 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); 1480 1481 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); 1482 1483 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1484 "[RCK] RF 0x1b / 0x1c = 0x%x / 0x%x\n", 1485 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK), 1486 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK)); 1487 } 1488 1489 static void _iqk_init(struct rtw89_dev *rtwdev) 1490 { 1491 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1492 u8 ch, path; 1493 1494 rtw89_phy_write32_clr(rtwdev, R_IQKINF, MASKDWORD); 1495 if (iqk_info->is_iqk_init) 1496 return; 1497 1498 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1499 iqk_info->is_iqk_init = true; 1500 iqk_info->is_nbiqk = false; 1501 iqk_info->iqk_fft_en = false; 1502 iqk_info->iqk_sram_en = false; 1503 iqk_info->iqk_cfir_en = false; 1504 iqk_info->iqk_xym_en = false; 1505 iqk_info->thermal_rek_en = false; 1506 iqk_info->iqk_times = 0x0; 1507 1508 for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) { 1509 iqk_info->iqk_channel[ch] = 0x0; 1510 for (path = 0; path < RTW8852C_IQK_SS; path++) { 1511 iqk_info->lok_cor_fail[ch][path] = false; 1512 iqk_info->lok_fin_fail[ch][path] = false; 1513 iqk_info->iqk_tx_fail[ch][path] = false; 1514 iqk_info->iqk_rx_fail[ch][path] = false; 1515 iqk_info->iqk_mcc_ch[ch][path] = 0x0; 1516 iqk_info->iqk_table_idx[path] = 0x0; 1517 } 1518 } 1519 } 1520 1521 static void _doiqk(struct rtw89_dev *rtwdev, bool force, 1522 enum rtw89_phy_idx phy_idx, u8 path) 1523 { 1524 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1525 u32 backup_bb_val[BACKUP_BB_REGS_NR]; 1526 u32 backup_rf_val[RTW8852C_IQK_SS][BACKUP_RF_REGS_NR]; 1527 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB); 1528 1529 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START); 1530 1531 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1532 "[IQK]==========IQK strat!!!!!==========\n"); 1533 iqk_info->iqk_times++; 1534 iqk_info->kcount = 0; 1535 iqk_info->version = RTW8852C_IQK_VER; 1536 1537 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version); 1538 _iqk_get_ch_info(rtwdev, phy_idx, path); 1539 _rfk_backup_bb_reg(rtwdev, backup_bb_val); 1540 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path); 1541 _iqk_macbb_setting(rtwdev, phy_idx, path); 1542 _iqk_preset(rtwdev, path); 1543 _iqk_start_iqk(rtwdev, phy_idx, path); 1544 _iqk_restore(rtwdev, path); 1545 _iqk_afebb_restore(rtwdev, phy_idx, path); 1546 _rfk_restore_bb_reg(rtwdev, backup_bb_val); 1547 _rfk_restore_rf_reg(rtwdev, backup_rf_val[path], path); 1548 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP); 1549 } 1550 1551 static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force) 1552 { 1553 switch (_kpath(rtwdev, phy_idx)) { 1554 case RF_A: 1555 _doiqk(rtwdev, force, phy_idx, RF_PATH_A); 1556 break; 1557 case RF_B: 1558 _doiqk(rtwdev, force, phy_idx, RF_PATH_B); 1559 break; 1560 case RF_AB: 1561 _doiqk(rtwdev, force, phy_idx, RF_PATH_A); 1562 _doiqk(rtwdev, force, phy_idx, RF_PATH_B); 1563 break; 1564 default: 1565 break; 1566 } 1567 } 1568 1569 static void _rx_dck_value_rewrite(struct rtw89_dev *rtwdev, u8 path, u8 addr, 1570 u8 val_i, u8 val_q) 1571 { 1572 u32 ofst_val; 1573 1574 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1575 "[RX_DCK] rewrite val_i = 0x%x, val_q = 0x%x\n", val_i, val_q); 1576 1577 /* val_i and val_q are 7 bits, and target is 6 bits. */ 1578 ofst_val = u32_encode_bits(val_q >> 1, RR_LUTWD0_MB) | 1579 u32_encode_bits(val_i >> 1, RR_LUTWD0_LB); 1580 1581 rtw89_write_rf(rtwdev, path, RR_LUTPLL, RR_CAL_RW, 0x1); 1582 rtw89_write_rf(rtwdev, path, RR_RFC, RR_WCAL, 0x1); 1583 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x1); 1584 rtw89_write_rf(rtwdev, path, RR_LUTWA, MASKBYTE0, addr); 1585 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ofst_val); 1586 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ofst_val); 1587 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); 1588 rtw89_write_rf(rtwdev, path, RR_RFC, RR_WCAL, 0x0); 1589 rtw89_write_rf(rtwdev, path, RR_LUTPLL, RR_CAL_RW, 0x0); 1590 1591 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] Final val_i = 0x%x, val_q = 0x%x\n", 1592 u32_get_bits(ofst_val, RR_LUTWD0_LB) << 1, 1593 u32_get_bits(ofst_val, RR_LUTWD0_MB) << 1); 1594 } 1595 1596 static bool _rx_dck_rek_check(struct rtw89_dev *rtwdev, u8 path) 1597 { 1598 u8 i_even_bs, q_even_bs; 1599 u8 i_odd_bs, q_odd_bs; 1600 u8 i_even, q_even; 1601 u8 i_odd, q_odd; 1602 const u8 th = 10; 1603 u8 i; 1604 1605 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 1606 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i]); 1607 i_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1608 q_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1609 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1610 "[RX_DCK] Gain[0x%x] i_even_bs/ q_even_bs = 0x%x/ 0x%x\n", 1611 _dck_addr_bs[i], i_even_bs, q_even_bs); 1612 1613 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i]); 1614 i_even = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1615 q_even = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1616 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1617 "[RX_DCK] Gain[0x%x] i_even/ q_even = 0x%x/ 0x%x\n", 1618 _dck_addr[i], i_even, q_even); 1619 1620 if (abs(i_even_bs - i_even) > th || abs(q_even_bs - q_even) > th) 1621 return true; 1622 1623 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i] + 1); 1624 i_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1625 q_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1626 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1627 "[RX_DCK] Gain[0x%x] i_odd_bs/ q_odd_bs = 0x%x/ 0x%x\n", 1628 _dck_addr_bs[i] + 1, i_odd_bs, q_odd_bs); 1629 1630 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i] + 1); 1631 i_odd = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1632 q_odd = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1633 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1634 "[RX_DCK] Gain[0x%x] i_odd/ q_odd = 0x%x/ 0x%x\n", 1635 _dck_addr[i] + 1, i_odd, q_odd); 1636 1637 if (abs(i_odd_bs - i_odd) > th || abs(q_odd_bs - q_odd) > th) 1638 return true; 1639 } 1640 1641 return false; 1642 } 1643 1644 static void _rx_dck_fix_if_need(struct rtw89_dev *rtwdev, u8 path, u8 addr, 1645 u8 val_i_bs, u8 val_q_bs, u8 val_i, u8 val_q) 1646 { 1647 const u8 th = 10; 1648 1649 if ((abs(val_i_bs - val_i) < th) && (abs(val_q_bs - val_q) <= th)) { 1650 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] offset check PASS!!\n"); 1651 return; 1652 } 1653 1654 if (abs(val_i_bs - val_i) > th) { 1655 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1656 "[RX_DCK] val_i over TH (0x%x / 0x%x)\n", val_i_bs, val_i); 1657 val_i = val_i_bs; 1658 } 1659 1660 if (abs(val_q_bs - val_q) > th) { 1661 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1662 "[RX_DCK] val_q over TH (0x%x / 0x%x)\n", val_q_bs, val_q); 1663 val_q = val_q_bs; 1664 } 1665 1666 _rx_dck_value_rewrite(rtwdev, path, addr, val_i, val_q); 1667 } 1668 1669 static void _rx_dck_recover(struct rtw89_dev *rtwdev, u8 path) 1670 { 1671 u8 i_even_bs, q_even_bs; 1672 u8 i_odd_bs, q_odd_bs; 1673 u8 i_even, q_even; 1674 u8 i_odd, q_odd; 1675 u8 i; 1676 1677 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] ===> recovery\n"); 1678 1679 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 1680 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i]); 1681 i_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1682 q_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1683 1684 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i] + 1); 1685 i_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1686 q_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1687 1688 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1689 "[RX_DCK] Gain[0x%x] i_even_bs/ q_even_bs = 0x%x/ 0x%x\n", 1690 _dck_addr_bs[i], i_even_bs, q_even_bs); 1691 1692 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i]); 1693 i_even = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1694 q_even = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1695 1696 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1697 "[RX_DCK] Gain[0x%x] i_even/ q_even = 0x%x/ 0x%x\n", 1698 _dck_addr[i], i_even, q_even); 1699 _rx_dck_fix_if_need(rtwdev, path, _dck_addr[i], 1700 i_even_bs, q_even_bs, i_even, q_even); 1701 1702 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1703 "[RX_DCK] Gain[0x%x] i_odd_bs/ q_odd_bs = 0x%x/ 0x%x\n", 1704 _dck_addr_bs[i] + 1, i_odd_bs, q_odd_bs); 1705 1706 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i] + 1); 1707 i_odd = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA); 1708 q_odd = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA); 1709 1710 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1711 "[RX_DCK] Gain[0x%x] i_odd/ q_odd = 0x%x/ 0x%x\n", 1712 _dck_addr[i] + 1, i_odd, q_odd); 1713 _rx_dck_fix_if_need(rtwdev, path, _dck_addr[i] + 1, 1714 i_odd_bs, q_odd_bs, i_odd, q_odd); 1715 } 1716 } 1717 1718 static void _rx_dck_toggle(struct rtw89_dev *rtwdev, u8 path) 1719 { 1720 int ret; 1721 u32 val; 1722 1723 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); 1724 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); 1725 1726 ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 1727 2, 2000, false, rtwdev, path, 1728 RR_DCK1, RR_DCK1_DONE); 1729 if (ret) 1730 rtw89_warn(rtwdev, "[RX_DCK] S%d RXDCK timeout\n", path); 1731 else 1732 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] S%d RXDCK finish\n", path); 1733 1734 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); 1735 } 1736 1737 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path, 1738 bool is_afe) 1739 { 1740 u8 res; 1741 1742 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0); 1743 1744 _rx_dck_toggle(rtwdev, path); 1745 if (rtw89_read_rf(rtwdev, path, RR_DCKC, RR_DCKC_CHK) == 0) 1746 return; 1747 res = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_DONE); 1748 if (res > 1) { 1749 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, res); 1750 _rx_dck_toggle(rtwdev, path); 1751 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, 0x1); 1752 } 1753 } 1754 1755 static 1756 u8 _rx_dck_channel_calc(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan) 1757 { 1758 u8 target_ch = 0; 1759 1760 if (chan->band_type == RTW89_BAND_5G) { 1761 if (chan->channel >= 36 && chan->channel <= 64) { 1762 target_ch = 100; 1763 } else if (chan->channel >= 100 && chan->channel <= 144) { 1764 target_ch = chan->channel + 32; 1765 if (target_ch > 144) 1766 target_ch = chan->channel + 33; 1767 } else if (chan->channel >= 149 && chan->channel <= 177) { 1768 target_ch = chan->channel - 33; 1769 } 1770 } else if (chan->band_type == RTW89_BAND_6G) { 1771 if (chan->channel >= 1 && chan->channel <= 125) 1772 target_ch = chan->channel + 32; 1773 else 1774 target_ch = chan->channel - 32; 1775 } else { 1776 target_ch = chan->channel; 1777 } 1778 1779 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1780 "[RX_DCK] cur_ch / target_ch = %d / %d\n", 1781 chan->channel, target_ch); 1782 1783 return target_ch; 1784 } 1785 1786 #define RTW8852C_RF_REL_VERSION 34 1787 #define RTW8852C_DPK_VER 0xf 1788 #define RTW8852C_DPK_TH_AVG_NUM 4 1789 #define RTW8852C_DPK_RF_PATH 2 1790 #define RTW8852C_DPK_KIP_REG_NUM 7 1791 #define RTW8852C_DPK_RXSRAM_DBG 0 1792 1793 enum rtw8852c_dpk_id { 1794 LBK_RXIQK = 0x06, 1795 SYNC = 0x10, 1796 MDPK_IDL = 0x11, 1797 MDPK_MPA = 0x12, 1798 GAIN_LOSS = 0x13, 1799 GAIN_CAL = 0x14, 1800 DPK_RXAGC = 0x15, 1801 KIP_PRESET = 0x16, 1802 KIP_RESTORE = 0x17, 1803 DPK_TXAGC = 0x19, 1804 D_KIP_PRESET = 0x28, 1805 D_TXAGC = 0x29, 1806 D_RXAGC = 0x2a, 1807 D_SYNC = 0x2b, 1808 D_GAIN_LOSS = 0x2c, 1809 D_MDPK_IDL = 0x2d, 1810 D_GAIN_NORM = 0x2f, 1811 D_KIP_THERMAL = 0x30, 1812 D_KIP_RESTORE = 0x31 1813 }; 1814 1815 #define DPK_TXAGC_LOWER 0x2e 1816 #define DPK_TXAGC_UPPER 0x3f 1817 #define DPK_TXAGC_INVAL 0xff 1818 1819 enum dpk_agc_step { 1820 DPK_AGC_STEP_SYNC_DGAIN, 1821 DPK_AGC_STEP_GAIN_LOSS_IDX, 1822 DPK_AGC_STEP_GL_GT_CRITERION, 1823 DPK_AGC_STEP_GL_LT_CRITERION, 1824 DPK_AGC_STEP_SET_TX_GAIN, 1825 }; 1826 1827 enum dpk_pas_result { 1828 DPK_PAS_NOR, 1829 DPK_PAS_GT, 1830 DPK_PAS_LT, 1831 }; 1832 1833 static void _rf_direct_cntrl(struct rtw89_dev *rtwdev, 1834 enum rtw89_rf_path path, bool is_bybb) 1835 { 1836 if (is_bybb) 1837 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); 1838 else 1839 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); 1840 } 1841 1842 static void _dpk_onoff(struct rtw89_dev *rtwdev, 1843 enum rtw89_rf_path path, bool off); 1844 1845 static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, const u32 reg[], 1846 u32 reg_bkup[][RTW8852C_DPK_KIP_REG_NUM], u8 path) 1847 { 1848 u8 i; 1849 1850 for (i = 0; i < RTW8852C_DPK_KIP_REG_NUM; i++) { 1851 reg_bkup[path][i] = 1852 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD); 1853 1854 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n", 1855 reg[i] + (path << 8), reg_bkup[path][i]); 1856 } 1857 } 1858 1859 static void _dpk_reload_kip(struct rtw89_dev *rtwdev, const u32 reg[], 1860 u32 reg_bkup[][RTW8852C_DPK_KIP_REG_NUM], u8 path) 1861 { 1862 u8 i; 1863 1864 for (i = 0; i < RTW8852C_DPK_KIP_REG_NUM; i++) { 1865 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), 1866 MASKDWORD, reg_bkup[path][i]); 1867 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n", 1868 reg[i] + (path << 8), reg_bkup[path][i]); 1869 } 1870 } 1871 1872 static u8 _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 1873 enum rtw89_rf_path path, enum rtw8852c_dpk_id id) 1874 { 1875 u16 dpk_cmd; 1876 u32 val; 1877 int ret; 1878 1879 dpk_cmd = (u16)((id << 8) | (0x19 + path * 0x12)); 1880 1881 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd); 1882 1883 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1884 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0); 1885 udelay(10); 1886 rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); 1887 1888 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1889 "[DPK] one-shot for %s = 0x%x (ret=%d)\n", 1890 id == 0x06 ? "LBK_RXIQK" : 1891 id == 0x10 ? "SYNC" : 1892 id == 0x11 ? "MDPK_IDL" : 1893 id == 0x12 ? "MDPK_MPA" : 1894 id == 0x13 ? "GAIN_LOSS" : "PWR_CAL", 1895 dpk_cmd, ret); 1896 1897 if (ret) { 1898 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1899 "[DPK] one-shot over 20ms!!!!\n"); 1900 return 1; 1901 } 1902 1903 return 0; 1904 } 1905 1906 static void _dpk_information(struct rtw89_dev *rtwdev, 1907 enum rtw89_phy_idx phy, 1908 enum rtw89_rf_path path) 1909 { 1910 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1911 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 1912 1913 u8 kidx = dpk->cur_idx[path]; 1914 1915 dpk->bp[path][kidx].band = chan->band_type; 1916 dpk->bp[path][kidx].ch = chan->channel; 1917 dpk->bp[path][kidx].bw = chan->band_width; 1918 1919 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1920 "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n", 1921 path, dpk->cur_idx[path], phy, 1922 rtwdev->is_tssi_mode[path] ? "on" : "off", 1923 rtwdev->dbcc_en ? "on" : "off", 1924 dpk->bp[path][kidx].band == 0 ? "2G" : 1925 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", 1926 dpk->bp[path][kidx].ch, 1927 dpk->bp[path][kidx].bw == 0 ? "20M" : 1928 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); 1929 } 1930 1931 static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev, 1932 enum rtw89_phy_idx phy, 1933 enum rtw89_rf_path path, u8 kpath) 1934 { 1935 /*1. Keep ADC_fifo reset*/ 1936 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1); 1937 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0); 1938 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1); 1939 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0); 1940 1941 /*2. BB for IQK DBG mode*/ 1942 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0xd801dffd); 1943 1944 /*3.Set DAC clk*/ 1945 rtw8852c_txck_force(rtwdev, path, true, DAC_960M); 1946 1947 /*4. Set ADC clk*/ 1948 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M); 1949 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), 1950 B_P0_NRBW_DBG, 0x1); 1951 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, MASKBYTE3, 0x1f); 1952 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, MASKBYTE3, 0x13); 1953 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, MASKHWORD, 0x0001); 1954 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, MASKHWORD, 0x0041); 1955 1956 /*5. ADDA fifo rst*/ 1957 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x1); 1958 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x1); 1959 1960 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE setting\n", path); 1961 } 1962 1963 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, u8 path) 1964 { 1965 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), 1966 B_P0_NRBW_DBG, 0x0); 1967 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1); 1968 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0); 1969 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1); 1970 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0); 1971 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0x00000000); 1972 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00); 1973 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x0); 1974 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x0); 1975 1976 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE restore\n", path); 1977 } 1978 1979 static void _dpk_tssi_pause(struct rtw89_dev *rtwdev, 1980 enum rtw89_rf_path path, bool is_pause) 1981 { 1982 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), 1983 B_P0_TSSI_TRK_EN, is_pause); 1984 1985 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, 1986 is_pause ? "pause" : "resume"); 1987 } 1988 1989 static void _dpk_kip_control_rfc(struct rtw89_dev *rtwdev, u8 path, bool ctrl_by_kip) 1990 { 1991 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_IQK_RFC_ON, ctrl_by_kip); 1992 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] RFC is controlled by %s\n", 1993 ctrl_by_kip ? "KIP" : "BB"); 1994 } 1995 1996 static void _dpk_txpwr_bb_force(struct rtw89_dev *rtwdev, u8 path, bool force) 1997 { 1998 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_ON, force); 1999 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force); 2000 2001 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d txpwr_bb_force %s\n", 2002 path, force ? "on" : "off"); 2003 } 2004 2005 static void _dpk_kip_restore(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2006 enum rtw89_rf_path path) 2007 { 2008 _dpk_one_shot(rtwdev, phy, path, D_KIP_RESTORE); 2009 _dpk_kip_control_rfc(rtwdev, path, false); 2010 _dpk_txpwr_bb_force(rtwdev, path, false); 2011 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); 2012 } 2013 2014 static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, 2015 enum rtw89_phy_idx phy, 2016 enum rtw89_rf_path path) 2017 { 2018 #define RX_TONE_IDX 0x00250025 /* Q.2 9.25MHz */ 2019 u8 cur_rxbb; 2020 u32 rf_11, reg_81cc; 2021 2022 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1); 2023 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1); 2024 2025 _dpk_kip_control_rfc(rtwdev, path, false); 2026 2027 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); 2028 rf_11 = rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK); 2029 reg_81cc = rtw89_phy_read32_mask(rtwdev, R_KIP_IQP + (path << 8), 2030 B_KIP_IQP_SW); 2031 2032 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); 2033 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x3); 2034 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0xd); 2035 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, 0x1f); 2036 2037 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x12); 2038 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, 0x3); 2039 2040 _dpk_kip_control_rfc(rtwdev, path, true); 2041 2042 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, MASKDWORD, RX_TONE_IDX); 2043 2044 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); 2045 2046 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, 2047 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD)); 2048 2049 _dpk_kip_control_rfc(rtwdev, path, false); 2050 2051 rtw89_write_rf(rtwdev, path, RR_TXIG, RFREG_MASK, rf_11); 2052 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, cur_rxbb); 2053 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, reg_81cc); 2054 2055 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0); 2056 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0); 2057 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1); 2058 2059 _dpk_kip_control_rfc(rtwdev, path, true); 2060 } 2061 2062 static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain, 2063 enum rtw89_rf_path path, u8 kidx) 2064 { 2065 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2066 2067 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { 2068 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 2069 0x50121 | BIT(rtwdev->dbcc_en)); 2070 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK); 2071 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x2); 2072 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4); 2073 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); 2074 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); 2075 2076 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2077 "[DPK] RF 0x0/0x83/0x9e/0x1a/0xdf/0x1001a = 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x\n", 2078 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), 2079 rtw89_read_rf(rtwdev, path, RR_RXBB, RFREG_MASK), 2080 rtw89_read_rf(rtwdev, path, RR_TIA, RFREG_MASK), 2081 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK), 2082 rtw89_read_rf(rtwdev, path, RR_LUTDBG, RFREG_MASK), 2083 rtw89_read_rf(rtwdev, path, 0x1001a, RFREG_MASK)); 2084 } else { 2085 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 2086 0x50101 | BIT(rtwdev->dbcc_en)); 2087 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK); 2088 2089 if (dpk->bp[path][kidx].band == RTW89_BAND_6G && dpk->bp[path][kidx].ch >= 161) 2090 rtw89_write_rf(rtwdev, path, RR_IQGEN, RR_IQGEN_BIAS, 0x8); 2091 2092 rtw89_write_rf(rtwdev, path, RR_LOGEN, RR_LOGEN_RPT, 0xd); 2093 rtw89_write_rf(rtwdev, path, RR_TXAC, RR_TXAC_IQG, 0x8); 2094 2095 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_ATT, 0x0); 2096 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT2, 0x3); 2097 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); 2098 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); 2099 2100 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160) 2101 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0); 2102 } 2103 } 2104 2105 static void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) 2106 { 2107 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2108 2109 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160) { 2110 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x3); 2111 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0x0180ff30); 2112 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) { 2113 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x0); 2114 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xffe0fa00); 2115 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) { 2116 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2); 2117 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xff4009e0); 2118 } else { 2119 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1); 2120 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xf9f007d0); 2121 } 2122 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n", 2123 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160 ? "160M" : 2124 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : 2125 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); 2126 } 2127 2128 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) 2129 { 2130 #define DPK_SYNC_TH_DC_I 200 2131 #define DPK_SYNC_TH_DC_Q 200 2132 #define DPK_SYNC_TH_CORR 170 2133 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2134 u16 dc_i, dc_q; 2135 u8 corr_val, corr_idx, rxbb; 2136 u8 rxbb_ov; 2137 2138 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0); 2139 2140 corr_idx = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI); 2141 corr_val = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV); 2142 2143 dpk->corr_idx[path][kidx] = corr_idx; 2144 dpk->corr_val[path][kidx] = corr_val; 2145 2146 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9); 2147 2148 dc_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); 2149 dc_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ); 2150 2151 dc_i = abs(sign_extend32(dc_i, 11)); 2152 dc_q = abs(sign_extend32(dc_q, 11)); 2153 2154 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2155 "[DPK] S%d Corr_idx/ Corr_val /DC I/Q, = %d / %d / %d / %d\n", 2156 path, corr_idx, corr_val, dc_i, dc_q); 2157 2158 dpk->dc_i[path][kidx] = dc_i; 2159 dpk->dc_q[path][kidx] = dc_q; 2160 2161 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x8); 2162 rxbb = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXBB); 2163 2164 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x31); 2165 rxbb_ov = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXOV); 2166 2167 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2168 "[DPK] S%d RXBB/ RXAGC_done /RXBB_ovlmt = %d / %d / %d\n", 2169 path, rxbb, 2170 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DONE), 2171 rxbb_ov); 2172 2173 if (dc_i > DPK_SYNC_TH_DC_I || dc_q > DPK_SYNC_TH_DC_Q || 2174 corr_val < DPK_SYNC_TH_CORR) 2175 return true; 2176 else 2177 return false; 2178 } 2179 2180 static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev) 2181 { 2182 u16 dgain = 0x0; 2183 2184 rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL); 2185 2186 dgain = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); 2187 2188 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x (%d)\n", dgain, dgain); 2189 2190 return dgain; 2191 } 2192 2193 static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev) 2194 { 2195 u8 result; 2196 2197 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); 2198 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); 2199 2200 result = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL); 2201 2202 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp GL = %d\n", result); 2203 2204 return result; 2205 } 2206 2207 static void _dpk_kset_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) 2208 { 2209 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2210 2211 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0x10); 2212 dpk->cur_k_set = 2213 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), 0xE0000000) - 1; 2214 } 2215 2216 static void _dpk_kip_set_txagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2217 enum rtw89_rf_path path, u8 dbm, bool set_from_bb) 2218 { 2219 if (set_from_bb) { 2220 dbm = clamp_t(u8, dbm, 7, 24); 2221 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set S%d txagc to %ddBm\n", path, dbm); 2222 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_VAL, dbm << 2); 2223 } 2224 _dpk_one_shot(rtwdev, phy, path, D_TXAGC); 2225 _dpk_kset_query(rtwdev, path); 2226 } 2227 2228 static u8 _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2229 enum rtw89_rf_path path, u8 kidx) 2230 { 2231 _dpk_one_shot(rtwdev, phy, path, D_GAIN_LOSS); 2232 _dpk_kip_set_txagc(rtwdev, phy, path, 0xff, false); 2233 2234 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A1, 0x0); 2235 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A0, 0x0); 2236 2237 return _dpk_gainloss_read(rtwdev); 2238 } 2239 2240 static enum dpk_pas_result _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check) 2241 { 2242 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; 2243 u32 val1_sqrt_sum, val2_sqrt_sum; 2244 u8 i; 2245 2246 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06); 2247 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0); 2248 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08); 2249 2250 if (is_check) { 2251 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00); 2252 val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD); 2253 val1_i = abs(sign_extend32(val1_i, 11)); 2254 val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD); 2255 val1_q = abs(sign_extend32(val1_q, 11)); 2256 2257 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f); 2258 val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD); 2259 val2_i = abs(sign_extend32(val2_i, 11)); 2260 val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD); 2261 val2_q = abs(sign_extend32(val2_q, 11)); 2262 2263 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n", 2264 phy_div(val1_i * val1_i + val1_q * val1_q, 2265 val2_i * val2_i + val2_q * val2_q)); 2266 } else { 2267 for (i = 0; i < 32; i++) { 2268 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i); 2269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_Read[%02d]= 0x%08x\n", i, 2270 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD)); 2271 } 2272 } 2273 2274 val1_sqrt_sum = val1_i * val1_i + val1_q * val1_q; 2275 val2_sqrt_sum = val2_i * val2_i + val2_q * val2_q; 2276 2277 if (val1_sqrt_sum < val2_sqrt_sum) 2278 return DPK_PAS_LT; 2279 else if (val1_sqrt_sum >= val2_sqrt_sum * 8 / 5) 2280 return DPK_PAS_GT; 2281 else 2282 return DPK_PAS_NOR; 2283 } 2284 2285 static bool _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2286 enum rtw89_rf_path path, u8 kidx) 2287 { 2288 _dpk_kip_control_rfc(rtwdev, path, false); 2289 rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD, 2290 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); 2291 _dpk_kip_control_rfc(rtwdev, path, true); 2292 2293 _dpk_one_shot(rtwdev, phy, path, D_RXAGC); 2294 2295 return _dpk_sync_check(rtwdev, path, kidx); 2296 } 2297 2298 static void _dpk_read_rxsram(struct rtw89_dev *rtwdev) 2299 { 2300 u32 addr; 2301 2302 rtw89_rfk_parser(rtwdev, &rtw8852c_read_rxsram_pre_defs_tbl); 2303 2304 for (addr = 0; addr < 0x200; addr++) { 2305 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 | addr); 2306 2307 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] RXSRAM[%03d] = 0x%07x\n", addr, 2308 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD)); 2309 } 2310 2311 rtw89_rfk_parser(rtwdev, &rtw8852c_read_rxsram_post_defs_tbl); 2312 } 2313 2314 static void _dpk_bypass_rxiqc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) 2315 { 2316 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1); 2317 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000002); 2318 2319 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Bypass RXIQC\n"); 2320 } 2321 2322 static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2323 enum rtw89_rf_path path, u8 kidx, u8 init_xdbm, u8 loss_only) 2324 { 2325 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2326 u8 step = DPK_AGC_STEP_SYNC_DGAIN; 2327 u8 tmp_dbm = init_xdbm, tmp_gl_idx = 0; 2328 u8 tmp_rxbb; 2329 u8 goout = 0, agc_cnt = 0; 2330 enum dpk_pas_result pas; 2331 u16 dgain = 0; 2332 bool is_fail = false; 2333 int limit = 200; 2334 2335 do { 2336 switch (step) { 2337 case DPK_AGC_STEP_SYNC_DGAIN: 2338 is_fail = _dpk_kip_set_rxagc(rtwdev, phy, path, kidx); 2339 2340 if (RTW8852C_DPK_RXSRAM_DBG) 2341 _dpk_read_rxsram(rtwdev); 2342 2343 if (is_fail) { 2344 goout = 1; 2345 break; 2346 } 2347 2348 dgain = _dpk_dgain_read(rtwdev); 2349 2350 if (dgain > 0x5fc || dgain < 0x556) { 2351 _dpk_one_shot(rtwdev, phy, path, D_SYNC); 2352 dgain = _dpk_dgain_read(rtwdev); 2353 } 2354 2355 if (agc_cnt == 0) { 2356 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) 2357 _dpk_bypass_rxiqc(rtwdev, path); 2358 else 2359 _dpk_lbk_rxiqk(rtwdev, phy, path); 2360 } 2361 step = DPK_AGC_STEP_GAIN_LOSS_IDX; 2362 break; 2363 2364 case DPK_AGC_STEP_GAIN_LOSS_IDX: 2365 tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx); 2366 pas = _dpk_pas_read(rtwdev, true); 2367 2368 if (pas == DPK_PAS_LT && tmp_gl_idx > 0) 2369 step = DPK_AGC_STEP_GL_LT_CRITERION; 2370 else if (pas == DPK_PAS_GT && tmp_gl_idx == 0) 2371 step = DPK_AGC_STEP_GL_GT_CRITERION; 2372 else if (tmp_gl_idx >= 7) 2373 step = DPK_AGC_STEP_GL_GT_CRITERION; 2374 else if (tmp_gl_idx == 0) 2375 step = DPK_AGC_STEP_GL_LT_CRITERION; 2376 else 2377 step = DPK_AGC_STEP_SET_TX_GAIN; 2378 break; 2379 2380 case DPK_AGC_STEP_GL_GT_CRITERION: 2381 if (tmp_dbm <= 7) { 2382 goout = 1; 2383 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Txagc@lower bound!!\n"); 2384 } else { 2385 tmp_dbm = max_t(u8, tmp_dbm - 3, 7); 2386 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true); 2387 } 2388 step = DPK_AGC_STEP_SYNC_DGAIN; 2389 agc_cnt++; 2390 break; 2391 2392 case DPK_AGC_STEP_GL_LT_CRITERION: 2393 if (tmp_dbm >= 24) { 2394 goout = 1; 2395 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Txagc@upper bound!!\n"); 2396 } else { 2397 tmp_dbm = min_t(u8, tmp_dbm + 2, 24); 2398 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true); 2399 } 2400 step = DPK_AGC_STEP_SYNC_DGAIN; 2401 agc_cnt++; 2402 break; 2403 2404 case DPK_AGC_STEP_SET_TX_GAIN: 2405 _dpk_kip_control_rfc(rtwdev, path, false); 2406 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); 2407 if (tmp_rxbb + tmp_gl_idx > 0x1f) 2408 tmp_rxbb = 0x1f; 2409 else 2410 tmp_rxbb = tmp_rxbb + tmp_gl_idx; 2411 2412 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb); 2413 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Adjust RXBB (%+d) = 0x%x\n", 2414 tmp_gl_idx, tmp_rxbb); 2415 _dpk_kip_control_rfc(rtwdev, path, true); 2416 goout = 1; 2417 break; 2418 default: 2419 goout = 1; 2420 break; 2421 } 2422 } while (!goout && agc_cnt < 6 && --limit > 0); 2423 2424 if (limit <= 0) 2425 rtw89_warn(rtwdev, "[DPK] exceed loop limit\n"); 2426 2427 return is_fail; 2428 } 2429 2430 static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order) 2431 { 2432 static const struct rtw89_rfk_tbl *order_tbls[] = { 2433 &rtw8852c_dpk_mdpd_order0_defs_tbl, 2434 &rtw8852c_dpk_mdpd_order1_defs_tbl, 2435 &rtw8852c_dpk_mdpd_order2_defs_tbl, 2436 &rtw8852c_dpk_mdpd_order3_defs_tbl, 2437 }; 2438 2439 if (order >= ARRAY_SIZE(order_tbls)) { 2440 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Wrong MDPD order!!(0x%x)\n", order); 2441 return; 2442 } 2443 2444 rtw89_rfk_parser(rtwdev, order_tbls[order]); 2445 2446 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Set %s for IDL\n", 2447 order == 0x0 ? "(5,3,1)" : 2448 order == 0x1 ? "(5,3,0)" : 2449 order == 0x2 ? "(5,0,0)" : "(7,3,1)"); 2450 } 2451 2452 static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2453 enum rtw89_rf_path path, u8 kidx) 2454 { 2455 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2456 u8 cnt; 2457 u8 ov_flag; 2458 u32 dpk_sync; 2459 2460 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_MA, 0x1); 2461 2462 if (rtw89_phy_read32_mask(rtwdev, R_DPK_MPA, B_DPK_MPA_T2) == 0x1) 2463 _dpk_set_mdpd_para(rtwdev, 0x2); 2464 else if (rtw89_phy_read32_mask(rtwdev, R_DPK_MPA, B_DPK_MPA_T1) == 0x1) 2465 _dpk_set_mdpd_para(rtwdev, 0x1); 2466 else if (rtw89_phy_read32_mask(rtwdev, R_DPK_MPA, B_DPK_MPA_T0) == 0x1) 2467 _dpk_set_mdpd_para(rtwdev, 0x0); 2468 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_5 || 2469 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_10 || 2470 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_20) 2471 _dpk_set_mdpd_para(rtwdev, 0x2); 2472 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 || 2473 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) 2474 _dpk_set_mdpd_para(rtwdev, 0x1); 2475 else 2476 _dpk_set_mdpd_para(rtwdev, 0x0); 2477 2478 rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL, 0x0); 2479 fsleep(1000); 2480 2481 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL); 2482 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0); 2483 dpk_sync = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); 2484 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] dpk_sync = 0x%x\n", dpk_sync); 2485 2486 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0xf); 2487 ov_flag = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_SYNERR); 2488 for (cnt = 0; cnt < 5 && ov_flag == 0x1; cnt++) { 2489 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] ReK due to MDPK ov!!!\n"); 2490 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL); 2491 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0xf); 2492 ov_flag = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_SYNERR); 2493 } 2494 2495 if (ov_flag) { 2496 _dpk_set_mdpd_para(rtwdev, 0x2); 2497 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL); 2498 } 2499 } 2500 2501 static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2502 enum rtw89_rf_path path) 2503 { 2504 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2505 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2506 bool is_reload = false; 2507 u8 idx, cur_band, cur_ch; 2508 2509 cur_band = chan->band_type; 2510 cur_ch = chan->channel; 2511 2512 for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) { 2513 if (cur_band != dpk->bp[path][idx].band || 2514 cur_ch != dpk->bp[path][idx].ch) 2515 continue; 2516 2517 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), 2518 B_COEF_SEL_MDPD, idx); 2519 dpk->cur_idx[path] = idx; 2520 is_reload = true; 2521 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2522 "[DPK] reload S%d[%d] success\n", path, idx); 2523 } 2524 2525 return is_reload; 2526 } 2527 2528 static void _dpk_kip_pwr_clk_onoff(struct rtw89_dev *rtwdev, bool turn_on) 2529 { 2530 rtw89_rfk_parser(rtwdev, turn_on ? &rtw8852c_dpk_kip_pwr_clk_on_defs_tbl : 2531 &rtw8852c_dpk_kip_pwr_clk_off_defs_tbl); 2532 } 2533 2534 static void _dpk_kip_preset_8852c(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2535 enum rtw89_rf_path path, u8 kidx) 2536 { 2537 rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD, 2538 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); 2539 2540 if (rtwdev->hal.cv == CHIP_CAV) 2541 rtw89_phy_write32_mask(rtwdev, 2542 R_DPD_CH0A + (path << 8) + (kidx << 2), 2543 B_DPD_SEL, 0x01); 2544 else 2545 rtw89_phy_write32_mask(rtwdev, 2546 R_DPD_CH0A + (path << 8) + (kidx << 2), 2547 B_DPD_SEL, 0x0c); 2548 2549 _dpk_kip_control_rfc(rtwdev, path, true); 2550 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx); 2551 2552 _dpk_one_shot(rtwdev, phy, path, D_KIP_PRESET); 2553 } 2554 2555 static void _dpk_para_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) 2556 { 2557 #define _DPK_PARA_TXAGC GENMASK(15, 10) 2558 #define _DPK_PARA_THER GENMASK(31, 26) 2559 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2560 u32 para; 2561 2562 para = rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8), 2563 MASKDWORD); 2564 2565 dpk->bp[path][kidx].txagc_dpk = FIELD_GET(_DPK_PARA_TXAGC, para); 2566 dpk->bp[path][kidx].ther_dpk = FIELD_GET(_DPK_PARA_THER, para); 2567 2568 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal/ txagc_RF (K%d) = 0x%x/ 0x%x\n", 2569 dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk, dpk->bp[path][kidx].txagc_dpk); 2570 } 2571 2572 static void _dpk_gain_normalize_8852c(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2573 enum rtw89_rf_path path, u8 kidx, bool is_execute) 2574 { 2575 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2576 2577 if (is_execute) { 2578 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8), B_DPK_GN_AG, 0x200); 2579 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8), B_DPK_GN_EN, 0x3); 2580 2581 _dpk_one_shot(rtwdev, phy, path, D_GAIN_NORM); 2582 } else { 2583 rtw89_phy_write32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8), 2584 0x0000007F, 0x5b); 2585 } 2586 dpk->bp[path][kidx].gs = 2587 rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8), 2588 0x0000007F); 2589 } 2590 2591 static u8 _dpk_order_convert(struct rtw89_dev *rtwdev) 2592 { 2593 u32 val32 = rtw89_phy_read32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP); 2594 u8 val; 2595 2596 switch (val32) { 2597 case 0: 2598 val = 0x6; 2599 break; 2600 case 1: 2601 val = 0x2; 2602 break; 2603 case 2: 2604 val = 0x0; 2605 break; 2606 case 3: 2607 val = 0x7; 2608 break; 2609 default: 2610 val = 0xff; 2611 break; 2612 } 2613 2614 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val); 2615 2616 return val; 2617 } 2618 2619 static void _dpk_on(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2620 enum rtw89_rf_path path, u8 kidx) 2621 { 2622 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2623 2624 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); 2625 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0); 2626 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), 2627 B_DPD_ORDER, _dpk_order_convert(rtwdev)); 2628 2629 dpk->bp[path][kidx].mdpd_en = BIT(dpk->cur_k_set); 2630 dpk->bp[path][kidx].path_ok = true; 2631 2632 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] path_ok = 0x%x\n", 2633 path, kidx, dpk->bp[path][kidx].mdpd_en); 2634 2635 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), 2636 B_DPD_MEN, dpk->bp[path][kidx].mdpd_en); 2637 2638 _dpk_gain_normalize_8852c(rtwdev, phy, path, kidx, false); 2639 } 2640 2641 static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2642 enum rtw89_rf_path path, u8 gain) 2643 { 2644 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2645 u8 kidx = dpk->cur_idx[path]; 2646 u8 init_xdbm = 15; 2647 bool is_fail; 2648 2649 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2650 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx); 2651 _dpk_kip_control_rfc(rtwdev, path, false); 2652 _rf_direct_cntrl(rtwdev, path, false); 2653 rtw89_write_rf(rtwdev, path, RR_BBDC, RFREG_MASK, 0x03ffd); 2654 _dpk_rf_setting(rtwdev, gain, path, kidx); 2655 _set_rx_dck(rtwdev, phy, path, false); 2656 _dpk_kip_pwr_clk_onoff(rtwdev, true); 2657 _dpk_kip_preset_8852c(rtwdev, phy, path, kidx); 2658 _dpk_txpwr_bb_force(rtwdev, path, true); 2659 _dpk_kip_set_txagc(rtwdev, phy, path, init_xdbm, true); 2660 _dpk_tpg_sel(rtwdev, path, kidx); 2661 2662 is_fail = _dpk_agc(rtwdev, phy, path, kidx, init_xdbm, false); 2663 if (is_fail) 2664 goto _error; 2665 2666 _dpk_idl_mpa(rtwdev, phy, path, kidx); 2667 _dpk_para_query(rtwdev, path, kidx); 2668 _dpk_on(rtwdev, phy, path, kidx); 2669 2670 _error: 2671 _dpk_kip_control_rfc(rtwdev, path, false); 2672 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX); 2673 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d]_K%d %s\n", path, kidx, 2674 dpk->cur_k_set, is_fail ? "need Check" : "is Success"); 2675 2676 return is_fail; 2677 } 2678 2679 static void _dpk_init(struct rtw89_dev *rtwdev, u8 path) 2680 { 2681 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2682 u8 kidx = dpk->cur_idx[path]; 2683 2684 dpk->bp[path][kidx].path_ok = false; 2685 } 2686 2687 static void _dpk_drf_direct_cntrl(struct rtw89_dev *rtwdev, u8 path, bool is_bybb) 2688 { 2689 if (is_bybb) 2690 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); 2691 else 2692 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); 2693 } 2694 2695 static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force, 2696 enum rtw89_phy_idx phy, u8 kpath) 2697 { 2698 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2699 static const u32 kip_reg[] = {0x813c, 0x8124, 0x8120, 0xc0c4, 0xc0e8, 0xc0d4, 0xc0d8}; 2700 u32 backup_rf_val[RTW8852C_DPK_RF_PATH][BACKUP_RF_REGS_NR]; 2701 u32 kip_bkup[RTW8852C_DPK_RF_PATH][RTW8852C_DPK_KIP_REG_NUM] = {}; 2702 u8 path; 2703 bool is_fail = true, reloaded[RTW8852C_DPK_RF_PATH] = {false}; 2704 2705 static_assert(ARRAY_SIZE(kip_reg) == RTW8852C_DPK_KIP_REG_NUM); 2706 2707 if (dpk->is_dpk_reload_en) { 2708 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) { 2709 if (!(kpath & BIT(path))) 2710 continue; 2711 2712 reloaded[path] = _dpk_reload_check(rtwdev, phy, path); 2713 if (!reloaded[path] && dpk->bp[path][0].ch != 0) 2714 dpk->cur_idx[path] = !dpk->cur_idx[path]; 2715 else 2716 _dpk_onoff(rtwdev, path, false); 2717 } 2718 } else { 2719 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) 2720 dpk->cur_idx[path] = 0; 2721 } 2722 2723 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) { 2724 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2725 "[DPK] ========= S%d[%d] DPK Init =========\n", 2726 path, dpk->cur_idx[path]); 2727 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); 2728 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path); 2729 _dpk_information(rtwdev, phy, path); 2730 _dpk_init(rtwdev, path); 2731 if (rtwdev->is_tssi_mode[path]) 2732 _dpk_tssi_pause(rtwdev, path, true); 2733 } 2734 2735 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) { 2736 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2737 "[DPK] ========= S%d[%d] DPK Start =========\n", 2738 path, dpk->cur_idx[path]); 2739 rtw8852c_disable_rxagc(rtwdev, path, 0x0); 2740 _dpk_drf_direct_cntrl(rtwdev, path, false); 2741 _dpk_bb_afe_setting(rtwdev, phy, path, kpath); 2742 is_fail = _dpk_main(rtwdev, phy, path, 1); 2743 _dpk_onoff(rtwdev, path, is_fail); 2744 } 2745 2746 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) { 2747 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2748 "[DPK] ========= S%d[%d] DPK Restore =========\n", 2749 path, dpk->cur_idx[path]); 2750 _dpk_kip_restore(rtwdev, phy, path); 2751 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); 2752 _rfk_restore_rf_reg(rtwdev, backup_rf_val[path], path); 2753 _dpk_bb_afe_restore(rtwdev, path); 2754 rtw8852c_disable_rxagc(rtwdev, path, 0x1); 2755 if (rtwdev->is_tssi_mode[path]) 2756 _dpk_tssi_pause(rtwdev, path, false); 2757 } 2758 2759 _dpk_kip_pwr_clk_onoff(rtwdev, false); 2760 } 2761 2762 static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) 2763 { 2764 struct rtw89_fem_info *fem = &rtwdev->fem; 2765 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2766 u8 band = chan->band_type; 2767 2768 if (rtwdev->hal.cv == CHIP_CAV && band != RTW89_BAND_2G) { 2769 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Skip DPK due to CAV & not 2G!!\n"); 2770 return true; 2771 } else if (fem->epa_2g && band == RTW89_BAND_2G) { 2772 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Skip DPK due to 2G_ext_PA exist!!\n"); 2773 return true; 2774 } else if (fem->epa_5g && band == RTW89_BAND_5G) { 2775 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Skip DPK due to 5G_ext_PA exist!!\n"); 2776 return true; 2777 } else if (fem->epa_6g && band == RTW89_BAND_6G) { 2778 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Skip DPK due to 6G_ext_PA exist!!\n"); 2779 return true; 2780 } 2781 2782 return false; 2783 } 2784 2785 static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) 2786 { 2787 u8 path, kpath; 2788 2789 kpath = _kpath(rtwdev, phy); 2790 2791 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) { 2792 if (kpath & BIT(path)) 2793 _dpk_onoff(rtwdev, path, true); 2794 } 2795 } 2796 2797 static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force) 2798 { 2799 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2800 "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n", 2801 RTW8852C_DPK_VER, rtwdev->hal.cv, 2802 RTW8852C_RF_REL_VERSION); 2803 2804 if (_dpk_bypass_check(rtwdev, phy)) 2805 _dpk_force_bypass(rtwdev, phy); 2806 else 2807 _dpk_cal_select(rtwdev, force, phy, _kpath(rtwdev, phy)); 2808 2809 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_DCKC, RR_DCKC_CHK) == 0x1) 2810 rtw8852c_rx_dck(rtwdev, phy, false); 2811 } 2812 2813 static void _dpk_onoff(struct rtw89_dev *rtwdev, 2814 enum rtw89_rf_path path, bool off) 2815 { 2816 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2817 u8 val, kidx = dpk->cur_idx[path]; 2818 2819 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok ? 2820 dpk->bp[path][kidx].mdpd_en : 0; 2821 2822 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), 2823 B_DPD_MEN, val); 2824 2825 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, 2826 kidx, dpk->is_dpk_enable && !off ? "enable" : "disable"); 2827 } 2828 2829 static void _dpk_track(struct rtw89_dev *rtwdev) 2830 { 2831 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 2832 u8 path, kidx; 2833 u8 txagc_rf = 0; 2834 s8 txagc_bb = 0, txagc_bb_tp = 0, txagc_ofst = 0; 2835 u8 cur_ther; 2836 s8 delta_ther = 0; 2837 s16 pwsf_tssi_ofst; 2838 2839 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) { 2840 kidx = dpk->cur_idx[path]; 2841 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2842 "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n", 2843 path, kidx, dpk->bp[path][kidx].ch); 2844 2845 txagc_rf = 2846 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), 0x0000003f); 2847 txagc_bb = 2848 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), MASKBYTE2); 2849 txagc_bb_tp = 2850 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BTP + (path << 13), B_TXAGC_BTP); 2851 2852 /* report from KIP */ 2853 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xf); 2854 cur_ther = 2855 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_TH); 2856 txagc_ofst = 2857 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_OF); 2858 pwsf_tssi_ofst = 2859 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_TSSI); 2860 pwsf_tssi_ofst = sign_extend32(pwsf_tssi_ofst, 12); 2861 2862 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); 2863 2864 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2865 "[DPK_TRK] thermal now = %d\n", cur_ther); 2866 2867 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) 2868 delta_ther = dpk->bp[path][kidx].ther_dpk - cur_ther; 2869 2870 delta_ther = delta_ther * 1 / 2; 2871 2872 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2873 "[DPK_TRK] extra delta_ther = %d (0x%x / 0x%x@k)\n", 2874 delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk); 2875 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2876 "[DPK_TRK] delta_txagc = %d (0x%x / 0x%x@k)\n", 2877 txagc_rf - dpk->bp[path][kidx].txagc_dpk, txagc_rf, 2878 dpk->bp[path][kidx].txagc_dpk); 2879 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2880 "[DPK_TRK] txagc_offset / pwsf_tssi_ofst = 0x%x / %+d\n", 2881 txagc_ofst, pwsf_tssi_ofst); 2882 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2883 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", 2884 txagc_bb_tp, txagc_bb); 2885 2886 if (rtw89_phy_read32_mask(rtwdev, R_DPK_WR, B_DPK_WR_ST) == 0x0 && 2887 txagc_rf != 0 && rtwdev->hal.cv == CHIP_CAV) { 2888 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2889 "[DPK_TRK] New pwsf = 0x%x\n", 0x78 - delta_ther); 2890 2891 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), 2892 0x07FC0000, 0x78 - delta_ther); 2893 } 2894 } 2895 } 2896 2897 static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2898 enum rtw89_rf_path path) 2899 { 2900 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2901 enum rtw89_band band = chan->band_type; 2902 2903 rtw89_rfk_parser(rtwdev, &rtw8852c_tssi_sys_defs_tbl); 2904 2905 if (path == RF_PATH_A) 2906 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, 2907 &rtw8852c_tssi_sys_defs_2g_a_tbl, 2908 &rtw8852c_tssi_sys_defs_5g_a_tbl); 2909 else 2910 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, 2911 &rtw8852c_tssi_sys_defs_2g_b_tbl, 2912 &rtw8852c_tssi_sys_defs_5g_b_tbl); 2913 } 2914 2915 static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2916 enum rtw89_rf_path path) 2917 { 2918 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 2919 &rtw8852c_tssi_txpwr_ctrl_bb_defs_a_tbl, 2920 &rtw8852c_tssi_txpwr_ctrl_bb_defs_b_tbl); 2921 } 2922 2923 static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev, 2924 enum rtw89_phy_idx phy, 2925 enum rtw89_rf_path path) 2926 { 2927 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 2928 &rtw8852c_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl, 2929 &rtw8852c_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl); 2930 } 2931 2932 static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2933 enum rtw89_rf_path path) 2934 { 2935 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2936 enum rtw89_band band = chan->band_type; 2937 2938 if (path == RF_PATH_A) { 2939 rtw89_rfk_parser(rtwdev, &rtw8852c_tssi_dck_defs_a_tbl); 2940 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, 2941 &rtw8852c_tssi_dck_defs_2g_a_tbl, 2942 &rtw8852c_tssi_dck_defs_5g_a_tbl); 2943 } else { 2944 rtw89_rfk_parser(rtwdev, &rtw8852c_tssi_dck_defs_b_tbl); 2945 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, 2946 &rtw8852c_tssi_dck_defs_2g_b_tbl, 2947 &rtw8852c_tssi_dck_defs_5g_b_tbl); 2948 } 2949 } 2950 2951 static void _tssi_set_bbgain_split(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2952 enum rtw89_rf_path path) 2953 { 2954 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 2955 &rtw8852c_tssi_set_bbgain_split_a_tbl, 2956 &rtw8852c_tssi_set_bbgain_split_b_tbl); 2957 } 2958 2959 static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 2960 enum rtw89_rf_path path) 2961 { 2962 #define RTW8852C_TSSI_GET_VAL(ptr, idx) \ 2963 ({ \ 2964 s8 *__ptr = (ptr); \ 2965 u8 __idx = (idx), __i, __v; \ 2966 u32 __val = 0; \ 2967 for (__i = 0; __i < 4; __i++) { \ 2968 __v = (__ptr[__idx + __i]); \ 2969 __val |= (__v << (8 * __i)); \ 2970 } \ 2971 __val; \ 2972 }) 2973 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 2974 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2975 u8 ch = chan->channel; 2976 u8 subband = chan->subband_type; 2977 const s8 *thm_up_a = NULL; 2978 const s8 *thm_down_a = NULL; 2979 const s8 *thm_up_b = NULL; 2980 const s8 *thm_down_b = NULL; 2981 u8 thermal = 0xff; 2982 s8 thm_ofst[64] = {0}; 2983 u32 tmp = 0; 2984 u8 i, j; 2985 2986 switch (subband) { 2987 default: 2988 case RTW89_CH_2G: 2989 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_2ga_p; 2990 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_2ga_n; 2991 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_2gb_p; 2992 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_2gb_n; 2993 break; 2994 case RTW89_CH_5G_BAND_1: 2995 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_5ga_p[0]; 2996 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_5ga_n[0]; 2997 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_5gb_p[0]; 2998 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_5gb_n[0]; 2999 break; 3000 case RTW89_CH_5G_BAND_3: 3001 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_5ga_p[1]; 3002 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_5ga_n[1]; 3003 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_5gb_p[1]; 3004 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_5gb_n[1]; 3005 break; 3006 case RTW89_CH_5G_BAND_4: 3007 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_5ga_p[2]; 3008 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_5ga_n[2]; 3009 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_5gb_p[2]; 3010 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_5gb_n[2]; 3011 break; 3012 case RTW89_CH_6G_BAND_IDX0: 3013 case RTW89_CH_6G_BAND_IDX1: 3014 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[0]; 3015 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[0]; 3016 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[0]; 3017 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[0]; 3018 break; 3019 case RTW89_CH_6G_BAND_IDX2: 3020 case RTW89_CH_6G_BAND_IDX3: 3021 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[1]; 3022 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[1]; 3023 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[1]; 3024 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[1]; 3025 break; 3026 case RTW89_CH_6G_BAND_IDX4: 3027 case RTW89_CH_6G_BAND_IDX5: 3028 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[2]; 3029 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[2]; 3030 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[2]; 3031 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[2]; 3032 break; 3033 case RTW89_CH_6G_BAND_IDX6: 3034 case RTW89_CH_6G_BAND_IDX7: 3035 thm_up_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[3]; 3036 thm_down_a = rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[3]; 3037 thm_up_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[3]; 3038 thm_down_b = rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[3]; 3039 break; 3040 } 3041 3042 if (path == RF_PATH_A) { 3043 thermal = tssi_info->thermal[RF_PATH_A]; 3044 3045 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3046 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal); 3047 3048 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0); 3049 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1); 3050 3051 if (thermal == 0xff) { 3052 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32); 3053 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32); 3054 3055 for (i = 0; i < 64; i += 4) { 3056 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0); 3057 3058 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3059 "[TSSI] write 0x%x val=0x%08x\n", 3060 0x5c00 + i, 0x0); 3061 } 3062 3063 } else { 3064 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal); 3065 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 3066 thermal); 3067 3068 i = 0; 3069 for (j = 0; j < 32; j++) 3070 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3071 -thm_down_a[i++] : 3072 -thm_down_a[DELTA_SWINGIDX_SIZE - 1]; 3073 3074 i = 1; 3075 for (j = 63; j >= 32; j--) 3076 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3077 thm_up_a[i++] : 3078 thm_up_a[DELTA_SWINGIDX_SIZE - 1]; 3079 3080 for (i = 0; i < 64; i += 4) { 3081 tmp = RTW8852C_TSSI_GET_VAL(thm_ofst, i); 3082 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp); 3083 3084 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3085 "[TSSI] write 0x%x val=0x%08x\n", 3086 0x5c00 + i, tmp); 3087 } 3088 } 3089 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1); 3090 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0); 3091 3092 } else { 3093 thermal = tssi_info->thermal[RF_PATH_B]; 3094 3095 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3096 "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal); 3097 3098 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0); 3099 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1); 3100 3101 if (thermal == 0xff) { 3102 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32); 3103 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32); 3104 3105 for (i = 0; i < 64; i += 4) { 3106 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0); 3107 3108 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3109 "[TSSI] write 0x%x val=0x%08x\n", 3110 0x7c00 + i, 0x0); 3111 } 3112 3113 } else { 3114 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal); 3115 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 3116 thermal); 3117 3118 i = 0; 3119 for (j = 0; j < 32; j++) 3120 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3121 -thm_down_b[i++] : 3122 -thm_down_b[DELTA_SWINGIDX_SIZE - 1]; 3123 3124 i = 1; 3125 for (j = 63; j >= 32; j--) 3126 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3127 thm_up_b[i++] : 3128 thm_up_b[DELTA_SWINGIDX_SIZE - 1]; 3129 3130 for (i = 0; i < 64; i += 4) { 3131 tmp = RTW8852C_TSSI_GET_VAL(thm_ofst, i); 3132 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp); 3133 3134 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3135 "[TSSI] write 0x%x val=0x%08x\n", 3136 0x7c00 + i, tmp); 3137 } 3138 } 3139 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1); 3140 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0); 3141 } 3142 #undef RTW8852C_TSSI_GET_VAL 3143 } 3144 3145 static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3146 enum rtw89_rf_path path) 3147 { 3148 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3149 enum rtw89_band band = chan->band_type; 3150 3151 if (path == RF_PATH_A) { 3152 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, 3153 &rtw8852c_tssi_slope_cal_org_defs_2g_a_tbl, 3154 &rtw8852c_tssi_slope_cal_org_defs_5g_a_tbl); 3155 } else { 3156 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, 3157 &rtw8852c_tssi_slope_cal_org_defs_2g_b_tbl, 3158 &rtw8852c_tssi_slope_cal_org_defs_5g_b_tbl); 3159 } 3160 } 3161 3162 static void _tssi_set_aligk_default(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3163 enum rtw89_rf_path path) 3164 { 3165 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3166 enum rtw89_band band = chan->band_type; 3167 const struct rtw89_rfk_tbl *tbl; 3168 3169 if (path == RF_PATH_A) { 3170 if (band == RTW89_BAND_2G) 3171 tbl = &rtw8852c_tssi_set_aligk_default_defs_2g_a_tbl; 3172 else if (band == RTW89_BAND_6G) 3173 tbl = &rtw8852c_tssi_set_aligk_default_defs_6g_a_tbl; 3174 else 3175 tbl = &rtw8852c_tssi_set_aligk_default_defs_5g_a_tbl; 3176 } else { 3177 if (band == RTW89_BAND_2G) 3178 tbl = &rtw8852c_tssi_set_aligk_default_defs_2g_b_tbl; 3179 else if (band == RTW89_BAND_6G) 3180 tbl = &rtw8852c_tssi_set_aligk_default_defs_6g_b_tbl; 3181 else 3182 tbl = &rtw8852c_tssi_set_aligk_default_defs_5g_b_tbl; 3183 } 3184 3185 rtw89_rfk_parser(rtwdev, tbl); 3186 } 3187 3188 static void _tssi_set_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3189 enum rtw89_rf_path path) 3190 { 3191 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 3192 &rtw8852c_tssi_slope_defs_a_tbl, 3193 &rtw8852c_tssi_slope_defs_b_tbl); 3194 } 3195 3196 static void _tssi_run_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3197 enum rtw89_rf_path path) 3198 { 3199 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 3200 &rtw8852c_tssi_run_slope_defs_a_tbl, 3201 &rtw8852c_tssi_run_slope_defs_b_tbl); 3202 } 3203 3204 static void _tssi_set_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3205 enum rtw89_rf_path path) 3206 { 3207 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 3208 &rtw8852c_tssi_track_defs_a_tbl, 3209 &rtw8852c_tssi_track_defs_b_tbl); 3210 } 3211 3212 static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev, 3213 enum rtw89_phy_idx phy, 3214 enum rtw89_rf_path path) 3215 { 3216 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, 3217 &rtw8852c_tssi_txagc_ofst_mv_avg_defs_a_tbl, 3218 &rtw8852c_tssi_txagc_ofst_mv_avg_defs_b_tbl); 3219 } 3220 3221 static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) 3222 { 3223 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3224 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C; 3225 3226 if (rtwdev->dbcc_en) { 3227 if (phy == RTW89_PHY_0) { 3228 path = RF_PATH_A; 3229 path_max = RF_PATH_B; 3230 } else if (phy == RTW89_PHY_1) { 3231 path = RF_PATH_B; 3232 path_max = RF_PATH_NUM_8852C; 3233 } 3234 } 3235 3236 for (i = path; i < path_max; i++) { 3237 _tssi_set_track(rtwdev, phy, i); 3238 _tssi_set_txagc_offset_mv_avg(rtwdev, phy, i); 3239 3240 rtw89_rfk_parser_by_cond(rtwdev, i == RF_PATH_A, 3241 &rtw8852c_tssi_enable_defs_a_tbl, 3242 &rtw8852c_tssi_enable_defs_b_tbl); 3243 3244 tssi_info->base_thermal[i] = 3245 ewma_thermal_read(&rtwdev->phystat.avg_thermal[i]); 3246 rtwdev->is_tssi_mode[i] = true; 3247 } 3248 } 3249 3250 static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) 3251 { 3252 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C; 3253 3254 if (rtwdev->dbcc_en) { 3255 if (phy == RTW89_PHY_0) { 3256 path = RF_PATH_A; 3257 path_max = RF_PATH_B; 3258 } else if (phy == RTW89_PHY_1) { 3259 path = RF_PATH_B; 3260 path_max = RF_PATH_NUM_8852C; 3261 } 3262 } 3263 3264 for (i = path; i < path_max; i++) { 3265 if (i == RF_PATH_A) { 3266 rtw89_rfk_parser(rtwdev, &rtw8852c_tssi_disable_defs_a_tbl); 3267 rtwdev->is_tssi_mode[RF_PATH_A] = false; 3268 } else if (i == RF_PATH_B) { 3269 rtw89_rfk_parser(rtwdev, &rtw8852c_tssi_disable_defs_b_tbl); 3270 rtwdev->is_tssi_mode[RF_PATH_B] = false; 3271 } 3272 } 3273 } 3274 3275 static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch) 3276 { 3277 switch (ch) { 3278 case 1 ... 2: 3279 return 0; 3280 case 3 ... 5: 3281 return 1; 3282 case 6 ... 8: 3283 return 2; 3284 case 9 ... 11: 3285 return 3; 3286 case 12 ... 13: 3287 return 4; 3288 case 14: 3289 return 5; 3290 } 3291 3292 return 0; 3293 } 3294 3295 #define TSSI_EXTRA_GROUP_BIT (BIT(31)) 3296 #define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx)) 3297 #define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT) 3298 #define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT) 3299 #define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) 3300 3301 static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch) 3302 { 3303 switch (ch) { 3304 case 1 ... 2: 3305 return 0; 3306 case 3 ... 5: 3307 return 1; 3308 case 6 ... 8: 3309 return 2; 3310 case 9 ... 11: 3311 return 3; 3312 case 12 ... 14: 3313 return 4; 3314 case 36 ... 40: 3315 return 5; 3316 case 41 ... 43: 3317 return TSSI_EXTRA_GROUP(5); 3318 case 44 ... 48: 3319 return 6; 3320 case 49 ... 51: 3321 return TSSI_EXTRA_GROUP(6); 3322 case 52 ... 56: 3323 return 7; 3324 case 57 ... 59: 3325 return TSSI_EXTRA_GROUP(7); 3326 case 60 ... 64: 3327 return 8; 3328 case 100 ... 104: 3329 return 9; 3330 case 105 ... 107: 3331 return TSSI_EXTRA_GROUP(9); 3332 case 108 ... 112: 3333 return 10; 3334 case 113 ... 115: 3335 return TSSI_EXTRA_GROUP(10); 3336 case 116 ... 120: 3337 return 11; 3338 case 121 ... 123: 3339 return TSSI_EXTRA_GROUP(11); 3340 case 124 ... 128: 3341 return 12; 3342 case 129 ... 131: 3343 return TSSI_EXTRA_GROUP(12); 3344 case 132 ... 136: 3345 return 13; 3346 case 137 ... 139: 3347 return TSSI_EXTRA_GROUP(13); 3348 case 140 ... 144: 3349 return 14; 3350 case 149 ... 153: 3351 return 15; 3352 case 154 ... 156: 3353 return TSSI_EXTRA_GROUP(15); 3354 case 157 ... 161: 3355 return 16; 3356 case 162 ... 164: 3357 return TSSI_EXTRA_GROUP(16); 3358 case 165 ... 169: 3359 return 17; 3360 case 170 ... 172: 3361 return TSSI_EXTRA_GROUP(17); 3362 case 173 ... 177: 3363 return 18; 3364 } 3365 3366 return 0; 3367 } 3368 3369 static u32 _tssi_get_6g_ofdm_group(struct rtw89_dev *rtwdev, u8 ch) 3370 { 3371 switch (ch) { 3372 case 1 ... 5: 3373 return 0; 3374 case 6 ... 8: 3375 return TSSI_EXTRA_GROUP(0); 3376 case 9 ... 13: 3377 return 1; 3378 case 14 ... 16: 3379 return TSSI_EXTRA_GROUP(1); 3380 case 17 ... 21: 3381 return 2; 3382 case 22 ... 24: 3383 return TSSI_EXTRA_GROUP(2); 3384 case 25 ... 29: 3385 return 3; 3386 case 33 ... 37: 3387 return 4; 3388 case 38 ... 40: 3389 return TSSI_EXTRA_GROUP(4); 3390 case 41 ... 45: 3391 return 5; 3392 case 46 ... 48: 3393 return TSSI_EXTRA_GROUP(5); 3394 case 49 ... 53: 3395 return 6; 3396 case 54 ... 56: 3397 return TSSI_EXTRA_GROUP(6); 3398 case 57 ... 61: 3399 return 7; 3400 case 65 ... 69: 3401 return 8; 3402 case 70 ... 72: 3403 return TSSI_EXTRA_GROUP(8); 3404 case 73 ... 77: 3405 return 9; 3406 case 78 ... 80: 3407 return TSSI_EXTRA_GROUP(9); 3408 case 81 ... 85: 3409 return 10; 3410 case 86 ... 88: 3411 return TSSI_EXTRA_GROUP(10); 3412 case 89 ... 93: 3413 return 11; 3414 case 97 ... 101: 3415 return 12; 3416 case 102 ... 104: 3417 return TSSI_EXTRA_GROUP(12); 3418 case 105 ... 109: 3419 return 13; 3420 case 110 ... 112: 3421 return TSSI_EXTRA_GROUP(13); 3422 case 113 ... 117: 3423 return 14; 3424 case 118 ... 120: 3425 return TSSI_EXTRA_GROUP(14); 3426 case 121 ... 125: 3427 return 15; 3428 case 129 ... 133: 3429 return 16; 3430 case 134 ... 136: 3431 return TSSI_EXTRA_GROUP(16); 3432 case 137 ... 141: 3433 return 17; 3434 case 142 ... 144: 3435 return TSSI_EXTRA_GROUP(17); 3436 case 145 ... 149: 3437 return 18; 3438 case 150 ... 152: 3439 return TSSI_EXTRA_GROUP(18); 3440 case 153 ... 157: 3441 return 19; 3442 case 161 ... 165: 3443 return 20; 3444 case 166 ... 168: 3445 return TSSI_EXTRA_GROUP(20); 3446 case 169 ... 173: 3447 return 21; 3448 case 174 ... 176: 3449 return TSSI_EXTRA_GROUP(21); 3450 case 177 ... 181: 3451 return 22; 3452 case 182 ... 184: 3453 return TSSI_EXTRA_GROUP(22); 3454 case 185 ... 189: 3455 return 23; 3456 case 193 ... 197: 3457 return 24; 3458 case 198 ... 200: 3459 return TSSI_EXTRA_GROUP(24); 3460 case 201 ... 205: 3461 return 25; 3462 case 206 ... 208: 3463 return TSSI_EXTRA_GROUP(25); 3464 case 209 ... 213: 3465 return 26; 3466 case 214 ... 216: 3467 return TSSI_EXTRA_GROUP(26); 3468 case 217 ... 221: 3469 return 27; 3470 case 225 ... 229: 3471 return 28; 3472 case 230 ... 232: 3473 return TSSI_EXTRA_GROUP(28); 3474 case 233 ... 237: 3475 return 29; 3476 case 238 ... 240: 3477 return TSSI_EXTRA_GROUP(29); 3478 case 241 ... 245: 3479 return 30; 3480 case 246 ... 248: 3481 return TSSI_EXTRA_GROUP(30); 3482 case 249 ... 253: 3483 return 31; 3484 } 3485 3486 return 0; 3487 } 3488 3489 static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch) 3490 { 3491 switch (ch) { 3492 case 1 ... 8: 3493 return 0; 3494 case 9 ... 14: 3495 return 1; 3496 case 36 ... 48: 3497 return 2; 3498 case 49 ... 51: 3499 return TSSI_EXTRA_GROUP(2); 3500 case 52 ... 64: 3501 return 3; 3502 case 100 ... 112: 3503 return 4; 3504 case 113 ... 115: 3505 return TSSI_EXTRA_GROUP(4); 3506 case 116 ... 128: 3507 return 5; 3508 case 132 ... 144: 3509 return 6; 3510 case 149 ... 177: 3511 return 7; 3512 } 3513 3514 return 0; 3515 } 3516 3517 static u32 _tssi_get_6g_trim_group(struct rtw89_dev *rtwdev, u8 ch) 3518 { 3519 switch (ch) { 3520 case 1 ... 13: 3521 return 0; 3522 case 14 ... 16: 3523 return TSSI_EXTRA_GROUP(0); 3524 case 17 ... 29: 3525 return 1; 3526 case 33 ... 45: 3527 return 2; 3528 case 46 ... 48: 3529 return TSSI_EXTRA_GROUP(2); 3530 case 49 ... 61: 3531 return 3; 3532 case 65 ... 77: 3533 return 4; 3534 case 78 ... 80: 3535 return TSSI_EXTRA_GROUP(4); 3536 case 81 ... 93: 3537 return 5; 3538 case 97 ... 109: 3539 return 6; 3540 case 110 ... 112: 3541 return TSSI_EXTRA_GROUP(6); 3542 case 113 ... 125: 3543 return 7; 3544 case 129 ... 141: 3545 return 8; 3546 case 142 ... 144: 3547 return TSSI_EXTRA_GROUP(8); 3548 case 145 ... 157: 3549 return 9; 3550 case 161 ... 173: 3551 return 10; 3552 case 174 ... 176: 3553 return TSSI_EXTRA_GROUP(10); 3554 case 177 ... 189: 3555 return 11; 3556 case 193 ... 205: 3557 return 12; 3558 case 206 ... 208: 3559 return TSSI_EXTRA_GROUP(12); 3560 case 209 ... 221: 3561 return 13; 3562 case 225 ... 237: 3563 return 14; 3564 case 238 ... 240: 3565 return TSSI_EXTRA_GROUP(14); 3566 case 241 ... 253: 3567 return 15; 3568 } 3569 3570 return 0; 3571 } 3572 3573 static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3574 enum rtw89_rf_path path) 3575 { 3576 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3577 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3578 enum rtw89_band band = chan->band_type; 3579 u8 ch = chan->channel; 3580 u32 gidx, gidx_1st, gidx_2nd; 3581 s8 de_1st; 3582 s8 de_2nd; 3583 s8 val; 3584 3585 if (band == RTW89_BAND_2G || band == RTW89_BAND_5G) { 3586 gidx = _tssi_get_ofdm_group(rtwdev, ch); 3587 3588 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3589 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3590 path, gidx); 3591 3592 if (IS_TSSI_EXTRA_GROUP(gidx)) { 3593 gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3594 gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3595 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; 3596 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; 3597 val = (de_1st + de_2nd) / 2; 3598 3599 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3600 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3601 path, val, de_1st, de_2nd); 3602 } else { 3603 val = tssi_info->tssi_mcs[path][gidx]; 3604 3605 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3606 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3607 } 3608 } else { 3609 gidx = _tssi_get_6g_ofdm_group(rtwdev, ch); 3610 3611 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3612 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3613 path, gidx); 3614 3615 if (IS_TSSI_EXTRA_GROUP(gidx)) { 3616 gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3617 gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3618 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st]; 3619 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd]; 3620 val = (de_1st + de_2nd) / 2; 3621 3622 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3623 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3624 path, val, de_1st, de_2nd); 3625 } else { 3626 val = tssi_info->tssi_6g_mcs[path][gidx]; 3627 3628 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3629 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3630 } 3631 } 3632 3633 return val; 3634 } 3635 3636 static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, 3637 enum rtw89_phy_idx phy, 3638 enum rtw89_rf_path path) 3639 { 3640 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3641 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3642 enum rtw89_band band = chan->band_type; 3643 u8 ch = chan->channel; 3644 u32 tgidx, tgidx_1st, tgidx_2nd; 3645 s8 tde_1st = 0; 3646 s8 tde_2nd = 0; 3647 s8 val; 3648 3649 if (band == RTW89_BAND_2G || band == RTW89_BAND_5G) { 3650 tgidx = _tssi_get_trim_group(rtwdev, ch); 3651 3652 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3653 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3654 path, tgidx); 3655 3656 if (IS_TSSI_EXTRA_GROUP(tgidx)) { 3657 tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3658 tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3659 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; 3660 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; 3661 val = (tde_1st + tde_2nd) / 2; 3662 3663 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3664 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3665 path, val, tde_1st, tde_2nd); 3666 } else { 3667 val = tssi_info->tssi_trim[path][tgidx]; 3668 3669 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3670 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3671 path, val); 3672 } 3673 } else { 3674 tgidx = _tssi_get_6g_trim_group(rtwdev, ch); 3675 3676 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3677 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3678 path, tgidx); 3679 3680 if (IS_TSSI_EXTRA_GROUP(tgidx)) { 3681 tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3682 tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3683 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st]; 3684 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd]; 3685 val = (tde_1st + tde_2nd) / 2; 3686 3687 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3688 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3689 path, val, tde_1st, tde_2nd); 3690 } else { 3691 val = tssi_info->tssi_trim_6g[path][tgidx]; 3692 3693 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3694 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3695 path, val); 3696 } 3697 } 3698 3699 return val; 3700 } 3701 3702 static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, 3703 enum rtw89_phy_idx phy) 3704 { 3705 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3706 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3707 u8 ch = chan->channel; 3708 u8 gidx; 3709 s8 ofdm_de; 3710 s8 trim_de; 3711 s32 val; 3712 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C; 3713 3714 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", 3715 phy, ch); 3716 3717 if (rtwdev->dbcc_en) { 3718 if (phy == RTW89_PHY_0) { 3719 path = RF_PATH_A; 3720 path_max = RF_PATH_B; 3721 } else if (phy == RTW89_PHY_1) { 3722 path = RF_PATH_B; 3723 path_max = RF_PATH_NUM_8852C; 3724 } 3725 } 3726 3727 for (i = path; i < path_max; i++) { 3728 gidx = _tssi_get_cck_group(rtwdev, ch); 3729 trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i); 3730 val = tssi_info->tssi_cck[i][gidx] + trim_de; 3731 3732 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3733 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", 3734 i, gidx, tssi_info->tssi_cck[i][gidx], trim_de); 3735 3736 rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_long[i], _TSSI_DE_MASK, val); 3737 rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_short[i], _TSSI_DE_MASK, val); 3738 3739 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3740 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", 3741 _tssi_de_cck_long[i], 3742 rtw89_phy_read32_mask(rtwdev, _tssi_de_cck_long[i], 3743 _TSSI_DE_MASK)); 3744 3745 ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i); 3746 trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i); 3747 val = ofdm_de + trim_de; 3748 3749 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3750 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", 3751 i, ofdm_de, trim_de); 3752 3753 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_20m[i], _TSSI_DE_MASK, val); 3754 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_40m[i], _TSSI_DE_MASK, val); 3755 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m[i], _TSSI_DE_MASK, val); 3756 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m_80m[i], _TSSI_DE_MASK, val); 3757 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_5m[i], _TSSI_DE_MASK, val); 3758 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_10m[i], _TSSI_DE_MASK, val); 3759 3760 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3761 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", 3762 _tssi_de_mcs_20m[i], 3763 rtw89_phy_read32_mask(rtwdev, _tssi_de_mcs_20m[i], 3764 _TSSI_DE_MASK)); 3765 } 3766 } 3767 3768 static void rtw8852c_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 3769 enum rtw89_rf_path path) 3770 { 3771 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 3772 static const u32 tssi_en[2] = {0x5820, 0x7820}; 3773 3774 if (en) { 3775 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 3776 rtw89_phy_write32_mask(rtwdev, tssi_en[path], BIT(31), 0x0); 3777 if (rtwdev->dbcc_en && path == RF_PATH_B) 3778 _tssi_set_efuse_to_de(rtwdev, RTW89_PHY_1); 3779 else 3780 _tssi_set_efuse_to_de(rtwdev, RTW89_PHY_0); 3781 } else { 3782 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 3783 rtw89_phy_write32_mask(rtwdev, tssi_en[path], BIT(31), 0x1); 3784 } 3785 } 3786 3787 void rtw8852c_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx) 3788 { 3789 if (!rtwdev->dbcc_en) { 3790 rtw8852c_tssi_cont_en(rtwdev, en, RF_PATH_A); 3791 rtw8852c_tssi_cont_en(rtwdev, en, RF_PATH_B); 3792 } else { 3793 if (phy_idx == RTW89_PHY_0) 3794 rtw8852c_tssi_cont_en(rtwdev, en, RF_PATH_A); 3795 else 3796 rtw8852c_tssi_cont_en(rtwdev, en, RF_PATH_B); 3797 } 3798 } 3799 3800 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 3801 enum rtw89_bandwidth bw, bool is_dav) 3802 { 3803 u32 rf_reg18; 3804 u32 reg_reg18_addr; 3805 3806 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===>%s\n", __func__); 3807 if (is_dav) 3808 reg_reg18_addr = RR_CFGCH; 3809 else 3810 reg_reg18_addr = RR_CFGCH_V1; 3811 3812 rf_reg18 = rtw89_read_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK); 3813 rf_reg18 &= ~RR_CFGCH_BW; 3814 3815 switch (bw) { 3816 case RTW89_CHANNEL_WIDTH_5: 3817 case RTW89_CHANNEL_WIDTH_10: 3818 case RTW89_CHANNEL_WIDTH_20: 3819 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_20M); 3820 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x3); 3821 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xf); 3822 break; 3823 case RTW89_CHANNEL_WIDTH_40: 3824 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_40M); 3825 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x3); 3826 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xf); 3827 break; 3828 case RTW89_CHANNEL_WIDTH_80: 3829 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_80M); 3830 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x2); 3831 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xd); 3832 break; 3833 case RTW89_CHANNEL_WIDTH_160: 3834 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_160M); 3835 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x1); 3836 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xb); 3837 break; 3838 default: 3839 break; 3840 } 3841 3842 rtw89_write_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK, rf_reg18); 3843 } 3844 3845 static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3846 enum rtw89_bandwidth bw) 3847 { 3848 bool is_dav; 3849 u8 kpath, path; 3850 u32 tmp = 0; 3851 3852 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===>%s\n", __func__); 3853 kpath = _kpath(rtwdev, phy); 3854 3855 for (path = 0; path < 2; path++) { 3856 if (!(kpath & BIT(path))) 3857 continue; 3858 3859 is_dav = true; 3860 _bw_setting(rtwdev, path, bw, is_dav); 3861 is_dav = false; 3862 _bw_setting(rtwdev, path, bw, is_dav); 3863 if (rtwdev->dbcc_en) 3864 continue; 3865 3866 if (path == RF_PATH_B && rtwdev->hal.cv == CHIP_CAV) { 3867 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0); 3868 tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK); 3869 rtw89_write_rf(rtwdev, RF_PATH_B, RR_APK, RR_APK_MOD, 0x3); 3870 rtw89_write_rf(rtwdev, RF_PATH_B, RR_CFGCH, RFREG_MASK, tmp); 3871 fsleep(100); 3872 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1); 3873 } 3874 } 3875 } 3876 3877 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 3878 u8 central_ch, enum rtw89_band band, bool is_dav) 3879 { 3880 u32 rf_reg18; 3881 u32 reg_reg18_addr; 3882 3883 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===>%s\n", __func__); 3884 if (is_dav) 3885 reg_reg18_addr = 0x18; 3886 else 3887 reg_reg18_addr = 0x10018; 3888 3889 rf_reg18 = rtw89_read_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK); 3890 rf_reg18 &= ~(RR_CFGCH_BAND1 | RR_CFGCH_BAND0 | RR_CFGCH_CH); 3891 rf_reg18 |= FIELD_PREP(RR_CFGCH_CH, central_ch); 3892 3893 switch (band) { 3894 case RTW89_BAND_2G: 3895 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_2G); 3896 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_2G); 3897 break; 3898 case RTW89_BAND_5G: 3899 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_5G); 3900 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_5G); 3901 break; 3902 case RTW89_BAND_6G: 3903 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_6G); 3904 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_6G); 3905 break; 3906 default: 3907 break; 3908 } 3909 rtw89_write_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK, rf_reg18); 3910 fsleep(100); 3911 } 3912 3913 static void _ctrl_ch(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3914 u8 central_ch, enum rtw89_band band) 3915 { 3916 u8 kpath, path; 3917 3918 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===>%s\n", __func__); 3919 if (band != RTW89_BAND_6G) { 3920 if ((central_ch > 14 && central_ch < 36) || 3921 (central_ch > 64 && central_ch < 100) || 3922 (central_ch > 144 && central_ch < 149) || central_ch > 177) 3923 return; 3924 } else { 3925 if (central_ch > 253 || central_ch == 2) 3926 return; 3927 } 3928 3929 kpath = _kpath(rtwdev, phy); 3930 3931 for (path = 0; path < 2; path++) { 3932 if (kpath & BIT(path)) { 3933 _ch_setting(rtwdev, path, central_ch, band, true); 3934 _ch_setting(rtwdev, path, central_ch, band, false); 3935 } 3936 } 3937 } 3938 3939 static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 3940 enum rtw89_bandwidth bw) 3941 { 3942 u8 kpath; 3943 u8 path; 3944 u32 val; 3945 3946 kpath = _kpath(rtwdev, phy); 3947 for (path = 0; path < 2; path++) { 3948 if (!(kpath & BIT(path))) 3949 continue; 3950 3951 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1); 3952 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0xa); 3953 switch (bw) { 3954 case RTW89_CHANNEL_WIDTH_20: 3955 val = 0x1b; 3956 break; 3957 case RTW89_CHANNEL_WIDTH_40: 3958 val = 0x13; 3959 break; 3960 case RTW89_CHANNEL_WIDTH_80: 3961 val = 0xb; 3962 break; 3963 case RTW89_CHANNEL_WIDTH_160: 3964 default: 3965 val = 0x3; 3966 break; 3967 } 3968 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, val); 3969 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0); 3970 } 3971 } 3972 3973 static void _lck_keep_thermal(struct rtw89_dev *rtwdev) 3974 { 3975 struct rtw89_lck_info *lck = &rtwdev->lck; 3976 int path; 3977 3978 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 3979 lck->thermal[path] = 3980 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); 3981 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 3982 "[LCK] path=%d thermal=0x%x", path, lck->thermal[path]); 3983 } 3984 } 3985 3986 static void _lck(struct rtw89_dev *rtwdev) 3987 { 3988 u32 tmp18[2]; 3989 int path = rtwdev->dbcc_en ? 2 : 1; 3990 int i; 3991 3992 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "[LCK] DO LCK\n"); 3993 3994 tmp18[0] = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK); 3995 tmp18[1] = rtw89_read_rf(rtwdev, RF_PATH_B, RR_CFGCH, RFREG_MASK); 3996 3997 for (i = 0; i < path; i++) { 3998 rtw89_write_rf(rtwdev, i, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1); 3999 rtw89_write_rf(rtwdev, i, RR_CFGCH, RFREG_MASK, tmp18[i]); 4000 rtw89_write_rf(rtwdev, i, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0); 4001 } 4002 4003 _lck_keep_thermal(rtwdev); 4004 } 4005 4006 #define RTW8852C_LCK_TH 8 4007 4008 void rtw8852c_lck_track(struct rtw89_dev *rtwdev) 4009 { 4010 struct rtw89_lck_info *lck = &rtwdev->lck; 4011 u8 cur_thermal; 4012 int delta; 4013 int path; 4014 4015 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 4016 cur_thermal = 4017 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); 4018 delta = abs((int)cur_thermal - lck->thermal[path]); 4019 4020 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 4021 "[LCK] path=%d current thermal=0x%x delta=0x%x\n", 4022 path, cur_thermal, delta); 4023 4024 if (delta >= RTW8852C_LCK_TH) { 4025 _lck(rtwdev); 4026 return; 4027 } 4028 } 4029 } 4030 4031 void rtw8852c_lck_init(struct rtw89_dev *rtwdev) 4032 { 4033 _lck_keep_thermal(rtwdev); 4034 } 4035 4036 static 4037 void rtw8852c_ctrl_bw_ch(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 4038 u8 central_ch, enum rtw89_band band, 4039 enum rtw89_bandwidth bw) 4040 { 4041 _ctrl_ch(rtwdev, phy, central_ch, band); 4042 _ctrl_bw(rtwdev, phy, bw); 4043 _rxbb_bw(rtwdev, phy, bw); 4044 } 4045 4046 void rtw8852c_set_channel_rf(struct rtw89_dev *rtwdev, 4047 const struct rtw89_chan *chan, 4048 enum rtw89_phy_idx phy_idx) 4049 { 4050 rtw8852c_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, 4051 chan->band_type, 4052 chan->band_width); 4053 } 4054 4055 void rtw8852c_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 4056 { 4057 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4058 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 4059 u8 idx = rfk_mcc->table_idx; 4060 int i; 4061 4062 for (i = 0; i < RTW89_IQK_CHS_NR; i++) { 4063 if (rfk_mcc->ch[idx] == 0) 4064 break; 4065 if (++idx >= RTW89_IQK_CHS_NR) 4066 idx = 0; 4067 } 4068 4069 rfk_mcc->table_idx = idx; 4070 rfk_mcc->ch[idx] = chan->channel; 4071 rfk_mcc->band[idx] = chan->band_type; 4072 } 4073 4074 void rtw8852c_rck(struct rtw89_dev *rtwdev) 4075 { 4076 u8 path; 4077 4078 for (path = 0; path < 2; path++) 4079 _rck(rtwdev, path); 4080 } 4081 4082 void rtw8852c_dack(struct rtw89_dev *rtwdev) 4083 { 4084 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0); 4085 4086 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START); 4087 _dac_cal(rtwdev, false); 4088 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP); 4089 } 4090 4091 void rtw8852c_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 4092 { 4093 u32 tx_en; 4094 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); 4095 4096 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START); 4097 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); 4098 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); 4099 4100 _iqk_init(rtwdev); 4101 _iqk(rtwdev, phy_idx, false); 4102 4103 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en); 4104 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP); 4105 } 4106 4107 #define RXDCK_VER_8852C 0xe 4108 4109 static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, 4110 bool is_afe, u8 retry_limit) 4111 { 4112 struct rtw89_rx_dck_info *rx_dck = &rtwdev->rx_dck; 4113 u8 path, kpath; 4114 u32 rf_reg5; 4115 bool is_fail; 4116 u8 rek_cnt; 4117 4118 kpath = _kpath(rtwdev, phy); 4119 rtw89_debug(rtwdev, RTW89_DBG_RFK, 4120 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n", 4121 RXDCK_VER_8852C, rtwdev->hal.cv); 4122 4123 for (path = 0; path < 2; path++) { 4124 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); 4125 if (!(kpath & BIT(path))) 4126 continue; 4127 4128 if (rtwdev->is_tssi_mode[path]) 4129 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), 4130 B_P0_TSSI_TRK_EN, 0x1); 4131 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); 4132 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); 4133 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_LO_SEL, rtwdev->dbcc_en); 4134 4135 for (rek_cnt = 0; rek_cnt < retry_limit; rek_cnt++) { 4136 _set_rx_dck(rtwdev, phy, path, is_afe); 4137 4138 /* To reduce IO of dck_rek_check(), the last try is seen 4139 * as failure always, and then do recovery procedure. 4140 */ 4141 if (rek_cnt == retry_limit - 1) { 4142 _rx_dck_recover(rtwdev, path); 4143 break; 4144 } 4145 4146 is_fail = _rx_dck_rek_check(rtwdev, path); 4147 if (!is_fail) 4148 break; 4149 } 4150 4151 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] rek_cnt[%d]=%d", 4152 path, rek_cnt); 4153 4154 rx_dck->thermal[path] = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); 4155 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); 4156 4157 if (rtwdev->is_tssi_mode[path]) 4158 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), 4159 B_P0_TSSI_TRK_EN, 0x0); 4160 } 4161 } 4162 4163 void rtw8852c_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool is_afe) 4164 { 4165 _rx_dck(rtwdev, phy, is_afe, 1); 4166 } 4167 4168 #define RTW8852C_RX_DCK_TH 12 4169 4170 void rtw8852c_rx_dck_track(struct rtw89_dev *rtwdev) 4171 { 4172 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4173 struct rtw89_rx_dck_info *rx_dck = &rtwdev->rx_dck; 4174 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4175 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); 4176 u8 dck_channel; 4177 u8 cur_thermal; 4178 u32 tx_en; 4179 int delta; 4180 int path; 4181 4182 if (chan->band_type == RTW89_BAND_2G) 4183 return; 4184 4185 if (rtwdev->scanning) 4186 return; 4187 4188 for (path = 0; path < RF_PATH_NUM_8852C; path++) { 4189 cur_thermal = 4190 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); 4191 delta = abs((int)cur_thermal - rx_dck->thermal[path]); 4192 4193 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 4194 "[RX_DCK] path=%d current thermal=0x%x delta=0x%x\n", 4195 path, cur_thermal, delta); 4196 4197 if (delta >= RTW8852C_RX_DCK_TH) 4198 goto trigger_rx_dck; 4199 } 4200 4201 return; 4202 4203 trigger_rx_dck: 4204 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START); 4205 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); 4206 4207 for (path = 0; path < RF_PATH_NUM_8852C; path++) { 4208 dck_channel = _rx_dck_channel_calc(rtwdev, chan); 4209 _ctrl_ch(rtwdev, RTW89_PHY_0, dck_channel, chan->band_type); 4210 } 4211 4212 _rx_dck(rtwdev, RTW89_PHY_0, false, 20); 4213 4214 for (path = 0; path < RF_PATH_NUM_8852C; path++) 4215 _ctrl_ch(rtwdev, RTW89_PHY_0, chan->channel, chan->band_type); 4216 4217 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en); 4218 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP); 4219 } 4220 4221 void rtw8852c_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 4222 { 4223 u32 tx_en; 4224 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); 4225 4226 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START); 4227 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); 4228 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); 4229 4230 rtwdev->dpk.is_dpk_enable = true; 4231 rtwdev->dpk.is_dpk_reload_en = false; 4232 _dpk(rtwdev, phy_idx, false); 4233 4234 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en); 4235 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP); 4236 } 4237 4238 void rtw8852c_dpk_track(struct rtw89_dev *rtwdev) 4239 { 4240 _dpk_track(rtwdev); 4241 } 4242 4243 void rtw8852c_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) 4244 { 4245 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C; 4246 4247 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", __func__, phy); 4248 4249 if (rtwdev->dbcc_en) { 4250 if (phy == RTW89_PHY_0) { 4251 path = RF_PATH_A; 4252 path_max = RF_PATH_B; 4253 } else if (phy == RTW89_PHY_1) { 4254 path = RF_PATH_B; 4255 path_max = RF_PATH_NUM_8852C; 4256 } 4257 } 4258 4259 _tssi_disable(rtwdev, phy); 4260 4261 for (i = path; i < path_max; i++) { 4262 _tssi_set_sys(rtwdev, phy, i); 4263 _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i); 4264 _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i); 4265 _tssi_set_dck(rtwdev, phy, i); 4266 _tssi_set_bbgain_split(rtwdev, phy, i); 4267 _tssi_set_tmeter_tbl(rtwdev, phy, i); 4268 _tssi_slope_cal_org(rtwdev, phy, i); 4269 _tssi_set_aligk_default(rtwdev, phy, i); 4270 _tssi_set_slope(rtwdev, phy, i); 4271 _tssi_run_slope(rtwdev, phy, i); 4272 } 4273 4274 _tssi_enable(rtwdev, phy); 4275 _tssi_set_efuse_to_de(rtwdev, phy); 4276 } 4277 4278 void rtw8852c_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) 4279 { 4280 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C; 4281 4282 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", 4283 __func__, phy); 4284 4285 if (!rtwdev->is_tssi_mode[RF_PATH_A]) 4286 return; 4287 if (!rtwdev->is_tssi_mode[RF_PATH_B]) 4288 return; 4289 4290 if (rtwdev->dbcc_en) { 4291 if (phy == RTW89_PHY_0) { 4292 path = RF_PATH_A; 4293 path_max = RF_PATH_B; 4294 } else if (phy == RTW89_PHY_1) { 4295 path = RF_PATH_B; 4296 path_max = RF_PATH_NUM_8852C; 4297 } 4298 } 4299 4300 _tssi_disable(rtwdev, phy); 4301 4302 for (i = path; i < path_max; i++) { 4303 _tssi_set_sys(rtwdev, phy, i); 4304 _tssi_set_dck(rtwdev, phy, i); 4305 _tssi_set_tmeter_tbl(rtwdev, phy, i); 4306 _tssi_slope_cal_org(rtwdev, phy, i); 4307 _tssi_set_aligk_default(rtwdev, phy, i); 4308 } 4309 4310 _tssi_enable(rtwdev, phy); 4311 _tssi_set_efuse_to_de(rtwdev, phy); 4312 } 4313 4314 static void rtw8852c_tssi_default_txagc(struct rtw89_dev *rtwdev, 4315 enum rtw89_phy_idx phy, bool enable) 4316 { 4317 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4318 u8 i; 4319 4320 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B]) 4321 return; 4322 4323 if (enable) { 4324 /* SCAN_START */ 4325 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0xc000 && 4326 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0x0) { 4327 for (i = 0; i < 6; i++) { 4328 tssi_info->default_txagc_offset[RF_PATH_A] = 4329 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, 4330 B_TXAGC_BB); 4331 if (tssi_info->default_txagc_offset[RF_PATH_A]) 4332 break; 4333 } 4334 } 4335 4336 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0xc000 && 4337 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0x0) { 4338 for (i = 0; i < 6; i++) { 4339 tssi_info->default_txagc_offset[RF_PATH_B] = 4340 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, 4341 B_TXAGC_BB_S1); 4342 if (tssi_info->default_txagc_offset[RF_PATH_B]) 4343 break; 4344 } 4345 } 4346 } else { 4347 /* SCAN_END */ 4348 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 4349 tssi_info->default_txagc_offset[RF_PATH_A]); 4350 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT, 4351 tssi_info->default_txagc_offset[RF_PATH_B]); 4352 4353 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0); 4354 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1); 4355 4356 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0); 4357 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1); 4358 } 4359 } 4360 4361 void rtw8852c_wifi_scan_notify(struct rtw89_dev *rtwdev, 4362 bool scan_start, enum rtw89_phy_idx phy_idx) 4363 { 4364 if (scan_start) 4365 rtw8852c_tssi_default_txagc(rtwdev, phy_idx, true); 4366 else 4367 rtw8852c_tssi_default_txagc(rtwdev, phy_idx, false); 4368 } 4369