1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "reg.h" 12 #include "rtw8852c.h" 13 #include "rtw8852c_rfk.h" 14 #include "rtw8852c_table.h" 15 #include "util.h" 16 17 #define RTW8852C_FW_FORMAT_MAX 0 18 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 19 #define RTW8852C_MODULE_FIRMWARE \ 20 RTW8852C_FW_BASENAME ".bin" 21 22 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 23 {13, 1614, grp_0}, /* ACH 0 */ 24 {13, 1614, grp_0}, /* ACH 1 */ 25 {13, 1614, grp_0}, /* ACH 2 */ 26 {13, 1614, grp_0}, /* ACH 3 */ 27 {13, 1614, grp_1}, /* ACH 4 */ 28 {13, 1614, grp_1}, /* ACH 5 */ 29 {13, 1614, grp_1}, /* ACH 6 */ 30 {13, 1614, grp_1}, /* ACH 7 */ 31 {13, 1614, grp_0}, /* B0MGQ */ 32 {13, 1614, grp_0}, /* B0HIQ */ 33 {13, 1614, grp_1}, /* B1MGQ */ 34 {13, 1614, grp_1}, /* B1HIQ */ 35 {40, 0, 0} /* FWCMDQ */ 36 }; 37 38 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 39 1614, /* Group 0 */ 40 1614, /* Group 1 */ 41 3228, /* Public Max */ 42 0 /* WP threshold */ 43 }; 44 45 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 46 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 47 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 48 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 49 RTW89_HCIFC_POH}, 50 [RTW89_QTA_INVALID] = {NULL}, 51 }; 52 53 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 54 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 55 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 56 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 57 &rtw89_mac_size.ple_qt47}, 58 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 59 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 60 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 61 &rtw89_mac_size.ple_qt45}, 62 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 63 NULL}, 64 }; 65 66 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 67 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 68 R_AX_H2CREG_DATA3_V1 69 }; 70 71 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 72 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 73 R_AX_C2HREG_DATA3_V1 74 }; 75 76 static const struct rtw89_page_regs rtw8852c_page_regs = { 77 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 78 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 79 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 80 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 81 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 82 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 83 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 84 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 85 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 86 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 87 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 88 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 89 }; 90 91 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 92 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 93 }; 94 95 static const struct rtw89_imr_info rtw8852c_imr_info = { 96 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 97 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 98 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 99 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 100 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 101 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 102 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 103 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 104 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 105 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 106 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 107 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 108 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 109 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 110 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 111 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 112 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 113 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 114 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 115 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 116 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 117 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 118 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 119 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 120 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 121 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 122 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 123 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 124 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 125 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 126 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 127 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 128 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 129 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 130 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 131 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 132 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 133 .rmac_imr_reg = R_AX_RX_ERR_IMR, 134 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 135 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 136 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 137 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 138 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 139 }; 140 141 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 142 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 143 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 144 }; 145 146 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 147 .seg0_pd_reg = R_SEG0R_PD, 148 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 149 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 150 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 151 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 152 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 153 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 154 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 155 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 156 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 157 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 158 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 159 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 160 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 161 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 162 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 163 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 164 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 165 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 166 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 167 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 168 }; 169 170 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 171 enum rtw89_phy_idx phy_idx); 172 173 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 174 enum rtw89_mac_idx mac_idx); 175 176 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 177 { 178 u32 val32; 179 u32 ret; 180 181 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 182 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 183 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 184 185 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 186 B_AX_AFSM_PCIE_SUS_EN); 187 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 188 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 189 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 190 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 191 192 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 193 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 194 if (ret) 195 return ret; 196 197 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 198 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 199 200 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 201 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 202 if (ret) 203 return ret; 204 205 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 206 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 207 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 208 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 209 210 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 211 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 212 213 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 214 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 215 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 216 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 217 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 218 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 219 B_AX_R_SYM_WLCMAC1_PC_EN); 220 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 221 222 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 223 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 224 if (ret) 225 return ret; 226 227 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 228 229 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 230 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 231 if (ret) 232 return ret; 233 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 234 XTAL_SI_OFF_WEI); 235 if (ret) 236 return ret; 237 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 238 XTAL_SI_OFF_EI); 239 if (ret) 240 return ret; 241 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 242 if (ret) 243 return ret; 244 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 245 XTAL_SI_PON_WEI); 246 if (ret) 247 return ret; 248 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 249 XTAL_SI_PON_EI); 250 if (ret) 251 return ret; 252 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 253 if (ret) 254 return ret; 255 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 256 if (ret) 257 return ret; 258 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 259 if (ret) 260 return ret; 261 262 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 263 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 264 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 265 266 fsleep(1000); 267 268 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 269 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 270 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 271 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 272 B_AX_LED1_PULL_LOW_EN); 273 274 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 275 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 276 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 277 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 278 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 279 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 280 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 281 282 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 283 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 284 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 285 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 286 B_AX_TMAC_EN | B_AX_RMAC_EN); 287 288 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 289 PINMUX_EESK_FUNC_SEL_BT_LOG); 290 291 return 0; 292 } 293 294 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 295 { 296 u32 val32; 297 u32 ret; 298 299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 300 XTAL_SI_RFC2RF); 301 if (ret) 302 return ret; 303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 304 if (ret) 305 return ret; 306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 307 if (ret) 308 return ret; 309 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 310 if (ret) 311 return ret; 312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 313 if (ret) 314 return ret; 315 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 316 XTAL_SI_SRAM2RFC); 317 if (ret) 318 return ret; 319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 320 if (ret) 321 return ret; 322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 323 if (ret) 324 return ret; 325 326 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 327 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 328 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 329 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 330 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 331 332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 333 if (ret) 334 return ret; 335 336 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 337 338 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 339 if (ret) 340 return ret; 341 342 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 343 344 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 345 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 346 if (ret) 347 return ret; 348 349 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 350 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 351 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 352 353 return 0; 354 } 355 356 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 357 struct rtw8852c_efuse *map) 358 { 359 ether_addr_copy(efuse->addr, map->e.mac_addr); 360 efuse->rfe_type = map->rfe_type; 361 efuse->xtal_cap = map->xtal_k; 362 } 363 364 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 365 struct rtw8852c_efuse *map) 366 { 367 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 368 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 369 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 370 u8 i, j; 371 372 tssi->thermal[RF_PATH_A] = map->path_a_therm; 373 tssi->thermal[RF_PATH_B] = map->path_b_therm; 374 375 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 376 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 377 sizeof(ofst[i]->cck_tssi)); 378 379 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 380 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 381 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 382 i, j, tssi->tssi_cck[i][j]); 383 384 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 385 sizeof(ofst[i]->bw40_tssi)); 386 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 387 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 388 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 389 sizeof(tssi->tssi_6g_mcs[i])); 390 391 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 392 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 393 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 394 i, j, tssi->tssi_mcs[i][j]); 395 } 396 } 397 398 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 399 { 400 if (high) 401 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 402 if (low) 403 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 404 405 return data != 0xff; 406 } 407 408 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 409 struct rtw8852c_efuse *map) 410 { 411 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 412 bool valid = false; 413 414 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 415 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 416 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 417 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 418 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 419 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 420 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 421 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 422 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 423 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 424 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 425 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 426 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 427 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 428 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 429 430 gain->offset_valid = valid; 431 } 432 433 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 434 { 435 struct rtw89_efuse *efuse = &rtwdev->efuse; 436 struct rtw8852c_efuse *map; 437 438 map = (struct rtw8852c_efuse *)log_map; 439 440 efuse->country_code[0] = map->country_code[0]; 441 efuse->country_code[1] = map->country_code[1]; 442 rtw8852c_efuse_parsing_tssi(rtwdev, map); 443 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 444 445 switch (rtwdev->hci.type) { 446 case RTW89_HCI_TYPE_PCIE: 447 rtw8852c_e_efuse_parsing(efuse, map); 448 break; 449 default: 450 return -ENOTSUPP; 451 } 452 453 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 454 455 return 0; 456 } 457 458 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 459 { 460 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 461 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 462 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 463 u32 addr = rtwdev->chip->phycap_addr; 464 bool pg = false; 465 u32 ofst; 466 u8 i, j; 467 468 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 469 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 470 /* addrs are in decreasing order */ 471 ofst = tssi_trim_addr[i] - addr - j; 472 tssi->tssi_trim[i][j] = phycap_map[ofst]; 473 474 if (phycap_map[ofst] != 0xff) 475 pg = true; 476 } 477 478 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 479 /* addrs are in decreasing order */ 480 ofst = tssi_trim_addr_6g[i] - addr - j; 481 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 482 483 if (phycap_map[ofst] != 0xff) 484 pg = true; 485 } 486 } 487 488 if (!pg) { 489 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 490 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 491 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 492 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 493 } 494 495 for (i = 0; i < RF_PATH_NUM_8852C; i++) 496 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 497 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 498 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 499 i, j, tssi->tssi_trim[i][j], 500 tssi_trim_addr[i] - j); 501 } 502 503 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 504 u8 *phycap_map) 505 { 506 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 507 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 508 u32 addr = rtwdev->chip->phycap_addr; 509 u8 i; 510 511 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 512 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 513 514 rtw89_debug(rtwdev, RTW89_DBG_RFK, 515 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 516 i, info->thermal_trim[i]); 517 518 if (info->thermal_trim[i] != 0xff) 519 info->pg_thermal_trim = true; 520 } 521 } 522 523 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 524 { 525 #define __thm_setting(raw) \ 526 ({ \ 527 u8 __v = (raw); \ 528 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 529 }) 530 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 531 u8 i, val; 532 533 if (!info->pg_thermal_trim) { 534 rtw89_debug(rtwdev, RTW89_DBG_RFK, 535 "[THERMAL][TRIM] no PG, do nothing\n"); 536 537 return; 538 } 539 540 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 541 val = __thm_setting(info->thermal_trim[i]); 542 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 543 544 rtw89_debug(rtwdev, RTW89_DBG_RFK, 545 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 546 i, val); 547 } 548 #undef __thm_setting 549 } 550 551 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 552 u8 *phycap_map) 553 { 554 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 555 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 556 u32 addr = rtwdev->chip->phycap_addr; 557 u8 i; 558 559 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 560 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 561 562 rtw89_debug(rtwdev, RTW89_DBG_RFK, 563 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 564 i, info->pa_bias_trim[i]); 565 566 if (info->pa_bias_trim[i] != 0xff) 567 info->pg_pa_bias_trim = true; 568 } 569 } 570 571 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 572 { 573 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 574 u8 pabias_2g, pabias_5g; 575 u8 i; 576 577 if (!info->pg_pa_bias_trim) { 578 rtw89_debug(rtwdev, RTW89_DBG_RFK, 579 "[PA_BIAS][TRIM] no PG, do nothing\n"); 580 581 return; 582 } 583 584 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 585 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 586 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 587 588 rtw89_debug(rtwdev, RTW89_DBG_RFK, 589 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 590 i, pabias_2g, pabias_5g); 591 592 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 593 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 594 } 595 } 596 597 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 598 { 599 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 600 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 601 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 602 603 return 0; 604 } 605 606 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 607 { 608 rtw8852c_thermal_trim(rtwdev); 609 rtw8852c_pa_bias_trim(rtwdev); 610 } 611 612 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 613 const struct rtw89_chan *chan, 614 u8 mac_idx) 615 { 616 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 617 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 618 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 619 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 620 u8 rf_mod_val = 0, chk_rate_mask = 0; 621 u32 txsc; 622 623 switch (chan->band_width) { 624 case RTW89_CHANNEL_WIDTH_160: 625 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 626 RTW89_CHANNEL_WIDTH_80); 627 fallthrough; 628 case RTW89_CHANNEL_WIDTH_80: 629 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 630 RTW89_CHANNEL_WIDTH_40); 631 fallthrough; 632 case RTW89_CHANNEL_WIDTH_40: 633 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 634 RTW89_CHANNEL_WIDTH_20); 635 break; 636 default: 637 break; 638 } 639 640 switch (chan->band_width) { 641 case RTW89_CHANNEL_WIDTH_160: 642 rf_mod_val = AX_WMAC_RFMOD_160M; 643 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 644 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 645 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 646 break; 647 case RTW89_CHANNEL_WIDTH_80: 648 rf_mod_val = AX_WMAC_RFMOD_80M; 649 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 650 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 651 break; 652 case RTW89_CHANNEL_WIDTH_40: 653 rf_mod_val = AX_WMAC_RFMOD_40M; 654 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 655 break; 656 case RTW89_CHANNEL_WIDTH_20: 657 default: 658 rf_mod_val = AX_WMAC_RFMOD_20M; 659 txsc = 0; 660 break; 661 } 662 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 663 rtw89_write32(rtwdev, sub_carr, txsc); 664 665 switch (chan->band_type) { 666 case RTW89_BAND_2G: 667 chk_rate_mask = B_AX_BAND_MODE; 668 break; 669 case RTW89_BAND_5G: 670 case RTW89_BAND_6G: 671 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 672 break; 673 default: 674 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 675 return; 676 } 677 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 678 B_AX_RTS_LIMIT_IN_OFDM6); 679 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 680 } 681 682 static const u32 rtw8852c_sco_barker_threshold[14] = { 683 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 684 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 685 }; 686 687 static const u32 rtw8852c_sco_cck_threshold[14] = { 688 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 689 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 690 }; 691 692 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 693 u8 primary_ch, enum rtw89_bandwidth bw) 694 { 695 u8 ch_element; 696 697 if (bw == RTW89_CHANNEL_WIDTH_20) { 698 ch_element = central_ch - 1; 699 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 700 if (primary_ch == 1) 701 ch_element = central_ch - 1 + 2; 702 else 703 ch_element = central_ch - 1 - 2; 704 } else { 705 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 706 return -EINVAL; 707 } 708 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 709 rtw8852c_sco_barker_threshold[ch_element]); 710 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 711 rtw8852c_sco_cck_threshold[ch_element]); 712 713 return 0; 714 } 715 716 struct rtw8852c_bb_gain { 717 u32 gain_g[BB_PATH_NUM_8852C]; 718 u32 gain_a[BB_PATH_NUM_8852C]; 719 u32 gain_mask; 720 }; 721 722 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 723 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 724 .gain_mask = 0x00ff0000 }, 725 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 726 .gain_mask = 0xff000000 }, 727 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 728 .gain_mask = 0x000000ff }, 729 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 730 .gain_mask = 0x0000ff00 }, 731 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 732 .gain_mask = 0x00ff0000 }, 733 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 734 .gain_mask = 0xff000000 }, 735 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 736 .gain_mask = 0x000000ff }, 737 }; 738 739 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 740 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 741 .gain_mask = 0x00ff0000 }, 742 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 743 .gain_mask = 0xff000000 }, 744 }; 745 746 struct rtw8852c_bb_gain_bypass { 747 u32 gain_g[BB_PATH_NUM_8852C]; 748 u32 gain_a[BB_PATH_NUM_8852C]; 749 u32 gain_mask_g; 750 u32 gain_mask_a; 751 }; 752 753 static 754 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 755 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 756 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 757 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 758 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 759 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 760 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 761 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 762 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 763 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 764 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 765 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 766 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 767 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 768 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 769 }; 770 771 struct rtw8852c_bb_gain_op1db { 772 struct { 773 u32 lna[BB_PATH_NUM_8852C]; 774 u32 tia_lna[BB_PATH_NUM_8852C]; 775 u32 mask; 776 } reg[LNA_GAIN_NUM]; 777 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 778 u32 mask_tia0_lna6; 779 }; 780 781 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 782 .reg = { 783 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 784 .mask = 0xff}, 785 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 786 .mask = 0xff00}, 787 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 788 .mask = 0xff0000}, 789 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 790 .mask = 0xff000000}, 791 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 792 .mask = 0xff}, 793 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 794 .mask = 0xff00}, 795 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 796 .mask = 0xff0000}, 797 }, 798 .reg_tia0_lna6 = {0x4674, 0x4758}, 799 .mask_tia0_lna6 = 0xff000000, 800 }; 801 802 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 803 enum rtw89_subband subband, 804 enum rtw89_rf_path path) 805 { 806 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 807 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 808 s32 val; 809 u32 reg; 810 u32 mask; 811 int i; 812 813 for (i = 0; i < LNA_GAIN_NUM; i++) { 814 if (subband == RTW89_CH_2G) 815 reg = bb_gain_lna[i].gain_g[path]; 816 else 817 reg = bb_gain_lna[i].gain_a[path]; 818 819 mask = bb_gain_lna[i].gain_mask; 820 val = gain->lna_gain[gain_band][path][i]; 821 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 822 823 if (subband == RTW89_CH_2G) { 824 reg = bb_gain_bypass_lna[i].gain_g[path]; 825 mask = bb_gain_bypass_lna[i].gain_mask_g; 826 } else { 827 reg = bb_gain_bypass_lna[i].gain_a[path]; 828 mask = bb_gain_bypass_lna[i].gain_mask_a; 829 } 830 831 val = gain->lna_gain_bypass[gain_band][path][i]; 832 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 833 834 if (subband != RTW89_CH_2G) { 835 reg = bb_gain_op1db_a.reg[i].lna[path]; 836 mask = bb_gain_op1db_a.reg[i].mask; 837 val = gain->lna_op1db[gain_band][path][i]; 838 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 839 840 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 841 mask = bb_gain_op1db_a.reg[i].mask; 842 val = gain->tia_lna_op1db[gain_band][path][i]; 843 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 844 } 845 } 846 847 if (subband != RTW89_CH_2G) { 848 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 849 mask = bb_gain_op1db_a.mask_tia0_lna6; 850 val = gain->tia_lna_op1db[gain_band][path][7]; 851 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 852 } 853 854 for (i = 0; i < TIA_GAIN_NUM; i++) { 855 if (subband == RTW89_CH_2G) 856 reg = bb_gain_tia[i].gain_g[path]; 857 else 858 reg = bb_gain_tia[i].gain_a[path]; 859 860 mask = bb_gain_tia[i].gain_mask; 861 val = gain->tia_gain[gain_band][path][i]; 862 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 863 } 864 } 865 866 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 867 const struct rtw89_chan *chan, 868 enum rtw89_phy_idx phy_idx, 869 enum rtw89_rf_path path) 870 { 871 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 872 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 873 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 874 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 875 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 876 enum rtw89_gain_offset gain_band; 877 s32 offset_q0, offset_base_q4; 878 s32 tmp = 0; 879 880 if (!efuse_gain->offset_valid) 881 return; 882 883 if (rtwdev->dbcc_en && path == RF_PATH_B) 884 phy_idx = RTW89_PHY_1; 885 886 if (chan->band_type == RTW89_BAND_2G) { 887 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 888 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 889 890 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 891 S8_MIN >> 1, S8_MAX >> 1); 892 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 893 } 894 895 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 896 897 offset_q0 = -efuse_gain->offset[path][gain_band]; 898 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 899 900 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 901 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 902 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 903 904 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 905 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 906 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 907 } 908 909 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 910 const struct rtw89_chan *chan, 911 enum rtw89_phy_idx phy_idx) 912 { 913 u8 sco; 914 u16 central_freq = chan->freq; 915 u8 central_ch = chan->channel; 916 u8 band = chan->band_type; 917 u8 subband = chan->subband_type; 918 bool is_2g = band == RTW89_BAND_2G; 919 u8 chan_idx; 920 921 if (!central_freq) { 922 rtw89_warn(rtwdev, "Invalid central_freq\n"); 923 return; 924 } 925 926 if (phy_idx == RTW89_PHY_0) { 927 /* Path A */ 928 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 929 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 930 931 if (is_2g) 932 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 933 B_PATH0_BAND_SEL_MSK_V1, 1, 934 phy_idx); 935 else 936 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 937 B_PATH0_BAND_SEL_MSK_V1, 0, 938 phy_idx); 939 /* Path B */ 940 if (!rtwdev->dbcc_en) { 941 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 942 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 943 944 if (is_2g) 945 rtw89_phy_write32_idx(rtwdev, 946 R_PATH1_BAND_SEL_V1, 947 B_PATH1_BAND_SEL_MSK_V1, 948 1, phy_idx); 949 else 950 rtw89_phy_write32_idx(rtwdev, 951 R_PATH1_BAND_SEL_V1, 952 B_PATH1_BAND_SEL_MSK_V1, 953 0, phy_idx); 954 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 955 } else { 956 if (is_2g) 957 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 958 else 959 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 960 } 961 /* SCO compensate FC setting */ 962 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 963 central_freq, phy_idx); 964 /* round_up((1/fc0)*pow(2,18)) */ 965 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 966 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 967 phy_idx); 968 } else { 969 /* Path B */ 970 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 971 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 972 973 if (is_2g) 974 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 975 B_PATH1_BAND_SEL_MSK_V1, 976 1, phy_idx); 977 else 978 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 979 B_PATH1_BAND_SEL_MSK_V1, 980 0, phy_idx); 981 /* SCO compensate FC setting */ 982 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 983 central_freq, phy_idx); 984 /* round_up((1/fc0)*pow(2,18)) */ 985 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 986 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 987 phy_idx); 988 } 989 /* CCK parameters */ 990 if (band == RTW89_BAND_2G) { 991 if (central_ch == 14) { 992 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 993 B_PCOEFF01_MSK_V1, 0x3b13ff); 994 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 995 B_PCOEFF23_MSK_V1, 0x1c42de); 996 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 997 B_PCOEFF45_MSK_V1, 0xfdb0ad); 998 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 999 B_PCOEFF67_MSK_V1, 0xf60f6e); 1000 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1001 B_PCOEFF89_MSK_V1, 0xfd8f92); 1002 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1003 B_PCOEFFAB_MSK_V1, 0x2d011); 1004 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1005 B_PCOEFFCD_MSK_V1, 0x1c02c); 1006 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1007 B_PCOEFFEF_MSK_V1, 0xfff00a); 1008 } else { 1009 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1010 B_PCOEFF01_MSK_V1, 0x3d23ff); 1011 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1012 B_PCOEFF23_MSK_V1, 0x29b354); 1013 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1014 B_PCOEFF45_MSK_V1, 0xfc1c8); 1015 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1016 B_PCOEFF67_MSK_V1, 0xfdb053); 1017 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1018 B_PCOEFF89_MSK_V1, 0xf86f9a); 1019 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1020 B_PCOEFFAB_MSK_V1, 0xfaef92); 1021 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1022 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1023 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1024 B_PCOEFFEF_MSK_V1, 0xffdff5); 1025 } 1026 } 1027 1028 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1029 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1030 } 1031 1032 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1033 { 1034 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1035 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1036 1037 switch (bw) { 1038 case RTW89_CHANNEL_WIDTH_5: 1039 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1040 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1041 break; 1042 case RTW89_CHANNEL_WIDTH_10: 1043 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1044 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1045 break; 1046 case RTW89_CHANNEL_WIDTH_20: 1047 case RTW89_CHANNEL_WIDTH_40: 1048 case RTW89_CHANNEL_WIDTH_80: 1049 case RTW89_CHANNEL_WIDTH_160: 1050 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1051 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1052 break; 1053 default: 1054 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1055 } 1056 } 1057 1058 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1059 enum rtw89_phy_idx phy_idx) 1060 { 1061 if (bw == RTW89_CHANNEL_WIDTH_20) { 1062 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1063 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1064 } else { 1065 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1066 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1067 } 1068 } 1069 1070 static void 1071 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1072 enum rtw89_phy_idx phy_idx) 1073 { 1074 u8 mod_sbw = 0; 1075 1076 switch (bw) { 1077 case RTW89_CHANNEL_WIDTH_5: 1078 case RTW89_CHANNEL_WIDTH_10: 1079 case RTW89_CHANNEL_WIDTH_20: 1080 if (bw == RTW89_CHANNEL_WIDTH_5) 1081 mod_sbw = 0x1; 1082 else if (bw == RTW89_CHANNEL_WIDTH_10) 1083 mod_sbw = 0x2; 1084 else if (bw == RTW89_CHANNEL_WIDTH_20) 1085 mod_sbw = 0x0; 1086 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1087 phy_idx); 1088 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1089 mod_sbw, phy_idx); 1090 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1091 phy_idx); 1092 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1093 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1094 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1095 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1096 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1097 B_PATH0_BW_SEL_MSK_V1, 0xf); 1098 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1099 B_PATH1_BW_SEL_MSK_V1, 0xf); 1100 break; 1101 case RTW89_CHANNEL_WIDTH_40: 1102 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1103 phy_idx); 1104 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1105 phy_idx); 1106 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1107 pri_ch, 1108 phy_idx); 1109 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1110 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1111 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1112 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1113 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1114 B_PATH0_BW_SEL_MSK_V1, 0xf); 1115 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1116 B_PATH1_BW_SEL_MSK_V1, 0xf); 1117 break; 1118 case RTW89_CHANNEL_WIDTH_80: 1119 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1120 phy_idx); 1121 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1122 phy_idx); 1123 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1124 pri_ch, 1125 phy_idx); 1126 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1127 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1128 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1129 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1130 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1131 B_PATH0_BW_SEL_MSK_V1, 0xd); 1132 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1133 B_PATH1_BW_SEL_MSK_V1, 0xd); 1134 break; 1135 case RTW89_CHANNEL_WIDTH_160: 1136 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1137 phy_idx); 1138 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1139 phy_idx); 1140 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1141 pri_ch, 1142 phy_idx); 1143 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1144 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1145 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1146 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1147 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1148 B_PATH0_BW_SEL_MSK_V1, 0xb); 1149 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1150 B_PATH1_BW_SEL_MSK_V1, 0xb); 1151 break; 1152 default: 1153 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1154 pri_ch); 1155 } 1156 1157 if (bw == RTW89_CHANNEL_WIDTH_40) { 1158 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1159 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1160 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1161 } else { 1162 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1163 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1164 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1165 } 1166 1167 if (phy_idx == RTW89_PHY_0) { 1168 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1169 if (!rtwdev->dbcc_en) 1170 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1171 } else { 1172 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1173 } 1174 1175 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1176 } 1177 1178 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1179 const struct rtw89_chan *chan) 1180 { 1181 u8 center_chan = chan->channel; 1182 u8 bw = chan->band_width; 1183 1184 switch (chan->band_type) { 1185 case RTW89_BAND_2G: 1186 if (bw == RTW89_CHANNEL_WIDTH_20) { 1187 if (center_chan >= 5 && center_chan <= 8) 1188 return 2440; 1189 if (center_chan == 13) 1190 return 2480; 1191 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1192 if (center_chan >= 3 && center_chan <= 10) 1193 return 2440; 1194 } 1195 break; 1196 case RTW89_BAND_5G: 1197 if (center_chan == 151 || center_chan == 153 || 1198 center_chan == 155 || center_chan == 163) 1199 return 5760; 1200 break; 1201 case RTW89_BAND_6G: 1202 if (center_chan == 195 || center_chan == 197 || 1203 center_chan == 199 || center_chan == 207) 1204 return 6920; 1205 break; 1206 default: 1207 break; 1208 } 1209 1210 return 0; 1211 } 1212 1213 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1214 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1215 #define MAX_TONE_NUM 2048 1216 1217 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1218 const struct rtw89_chan *chan, 1219 enum rtw89_phy_idx phy_idx) 1220 { 1221 u32 spur_freq; 1222 s32 freq_diff, csi_idx, csi_tone_idx; 1223 1224 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1225 if (spur_freq == 0) { 1226 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1227 return; 1228 } 1229 1230 freq_diff = (spur_freq - chan->freq) * 1000000; 1231 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1232 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1233 1234 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1235 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1236 } 1237 1238 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1239 [RF_PATH_A] = { 1240 .notch1_idx = {0x4C14, 0xFF}, 1241 .notch1_frac_idx = {0x4C14, 0xC00}, 1242 .notch1_en = {0x4C14, 0x1000}, 1243 .notch2_idx = {0x4C20, 0xFF}, 1244 .notch2_frac_idx = {0x4C20, 0xC00}, 1245 .notch2_en = {0x4C20, 0x1000}, 1246 }, 1247 [RF_PATH_B] = { 1248 .notch1_idx = {0x4CD8, 0xFF}, 1249 .notch1_frac_idx = {0x4CD8, 0xC00}, 1250 .notch1_en = {0x4CD8, 0x1000}, 1251 .notch2_idx = {0x4CE4, 0xFF}, 1252 .notch2_frac_idx = {0x4CE4, 0xC00}, 1253 .notch2_en = {0x4CE4, 0x1000}, 1254 }, 1255 }; 1256 1257 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1258 const struct rtw89_chan *chan, 1259 enum rtw89_rf_path path) 1260 { 1261 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1262 u32 spur_freq, fc; 1263 s32 freq_diff; 1264 s32 nbi_idx, nbi_tone_idx; 1265 s32 nbi_frac_idx, nbi_frac_tone_idx; 1266 bool notch2_chk = false; 1267 1268 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1269 if (spur_freq == 0) { 1270 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1271 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1272 return; 1273 } 1274 1275 fc = chan->freq; 1276 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1277 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1278 if ((fc > spur_freq && 1279 chan->channel < chan->primary_channel) || 1280 (fc < spur_freq && 1281 chan->channel > chan->primary_channel)) 1282 notch2_chk = true; 1283 } 1284 1285 freq_diff = (spur_freq - fc) * 1000000; 1286 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1287 1288 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1289 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1290 } else { 1291 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1292 128 : 256; 1293 1294 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1295 } 1296 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1297 1298 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1299 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1300 nbi->notch2_idx.mask, nbi_tone_idx); 1301 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1302 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1303 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1304 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1305 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1306 } else { 1307 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1308 nbi->notch1_idx.mask, nbi_tone_idx); 1309 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1310 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1311 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1312 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1313 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1314 } 1315 } 1316 1317 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1318 enum rtw89_phy_idx phy_idx) 1319 { 1320 u32 notch; 1321 u32 notch2; 1322 1323 if (phy_idx == RTW89_PHY_0) { 1324 notch = R_PATH0_NOTCH; 1325 notch2 = R_PATH0_NOTCH2; 1326 } else { 1327 notch = R_PATH1_NOTCH; 1328 notch2 = R_PATH1_NOTCH2; 1329 } 1330 1331 rtw89_phy_write32_mask(rtwdev, notch, 1332 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1333 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1334 rtw89_phy_write32_mask(rtwdev, notch2, 1335 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1336 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1337 } 1338 1339 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1340 const struct rtw89_chan *chan, 1341 u8 pri_ch_idx, 1342 enum rtw89_phy_idx phy_idx) 1343 { 1344 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1345 1346 if (phy_idx == RTW89_PHY_0) { 1347 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1348 (pri_ch_idx == RTW89_SC_20_LOWER || 1349 pri_ch_idx == RTW89_SC_20_UP3X)) { 1350 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1351 if (!rtwdev->dbcc_en) 1352 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1353 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1354 (pri_ch_idx == RTW89_SC_20_UPPER || 1355 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1356 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1357 if (!rtwdev->dbcc_en) 1358 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1359 } else { 1360 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1361 if (!rtwdev->dbcc_en) 1362 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1363 RF_PATH_B); 1364 } 1365 } else { 1366 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1367 (pri_ch_idx == RTW89_SC_20_LOWER || 1368 pri_ch_idx == RTW89_SC_20_UP3X)) { 1369 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1370 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1371 (pri_ch_idx == RTW89_SC_20_UPPER || 1372 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1373 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1374 } else { 1375 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1376 } 1377 } 1378 1379 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1380 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1381 else 1382 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1383 } 1384 1385 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1386 const struct rtw89_chan *chan, 1387 enum rtw89_phy_idx phy_idx) 1388 { 1389 u8 pri_ch = chan->pri_ch_idx; 1390 bool mask_5m_low; 1391 bool mask_5m_en; 1392 1393 switch (chan->band_width) { 1394 case RTW89_CHANNEL_WIDTH_40: 1395 mask_5m_en = true; 1396 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1397 break; 1398 case RTW89_CHANNEL_WIDTH_80: 1399 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1400 pri_ch == RTW89_SC_20_LOWEST; 1401 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1402 break; 1403 default: 1404 mask_5m_en = false; 1405 mask_5m_low = false; 1406 break; 1407 } 1408 1409 if (!mask_5m_en) { 1410 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1411 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1412 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1413 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1414 } else { 1415 if (mask_5m_low) { 1416 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1417 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1418 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1419 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1420 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1421 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1422 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1423 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1424 } else { 1425 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1426 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1427 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1428 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1429 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1430 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1431 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1432 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1433 } 1434 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1435 } 1436 } 1437 1438 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1439 enum rtw89_phy_idx phy_idx) 1440 { 1441 /*HW SI reset*/ 1442 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1443 0x7); 1444 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1445 0x7); 1446 1447 udelay(1); 1448 1449 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1450 phy_idx); 1451 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1452 phy_idx); 1453 /*HW SI reset*/ 1454 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1455 0x0); 1456 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1457 0x0); 1458 1459 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1460 phy_idx); 1461 } 1462 1463 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1464 enum rtw89_phy_idx phy_idx, bool en) 1465 { 1466 if (en) { 1467 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1468 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1469 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1470 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1471 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1472 phy_idx); 1473 if (band == RTW89_BAND_2G) 1474 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1475 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1476 } else { 1477 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1478 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1479 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1480 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1481 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1482 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1483 fsleep(1); 1484 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1485 phy_idx); 1486 } 1487 } 1488 1489 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1490 enum rtw89_phy_idx phy_idx) 1491 { 1492 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1493 } 1494 1495 static 1496 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1497 u8 tx_path_en, u8 trsw_tx, 1498 u8 trsw_rx, u8 trsw, u8 trsw_b) 1499 { 1500 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1501 u32 mask_ofst = 16; 1502 u32 cr; 1503 u32 val; 1504 1505 if (path >= ARRAY_SIZE(path_cr_bases)) 1506 return; 1507 1508 cr = path_cr_bases[path]; 1509 1510 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1511 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1512 1513 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1514 } 1515 1516 enum rtw8852c_rfe_src { 1517 PAPE_RFM, 1518 TRSW_RFM, 1519 LNAON_RFM, 1520 }; 1521 1522 static 1523 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1524 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1525 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1526 { 1527 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1528 static const u32 masks[] = {0, 8, 16}; 1529 u32 mask, mask_ofst; 1530 u32 cr; 1531 u32 val; 1532 1533 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1534 return; 1535 1536 mask_ofst = masks[src]; 1537 cr = path_cr_bases[path]; 1538 1539 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1540 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1541 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1542 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1543 mask = 0xff << mask_ofst; 1544 1545 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1546 } 1547 1548 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1549 { 1550 static const u32 cr_bases[] = {0x5800, 0x7800}; 1551 u32 addr; 1552 u8 i; 1553 1554 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1555 addr = cr_bases[i]; 1556 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1557 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1558 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1559 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1560 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1561 } 1562 1563 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1564 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1565 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1566 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1567 1568 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1569 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1570 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1571 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1572 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1573 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1574 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1575 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1576 1577 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1578 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1579 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1580 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1581 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1582 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1583 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1584 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1585 1586 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1587 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1588 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1589 1590 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1591 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1592 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1593 } 1594 1595 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1596 enum rtw89_phy_idx phy_idx) 1597 { 1598 u32 addr; 1599 1600 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1601 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1602 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1603 } 1604 1605 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1606 { 1607 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1608 1609 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1610 B_DBCC_80P80_SEL_EVM_RPT_EN); 1611 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1612 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1613 1614 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1615 rtw8852c_bb_gpio_init(rtwdev); 1616 1617 /* read these registers after loading BB parameters */ 1618 gain->offset_base[RTW89_PHY_0] = 1619 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1620 gain->offset_base[RTW89_PHY_1] = 1621 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1622 } 1623 1624 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1625 const struct rtw89_chan *chan, 1626 enum rtw89_phy_idx phy_idx) 1627 { 1628 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1629 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1630 struct rtw89_hal *hal = &rtwdev->hal; 1631 bool cck_en = chan->band_type == RTW89_BAND_2G; 1632 u8 pri_ch_idx = chan->pri_ch_idx; 1633 u32 mask, reg; 1634 u8 ntx_path; 1635 1636 if (chan->band_type == RTW89_BAND_2G) 1637 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1638 chan->primary_channel, 1639 chan->band_width); 1640 1641 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1642 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1643 if (cck_en) { 1644 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1645 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1646 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1647 B_PD_ARBITER_OFF, 0x0, phy_idx); 1648 } else { 1649 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1650 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1651 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1652 B_PD_ARBITER_OFF, 0x1, phy_idx); 1653 } 1654 1655 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1656 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G, 1657 RTW89_PHY_0); 1658 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1659 1660 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1661 rtwdev->hal.cv != CHIP_CAV) { 1662 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1663 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1664 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1665 if (chan->primary_channel > chan->channel) { 1666 rtw89_phy_write32_mask(rtwdev, 1667 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1668 ru_alloc_msk[phy_idx], 1); 1669 rtw89_write32_mask(rtwdev, reg, 1670 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1671 } else { 1672 rtw89_phy_write32_mask(rtwdev, 1673 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1674 ru_alloc_msk[phy_idx], 0); 1675 rtw89_write32_mask(rtwdev, reg, 1676 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1677 } 1678 } 1679 1680 if (chan->band_type == RTW89_BAND_6G && 1681 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1682 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1683 B_CDD_EVM_CHK_EN, 0, phy_idx); 1684 else 1685 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1686 B_CDD_EVM_CHK_EN, 1, phy_idx); 1687 1688 if (!rtwdev->dbcc_en) { 1689 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1690 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1691 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1692 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1693 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1694 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1695 } else { 1696 if (phy_idx == RTW89_PHY_0) { 1697 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1698 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1699 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1700 } else { 1701 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1702 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1703 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1704 } 1705 } 1706 1707 if (chan->band_type == RTW89_BAND_6G) 1708 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1709 else 1710 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1711 1712 if (hal->antenna_tx) 1713 ntx_path = hal->antenna_tx; 1714 else 1715 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1716 1717 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1718 1719 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1720 } 1721 1722 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1723 const struct rtw89_chan *chan, 1724 enum rtw89_mac_idx mac_idx, 1725 enum rtw89_phy_idx phy_idx) 1726 { 1727 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1728 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1729 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1730 } 1731 1732 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1733 { 1734 if (en) 1735 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1736 else 1737 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1738 } 1739 1740 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1741 { 1742 if (en) 1743 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1744 0x0); 1745 else 1746 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1747 0xf); 1748 } 1749 1750 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1751 struct rtw89_channel_help_params *p, 1752 const struct rtw89_chan *chan, 1753 enum rtw89_mac_idx mac_idx, 1754 enum rtw89_phy_idx phy_idx) 1755 { 1756 if (enter) { 1757 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1758 RTW89_SCH_TX_SEL_ALL); 1759 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1760 rtw8852c_dfs_en(rtwdev, false); 1761 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1762 rtw8852c_adc_en(rtwdev, false); 1763 fsleep(40); 1764 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1765 } else { 1766 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1767 rtw8852c_adc_en(rtwdev, true); 1768 rtw8852c_dfs_en(rtwdev, true); 1769 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1770 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1771 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1772 } 1773 } 1774 1775 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1776 { 1777 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1778 1779 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1780 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1781 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1782 rtw8852c_lck_init(rtwdev); 1783 rtw8852c_dpk_init(rtwdev); 1784 1785 rtw8852c_rck(rtwdev); 1786 rtw8852c_dack(rtwdev); 1787 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1788 } 1789 1790 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1791 { 1792 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1793 1794 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1795 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1796 rtw8852c_iqk(rtwdev, phy_idx); 1797 rtw8852c_tssi(rtwdev, phy_idx); 1798 rtw8852c_dpk(rtwdev, phy_idx); 1799 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1800 } 1801 1802 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1803 enum rtw89_phy_idx phy_idx) 1804 { 1805 rtw8852c_tssi_scan(rtwdev, phy_idx); 1806 } 1807 1808 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1809 { 1810 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1811 } 1812 1813 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1814 { 1815 rtw8852c_dpk_track(rtwdev); 1816 rtw8852c_lck_track(rtwdev); 1817 rtw8852c_rx_dck_track(rtwdev); 1818 } 1819 1820 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1821 enum rtw89_phy_idx phy_idx, s16 ref) 1822 { 1823 s8 ofst_int = 0; 1824 u8 base_cw_0db = 0x27; 1825 u16 tssi_16dbm_cw = 0x12c; 1826 s16 pwr_s10_3 = 0; 1827 s16 rf_pwr_cw = 0; 1828 u16 bb_pwr_cw = 0; 1829 u32 pwr_cw = 0; 1830 u32 tssi_ofst_cw = 0; 1831 1832 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1833 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1834 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1835 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1836 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1837 1838 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1839 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1840 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1841 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1842 1843 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1844 } 1845 1846 static 1847 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1848 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1849 { 1850 s8 pw_ofst_2tx; 1851 s8 val_1t; 1852 s8 val_2t; 1853 u32 reg; 1854 u8 i; 1855 1856 if (pw_ofst < -32 || pw_ofst > 31) { 1857 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1858 return; 1859 } 1860 val_1t = pw_ofst << 2; 1861 pw_ofst_2tx = max(pw_ofst - 3, -32); 1862 val_2t = pw_ofst_2tx << 2; 1863 1864 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1865 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1866 1867 for (i = 0; i < 4; i++) { 1868 /* 1TX */ 1869 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1870 rtw89_write32_mask(rtwdev, reg, 1871 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1872 val_1t); 1873 /* 2TX */ 1874 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1875 rtw89_write32_mask(rtwdev, reg, 1876 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1877 val_2t); 1878 } 1879 } 1880 1881 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1882 enum rtw89_phy_idx phy_idx) 1883 { 1884 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1885 const u32 mask = 0x7FFFFFF; 1886 const u8 ofst_ofdm = 0x4; 1887 const u8 ofst_cck = 0x8; 1888 s16 ref_ofdm = 0; 1889 s16 ref_cck = 0; 1890 u32 val; 1891 u8 i; 1892 1893 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1894 1895 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1896 GENMASK(27, 10), 0x0); 1897 1898 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1899 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1900 1901 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1902 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1903 phy_idx); 1904 1905 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1906 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1907 1908 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1909 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1910 phy_idx); 1911 } 1912 1913 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1914 const struct rtw89_chan *chan, 1915 u8 tx_shape_idx, 1916 enum rtw89_phy_idx phy_idx) 1917 { 1918 #define __DFIR_CFG_MASK 0xffffff 1919 #define __DFIR_CFG_NR 8 1920 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1921 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1922 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1923 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1924 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1925 1926 __DECL_DFIR_PARAM(flat, 1927 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1928 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1929 __DECL_DFIR_PARAM(sharp, 1930 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1931 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1932 __DECL_DFIR_PARAM(sharp_14, 1933 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1934 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1935 __DECL_DFIR_ADDR(filter, 1936 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1937 0x45C4, 0x45C8); 1938 u8 ch = chan->channel; 1939 const u32 *param; 1940 int i; 1941 1942 if (ch > 14) { 1943 rtw89_warn(rtwdev, 1944 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1945 return; 1946 } 1947 1948 if (ch == 14) 1949 param = param_sharp_14; 1950 else 1951 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1952 1953 for (i = 0; i < __DFIR_CFG_NR; i++) { 1954 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1955 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 1956 param[i]); 1957 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 1958 param[i], phy_idx); 1959 } 1960 1961 #undef __DECL_DFIR_ADDR 1962 #undef __DECL_DFIR_PARAM 1963 #undef __DECL_DFIR_VAR 1964 #undef __DFIR_CFG_NR 1965 #undef __DFIR_CFG_MASK 1966 } 1967 1968 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 1969 const struct rtw89_chan *chan, 1970 enum rtw89_phy_idx phy_idx) 1971 { 1972 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1973 u8 band = chan->band_type; 1974 u8 regd = rtw89_regd_get(rtwdev, band); 1975 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 1976 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 1977 1978 if (band == RTW89_BAND_2G) 1979 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1980 1981 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 1982 (enum rtw89_mac_idx)phy_idx, 1983 tx_shape_ofdm); 1984 1985 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN, 1986 B_P0_DAC_COMP_POST_DPD_EN); 1987 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN, 1988 B_P1_DAC_COMP_POST_DPD_EN); 1989 } 1990 1991 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 1992 const struct rtw89_chan *chan, 1993 enum rtw89_phy_idx phy_idx) 1994 { 1995 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1996 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1997 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 1998 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1999 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 2000 } 2001 2002 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 2003 enum rtw89_phy_idx phy_idx) 2004 { 2005 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 2006 } 2007 2008 static void 2009 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2010 { 2011 static const struct rtw89_reg2_def ctrl_ini[] = { 2012 {0xD938, 0x00010100}, 2013 {0xD93C, 0x0500D500}, 2014 {0xD940, 0x00000500}, 2015 {0xD944, 0x00000005}, 2016 {0xD94C, 0x00220000}, 2017 {0xD950, 0x00030000}, 2018 }; 2019 u32 addr; 2020 int i; 2021 2022 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2023 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2024 2025 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2026 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2027 ctrl_ini[i].data); 2028 2029 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2030 (enum rtw89_mac_idx)phy_idx, 2031 RTW89_TSSI_BANDEDGE_FLAT); 2032 } 2033 2034 static int 2035 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2036 { 2037 int ret; 2038 2039 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2040 if (ret) 2041 return ret; 2042 2043 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2044 if (ret) 2045 return ret; 2046 2047 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2048 if (ret) 2049 return ret; 2050 2051 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2052 RTW89_MAC_1 : 2053 RTW89_MAC_0); 2054 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2055 2056 return 0; 2057 } 2058 2059 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2060 { 2061 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2062 u8 band = chan->band_type; 2063 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2064 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2065 2066 if (rtwdev->dbcc_en) { 2067 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2068 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2069 RTW89_PHY_1); 2070 2071 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2072 1); 2073 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2074 1); 2075 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2076 RTW89_PHY_1); 2077 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2078 RTW89_PHY_1); 2079 2080 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2081 B_RXHT_MCS_LIMIT, 0); 2082 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2083 B_RXVHT_MCS_LIMIT, 0); 2084 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2085 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2086 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2087 2088 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2089 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2090 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2091 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2092 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2093 RTW89_PHY_1); 2094 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2095 RTW89_PHY_1); 2096 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2097 RTW89_PHY_1); 2098 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2099 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2100 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2101 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2102 } else { 2103 if (rx_path == RF_PATH_A) { 2104 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2105 B_ANT_RX_SEG0, 1); 2106 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2107 B_ANT_RX_1RCCA_SEG0, 1); 2108 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2109 B_ANT_RX_1RCCA_SEG1, 1); 2110 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2111 B_RXHT_MCS_LIMIT, 0); 2112 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2113 B_RXVHT_MCS_LIMIT, 0); 2114 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2115 0); 2116 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2117 0); 2118 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2119 rst_mask0, 1); 2120 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2121 rst_mask0, 3); 2122 } else if (rx_path == RF_PATH_B) { 2123 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2124 B_ANT_RX_SEG0, 2); 2125 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2126 B_ANT_RX_1RCCA_SEG0, 2); 2127 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2128 B_ANT_RX_1RCCA_SEG1, 2); 2129 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2130 B_RXHT_MCS_LIMIT, 0); 2131 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2132 B_RXVHT_MCS_LIMIT, 0); 2133 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2134 0); 2135 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2136 0); 2137 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2138 rst_mask1, 1); 2139 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2140 rst_mask1, 3); 2141 } else { 2142 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2143 B_ANT_RX_SEG0, 3); 2144 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2145 B_ANT_RX_1RCCA_SEG0, 3); 2146 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2147 B_ANT_RX_1RCCA_SEG1, 3); 2148 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2149 B_RXHT_MCS_LIMIT, 1); 2150 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2151 B_RXVHT_MCS_LIMIT, 1); 2152 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2153 1); 2154 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2155 1); 2156 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G, 2157 RTW89_PHY_0); 2158 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2159 rst_mask0, 1); 2160 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2161 rst_mask0, 3); 2162 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2163 rst_mask1, 1); 2164 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2165 rst_mask1, 3); 2166 } 2167 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2168 } 2169 } 2170 2171 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2172 enum rtw89_mac_idx mac_idx) 2173 { 2174 struct rtw89_reg2_def path_com[] = { 2175 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2176 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2177 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2178 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2179 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2180 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2181 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2182 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2183 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2184 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2185 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2186 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2187 }; 2188 u32 addr; 2189 u32 reg; 2190 u8 cr_size = ARRAY_SIZE(path_com); 2191 u8 i = 0; 2192 2193 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2194 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2195 2196 for (addr = R_AX_MACID_ANT_TABLE; 2197 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2198 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2199 rtw89_write32(rtwdev, reg, 0); 2200 } 2201 2202 if (tx_path == RF_A) { 2203 path_com[0].data = AX_PATH_COM0_PATHA; 2204 path_com[1].data = AX_PATH_COM1_PATHA; 2205 path_com[2].data = AX_PATH_COM2_PATHA; 2206 path_com[7].data = AX_PATH_COM7_PATHA; 2207 path_com[8].data = AX_PATH_COM8_PATHA; 2208 } else if (tx_path == RF_B) { 2209 path_com[0].data = AX_PATH_COM0_PATHB; 2210 path_com[1].data = AX_PATH_COM1_PATHB; 2211 path_com[2].data = AX_PATH_COM2_PATHB; 2212 path_com[7].data = AX_PATH_COM7_PATHB; 2213 path_com[8].data = AX_PATH_COM8_PATHB; 2214 } else if (tx_path == RF_AB) { 2215 path_com[0].data = AX_PATH_COM0_PATHAB; 2216 path_com[1].data = AX_PATH_COM1_PATHAB; 2217 path_com[2].data = AX_PATH_COM2_PATHAB; 2218 path_com[7].data = AX_PATH_COM7_PATHAB; 2219 path_com[8].data = AX_PATH_COM8_PATHAB; 2220 } else { 2221 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2222 return; 2223 } 2224 2225 for (i = 0; i < cr_size; i++) { 2226 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2227 path_com[i].addr, path_com[i].data); 2228 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2229 rtw89_write32(rtwdev, reg, path_com[i].data); 2230 } 2231 } 2232 2233 static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 2234 enum rtw89_phy_idx phy_idx) 2235 { 2236 if (en) { 2237 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2238 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2239 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2240 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2241 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2242 B_PATH0_RXBB_MSK_V1, 0xf); 2243 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2244 B_PATH1_RXBB_MSK_V1, 0xf); 2245 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2246 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2247 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2248 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2249 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2250 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2251 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2252 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2253 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2254 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2255 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2256 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2257 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2258 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2259 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2260 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2261 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2262 B_P0_BACKOFF_IBADC_V1, 0x34); 2263 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2264 B_P1_BACKOFF_IBADC_V1, 0x34); 2265 } else { 2266 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2267 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2268 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2269 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2270 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2271 B_PATH0_RXBB_MSK_V1, 0x60); 2272 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2273 B_PATH1_RXBB_MSK_V1, 0x60); 2274 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2275 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2276 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2277 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2278 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2279 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2280 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2281 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2282 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2283 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2284 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2285 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2286 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2287 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2288 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2289 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2290 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2291 B_P0_BACKOFF_IBADC_V1, 0x26); 2292 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2293 B_P1_BACKOFF_IBADC_V1, 0x26); 2294 } 2295 } 2296 2297 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2298 { 2299 struct rtw89_hal *hal = &rtwdev->hal; 2300 2301 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2302 2303 if (hal->rx_nss == 1) { 2304 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2305 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2306 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2307 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2308 } else { 2309 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2310 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2311 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2312 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2313 } 2314 } 2315 2316 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2317 { 2318 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2319 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2320 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2321 2322 fsleep(200); 2323 2324 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2325 } 2326 2327 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2328 { 2329 struct rtw89_btc *btc = &rtwdev->btc; 2330 struct rtw89_btc_module *module = &btc->mdinfo; 2331 2332 module->rfe_type = rtwdev->efuse.rfe_type; 2333 module->cv = rtwdev->hal.cv; 2334 module->bt_solo = 0; 2335 module->switch_type = BTC_SWITCH_INTERNAL; 2336 2337 if (module->rfe_type > 0) 2338 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 2339 else 2340 module->ant.num = 2; 2341 2342 module->ant.diversity = 0; 2343 module->ant.isolation = 10; 2344 2345 if (module->ant.num == 3) { 2346 module->ant.type = BTC_ANT_DEDICATED; 2347 module->bt_pos = BTC_BT_ALONE; 2348 } else { 2349 module->ant.type = BTC_ANT_SHARED; 2350 module->bt_pos = BTC_BT_BTG; 2351 } 2352 } 2353 2354 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 2355 enum rtw89_phy_idx phy_idx) 2356 { 2357 if (en) { 2358 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2359 B_PATH0_BT_SHARE_V1, 0x1); 2360 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2361 B_PATH0_BTG_PATH_V1, 0x0); 2362 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2363 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2364 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2365 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2366 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2367 B_PATH1_BT_SHARE_V1, 0x1); 2368 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2369 B_PATH1_BTG_PATH_V1, 0x1); 2370 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2371 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2372 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2373 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2374 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2375 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2376 0x1); 2377 } else { 2378 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2379 B_PATH0_BT_SHARE_V1, 0x0); 2380 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2381 B_PATH0_BTG_PATH_V1, 0x0); 2382 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2383 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2384 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2385 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2386 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2387 B_PATH1_BT_SHARE_V1, 0x0); 2388 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2389 B_PATH1_BTG_PATH_V1, 0x0); 2390 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2391 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2392 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2393 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2394 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2395 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2396 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2397 0x0); 2398 } 2399 } 2400 2401 static 2402 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2403 { 2404 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2405 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2406 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2407 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2408 } 2409 2410 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2411 { 2412 struct rtw89_btc *btc = &rtwdev->btc; 2413 struct rtw89_btc_module *module = &btc->mdinfo; 2414 const struct rtw89_chip_info *chip = rtwdev->chip; 2415 const struct rtw89_mac_ax_coex coex_params = { 2416 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2417 .direction = RTW89_MAC_AX_COEX_INNER, 2418 }; 2419 2420 /* PTA init */ 2421 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2422 2423 /* set WL Tx response = Hi-Pri */ 2424 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2425 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2426 2427 /* set rf gnt debug off */ 2428 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2429 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2430 2431 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2432 if (module->ant.type == BTC_ANT_SHARED) { 2433 rtw8852c_set_trx_mask(rtwdev, 2434 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2435 rtw8852c_set_trx_mask(rtwdev, 2436 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2437 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2438 rtw8852c_set_trx_mask(rtwdev, 2439 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2440 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2441 rtw8852c_set_trx_mask(rtwdev, 2442 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2443 rtw8852c_set_trx_mask(rtwdev, 2444 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2445 } 2446 2447 /* set PTA break table */ 2448 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2449 2450 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2451 rtw89_write32_set(rtwdev, 2452 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2453 B_AX_BT_CNT_RST_V1); 2454 btc->cx.wl.status.map.init_ok = true; 2455 } 2456 2457 static 2458 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2459 { 2460 u32 bitmap = 0; 2461 u32 reg = 0; 2462 2463 switch (map) { 2464 case BTC_PRI_MASK_TX_RESP: 2465 reg = R_BTC_COEX_WL_REQ; 2466 bitmap = B_BTC_RSP_ACK_HI; 2467 break; 2468 case BTC_PRI_MASK_BEACON: 2469 reg = R_BTC_COEX_WL_REQ; 2470 bitmap = B_BTC_TX_BCN_HI; 2471 break; 2472 default: 2473 return; 2474 } 2475 2476 if (state) 2477 rtw89_write32_set(rtwdev, reg, bitmap); 2478 else 2479 rtw89_write32_clr(rtwdev, reg, bitmap); 2480 } 2481 2482 union rtw8852c_btc_wl_txpwr_ctrl { 2483 u32 txpwr_val; 2484 struct { 2485 union { 2486 u16 ctrl_all_time; 2487 struct { 2488 s16 data:9; 2489 u16 rsvd:6; 2490 u16 flag:1; 2491 } all_time; 2492 }; 2493 union { 2494 u16 ctrl_gnt_bt; 2495 struct { 2496 s16 data:9; 2497 u16 rsvd:7; 2498 } gnt_bt; 2499 }; 2500 }; 2501 } __packed; 2502 2503 static void 2504 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2505 { 2506 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2507 s32 val; 2508 2509 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2510 do { \ 2511 u32 _wrt = FIELD_PREP(_msk, _val); \ 2512 BUILD_BUG_ON((_msk & _en) != 0); \ 2513 if (_cond) \ 2514 _wrt |= _en; \ 2515 else \ 2516 _wrt &= ~_en; \ 2517 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2518 _msk | _en, _wrt); \ 2519 } while (0) 2520 2521 switch (arg.ctrl_all_time) { 2522 case 0xffff: 2523 val = 0; 2524 break; 2525 default: 2526 val = arg.all_time.data; 2527 break; 2528 } 2529 2530 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2531 val, B_AX_FORCE_PWR_BY_RATE_EN, 2532 arg.ctrl_all_time != 0xffff); 2533 2534 switch (arg.ctrl_gnt_bt) { 2535 case 0xffff: 2536 val = 0; 2537 break; 2538 default: 2539 val = arg.gnt_bt.data; 2540 break; 2541 } 2542 2543 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2544 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2545 2546 #undef __write_ctrl 2547 } 2548 2549 static 2550 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2551 { 2552 /* +6 for compensate offset */ 2553 return clamp_t(s8, val + 6, -100, 0) + 100; 2554 } 2555 2556 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2557 {255, 0, 0, 7}, /* 0 -> original */ 2558 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2559 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2560 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2561 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2562 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2563 {6, 1, 0, 7}, 2564 {13, 1, 0, 7}, 2565 {13, 1, 0, 7} 2566 }; 2567 2568 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2569 {255, 0, 0, 7}, /* 0 -> original */ 2570 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2571 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2572 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2573 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2574 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2575 {255, 1, 0, 7}, 2576 {255, 1, 0, 7}, 2577 {255, 1, 0, 7} 2578 }; 2579 2580 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2581 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2582 2583 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2584 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2585 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2586 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2587 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2588 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2589 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2590 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2591 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2592 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2593 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2594 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2595 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2596 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2597 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2598 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2599 }; 2600 2601 static 2602 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2603 { 2604 /* Feature move to firmware */ 2605 } 2606 2607 static 2608 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2609 { 2610 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2611 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2612 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2613 2614 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2615 if (state) 2616 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2617 RFREG_MASK, 0x179c); 2618 else 2619 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2620 RFREG_MASK, 0x208); 2621 2622 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2623 } 2624 2625 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2626 { 2627 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2628 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2629 * To improve BT ACI in co-rx 2630 */ 2631 2632 switch (level) { 2633 case 0: /* default */ 2634 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2635 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2636 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2637 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2638 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2639 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2640 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2641 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2642 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2643 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2644 break; 2645 case 1: /* Fix LNA2=5 */ 2646 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2647 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2648 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2649 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2650 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2651 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2652 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2653 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2654 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2655 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2656 break; 2657 } 2658 } 2659 2660 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2661 { 2662 struct rtw89_btc *btc = &rtwdev->btc; 2663 2664 switch (level) { 2665 case 0: /* original */ 2666 default: 2667 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2668 btc->dm.wl_lna2 = 0; 2669 break; 2670 case 1: /* for FDD free-run */ 2671 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2672 btc->dm.wl_lna2 = 0; 2673 break; 2674 case 2: /* for BTG Co-Rx*/ 2675 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2676 btc->dm.wl_lna2 = 1; 2677 break; 2678 } 2679 2680 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2681 } 2682 2683 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2684 struct rtw89_rx_phy_ppdu *phy_ppdu, 2685 struct ieee80211_rx_status *status) 2686 { 2687 u8 chan_idx = phy_ppdu->chan_idx; 2688 enum nl80211_band band; 2689 u8 ch; 2690 2691 if (chan_idx == 0) 2692 return; 2693 2694 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2695 status->freq = ieee80211_channel_to_frequency(ch, band); 2696 status->band = band; 2697 } 2698 2699 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2700 struct rtw89_rx_phy_ppdu *phy_ppdu, 2701 struct ieee80211_rx_status *status) 2702 { 2703 u8 path; 2704 u8 *rx_power = phy_ppdu->rssi; 2705 2706 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2707 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2708 status->chains |= BIT(path); 2709 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2710 } 2711 if (phy_ppdu->valid) 2712 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2713 } 2714 2715 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2716 { 2717 int ret; 2718 2719 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2720 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2721 2722 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2723 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2724 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2725 2726 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2727 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2728 2729 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2730 if (ret) 2731 return ret; 2732 2733 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2734 if (ret) 2735 return ret; 2736 2737 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2738 if (ret) 2739 return ret; 2740 2741 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2742 if (ret) 2743 return ret; 2744 2745 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2746 if (ret) 2747 return ret; 2748 2749 return 0; 2750 } 2751 2752 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2753 { 2754 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2755 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2756 2757 return 0; 2758 } 2759 2760 static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = { 2761 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb, 2762 }; 2763 2764 #ifdef CONFIG_PM 2765 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2766 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2767 .n_patterns = RTW89_MAX_PATTERN_NUM, 2768 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2769 .pattern_min_len = 1, 2770 }; 2771 #endif 2772 2773 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2774 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2775 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2776 .bb_preinit = NULL, 2777 .bb_reset = rtw8852c_bb_reset, 2778 .bb_sethw = rtw8852c_bb_sethw, 2779 .read_rf = rtw89_phy_read_rf_v1, 2780 .write_rf = rtw89_phy_write_rf_v1, 2781 .set_channel = rtw8852c_set_channel, 2782 .set_channel_help = rtw8852c_set_channel_help, 2783 .read_efuse = rtw8852c_read_efuse, 2784 .read_phycap = rtw8852c_read_phycap, 2785 .fem_setup = NULL, 2786 .rfe_gpio = NULL, 2787 .rfk_init = rtw8852c_rfk_init, 2788 .rfk_channel = rtw8852c_rfk_channel, 2789 .rfk_band_changed = rtw8852c_rfk_band_changed, 2790 .rfk_scan = rtw8852c_rfk_scan, 2791 .rfk_track = rtw8852c_rfk_track, 2792 .power_trim = rtw8852c_power_trim, 2793 .set_txpwr = rtw8852c_set_txpwr, 2794 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2795 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2796 .get_thermal = rtw8852c_get_thermal, 2797 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx, 2798 .query_ppdu = rtw8852c_query_ppdu, 2799 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx, 2800 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2801 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2802 .pwr_on_func = rtw8852c_pwr_on_func, 2803 .pwr_off_func = rtw8852c_pwr_off_func, 2804 .query_rxdesc = rtw89_core_query_rxdesc, 2805 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2806 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2807 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2808 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2809 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2810 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2811 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2812 2813 .btc_set_rfe = rtw8852c_btc_set_rfe, 2814 .btc_init_cfg = rtw8852c_btc_init_cfg, 2815 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2816 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2817 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2818 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2819 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2820 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2821 .btc_set_policy = rtw89_btc_set_policy_v1, 2822 }; 2823 2824 const struct rtw89_chip_info rtw8852c_chip_info = { 2825 .chip_id = RTL8852C, 2826 .chip_gen = RTW89_CHIP_AX, 2827 .ops = &rtw8852c_chip_ops, 2828 .mac_def = &rtw89_mac_gen_ax, 2829 .phy_def = &rtw89_phy_gen_ax, 2830 .fw_basename = RTW8852C_FW_BASENAME, 2831 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2832 .try_ce_fw = false, 2833 .bbmcu_nr = 0, 2834 .needed_fw_elms = 0, 2835 .fifo_size = 458752, 2836 .small_fifo_size = false, 2837 .dle_scc_rsvd_size = 0, 2838 .max_amsdu_limit = 8000, 2839 .dis_2g_40m_ul_ofdma = false, 2840 .rsvd_ple_ofst = 0x6f800, 2841 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2842 .dle_mem = rtw8852c_dle_mem_pcie, 2843 .wde_qempty_acq_num = 16, 2844 .wde_qempty_mgq_sel = 16, 2845 .rf_base_addr = {0xe000, 0xf000}, 2846 .pwr_on_seq = NULL, 2847 .pwr_off_seq = NULL, 2848 .bb_table = &rtw89_8852c_phy_bb_table, 2849 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2850 .rf_table = {&rtw89_8852c_phy_radiob_table, 2851 &rtw89_8852c_phy_radioa_table,}, 2852 .nctl_table = &rtw89_8852c_phy_nctl_table, 2853 .nctl_post_table = NULL, 2854 .dflt_parms = &rtw89_8852c_dflt_parms, 2855 .rfe_parms_conf = NULL, 2856 .chanctx_listener = &rtw8852c_chanctx_listener, 2857 .txpwr_factor_rf = 2, 2858 .txpwr_factor_mac = 1, 2859 .dig_table = NULL, 2860 .dig_regs = &rtw8852c_dig_regs, 2861 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2862 .support_chanctx_num = 2, 2863 .support_bands = BIT(NL80211_BAND_2GHZ) | 2864 BIT(NL80211_BAND_5GHZ) | 2865 BIT(NL80211_BAND_6GHZ), 2866 .support_bw160 = true, 2867 .support_unii4 = true, 2868 .ul_tb_waveform_ctrl = false, 2869 .ul_tb_pwr_diff = true, 2870 .hw_sec_hdr = true, 2871 .rf_path_num = 2, 2872 .tx_nss = 2, 2873 .rx_nss = 2, 2874 .acam_num = 128, 2875 .bcam_num = 20, 2876 .scam_num = 128, 2877 .bacam_num = 8, 2878 .bacam_dynamic_num = 8, 2879 .bacam_ver = RTW89_BACAM_V0_EXT, 2880 .sec_ctrl_efuse_size = 4, 2881 .physical_efuse_size = 1216, 2882 .logical_efuse_size = 2048, 2883 .limit_efuse_size = 1280, 2884 .dav_phy_efuse_size = 96, 2885 .dav_log_efuse_size = 16, 2886 .phycap_addr = 0x590, 2887 .phycap_size = 0x60, 2888 .para_ver = 0x1, 2889 .wlcx_desired = 0x06000000, 2890 .btcx_desired = 0x7, 2891 .scbd = 0x1, 2892 .mailbox = 0x1, 2893 2894 .afh_guard_ch = 6, 2895 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2896 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2897 .rssi_tol = 2, 2898 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2899 .mon_reg = rtw89_btc_8852c_mon_reg, 2900 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2901 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2902 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2903 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2904 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2905 BIT(RTW89_PS_MODE_CLK_GATED) | 2906 BIT(RTW89_PS_MODE_PWR_GATED), 2907 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2908 BIT(RTW89_PS_MODE_PWR_GATED), 2909 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2910 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2911 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2912 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2913 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2914 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2915 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2916 .h2c_regs = rtw8852c_h2c_regs, 2917 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2918 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2919 .c2h_regs = rtw8852c_c2h_regs, 2920 .page_regs = &rtw8852c_page_regs, 2921 .cfo_src_fd = false, 2922 .cfo_hw_comp = false, 2923 .dcfo_comp = &rtw8852c_dcfo_comp, 2924 .dcfo_comp_sft = 12, 2925 .imr_info = &rtw8852c_imr_info, 2926 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 2927 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2928 .bss_clr_map_reg = R_BSS_CLR_MAP, 2929 .dma_ch_mask = 0, 2930 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL, 2931 #ifdef CONFIG_PM 2932 .wowlan_stub = &rtw_wowlan_stub_8852c, 2933 #endif 2934 .xtal_info = NULL, 2935 }; 2936 EXPORT_SYMBOL(rtw8852c_chip_info); 2937 2938 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 2939 MODULE_AUTHOR("Realtek Corporation"); 2940 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 2941 MODULE_LICENSE("Dual BSD/GPL"); 2942