1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "reg.h" 12 #include "rtw8852c.h" 13 #include "rtw8852c_rfk.h" 14 #include "rtw8852c_table.h" 15 #include "sar.h" 16 #include "util.h" 17 18 #define RTW8852C_FW_FORMAT_MAX 2 19 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 20 #define RTW8852C_MODULE_FIRMWARE \ 21 RTW8852C_FW_BASENAME "-" __stringify(RTW8852C_FW_FORMAT_MAX) ".bin" 22 23 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 24 {13, 1614, grp_0}, /* ACH 0 */ 25 {13, 1614, grp_0}, /* ACH 1 */ 26 {13, 1614, grp_0}, /* ACH 2 */ 27 {13, 1614, grp_0}, /* ACH 3 */ 28 {13, 1614, grp_1}, /* ACH 4 */ 29 {13, 1614, grp_1}, /* ACH 5 */ 30 {13, 1614, grp_1}, /* ACH 6 */ 31 {13, 1614, grp_1}, /* ACH 7 */ 32 {13, 1614, grp_0}, /* B0MGQ */ 33 {13, 1614, grp_0}, /* B0HIQ */ 34 {13, 1614, grp_1}, /* B1MGQ */ 35 {13, 1614, grp_1}, /* B1HIQ */ 36 {40, 0, 0} /* FWCMDQ */ 37 }; 38 39 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 40 1614, /* Group 0 */ 41 1614, /* Group 1 */ 42 3228, /* Public Max */ 43 0 /* WP threshold */ 44 }; 45 46 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 47 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 50 RTW89_HCIFC_POH}, 51 [RTW89_QTA_INVALID] = {NULL}, 52 }; 53 54 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 55 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 56 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 57 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 58 &rtw89_mac_size.ple_qt47}, 59 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 60 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 61 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 62 &rtw89_mac_size.ple_qt45}, 63 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 64 NULL}, 65 }; 66 67 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 68 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 69 R_AX_H2CREG_DATA3_V1 70 }; 71 72 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 73 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 74 R_AX_C2HREG_DATA3_V1 75 }; 76 77 static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 78 R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW, 79 }; 80 81 static const struct rtw89_page_regs rtw8852c_page_regs = { 82 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 83 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 84 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 85 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 86 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 87 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 88 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 89 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 90 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 91 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 92 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 93 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 94 }; 95 96 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 97 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 98 }; 99 100 static const struct rtw89_imr_info rtw8852c_imr_info = { 101 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 102 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 103 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 104 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 105 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 106 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 107 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 108 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 109 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 110 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 111 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 112 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 113 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 114 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 115 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 116 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 117 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 118 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 119 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 120 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 121 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 122 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 123 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 124 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 125 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 126 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 127 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 128 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 129 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 130 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 131 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 132 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 133 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 134 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 135 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 136 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 137 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 138 .rmac_imr_reg = R_AX_RX_ERR_IMR, 139 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 140 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 141 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 142 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 143 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 144 }; 145 146 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 147 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 148 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 149 }; 150 151 static const struct rtw89_rfkill_regs rtw8852c_rfkill_regs = { 152 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 153 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 154 0xf}, 155 .mode = {R_AX_GPIO_EXT_CTRL + 2, 156 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 157 0x0}, 158 }; 159 160 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 161 .seg0_pd_reg = R_SEG0R_PD, 162 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 163 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 164 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 165 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 166 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 167 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 168 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 169 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 170 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 171 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 172 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 173 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 174 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 175 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 176 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 177 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 178 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 179 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 180 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 181 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 182 }; 183 184 static const struct rtw89_edcca_regs rtw8852c_edcca_regs = { 185 .edcca_level = R_SEG0R_EDCCA_LVL, 186 .edcca_mask = B_EDCCA_LVL_MSK0, 187 .edcca_p_mask = B_EDCCA_LVL_MSK1, 188 .ppdu_level = R_SEG0R_EDCCA_LVL, 189 .ppdu_mask = B_EDCCA_LVL_MSK3, 190 .p = {{ 191 .rpt_a = R_EDCCA_RPT_A, 192 .rpt_b = R_EDCCA_RPT_B, 193 .rpt_sel = R_EDCCA_RPT_SEL, 194 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 195 }, { 196 .rpt_a = R_EDCCA_RPT_P1_A, 197 .rpt_b = R_EDCCA_RPT_P1_B, 198 .rpt_sel = R_EDCCA_RPT_SEL, 199 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK, 200 }}, 201 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 202 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 203 }; 204 205 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 206 enum rtw89_phy_idx phy_idx); 207 208 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 209 enum rtw89_mac_idx mac_idx); 210 211 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 212 { 213 u32 val32; 214 int ret; 215 216 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 217 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 218 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 219 220 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 221 B_AX_AFSM_PCIE_SUS_EN); 222 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 223 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 224 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 225 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 226 227 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 228 B_AX_OCP_L1_MASK, 0x7); 229 230 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 231 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 232 if (ret) 233 return ret; 234 235 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 236 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 237 238 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 239 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 240 if (ret) 241 return ret; 242 243 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 244 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 245 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 246 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 247 248 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 249 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 250 251 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 252 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 253 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 254 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 255 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 256 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 257 B_AX_R_SYM_WLCMAC1_PC_EN); 258 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 259 260 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 261 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 262 if (ret) 263 return ret; 264 265 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 266 267 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 268 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 269 if (ret) 270 return ret; 271 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 272 XTAL_SI_OFF_WEI); 273 if (ret) 274 return ret; 275 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 276 XTAL_SI_OFF_EI); 277 if (ret) 278 return ret; 279 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 280 if (ret) 281 return ret; 282 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 283 XTAL_SI_PON_WEI); 284 if (ret) 285 return ret; 286 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 287 XTAL_SI_PON_EI); 288 if (ret) 289 return ret; 290 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 291 if (ret) 292 return ret; 293 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0x10, XTAL_SI_LDO_LPS); 294 if (ret) 295 return ret; 296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 297 if (ret) 298 return ret; 299 300 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 301 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 302 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 303 304 fsleep(1000); 305 306 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 307 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 308 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 309 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 310 B_AX_LED1_PULL_LOW_EN); 311 312 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 313 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 314 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 315 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 316 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 317 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 318 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 319 320 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 321 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 322 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 323 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 324 B_AX_TMAC_EN | B_AX_RMAC_EN); 325 326 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 327 PINMUX_EESK_FUNC_SEL_BT_LOG); 328 329 return 0; 330 } 331 332 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 333 { 334 u32 val32; 335 int ret; 336 337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 338 XTAL_SI_RFC2RF); 339 if (ret) 340 return ret; 341 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 342 if (ret) 343 return ret; 344 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 345 if (ret) 346 return ret; 347 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 348 if (ret) 349 return ret; 350 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 351 if (ret) 352 return ret; 353 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 354 XTAL_SI_SRAM2RFC); 355 if (ret) 356 return ret; 357 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 358 if (ret) 359 return ret; 360 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 361 if (ret) 362 return ret; 363 364 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 365 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 366 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 367 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 368 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 369 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 370 371 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 372 if (ret) 373 return ret; 374 375 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 376 377 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 378 if (ret) 379 return ret; 380 381 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 382 383 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 384 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 385 if (ret) 386 return ret; 387 388 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 389 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 390 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 391 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 392 B_AX_REG_ZCDC_H_MASK, 0x3); 393 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 394 395 return 0; 396 } 397 398 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 399 struct rtw8852c_efuse *map) 400 { 401 ether_addr_copy(efuse->addr, map->e.mac_addr); 402 efuse->rfe_type = map->rfe_type; 403 efuse->xtal_cap = map->xtal_k; 404 } 405 406 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 407 struct rtw8852c_efuse *map) 408 { 409 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 410 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 411 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 412 u8 i, j; 413 414 tssi->thermal[RF_PATH_A] = map->path_a_therm; 415 tssi->thermal[RF_PATH_B] = map->path_b_therm; 416 417 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 418 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 419 sizeof(ofst[i]->cck_tssi)); 420 421 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 422 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 423 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 424 i, j, tssi->tssi_cck[i][j]); 425 426 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 427 sizeof(ofst[i]->bw40_tssi)); 428 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 429 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 430 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 431 sizeof(tssi->tssi_6g_mcs[i])); 432 433 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 434 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 435 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 436 i, j, tssi->tssi_mcs[i][j]); 437 } 438 } 439 440 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 441 { 442 if (high) 443 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 444 if (low) 445 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 446 447 return data != 0xff; 448 } 449 450 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 451 struct rtw8852c_efuse *map) 452 { 453 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 454 bool valid = false; 455 456 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 457 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 458 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 459 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 460 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 461 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 462 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 463 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 464 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 465 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 466 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 467 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 468 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 469 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 470 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 471 valid |= _decode_efuse_gain(map->rx_gain_6g_l0, 472 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0], 473 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]); 474 valid |= _decode_efuse_gain(map->rx_gain_6g_l1, 475 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1], 476 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]); 477 valid |= _decode_efuse_gain(map->rx_gain_6g_m0, 478 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0], 479 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]); 480 valid |= _decode_efuse_gain(map->rx_gain_6g_m1, 481 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1], 482 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]); 483 valid |= _decode_efuse_gain(map->rx_gain_6g_h0, 484 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0], 485 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]); 486 valid |= _decode_efuse_gain(map->rx_gain_6g_h1, 487 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1], 488 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]); 489 valid |= _decode_efuse_gain(map->rx_gain_6g_uh0, 490 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0], 491 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]); 492 valid |= _decode_efuse_gain(map->rx_gain_6g_uh1, 493 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1], 494 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]); 495 496 gain->offset_valid = valid; 497 } 498 499 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 500 enum rtw89_efuse_block block) 501 { 502 struct rtw89_efuse *efuse = &rtwdev->efuse; 503 struct rtw8852c_efuse *map; 504 505 map = (struct rtw8852c_efuse *)log_map; 506 507 efuse->country_code[0] = map->country_code[0]; 508 efuse->country_code[1] = map->country_code[1]; 509 rtw8852c_efuse_parsing_tssi(rtwdev, map); 510 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 511 512 switch (rtwdev->hci.type) { 513 case RTW89_HCI_TYPE_PCIE: 514 rtw8852c_e_efuse_parsing(efuse, map); 515 break; 516 default: 517 return -ENOTSUPP; 518 } 519 520 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 521 522 return 0; 523 } 524 525 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 526 { 527 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 528 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 529 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 530 u32 addr = rtwdev->chip->phycap_addr; 531 bool pg = false; 532 u32 ofst; 533 u8 i, j; 534 535 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 536 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 537 /* addrs are in decreasing order */ 538 ofst = tssi_trim_addr[i] - addr - j; 539 tssi->tssi_trim[i][j] = phycap_map[ofst]; 540 541 if (phycap_map[ofst] != 0xff) 542 pg = true; 543 } 544 545 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 546 /* addrs are in decreasing order */ 547 ofst = tssi_trim_addr_6g[i] - addr - j; 548 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 549 550 if (phycap_map[ofst] != 0xff) 551 pg = true; 552 } 553 } 554 555 if (!pg) { 556 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 557 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 558 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 559 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 560 } 561 562 for (i = 0; i < RF_PATH_NUM_8852C; i++) 563 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 564 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 565 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 566 i, j, tssi->tssi_trim[i][j], 567 tssi_trim_addr[i] - j); 568 } 569 570 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 571 u8 *phycap_map) 572 { 573 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 574 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 575 u32 addr = rtwdev->chip->phycap_addr; 576 u8 i; 577 578 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 579 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 580 581 rtw89_debug(rtwdev, RTW89_DBG_RFK, 582 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 583 i, info->thermal_trim[i]); 584 585 if (info->thermal_trim[i] != 0xff) 586 info->pg_thermal_trim = true; 587 } 588 } 589 590 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 591 { 592 #define __thm_setting(raw) \ 593 ({ \ 594 u8 __v = (raw); \ 595 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 596 }) 597 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 598 u8 i, val; 599 600 if (!info->pg_thermal_trim) { 601 rtw89_debug(rtwdev, RTW89_DBG_RFK, 602 "[THERMAL][TRIM] no PG, do nothing\n"); 603 604 return; 605 } 606 607 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 608 val = __thm_setting(info->thermal_trim[i]); 609 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 610 611 rtw89_debug(rtwdev, RTW89_DBG_RFK, 612 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 613 i, val); 614 } 615 #undef __thm_setting 616 } 617 618 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 619 u8 *phycap_map) 620 { 621 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 622 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 623 u32 addr = rtwdev->chip->phycap_addr; 624 u8 i; 625 626 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 627 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 628 629 rtw89_debug(rtwdev, RTW89_DBG_RFK, 630 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 631 i, info->pa_bias_trim[i]); 632 633 if (info->pa_bias_trim[i] != 0xff) 634 info->pg_pa_bias_trim = true; 635 } 636 } 637 638 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 639 { 640 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 641 u8 pabias_2g, pabias_5g; 642 u8 i; 643 644 if (!info->pg_pa_bias_trim) { 645 rtw89_debug(rtwdev, RTW89_DBG_RFK, 646 "[PA_BIAS][TRIM] no PG, do nothing\n"); 647 648 return; 649 } 650 651 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 652 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 653 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 654 655 rtw89_debug(rtwdev, RTW89_DBG_RFK, 656 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 657 i, pabias_2g, pabias_5g); 658 659 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 660 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 661 } 662 } 663 664 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 665 { 666 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 667 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 668 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 669 670 return 0; 671 } 672 673 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 674 { 675 rtw8852c_thermal_trim(rtwdev); 676 rtw8852c_pa_bias_trim(rtwdev); 677 } 678 679 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 680 const struct rtw89_chan *chan, 681 u8 mac_idx) 682 { 683 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 684 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 685 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 686 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 687 u8 rf_mod_val = 0, chk_rate_mask = 0; 688 u32 txsc; 689 690 switch (chan->band_width) { 691 case RTW89_CHANNEL_WIDTH_160: 692 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 693 RTW89_CHANNEL_WIDTH_80); 694 fallthrough; 695 case RTW89_CHANNEL_WIDTH_80: 696 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 697 RTW89_CHANNEL_WIDTH_40); 698 fallthrough; 699 case RTW89_CHANNEL_WIDTH_40: 700 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 701 RTW89_CHANNEL_WIDTH_20); 702 break; 703 default: 704 break; 705 } 706 707 switch (chan->band_width) { 708 case RTW89_CHANNEL_WIDTH_160: 709 rf_mod_val = AX_WMAC_RFMOD_160M; 710 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 711 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 712 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 713 break; 714 case RTW89_CHANNEL_WIDTH_80: 715 rf_mod_val = AX_WMAC_RFMOD_80M; 716 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 717 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 718 break; 719 case RTW89_CHANNEL_WIDTH_40: 720 rf_mod_val = AX_WMAC_RFMOD_40M; 721 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 722 break; 723 case RTW89_CHANNEL_WIDTH_20: 724 default: 725 rf_mod_val = AX_WMAC_RFMOD_20M; 726 txsc = 0; 727 break; 728 } 729 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 730 rtw89_write32(rtwdev, sub_carr, txsc); 731 732 switch (chan->band_type) { 733 case RTW89_BAND_2G: 734 chk_rate_mask = B_AX_BAND_MODE; 735 break; 736 case RTW89_BAND_5G: 737 case RTW89_BAND_6G: 738 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 739 break; 740 default: 741 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 742 return; 743 } 744 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 745 B_AX_RTS_LIMIT_IN_OFDM6); 746 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 747 } 748 749 static const u32 rtw8852c_sco_barker_threshold[14] = { 750 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 751 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 752 }; 753 754 static const u32 rtw8852c_sco_cck_threshold[14] = { 755 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 756 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 757 }; 758 759 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 760 u8 primary_ch, enum rtw89_bandwidth bw) 761 { 762 u8 ch_element; 763 764 if (bw == RTW89_CHANNEL_WIDTH_20) { 765 ch_element = central_ch - 1; 766 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 767 if (primary_ch == 1) 768 ch_element = central_ch - 1 + 2; 769 else 770 ch_element = central_ch - 1 - 2; 771 } else { 772 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 773 return -EINVAL; 774 } 775 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 776 rtw8852c_sco_barker_threshold[ch_element]); 777 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 778 rtw8852c_sco_cck_threshold[ch_element]); 779 780 return 0; 781 } 782 783 struct rtw8852c_bb_gain { 784 u32 gain_g[BB_PATH_NUM_8852C]; 785 u32 gain_a[BB_PATH_NUM_8852C]; 786 u32 gain_mask; 787 }; 788 789 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 790 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 791 .gain_mask = 0x00ff0000 }, 792 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 793 .gain_mask = 0xff000000 }, 794 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 795 .gain_mask = 0x000000ff }, 796 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 797 .gain_mask = 0x0000ff00 }, 798 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 799 .gain_mask = 0x00ff0000 }, 800 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 801 .gain_mask = 0xff000000 }, 802 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 803 .gain_mask = 0x000000ff }, 804 }; 805 806 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 807 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 808 .gain_mask = 0x00ff0000 }, 809 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 810 .gain_mask = 0xff000000 }, 811 }; 812 813 struct rtw8852c_bb_gain_bypass { 814 u32 gain_g[BB_PATH_NUM_8852C]; 815 u32 gain_a[BB_PATH_NUM_8852C]; 816 u32 gain_mask_g; 817 u32 gain_mask_a; 818 }; 819 820 static 821 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 822 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 823 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 824 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 825 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 826 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 827 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 828 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 829 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 830 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 831 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 832 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 833 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 834 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 835 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 836 }; 837 838 struct rtw8852c_bb_gain_op1db { 839 struct { 840 u32 lna[BB_PATH_NUM_8852C]; 841 u32 tia_lna[BB_PATH_NUM_8852C]; 842 u32 mask; 843 } reg[LNA_GAIN_NUM]; 844 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 845 u32 mask_tia0_lna6; 846 }; 847 848 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 849 .reg = { 850 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 851 .mask = 0xff}, 852 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 853 .mask = 0xff00}, 854 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 855 .mask = 0xff0000}, 856 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 857 .mask = 0xff000000}, 858 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 859 .mask = 0xff}, 860 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 861 .mask = 0xff00}, 862 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 863 .mask = 0xff0000}, 864 }, 865 .reg_tia0_lna6 = {0x4674, 0x4758}, 866 .mask_tia0_lna6 = 0xff000000, 867 }; 868 869 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 870 enum rtw89_subband subband, 871 enum rtw89_rf_path path) 872 { 873 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 874 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 875 s32 val; 876 u32 reg; 877 u32 mask; 878 int i; 879 880 for (i = 0; i < LNA_GAIN_NUM; i++) { 881 if (subband == RTW89_CH_2G) 882 reg = bb_gain_lna[i].gain_g[path]; 883 else 884 reg = bb_gain_lna[i].gain_a[path]; 885 886 mask = bb_gain_lna[i].gain_mask; 887 val = gain->lna_gain[gain_band][path][i]; 888 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 889 890 if (subband == RTW89_CH_2G) { 891 reg = bb_gain_bypass_lna[i].gain_g[path]; 892 mask = bb_gain_bypass_lna[i].gain_mask_g; 893 } else { 894 reg = bb_gain_bypass_lna[i].gain_a[path]; 895 mask = bb_gain_bypass_lna[i].gain_mask_a; 896 } 897 898 val = gain->lna_gain_bypass[gain_band][path][i]; 899 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 900 901 if (subband != RTW89_CH_2G) { 902 reg = bb_gain_op1db_a.reg[i].lna[path]; 903 mask = bb_gain_op1db_a.reg[i].mask; 904 val = gain->lna_op1db[gain_band][path][i]; 905 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 906 907 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 908 mask = bb_gain_op1db_a.reg[i].mask; 909 val = gain->tia_lna_op1db[gain_band][path][i]; 910 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 911 } 912 } 913 914 if (subband != RTW89_CH_2G) { 915 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 916 mask = bb_gain_op1db_a.mask_tia0_lna6; 917 val = gain->tia_lna_op1db[gain_band][path][7]; 918 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 919 } 920 921 for (i = 0; i < TIA_GAIN_NUM; i++) { 922 if (subband == RTW89_CH_2G) 923 reg = bb_gain_tia[i].gain_g[path]; 924 else 925 reg = bb_gain_tia[i].gain_a[path]; 926 927 mask = bb_gain_tia[i].gain_mask; 928 val = gain->tia_gain[gain_band][path][i]; 929 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 930 } 931 } 932 933 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 934 const struct rtw89_chan *chan, 935 enum rtw89_phy_idx phy_idx, 936 enum rtw89_rf_path path) 937 { 938 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 939 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 940 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 941 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 942 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 943 enum rtw89_gain_offset gain_band; 944 s32 offset_q0, offset_base_q4; 945 s32 tmp = 0; 946 947 if (!efuse_gain->offset_valid) 948 return; 949 950 if (rtwdev->dbcc_en && path == RF_PATH_B) 951 phy_idx = RTW89_PHY_1; 952 953 if (chan->band_type == RTW89_BAND_2G) { 954 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 955 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 956 957 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 958 S8_MIN >> 1, S8_MAX >> 1); 959 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 960 } 961 962 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 963 964 offset_q0 = -efuse_gain->offset[path][gain_band]; 965 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 966 967 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 968 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 969 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 970 971 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 972 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 973 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 974 } 975 976 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 977 const struct rtw89_chan *chan, 978 enum rtw89_phy_idx phy_idx) 979 { 980 u8 sco; 981 u16 central_freq = chan->freq; 982 u8 central_ch = chan->channel; 983 u8 band = chan->band_type; 984 u8 subband = chan->subband_type; 985 bool is_2g = band == RTW89_BAND_2G; 986 u8 chan_idx; 987 988 if (!central_freq) { 989 rtw89_warn(rtwdev, "Invalid central_freq\n"); 990 return; 991 } 992 993 if (phy_idx == RTW89_PHY_0) { 994 /* Path A */ 995 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 996 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 997 998 if (is_2g) 999 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1000 B_PATH0_BAND_SEL_MSK_V1, 1, 1001 phy_idx); 1002 else 1003 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1004 B_PATH0_BAND_SEL_MSK_V1, 0, 1005 phy_idx); 1006 /* Path B */ 1007 if (!rtwdev->dbcc_en) { 1008 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1009 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1010 1011 if (is_2g) 1012 rtw89_phy_write32_idx(rtwdev, 1013 R_PATH1_BAND_SEL_V1, 1014 B_PATH1_BAND_SEL_MSK_V1, 1015 1, phy_idx); 1016 else 1017 rtw89_phy_write32_idx(rtwdev, 1018 R_PATH1_BAND_SEL_V1, 1019 B_PATH1_BAND_SEL_MSK_V1, 1020 0, phy_idx); 1021 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1022 } else { 1023 if (is_2g) 1024 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1025 else 1026 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1027 } 1028 /* SCO compensate FC setting */ 1029 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1030 central_freq, phy_idx); 1031 /* round_up((1/fc0)*pow(2,18)) */ 1032 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1033 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1034 phy_idx); 1035 } else { 1036 /* Path B */ 1037 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1038 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1039 1040 if (is_2g) 1041 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1042 B_PATH1_BAND_SEL_MSK_V1, 1043 1, phy_idx); 1044 else 1045 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1046 B_PATH1_BAND_SEL_MSK_V1, 1047 0, phy_idx); 1048 /* SCO compensate FC setting */ 1049 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1050 central_freq, phy_idx); 1051 /* round_up((1/fc0)*pow(2,18)) */ 1052 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1053 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1054 phy_idx); 1055 } 1056 /* CCK parameters */ 1057 if (band == RTW89_BAND_2G) { 1058 if (central_ch == 14) { 1059 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1060 B_PCOEFF01_MSK_V1, 0x3b13ff); 1061 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1062 B_PCOEFF23_MSK_V1, 0x1c42de); 1063 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1064 B_PCOEFF45_MSK_V1, 0xfdb0ad); 1065 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1066 B_PCOEFF67_MSK_V1, 0xf60f6e); 1067 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1068 B_PCOEFF89_MSK_V1, 0xfd8f92); 1069 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1070 B_PCOEFFAB_MSK_V1, 0x2d011); 1071 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1072 B_PCOEFFCD_MSK_V1, 0x1c02c); 1073 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1074 B_PCOEFFEF_MSK_V1, 0xfff00a); 1075 } else { 1076 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1077 B_PCOEFF01_MSK_V1, 0x3d23ff); 1078 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1079 B_PCOEFF23_MSK_V1, 0x29b354); 1080 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1081 B_PCOEFF45_MSK_V1, 0xfc1c8); 1082 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1083 B_PCOEFF67_MSK_V1, 0xfdb053); 1084 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1085 B_PCOEFF89_MSK_V1, 0xf86f9a); 1086 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1087 B_PCOEFFAB_MSK_V1, 0xfaef92); 1088 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1089 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1090 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1091 B_PCOEFFEF_MSK_V1, 0xffdff5); 1092 } 1093 } 1094 1095 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1096 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1097 } 1098 1099 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1100 { 1101 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1102 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1103 1104 switch (bw) { 1105 case RTW89_CHANNEL_WIDTH_5: 1106 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1107 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1108 break; 1109 case RTW89_CHANNEL_WIDTH_10: 1110 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1111 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1112 break; 1113 case RTW89_CHANNEL_WIDTH_20: 1114 case RTW89_CHANNEL_WIDTH_40: 1115 case RTW89_CHANNEL_WIDTH_80: 1116 case RTW89_CHANNEL_WIDTH_160: 1117 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1118 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1119 break; 1120 default: 1121 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1122 } 1123 } 1124 1125 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1126 enum rtw89_phy_idx phy_idx) 1127 { 1128 if (bw == RTW89_CHANNEL_WIDTH_20) { 1129 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1130 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1131 } else { 1132 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1133 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1134 } 1135 } 1136 1137 static void 1138 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1139 enum rtw89_phy_idx phy_idx) 1140 { 1141 u8 mod_sbw = 0; 1142 1143 switch (bw) { 1144 case RTW89_CHANNEL_WIDTH_5: 1145 case RTW89_CHANNEL_WIDTH_10: 1146 case RTW89_CHANNEL_WIDTH_20: 1147 if (bw == RTW89_CHANNEL_WIDTH_5) 1148 mod_sbw = 0x1; 1149 else if (bw == RTW89_CHANNEL_WIDTH_10) 1150 mod_sbw = 0x2; 1151 else if (bw == RTW89_CHANNEL_WIDTH_20) 1152 mod_sbw = 0x0; 1153 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1154 phy_idx); 1155 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1156 mod_sbw, phy_idx); 1157 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1158 phy_idx); 1159 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1160 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1161 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1162 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1163 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1164 B_PATH0_BW_SEL_MSK_V1, 0xf); 1165 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1166 B_PATH1_BW_SEL_MSK_V1, 0xf); 1167 break; 1168 case RTW89_CHANNEL_WIDTH_40: 1169 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1170 phy_idx); 1171 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1172 phy_idx); 1173 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1174 pri_ch, 1175 phy_idx); 1176 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1177 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1178 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1179 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1180 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1181 B_PATH0_BW_SEL_MSK_V1, 0xf); 1182 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1183 B_PATH1_BW_SEL_MSK_V1, 0xf); 1184 break; 1185 case RTW89_CHANNEL_WIDTH_80: 1186 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1187 phy_idx); 1188 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1189 phy_idx); 1190 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1191 pri_ch, 1192 phy_idx); 1193 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1194 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1195 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1196 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1197 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1198 B_PATH0_BW_SEL_MSK_V1, 0xd); 1199 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1200 B_PATH1_BW_SEL_MSK_V1, 0xd); 1201 break; 1202 case RTW89_CHANNEL_WIDTH_160: 1203 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1204 phy_idx); 1205 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1206 phy_idx); 1207 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1208 pri_ch, 1209 phy_idx); 1210 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1211 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1212 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1213 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1214 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1215 B_PATH0_BW_SEL_MSK_V1, 0xb); 1216 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1217 B_PATH1_BW_SEL_MSK_V1, 0xb); 1218 break; 1219 default: 1220 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1221 pri_ch); 1222 } 1223 1224 if (bw == RTW89_CHANNEL_WIDTH_40) { 1225 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1226 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1227 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1228 } else { 1229 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1230 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1231 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1232 } 1233 1234 if (phy_idx == RTW89_PHY_0) { 1235 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1236 if (!rtwdev->dbcc_en) 1237 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1238 } else { 1239 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1240 } 1241 1242 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1243 } 1244 1245 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1246 const struct rtw89_chan *chan) 1247 { 1248 u8 center_chan = chan->channel; 1249 u8 bw = chan->band_width; 1250 1251 switch (chan->band_type) { 1252 case RTW89_BAND_2G: 1253 if (bw == RTW89_CHANNEL_WIDTH_20) { 1254 if (center_chan >= 5 && center_chan <= 8) 1255 return 2440; 1256 if (center_chan == 13) 1257 return 2480; 1258 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1259 if (center_chan >= 3 && center_chan <= 10) 1260 return 2440; 1261 } 1262 break; 1263 case RTW89_BAND_5G: 1264 if (center_chan == 151 || center_chan == 153 || 1265 center_chan == 155 || center_chan == 163) 1266 return 5760; 1267 break; 1268 case RTW89_BAND_6G: 1269 if (center_chan == 195 || center_chan == 197 || 1270 center_chan == 199 || center_chan == 207) 1271 return 6920; 1272 break; 1273 default: 1274 break; 1275 } 1276 1277 return 0; 1278 } 1279 1280 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1281 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1282 #define MAX_TONE_NUM 2048 1283 1284 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1285 const struct rtw89_chan *chan, 1286 enum rtw89_phy_idx phy_idx) 1287 { 1288 u32 spur_freq; 1289 s32 freq_diff, csi_idx, csi_tone_idx; 1290 1291 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1292 if (spur_freq == 0) { 1293 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1294 return; 1295 } 1296 1297 freq_diff = (spur_freq - chan->freq) * 1000000; 1298 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1299 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1300 1301 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1302 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1303 } 1304 1305 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1306 [RF_PATH_A] = { 1307 .notch1_idx = {0x4C14, 0xFF}, 1308 .notch1_frac_idx = {0x4C14, 0xC00}, 1309 .notch1_en = {0x4C14, 0x1000}, 1310 .notch2_idx = {0x4C20, 0xFF}, 1311 .notch2_frac_idx = {0x4C20, 0xC00}, 1312 .notch2_en = {0x4C20, 0x1000}, 1313 }, 1314 [RF_PATH_B] = { 1315 .notch1_idx = {0x4CD8, 0xFF}, 1316 .notch1_frac_idx = {0x4CD8, 0xC00}, 1317 .notch1_en = {0x4CD8, 0x1000}, 1318 .notch2_idx = {0x4CE4, 0xFF}, 1319 .notch2_frac_idx = {0x4CE4, 0xC00}, 1320 .notch2_en = {0x4CE4, 0x1000}, 1321 }, 1322 }; 1323 1324 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1325 const struct rtw89_chan *chan, 1326 enum rtw89_rf_path path) 1327 { 1328 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1329 u32 spur_freq, fc; 1330 s32 freq_diff; 1331 s32 nbi_idx, nbi_tone_idx; 1332 s32 nbi_frac_idx, nbi_frac_tone_idx; 1333 bool notch2_chk = false; 1334 1335 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1336 if (spur_freq == 0) { 1337 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1338 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1339 return; 1340 } 1341 1342 fc = chan->freq; 1343 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1344 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1345 if ((fc > spur_freq && 1346 chan->channel < chan->primary_channel) || 1347 (fc < spur_freq && 1348 chan->channel > chan->primary_channel)) 1349 notch2_chk = true; 1350 } 1351 1352 freq_diff = (spur_freq - fc) * 1000000; 1353 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1354 1355 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1356 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1357 } else { 1358 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1359 128 : 256; 1360 1361 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1362 } 1363 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1364 1365 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1366 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1367 nbi->notch2_idx.mask, nbi_tone_idx); 1368 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1369 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1370 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1371 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1372 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1373 } else { 1374 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1375 nbi->notch1_idx.mask, nbi_tone_idx); 1376 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1377 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1378 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1379 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1380 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1381 } 1382 } 1383 1384 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1385 enum rtw89_phy_idx phy_idx) 1386 { 1387 u32 notch; 1388 u32 notch2; 1389 1390 if (phy_idx == RTW89_PHY_0) { 1391 notch = R_PATH0_NOTCH; 1392 notch2 = R_PATH0_NOTCH2; 1393 } else { 1394 notch = R_PATH1_NOTCH; 1395 notch2 = R_PATH1_NOTCH2; 1396 } 1397 1398 rtw89_phy_write32_mask(rtwdev, notch, 1399 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1400 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1401 rtw89_phy_write32_mask(rtwdev, notch2, 1402 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1403 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1404 } 1405 1406 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1407 const struct rtw89_chan *chan, 1408 u8 pri_ch_idx, 1409 enum rtw89_phy_idx phy_idx) 1410 { 1411 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1412 1413 if (phy_idx == RTW89_PHY_0) { 1414 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1415 (pri_ch_idx == RTW89_SC_20_LOWER || 1416 pri_ch_idx == RTW89_SC_20_UP3X)) { 1417 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1418 if (!rtwdev->dbcc_en) 1419 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1420 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1421 (pri_ch_idx == RTW89_SC_20_UPPER || 1422 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1423 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1424 if (!rtwdev->dbcc_en) 1425 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1426 } else { 1427 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1428 if (!rtwdev->dbcc_en) 1429 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1430 RF_PATH_B); 1431 } 1432 } else { 1433 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1434 (pri_ch_idx == RTW89_SC_20_LOWER || 1435 pri_ch_idx == RTW89_SC_20_UP3X)) { 1436 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1437 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1438 (pri_ch_idx == RTW89_SC_20_UPPER || 1439 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1440 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1441 } else { 1442 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1443 } 1444 } 1445 1446 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1447 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1448 else 1449 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1450 } 1451 1452 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1453 const struct rtw89_chan *chan, 1454 enum rtw89_phy_idx phy_idx) 1455 { 1456 u8 pri_ch = chan->pri_ch_idx; 1457 bool mask_5m_low; 1458 bool mask_5m_en; 1459 1460 switch (chan->band_width) { 1461 case RTW89_CHANNEL_WIDTH_40: 1462 mask_5m_en = true; 1463 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1464 break; 1465 case RTW89_CHANNEL_WIDTH_80: 1466 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1467 pri_ch == RTW89_SC_20_LOWEST; 1468 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1469 break; 1470 default: 1471 mask_5m_en = false; 1472 mask_5m_low = false; 1473 break; 1474 } 1475 1476 if (!mask_5m_en) { 1477 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1478 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1479 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1480 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1481 } else { 1482 if (mask_5m_low) { 1483 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1484 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1485 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1486 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1487 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1488 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1489 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1490 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1491 } else { 1492 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1493 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1494 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1495 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1496 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1497 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1498 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1499 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1500 } 1501 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1502 } 1503 } 1504 1505 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1506 enum rtw89_phy_idx phy_idx) 1507 { 1508 /*HW SI reset*/ 1509 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1510 0x7); 1511 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1512 0x7); 1513 1514 udelay(1); 1515 1516 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1517 phy_idx); 1518 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1519 phy_idx); 1520 /*HW SI reset*/ 1521 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1522 0x0); 1523 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1524 0x0); 1525 1526 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1527 phy_idx); 1528 } 1529 1530 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1531 enum rtw89_phy_idx phy_idx, bool en) 1532 { 1533 if (en) { 1534 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1535 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1536 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1537 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1538 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1539 phy_idx); 1540 if (band == RTW89_BAND_2G) 1541 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1542 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1543 } else { 1544 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1545 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1546 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1547 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1548 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1549 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1550 fsleep(1); 1551 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1552 phy_idx); 1553 } 1554 } 1555 1556 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1557 enum rtw89_phy_idx phy_idx) 1558 { 1559 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1560 } 1561 1562 static 1563 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1564 u8 tx_path_en, u8 trsw_tx, 1565 u8 trsw_rx, u8 trsw, u8 trsw_b) 1566 { 1567 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1568 u32 mask_ofst = 16; 1569 u32 cr; 1570 u32 val; 1571 1572 if (path >= ARRAY_SIZE(path_cr_bases)) 1573 return; 1574 1575 cr = path_cr_bases[path]; 1576 1577 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1578 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1579 1580 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1581 } 1582 1583 enum rtw8852c_rfe_src { 1584 PAPE_RFM, 1585 TRSW_RFM, 1586 LNAON_RFM, 1587 }; 1588 1589 static 1590 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1591 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1592 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1593 { 1594 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1595 static const u32 masks[] = {0, 8, 16}; 1596 u32 mask, mask_ofst; 1597 u32 cr; 1598 u32 val; 1599 1600 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1601 return; 1602 1603 mask_ofst = masks[src]; 1604 cr = path_cr_bases[path]; 1605 1606 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1607 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1608 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1609 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1610 mask = 0xff << mask_ofst; 1611 1612 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1613 } 1614 1615 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1616 { 1617 static const u32 cr_bases[] = {0x5800, 0x7800}; 1618 u32 addr; 1619 u8 i; 1620 1621 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1622 addr = cr_bases[i]; 1623 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1624 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1625 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1626 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1627 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1628 } 1629 1630 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1631 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1632 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1633 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1634 1635 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1636 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1637 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1638 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1639 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1640 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1641 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1642 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1643 1644 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1645 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1646 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1647 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1648 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1649 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1650 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1651 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1652 1653 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1654 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1655 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1656 1657 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1658 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1659 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1660 } 1661 1662 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1663 enum rtw89_phy_idx phy_idx) 1664 { 1665 u32 addr; 1666 1667 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1668 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1669 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1670 } 1671 1672 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1673 { 1674 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1675 1676 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1677 B_DBCC_80P80_SEL_EVM_RPT_EN); 1678 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1679 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1680 1681 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1682 rtw8852c_bb_gpio_init(rtwdev); 1683 1684 /* read these registers after loading BB parameters */ 1685 gain->offset_base[RTW89_PHY_0] = 1686 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1687 gain->offset_base[RTW89_PHY_1] = 1688 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1689 } 1690 1691 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1692 const struct rtw89_chan *chan, 1693 enum rtw89_phy_idx phy_idx) 1694 { 1695 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1696 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1697 struct rtw89_hal *hal = &rtwdev->hal; 1698 bool cck_en = chan->band_type == RTW89_BAND_2G; 1699 u8 pri_ch_idx = chan->pri_ch_idx; 1700 u32 mask, reg; 1701 u8 ntx_path; 1702 1703 if (chan->band_type == RTW89_BAND_2G) 1704 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1705 chan->primary_channel, 1706 chan->band_width); 1707 1708 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1709 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1710 if (cck_en) { 1711 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1712 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1713 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1714 B_PD_ARBITER_OFF, 0x0, phy_idx); 1715 } else { 1716 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1717 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1718 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1719 B_PD_ARBITER_OFF, 0x1, phy_idx); 1720 } 1721 1722 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1723 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G, 1724 RTW89_PHY_0); 1725 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1726 1727 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1728 rtwdev->hal.cv != CHIP_CAV) { 1729 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1730 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1731 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1732 if (chan->primary_channel > chan->channel) { 1733 rtw89_phy_write32_mask(rtwdev, 1734 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1735 ru_alloc_msk[phy_idx], 1); 1736 rtw89_write32_mask(rtwdev, reg, 1737 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1738 } else { 1739 rtw89_phy_write32_mask(rtwdev, 1740 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1741 ru_alloc_msk[phy_idx], 0); 1742 rtw89_write32_mask(rtwdev, reg, 1743 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1744 } 1745 } 1746 1747 if (chan->band_type == RTW89_BAND_6G && 1748 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1749 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1750 B_CDD_EVM_CHK_EN, 0, phy_idx); 1751 else 1752 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1753 B_CDD_EVM_CHK_EN, 1, phy_idx); 1754 1755 if (!rtwdev->dbcc_en) { 1756 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1757 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1758 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1759 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1760 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1761 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1762 } else { 1763 if (phy_idx == RTW89_PHY_0) { 1764 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1765 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1766 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1767 } else { 1768 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1769 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1770 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1771 } 1772 } 1773 1774 if (chan->band_type == RTW89_BAND_6G) 1775 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1776 else 1777 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1778 1779 if (hal->antenna_tx) 1780 ntx_path = hal->antenna_tx; 1781 else 1782 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1783 1784 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1785 1786 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1787 } 1788 1789 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1790 const struct rtw89_chan *chan, 1791 enum rtw89_mac_idx mac_idx, 1792 enum rtw89_phy_idx phy_idx) 1793 { 1794 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1795 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1796 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1797 } 1798 1799 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1800 { 1801 if (en) 1802 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1803 else 1804 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1805 } 1806 1807 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1808 { 1809 if (en) 1810 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1811 0x0); 1812 else 1813 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1814 0xf); 1815 } 1816 1817 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1818 struct rtw89_channel_help_params *p, 1819 const struct rtw89_chan *chan, 1820 enum rtw89_mac_idx mac_idx, 1821 enum rtw89_phy_idx phy_idx) 1822 { 1823 if (enter) { 1824 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1825 RTW89_SCH_TX_SEL_ALL); 1826 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1827 rtw8852c_dfs_en(rtwdev, false); 1828 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx, chan); 1829 rtw8852c_adc_en(rtwdev, false); 1830 fsleep(40); 1831 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1832 } else { 1833 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1834 rtw8852c_adc_en(rtwdev, true); 1835 rtw8852c_dfs_en(rtwdev, true); 1836 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx, chan); 1837 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1838 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1839 } 1840 } 1841 1842 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1843 { 1844 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1845 1846 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1847 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1848 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1849 rtw8852c_lck_init(rtwdev); 1850 rtw8852c_dpk_init(rtwdev); 1851 1852 rtw8852c_rck(rtwdev); 1853 rtw8852c_dack(rtwdev, RTW89_CHANCTX_0); 1854 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1855 } 1856 1857 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev, 1858 struct rtw89_vif_link *rtwvif_link) 1859 { 1860 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx; 1861 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 1862 1863 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1864 rtw89_btc_ntfy_conn_rfk(rtwdev, true); 1865 1866 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1867 rtw8852c_iqk(rtwdev, phy_idx, chanctx_idx); 1868 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1869 rtw8852c_tssi(rtwdev, phy_idx, chanctx_idx); 1870 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1871 rtw8852c_dpk(rtwdev, phy_idx, chanctx_idx); 1872 1873 rtw89_btc_ntfy_conn_rfk(rtwdev, false); 1874 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1875 } 1876 1877 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1878 enum rtw89_phy_idx phy_idx, 1879 const struct rtw89_chan *chan) 1880 { 1881 rtw8852c_tssi_scan(rtwdev, phy_idx, chan); 1882 } 1883 1884 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, 1885 struct rtw89_vif_link *rtwvif_link, 1886 bool start) 1887 { 1888 rtw8852c_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx); 1889 } 1890 1891 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1892 { 1893 rtw8852c_dpk_track(rtwdev); 1894 rtw8852c_lck_track(rtwdev); 1895 rtw8852c_rx_dck_track(rtwdev); 1896 } 1897 1898 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1899 enum rtw89_phy_idx phy_idx, 1900 s16 ref, u16 pwr_ofst_decrease) 1901 { 1902 u8 base_cw_0db = 0x27; 1903 u16 tssi_16dbm_cw = 0x12c; 1904 s16 pwr_s10_3 = 0; 1905 s16 rf_pwr_cw = 0; 1906 u16 bb_pwr_cw = 0; 1907 u32 pwr_cw = 0; 1908 u32 tssi_ofst_cw = 0; 1909 1910 pwr_s10_3 = (ref << 1) + (s16)(base_cw_0db << 3) - pwr_ofst_decrease; 1911 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1912 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1913 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1914 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1915 1916 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)) - 1917 pwr_ofst_decrease; 1918 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1919 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1920 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1921 1922 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1923 } 1924 1925 static 1926 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1927 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1928 { 1929 s8 pw_ofst_2tx; 1930 s8 val_1t; 1931 s8 val_2t; 1932 u32 reg; 1933 u8 i; 1934 1935 if (pw_ofst < -32 || pw_ofst > 31) { 1936 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1937 return; 1938 } 1939 val_1t = pw_ofst << 2; 1940 pw_ofst_2tx = max(pw_ofst - 3, -32); 1941 val_2t = pw_ofst_2tx << 2; 1942 1943 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1944 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1945 1946 for (i = 0; i < 4; i++) { 1947 /* 1TX */ 1948 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1949 rtw89_write32_mask(rtwdev, reg, 1950 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1951 val_1t); 1952 /* 2TX */ 1953 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1954 rtw89_write32_mask(rtwdev, reg, 1955 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1956 val_2t); 1957 } 1958 } 1959 1960 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1961 enum rtw89_phy_idx phy_idx, s16 pwr_ofst) 1962 { 1963 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1964 u16 ofst_dec[RF_PATH_NUM_8852C]; 1965 const u32 mask = 0x7FFFFFF; 1966 const u8 ofst_ofdm = 0x4; 1967 const u8 ofst_cck = 0x8; 1968 s16 ref_ofdm = 0; 1969 s16 ref_cck = 0; 1970 u32 val; 1971 u8 i; 1972 1973 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1974 1975 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1976 GENMASK(27, 10), 0x0); 1977 1978 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? 0 : abs(pwr_ofst); 1979 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ofst : 0; 1980 1981 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1982 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 1983 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm, ofst_dec[i]); 1984 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, phy_idx); 1985 } 1986 1987 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1988 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 1989 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck, ofst_dec[i]); 1990 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, phy_idx); 1991 } 1992 } 1993 1994 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1995 const struct rtw89_chan *chan, 1996 u8 tx_shape_idx, 1997 enum rtw89_phy_idx phy_idx) 1998 { 1999 #define __DFIR_CFG_MASK 0xffffff 2000 #define __DFIR_CFG_NR 8 2001 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 2002 static const u32 _prefix ## _ ## _name[] = {_val}; \ 2003 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 2004 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 2005 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 2006 2007 __DECL_DFIR_PARAM(flat, 2008 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 2009 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 2010 __DECL_DFIR_PARAM(sharp, 2011 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 2012 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 2013 __DECL_DFIR_PARAM(sharp_14, 2014 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 2015 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 2016 __DECL_DFIR_ADDR(filter, 2017 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 2018 0x45C4, 0x45C8); 2019 u8 ch = chan->channel; 2020 const u32 *param; 2021 int i; 2022 2023 if (ch > 14) { 2024 rtw89_warn(rtwdev, 2025 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 2026 return; 2027 } 2028 2029 if (ch == 14) 2030 param = param_sharp_14; 2031 else 2032 param = tx_shape_idx == 0 ? param_flat : param_sharp; 2033 2034 for (i = 0; i < __DFIR_CFG_NR; i++) { 2035 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2036 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 2037 param[i]); 2038 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 2039 param[i], phy_idx); 2040 } 2041 2042 #undef __DECL_DFIR_ADDR 2043 #undef __DECL_DFIR_PARAM 2044 #undef __DECL_DFIR_VAR 2045 #undef __DFIR_CFG_NR 2046 #undef __DFIR_CFG_MASK 2047 } 2048 2049 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 2050 const struct rtw89_chan *chan, 2051 enum rtw89_phy_idx phy_idx) 2052 { 2053 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2054 u8 band = chan->band_type; 2055 u8 regd = rtw89_regd_get(rtwdev, band); 2056 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 2057 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 2058 2059 if (band == RTW89_BAND_2G) 2060 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 2061 2062 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2063 (enum rtw89_mac_idx)phy_idx, 2064 tx_shape_ofdm); 2065 2066 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN, 2067 B_P0_DAC_COMP_POST_DPD_EN); 2068 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN, 2069 B_P1_DAC_COMP_POST_DPD_EN); 2070 } 2071 2072 static void rtw8852c_set_txpwr_diff(struct rtw89_dev *rtwdev, 2073 const struct rtw89_chan *chan, 2074 enum rtw89_phy_idx phy_idx) 2075 { 2076 s16 pwr_ofst; 2077 2078 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan); 2079 rtw8852c_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst); 2080 } 2081 2082 static void rtw8852c_set_txpwr_sar_diff(struct rtw89_dev *rtwdev, 2083 const struct rtw89_chan *chan, 2084 enum rtw89_phy_idx phy_idx) 2085 { 2086 struct rtw89_sar_parm sar_parm = { 2087 .center_freq = chan->freq, 2088 .force_path = true, 2089 }; 2090 s16 sar_rf; 2091 s8 sar_mac; 2092 2093 if (phy_idx != RTW89_PHY_0) 2094 return; 2095 2096 sar_parm.path = RF_PATH_A; 2097 sar_mac = rtw89_query_sar(rtwdev, &sar_parm); 2098 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac); 2099 rtw89_phy_write32_mask(rtwdev, R_TXPWRB, B_TXPWRB_MAX, sar_rf); 2100 2101 sar_parm.path = RF_PATH_B; 2102 sar_mac = rtw89_query_sar(rtwdev, &sar_parm); 2103 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac); 2104 rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB, B_TXPWRB_MAX, sar_rf); 2105 } 2106 2107 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 2108 const struct rtw89_chan *chan, 2109 enum rtw89_phy_idx phy_idx) 2110 { 2111 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 2112 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 2113 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 2114 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 2115 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 2116 rtw8852c_set_txpwr_diff(rtwdev, chan, phy_idx); 2117 rtw8852c_set_txpwr_sar_diff(rtwdev, chan, phy_idx); 2118 } 2119 2120 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 2121 enum rtw89_phy_idx phy_idx) 2122 { 2123 rtw8852c_set_txpwr_ref(rtwdev, phy_idx, 0); 2124 } 2125 2126 static void 2127 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2128 { 2129 static const struct rtw89_reg2_def ctrl_ini[] = { 2130 {0xD938, 0x00010100}, 2131 {0xD93C, 0x0500D500}, 2132 {0xD940, 0x00000500}, 2133 {0xD944, 0x00000005}, 2134 {0xD94C, 0x00220000}, 2135 {0xD950, 0x00030000}, 2136 }; 2137 u32 addr; 2138 int i; 2139 2140 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2141 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2142 2143 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2144 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2145 ctrl_ini[i].data); 2146 2147 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2148 (enum rtw89_mac_idx)phy_idx, 2149 RTW89_TSSI_BANDEDGE_FLAT); 2150 } 2151 2152 static int 2153 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2154 { 2155 int ret; 2156 2157 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2158 if (ret) 2159 return ret; 2160 2161 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2162 if (ret) 2163 return ret; 2164 2165 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2166 if (ret) 2167 return ret; 2168 2169 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2170 RTW89_MAC_1 : 2171 RTW89_MAC_0); 2172 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2173 2174 return 0; 2175 } 2176 2177 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2178 { 2179 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 2180 u8 band = chan->band_type; 2181 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2182 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2183 2184 if (rtwdev->dbcc_en) { 2185 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2186 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2187 RTW89_PHY_1); 2188 2189 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2190 1); 2191 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2192 1); 2193 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2194 RTW89_PHY_1); 2195 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2196 RTW89_PHY_1); 2197 2198 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2199 B_RXHT_MCS_LIMIT, 0); 2200 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2201 B_RXVHT_MCS_LIMIT, 0); 2202 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2203 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2204 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2205 2206 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2207 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2208 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2209 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2210 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2211 RTW89_PHY_1); 2212 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2213 RTW89_PHY_1); 2214 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2215 RTW89_PHY_1); 2216 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2217 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2218 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2219 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2220 } else { 2221 if (rx_path == RF_PATH_A) { 2222 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2223 B_ANT_RX_SEG0, 1); 2224 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2225 B_ANT_RX_1RCCA_SEG0, 1); 2226 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2227 B_ANT_RX_1RCCA_SEG1, 1); 2228 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2229 B_RXHT_MCS_LIMIT, 0); 2230 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2231 B_RXVHT_MCS_LIMIT, 0); 2232 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2233 0); 2234 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2235 0); 2236 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2237 rst_mask0, 1); 2238 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2239 rst_mask0, 3); 2240 } else if (rx_path == RF_PATH_B) { 2241 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2242 B_ANT_RX_SEG0, 2); 2243 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2244 B_ANT_RX_1RCCA_SEG0, 2); 2245 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2246 B_ANT_RX_1RCCA_SEG1, 2); 2247 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2248 B_RXHT_MCS_LIMIT, 0); 2249 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2250 B_RXVHT_MCS_LIMIT, 0); 2251 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2252 0); 2253 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2254 0); 2255 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2256 rst_mask1, 1); 2257 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2258 rst_mask1, 3); 2259 } else { 2260 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2261 B_ANT_RX_SEG0, 3); 2262 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2263 B_ANT_RX_1RCCA_SEG0, 3); 2264 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2265 B_ANT_RX_1RCCA_SEG1, 3); 2266 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2267 B_RXHT_MCS_LIMIT, 1); 2268 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2269 B_RXVHT_MCS_LIMIT, 1); 2270 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2271 1); 2272 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2273 1); 2274 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G, 2275 RTW89_PHY_0); 2276 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2277 rst_mask0, 1); 2278 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2279 rst_mask0, 3); 2280 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2281 rst_mask1, 1); 2282 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2283 rst_mask1, 3); 2284 } 2285 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2286 } 2287 } 2288 2289 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2290 enum rtw89_mac_idx mac_idx) 2291 { 2292 struct rtw89_reg2_def path_com[] = { 2293 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2294 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2295 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2296 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2297 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2298 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2299 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2300 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2301 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2302 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2303 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2304 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2305 }; 2306 u32 addr; 2307 u32 reg; 2308 u8 cr_size = ARRAY_SIZE(path_com); 2309 u8 i = 0; 2310 2311 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2312 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2313 2314 for (addr = R_AX_MACID_ANT_TABLE; 2315 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2316 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2317 rtw89_write32(rtwdev, reg, 0); 2318 } 2319 2320 if (tx_path == RF_A) { 2321 path_com[0].data = AX_PATH_COM0_PATHA; 2322 path_com[1].data = AX_PATH_COM1_PATHA; 2323 path_com[2].data = AX_PATH_COM2_PATHA; 2324 path_com[7].data = AX_PATH_COM7_PATHA; 2325 path_com[8].data = AX_PATH_COM8_PATHA; 2326 } else if (tx_path == RF_B) { 2327 path_com[0].data = AX_PATH_COM0_PATHB; 2328 path_com[1].data = AX_PATH_COM1_PATHB; 2329 path_com[2].data = AX_PATH_COM2_PATHB; 2330 path_com[7].data = AX_PATH_COM7_PATHB; 2331 path_com[8].data = AX_PATH_COM8_PATHB; 2332 } else if (tx_path == RF_AB) { 2333 path_com[0].data = AX_PATH_COM0_PATHAB; 2334 path_com[1].data = AX_PATH_COM1_PATHAB; 2335 path_com[2].data = AX_PATH_COM2_PATHAB; 2336 path_com[7].data = AX_PATH_COM7_PATHAB; 2337 path_com[8].data = AX_PATH_COM8_PATHAB; 2338 } else { 2339 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2340 return; 2341 } 2342 2343 for (i = 0; i < cr_size; i++) { 2344 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2345 path_com[i].addr, path_com[i].data); 2346 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2347 rtw89_write32(rtwdev, reg, path_com[i].data); 2348 } 2349 } 2350 2351 static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 2352 enum rtw89_phy_idx phy_idx) 2353 { 2354 if (en) { 2355 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2356 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2357 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2358 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2359 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2360 B_PATH0_RXBB_MSK_V1, 0xf); 2361 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2362 B_PATH1_RXBB_MSK_V1, 0xf); 2363 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2364 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2365 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2366 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2367 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2368 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2369 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2370 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2371 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2372 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2373 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2374 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2375 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2376 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2377 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2378 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2379 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2380 B_P0_BACKOFF_IBADC_V1, 0x34); 2381 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2382 B_P1_BACKOFF_IBADC_V1, 0x34); 2383 } else { 2384 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2385 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2386 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2387 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2388 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2389 B_PATH0_RXBB_MSK_V1, 0x60); 2390 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2391 B_PATH1_RXBB_MSK_V1, 0x60); 2392 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2393 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2394 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2395 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2396 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2397 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2398 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2399 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2400 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2401 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2402 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2403 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2404 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2405 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2406 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2407 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2408 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2409 B_P0_BACKOFF_IBADC_V1, 0x26); 2410 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2411 B_P1_BACKOFF_IBADC_V1, 0x26); 2412 } 2413 } 2414 2415 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2416 { 2417 struct rtw89_hal *hal = &rtwdev->hal; 2418 2419 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2420 2421 if (hal->rx_nss == 1) { 2422 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2423 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2424 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2425 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2426 } else { 2427 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2428 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2429 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2430 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2431 } 2432 } 2433 2434 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2435 { 2436 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2437 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2438 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2439 2440 fsleep(200); 2441 2442 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2443 } 2444 2445 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2446 { 2447 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2448 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 2449 2450 if (ver->fcxinit == 7) { 2451 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 2452 md->md_v7.kt_ver = rtwdev->hal.cv; 2453 md->md_v7.bt_solo = 0; 2454 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 2455 2456 if (md->md_v7.rfe_type > 0) 2457 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 2458 else 2459 md->md_v7.ant.num = 2; 2460 2461 md->md_v7.ant.diversity = 0; 2462 md->md_v7.ant.isolation = 10; 2463 2464 if (md->md_v7.ant.num == 3) { 2465 md->md_v7.ant.type = BTC_ANT_DEDICATED; 2466 md->md_v7.bt_pos = BTC_BT_ALONE; 2467 } else { 2468 md->md_v7.ant.type = BTC_ANT_SHARED; 2469 md->md_v7.bt_pos = BTC_BT_BTG; 2470 } 2471 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 2472 rtwdev->btc.ant_type = md->md_v7.ant.type; 2473 } else { 2474 md->md.rfe_type = rtwdev->efuse.rfe_type; 2475 md->md.cv = rtwdev->hal.cv; 2476 md->md.bt_solo = 0; 2477 md->md.switch_type = BTC_SWITCH_INTERNAL; 2478 2479 if (md->md.rfe_type > 0) 2480 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 2481 else 2482 md->md.ant.num = 2; 2483 2484 md->md.ant.diversity = 0; 2485 md->md.ant.isolation = 10; 2486 2487 if (md->md.ant.num == 3) { 2488 md->md.ant.type = BTC_ANT_DEDICATED; 2489 md->md.bt_pos = BTC_BT_ALONE; 2490 } else { 2491 md->md.ant.type = BTC_ANT_SHARED; 2492 md->md.bt_pos = BTC_BT_BTG; 2493 } 2494 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2495 rtwdev->btc.ant_type = md->md.ant.type; 2496 } 2497 } 2498 2499 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 2500 enum rtw89_phy_idx phy_idx) 2501 { 2502 if (en) { 2503 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2504 B_PATH0_BT_SHARE_V1, 0x1); 2505 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2506 B_PATH0_BTG_PATH_V1, 0x0); 2507 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2508 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2509 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2510 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2511 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2512 B_PATH1_BT_SHARE_V1, 0x1); 2513 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2514 B_PATH1_BTG_PATH_V1, 0x1); 2515 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2516 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2517 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2518 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2519 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2520 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2521 0x1); 2522 } else { 2523 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2524 B_PATH0_BT_SHARE_V1, 0x0); 2525 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2526 B_PATH0_BTG_PATH_V1, 0x0); 2527 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2528 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2529 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2530 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2531 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2532 B_PATH1_BT_SHARE_V1, 0x0); 2533 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2534 B_PATH1_BTG_PATH_V1, 0x0); 2535 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2536 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2537 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2538 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2539 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2540 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2541 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2542 0x0); 2543 } 2544 } 2545 2546 static 2547 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2548 { 2549 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2550 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2551 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2552 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2553 } 2554 2555 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2556 { 2557 struct rtw89_btc *btc = &rtwdev->btc; 2558 const struct rtw89_chip_info *chip = rtwdev->chip; 2559 const struct rtw89_mac_ax_coex coex_params = { 2560 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2561 .direction = RTW89_MAC_AX_COEX_INNER, 2562 }; 2563 2564 /* PTA init */ 2565 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2566 2567 /* set WL Tx response = Hi-Pri */ 2568 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2569 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2570 2571 /* set rf gnt debug off */ 2572 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2573 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2574 2575 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2576 if (btc->ant_type == BTC_ANT_SHARED) { 2577 rtw8852c_set_trx_mask(rtwdev, 2578 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2579 rtw8852c_set_trx_mask(rtwdev, 2580 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2581 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2582 rtw8852c_set_trx_mask(rtwdev, 2583 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2584 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2585 rtw8852c_set_trx_mask(rtwdev, 2586 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2587 rtw8852c_set_trx_mask(rtwdev, 2588 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2589 } 2590 2591 /* set PTA break table */ 2592 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2593 2594 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2595 rtw89_write32_set(rtwdev, 2596 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2597 B_AX_BT_CNT_RST_V1); 2598 btc->cx.wl.status.map.init_ok = true; 2599 } 2600 2601 static 2602 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2603 { 2604 u32 bitmap = 0; 2605 u32 reg = 0; 2606 2607 switch (map) { 2608 case BTC_PRI_MASK_TX_RESP: 2609 reg = R_BTC_COEX_WL_REQ; 2610 bitmap = B_BTC_RSP_ACK_HI; 2611 break; 2612 case BTC_PRI_MASK_BEACON: 2613 reg = R_BTC_COEX_WL_REQ; 2614 bitmap = B_BTC_TX_BCN_HI; 2615 break; 2616 default: 2617 return; 2618 } 2619 2620 if (state) 2621 rtw89_write32_set(rtwdev, reg, bitmap); 2622 else 2623 rtw89_write32_clr(rtwdev, reg, bitmap); 2624 } 2625 2626 union rtw8852c_btc_wl_txpwr_ctrl { 2627 u32 txpwr_val; 2628 struct { 2629 union { 2630 u16 ctrl_all_time; 2631 struct { 2632 s16 data:9; 2633 u16 rsvd:6; 2634 u16 flag:1; 2635 } all_time; 2636 }; 2637 union { 2638 u16 ctrl_gnt_bt; 2639 struct { 2640 s16 data:9; 2641 u16 rsvd:7; 2642 } gnt_bt; 2643 }; 2644 }; 2645 } __packed; 2646 2647 static void 2648 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2649 { 2650 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2651 s32 val; 2652 2653 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2654 do { \ 2655 u32 _wrt = FIELD_PREP(_msk, _val); \ 2656 BUILD_BUG_ON((_msk & _en) != 0); \ 2657 if (_cond) \ 2658 _wrt |= _en; \ 2659 else \ 2660 _wrt &= ~_en; \ 2661 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2662 _msk | _en, _wrt); \ 2663 } while (0) 2664 2665 switch (arg.ctrl_all_time) { 2666 case 0xffff: 2667 val = 0; 2668 break; 2669 default: 2670 val = arg.all_time.data; 2671 break; 2672 } 2673 2674 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2675 val, B_AX_FORCE_PWR_BY_RATE_EN, 2676 arg.ctrl_all_time != 0xffff); 2677 2678 switch (arg.ctrl_gnt_bt) { 2679 case 0xffff: 2680 val = 0; 2681 break; 2682 default: 2683 val = arg.gnt_bt.data; 2684 break; 2685 } 2686 2687 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2688 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2689 2690 #undef __write_ctrl 2691 } 2692 2693 static 2694 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2695 { 2696 /* +6 for compensate offset */ 2697 return clamp_t(s8, val + 6, -100, 0) + 100; 2698 } 2699 2700 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2701 {255, 0, 0, 7}, /* 0 -> original */ 2702 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2703 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2704 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2705 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2706 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2707 {6, 1, 0, 7}, 2708 {13, 1, 0, 7}, 2709 {13, 1, 0, 7} 2710 }; 2711 2712 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2713 {255, 0, 0, 7}, /* 0 -> original */ 2714 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2715 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2716 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2717 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2718 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2719 {255, 1, 0, 7}, 2720 {255, 1, 0, 7}, 2721 {255, 1, 0, 7} 2722 }; 2723 2724 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2725 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2726 2727 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2728 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2729 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2730 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2731 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2732 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2733 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2734 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2735 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2736 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2737 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2738 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2739 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2740 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2741 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2742 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2743 }; 2744 2745 static 2746 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2747 { 2748 /* Feature move to firmware */ 2749 } 2750 2751 static 2752 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2753 { 2754 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2755 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2756 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2757 2758 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2759 if (state) 2760 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2761 RFREG_MASK, 0x179c); 2762 else 2763 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2764 RFREG_MASK, 0x208); 2765 2766 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2767 } 2768 2769 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2770 { 2771 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2772 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2773 * To improve BT ACI in co-rx 2774 */ 2775 2776 switch (level) { 2777 case 0: /* default */ 2778 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2779 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2780 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2781 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2782 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2783 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2784 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2785 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2786 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2787 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2788 break; 2789 case 1: /* Fix LNA2=5 */ 2790 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2791 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2792 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2793 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2794 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2795 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2796 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2797 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2798 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2799 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2800 break; 2801 } 2802 } 2803 2804 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2805 { 2806 struct rtw89_btc *btc = &rtwdev->btc; 2807 2808 switch (level) { 2809 case 0: /* original */ 2810 default: 2811 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2812 btc->dm.wl_lna2 = 0; 2813 break; 2814 case 1: /* for FDD free-run */ 2815 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2816 btc->dm.wl_lna2 = 0; 2817 break; 2818 case 2: /* for BTG Co-Rx*/ 2819 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2820 btc->dm.wl_lna2 = 1; 2821 break; 2822 } 2823 2824 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2825 } 2826 2827 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2828 struct rtw89_rx_phy_ppdu *phy_ppdu, 2829 struct ieee80211_rx_status *status) 2830 { 2831 u8 chan_idx = phy_ppdu->chan_idx; 2832 enum nl80211_band band; 2833 u8 ch; 2834 2835 if (chan_idx == 0) 2836 return; 2837 2838 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2839 status->freq = ieee80211_channel_to_frequency(ch, band); 2840 status->band = band; 2841 } 2842 2843 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2844 struct rtw89_rx_phy_ppdu *phy_ppdu, 2845 struct ieee80211_rx_status *status) 2846 { 2847 u8 path; 2848 u8 *rx_power = phy_ppdu->rssi; 2849 2850 if (!status->signal) 2851 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], 2852 rx_power[RF_PATH_B])); 2853 2854 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2855 status->chains |= BIT(path); 2856 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2857 } 2858 if (phy_ppdu->valid) 2859 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2860 } 2861 2862 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2863 { 2864 int ret; 2865 2866 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2867 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2868 2869 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2870 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2871 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2872 2873 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2874 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2875 2876 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2877 if (ret) 2878 return ret; 2879 2880 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2881 if (ret) 2882 return ret; 2883 2884 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2885 if (ret) 2886 return ret; 2887 2888 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2889 if (ret) 2890 return ret; 2891 2892 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2893 if (ret) 2894 return ret; 2895 2896 return 0; 2897 } 2898 2899 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2900 { 2901 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2902 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2903 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2904 2905 return 0; 2906 } 2907 2908 static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = { 2909 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb, 2910 .callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb, 2911 }; 2912 2913 #ifdef CONFIG_PM 2914 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2915 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT | 2916 WIPHY_WOWLAN_NET_DETECT, 2917 .n_patterns = RTW89_MAX_PATTERN_NUM, 2918 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2919 .pattern_min_len = 1, 2920 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID, 2921 }; 2922 #endif 2923 2924 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2925 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2926 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2927 .bb_preinit = NULL, 2928 .bb_postinit = NULL, 2929 .bb_reset = rtw8852c_bb_reset, 2930 .bb_sethw = rtw8852c_bb_sethw, 2931 .read_rf = rtw89_phy_read_rf_v1, 2932 .write_rf = rtw89_phy_write_rf_v1, 2933 .set_channel = rtw8852c_set_channel, 2934 .set_channel_help = rtw8852c_set_channel_help, 2935 .read_efuse = rtw8852c_read_efuse, 2936 .read_phycap = rtw8852c_read_phycap, 2937 .fem_setup = NULL, 2938 .rfe_gpio = NULL, 2939 .rfk_hw_init = NULL, 2940 .rfk_init = rtw8852c_rfk_init, 2941 .rfk_init_late = NULL, 2942 .rfk_channel = rtw8852c_rfk_channel, 2943 .rfk_band_changed = rtw8852c_rfk_band_changed, 2944 .rfk_scan = rtw8852c_rfk_scan, 2945 .rfk_track = rtw8852c_rfk_track, 2946 .power_trim = rtw8852c_power_trim, 2947 .set_txpwr = rtw8852c_set_txpwr, 2948 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2949 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2950 .get_thermal = rtw8852c_get_thermal, 2951 .chan_to_rf18_val = NULL, 2952 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx, 2953 .query_ppdu = rtw8852c_query_ppdu, 2954 .convert_rpl_to_rssi = NULL, 2955 .phy_rpt_to_rssi = NULL, 2956 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx, 2957 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2958 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2959 .digital_pwr_comp = NULL, 2960 .pwr_on_func = rtw8852c_pwr_on_func, 2961 .pwr_off_func = rtw8852c_pwr_off_func, 2962 .query_rxdesc = rtw89_core_query_rxdesc, 2963 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2964 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2965 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2966 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2967 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2968 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2969 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2970 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2971 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2972 .h2c_ampdu_cmac_tbl = NULL, 2973 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl, 2974 .h2c_punctured_cmac_tbl = NULL, 2975 .h2c_default_dmac_tbl = NULL, 2976 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2977 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2978 2979 .btc_set_rfe = rtw8852c_btc_set_rfe, 2980 .btc_init_cfg = rtw8852c_btc_init_cfg, 2981 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2982 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2983 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2984 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2985 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2986 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2987 .btc_set_policy = rtw89_btc_set_policy_v1, 2988 }; 2989 2990 const struct rtw89_chip_info rtw8852c_chip_info = { 2991 .chip_id = RTL8852C, 2992 .chip_gen = RTW89_CHIP_AX, 2993 .ops = &rtw8852c_chip_ops, 2994 .mac_def = &rtw89_mac_gen_ax, 2995 .phy_def = &rtw89_phy_gen_ax, 2996 .fw_basename = RTW8852C_FW_BASENAME, 2997 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2998 .try_ce_fw = false, 2999 .bbmcu_nr = 0, 3000 .needed_fw_elms = 0, 3001 .fw_blacklist = &rtw89_fw_blacklist_default, 3002 .fifo_size = 458752, 3003 .small_fifo_size = false, 3004 .dle_scc_rsvd_size = 0, 3005 .max_amsdu_limit = 8000, 3006 .dis_2g_40m_ul_ofdma = false, 3007 .rsvd_ple_ofst = 0x6f800, 3008 .hfc_param_ini = {rtw8852c_hfc_param_ini_pcie, NULL, NULL}, 3009 .dle_mem = {rtw8852c_dle_mem_pcie, NULL, NULL, NULL}, 3010 .wde_qempty_acq_grpnum = 16, 3011 .wde_qempty_mgq_grpsel = 16, 3012 .rf_base_addr = {0xe000, 0xf000}, 3013 .thermal_th = {0x32, 0x35}, 3014 .pwr_on_seq = NULL, 3015 .pwr_off_seq = NULL, 3016 .bb_table = &rtw89_8852c_phy_bb_table, 3017 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 3018 .rf_table = {&rtw89_8852c_phy_radiob_table, 3019 &rtw89_8852c_phy_radioa_table,}, 3020 .nctl_table = &rtw89_8852c_phy_nctl_table, 3021 .nctl_post_table = NULL, 3022 .dflt_parms = &rtw89_8852c_dflt_parms, 3023 .rfe_parms_conf = NULL, 3024 .chanctx_listener = &rtw8852c_chanctx_listener, 3025 .txpwr_factor_bb = 3, 3026 .txpwr_factor_rf = 2, 3027 .txpwr_factor_mac = 1, 3028 .dig_table = NULL, 3029 .dig_regs = &rtw8852c_dig_regs, 3030 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 3031 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 3032 .support_link_num = 0, 3033 .support_chanctx_num = 2, 3034 .support_rnr = false, 3035 .support_bands = BIT(NL80211_BAND_2GHZ) | 3036 BIT(NL80211_BAND_5GHZ) | 3037 BIT(NL80211_BAND_6GHZ), 3038 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 3039 BIT(NL80211_CHAN_WIDTH_40) | 3040 BIT(NL80211_CHAN_WIDTH_80) | 3041 BIT(NL80211_CHAN_WIDTH_160), 3042 .support_unii4 = true, 3043 .support_ant_gain = true, 3044 .support_tas = true, 3045 .support_sar_by_ant = true, 3046 .ul_tb_waveform_ctrl = false, 3047 .ul_tb_pwr_diff = true, 3048 .rx_freq_frome_ie = false, 3049 .hw_sec_hdr = true, 3050 .hw_mgmt_tx_encrypt = true, 3051 .hw_tkip_crypto = true, 3052 .hw_mlo_bmc_crypto = false, 3053 .rf_path_num = 2, 3054 .tx_nss = 2, 3055 .rx_nss = 2, 3056 .acam_num = 128, 3057 .bcam_num = 20, 3058 .scam_num = 128, 3059 .bacam_num = 8, 3060 .bacam_dynamic_num = 8, 3061 .bacam_ver = RTW89_BACAM_V0_EXT, 3062 .ppdu_max_usr = 8, 3063 .sec_ctrl_efuse_size = 4, 3064 .physical_efuse_size = 1216, 3065 .logical_efuse_size = 2048, 3066 .limit_efuse_size = 1280, 3067 .dav_phy_efuse_size = 96, 3068 .dav_log_efuse_size = 16, 3069 .efuse_blocks = NULL, 3070 .phycap_addr = 0x590, 3071 .phycap_size = 0x60, 3072 .para_ver = 0x1, 3073 .wlcx_desired = 0x06000000, 3074 .scbd = 0x1, 3075 .mailbox = 0x1, 3076 3077 .afh_guard_ch = 6, 3078 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 3079 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 3080 .rssi_tol = 2, 3081 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 3082 .mon_reg = rtw89_btc_8852c_mon_reg, 3083 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 3084 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 3085 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 3086 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 3087 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 3088 BIT(RTW89_PS_MODE_CLK_GATED) | 3089 BIT(RTW89_PS_MODE_PWR_GATED), 3090 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 3091 BIT(RTW89_PS_MODE_PWR_GATED), 3092 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 3093 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 3094 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 3095 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 3096 .txwd_info_size = sizeof(struct rtw89_txwd_info), 3097 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 3098 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 3099 .h2c_regs = rtw8852c_h2c_regs, 3100 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 3101 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 3102 .c2h_regs = rtw8852c_c2h_regs, 3103 .page_regs = &rtw8852c_page_regs, 3104 .wow_reason_reg = rtw8852c_wow_wakeup_regs, 3105 .cfo_src_fd = false, 3106 .cfo_hw_comp = false, 3107 .dcfo_comp = &rtw8852c_dcfo_comp, 3108 .dcfo_comp_sft = 12, 3109 .imr_info = &rtw8852c_imr_info, 3110 .imr_dmac_table = NULL, 3111 .imr_cmac_table = NULL, 3112 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 3113 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 3114 .bss_clr_map_reg = R_BSS_CLR_MAP, 3115 .rfkill_init = &rtw8852c_rfkill_regs, 3116 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 3117 .dma_ch_mask = 0, 3118 .edcca_regs = &rtw8852c_edcca_regs, 3119 #ifdef CONFIG_PM 3120 .wowlan_stub = &rtw_wowlan_stub_8852c, 3121 #endif 3122 .xtal_info = NULL, 3123 }; 3124 EXPORT_SYMBOL(rtw8852c_chip_info); 3125 3126 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 3127 MODULE_AUTHOR("Realtek Corporation"); 3128 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 3129 MODULE_LICENSE("Dual BSD/GPL"); 3130