1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "reg.h" 12 #include "rtw8852c.h" 13 #include "rtw8852c_rfk.h" 14 #include "rtw8852c_table.h" 15 #include "util.h" 16 17 #define RTW8852C_FW_FORMAT_MAX 1 18 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 19 #define RTW8852C_MODULE_FIRMWARE \ 20 RTW8852C_FW_BASENAME "-" __stringify(RTW8852C_FW_FORMAT_MAX) ".bin" 21 22 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 23 {13, 1614, grp_0}, /* ACH 0 */ 24 {13, 1614, grp_0}, /* ACH 1 */ 25 {13, 1614, grp_0}, /* ACH 2 */ 26 {13, 1614, grp_0}, /* ACH 3 */ 27 {13, 1614, grp_1}, /* ACH 4 */ 28 {13, 1614, grp_1}, /* ACH 5 */ 29 {13, 1614, grp_1}, /* ACH 6 */ 30 {13, 1614, grp_1}, /* ACH 7 */ 31 {13, 1614, grp_0}, /* B0MGQ */ 32 {13, 1614, grp_0}, /* B0HIQ */ 33 {13, 1614, grp_1}, /* B1MGQ */ 34 {13, 1614, grp_1}, /* B1HIQ */ 35 {40, 0, 0} /* FWCMDQ */ 36 }; 37 38 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 39 1614, /* Group 0 */ 40 1614, /* Group 1 */ 41 3228, /* Public Max */ 42 0 /* WP threshold */ 43 }; 44 45 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 46 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 47 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 48 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 49 RTW89_HCIFC_POH}, 50 [RTW89_QTA_INVALID] = {NULL}, 51 }; 52 53 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 54 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 55 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 56 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 57 &rtw89_mac_size.ple_qt47}, 58 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 59 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 60 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 61 &rtw89_mac_size.ple_qt45}, 62 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 63 NULL}, 64 }; 65 66 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 67 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 68 R_AX_H2CREG_DATA3_V1 69 }; 70 71 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 72 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 73 R_AX_C2HREG_DATA3_V1 74 }; 75 76 static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 77 R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW, 78 }; 79 80 static const struct rtw89_page_regs rtw8852c_page_regs = { 81 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 82 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 83 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 84 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 85 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 86 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 87 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 88 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 89 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 90 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 91 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 92 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 93 }; 94 95 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 96 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 97 }; 98 99 static const struct rtw89_imr_info rtw8852c_imr_info = { 100 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 101 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 102 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 103 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 104 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 105 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 106 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 107 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 108 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 109 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 110 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 111 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 112 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 113 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 114 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 115 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 116 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 117 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 118 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 119 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 120 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 121 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 122 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 123 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 124 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 125 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 126 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 127 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 128 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 129 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 130 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 131 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 132 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 133 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 134 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 135 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 136 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 137 .rmac_imr_reg = R_AX_RX_ERR_IMR, 138 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 139 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 140 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 141 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 142 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 143 }; 144 145 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 146 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 147 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 148 }; 149 150 static const struct rtw89_rfkill_regs rtw8852c_rfkill_regs = { 151 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 152 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 153 0xf}, 154 .mode = {R_AX_GPIO_EXT_CTRL + 2, 155 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 156 0x0}, 157 }; 158 159 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 160 .seg0_pd_reg = R_SEG0R_PD, 161 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 162 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 163 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 164 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 165 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 166 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 167 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 168 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 169 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 170 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 171 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 172 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 173 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 174 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 175 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 176 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 177 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 178 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 179 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 180 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 181 }; 182 183 static const struct rtw89_edcca_regs rtw8852c_edcca_regs = { 184 .edcca_level = R_SEG0R_EDCCA_LVL, 185 .edcca_mask = B_EDCCA_LVL_MSK0, 186 .edcca_p_mask = B_EDCCA_LVL_MSK1, 187 .ppdu_level = R_SEG0R_EDCCA_LVL, 188 .ppdu_mask = B_EDCCA_LVL_MSK3, 189 .p = {{ 190 .rpt_a = R_EDCCA_RPT_A, 191 .rpt_b = R_EDCCA_RPT_B, 192 .rpt_sel = R_EDCCA_RPT_SEL, 193 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 194 }, { 195 .rpt_a = R_EDCCA_RPT_P1_A, 196 .rpt_b = R_EDCCA_RPT_P1_B, 197 .rpt_sel = R_EDCCA_RPT_SEL, 198 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK, 199 }}, 200 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 201 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 202 }; 203 204 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 205 enum rtw89_phy_idx phy_idx); 206 207 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 208 enum rtw89_mac_idx mac_idx); 209 210 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 211 { 212 u32 val32; 213 int ret; 214 215 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 216 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 217 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 218 219 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 220 B_AX_AFSM_PCIE_SUS_EN); 221 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 222 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 223 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 224 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 225 226 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 227 B_AX_OCP_L1_MASK, 0x7); 228 229 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 230 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 231 if (ret) 232 return ret; 233 234 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 235 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 236 237 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 238 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 239 if (ret) 240 return ret; 241 242 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 243 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 244 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 245 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 246 247 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 248 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 249 250 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 251 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 252 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 253 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 254 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 255 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 256 B_AX_R_SYM_WLCMAC1_PC_EN); 257 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 258 259 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 260 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 261 if (ret) 262 return ret; 263 264 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 265 266 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 267 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 268 if (ret) 269 return ret; 270 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 271 XTAL_SI_OFF_WEI); 272 if (ret) 273 return ret; 274 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 275 XTAL_SI_OFF_EI); 276 if (ret) 277 return ret; 278 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 279 if (ret) 280 return ret; 281 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 282 XTAL_SI_PON_WEI); 283 if (ret) 284 return ret; 285 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 286 XTAL_SI_PON_EI); 287 if (ret) 288 return ret; 289 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 290 if (ret) 291 return ret; 292 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0x10, XTAL_SI_LDO_LPS); 293 if (ret) 294 return ret; 295 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 296 if (ret) 297 return ret; 298 299 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 300 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 301 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 302 303 fsleep(1000); 304 305 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 306 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 307 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 308 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 309 B_AX_LED1_PULL_LOW_EN); 310 311 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 312 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 313 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 314 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 315 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 316 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 317 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 318 319 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 320 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 321 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 322 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 323 B_AX_TMAC_EN | B_AX_RMAC_EN); 324 325 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 326 PINMUX_EESK_FUNC_SEL_BT_LOG); 327 328 return 0; 329 } 330 331 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 332 { 333 u32 val32; 334 int ret; 335 336 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 337 XTAL_SI_RFC2RF); 338 if (ret) 339 return ret; 340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 341 if (ret) 342 return ret; 343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 344 if (ret) 345 return ret; 346 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 347 if (ret) 348 return ret; 349 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 350 if (ret) 351 return ret; 352 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 353 XTAL_SI_SRAM2RFC); 354 if (ret) 355 return ret; 356 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 357 if (ret) 358 return ret; 359 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 360 if (ret) 361 return ret; 362 363 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 364 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 365 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 366 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 367 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 368 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 369 370 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 371 if (ret) 372 return ret; 373 374 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 375 376 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 377 if (ret) 378 return ret; 379 380 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 381 382 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 383 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 384 if (ret) 385 return ret; 386 387 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 388 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 389 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 390 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 391 B_AX_REG_ZCDC_H_MASK, 0x3); 392 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 393 394 return 0; 395 } 396 397 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 398 struct rtw8852c_efuse *map) 399 { 400 ether_addr_copy(efuse->addr, map->e.mac_addr); 401 efuse->rfe_type = map->rfe_type; 402 efuse->xtal_cap = map->xtal_k; 403 } 404 405 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 406 struct rtw8852c_efuse *map) 407 { 408 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 409 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 410 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 411 u8 i, j; 412 413 tssi->thermal[RF_PATH_A] = map->path_a_therm; 414 tssi->thermal[RF_PATH_B] = map->path_b_therm; 415 416 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 417 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 418 sizeof(ofst[i]->cck_tssi)); 419 420 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 421 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 422 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 423 i, j, tssi->tssi_cck[i][j]); 424 425 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 426 sizeof(ofst[i]->bw40_tssi)); 427 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 428 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 429 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 430 sizeof(tssi->tssi_6g_mcs[i])); 431 432 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 433 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 434 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 435 i, j, tssi->tssi_mcs[i][j]); 436 } 437 } 438 439 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 440 { 441 if (high) 442 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 443 if (low) 444 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 445 446 return data != 0xff; 447 } 448 449 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 450 struct rtw8852c_efuse *map) 451 { 452 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 453 bool valid = false; 454 455 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 456 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 457 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 458 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 459 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 460 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 461 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 462 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 463 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 464 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 465 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 466 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 467 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 468 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 469 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 470 valid |= _decode_efuse_gain(map->rx_gain_6g_l0, 471 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0], 472 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]); 473 valid |= _decode_efuse_gain(map->rx_gain_6g_l1, 474 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1], 475 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]); 476 valid |= _decode_efuse_gain(map->rx_gain_6g_m0, 477 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0], 478 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]); 479 valid |= _decode_efuse_gain(map->rx_gain_6g_m1, 480 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1], 481 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]); 482 valid |= _decode_efuse_gain(map->rx_gain_6g_h0, 483 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0], 484 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]); 485 valid |= _decode_efuse_gain(map->rx_gain_6g_h1, 486 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1], 487 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]); 488 valid |= _decode_efuse_gain(map->rx_gain_6g_uh0, 489 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0], 490 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]); 491 valid |= _decode_efuse_gain(map->rx_gain_6g_uh1, 492 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1], 493 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]); 494 495 gain->offset_valid = valid; 496 } 497 498 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 499 enum rtw89_efuse_block block) 500 { 501 struct rtw89_efuse *efuse = &rtwdev->efuse; 502 struct rtw8852c_efuse *map; 503 504 map = (struct rtw8852c_efuse *)log_map; 505 506 efuse->country_code[0] = map->country_code[0]; 507 efuse->country_code[1] = map->country_code[1]; 508 rtw8852c_efuse_parsing_tssi(rtwdev, map); 509 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 510 511 switch (rtwdev->hci.type) { 512 case RTW89_HCI_TYPE_PCIE: 513 rtw8852c_e_efuse_parsing(efuse, map); 514 break; 515 default: 516 return -ENOTSUPP; 517 } 518 519 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 520 521 return 0; 522 } 523 524 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 525 { 526 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 527 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 528 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 529 u32 addr = rtwdev->chip->phycap_addr; 530 bool pg = false; 531 u32 ofst; 532 u8 i, j; 533 534 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 535 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 536 /* addrs are in decreasing order */ 537 ofst = tssi_trim_addr[i] - addr - j; 538 tssi->tssi_trim[i][j] = phycap_map[ofst]; 539 540 if (phycap_map[ofst] != 0xff) 541 pg = true; 542 } 543 544 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 545 /* addrs are in decreasing order */ 546 ofst = tssi_trim_addr_6g[i] - addr - j; 547 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 548 549 if (phycap_map[ofst] != 0xff) 550 pg = true; 551 } 552 } 553 554 if (!pg) { 555 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 556 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 557 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 558 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 559 } 560 561 for (i = 0; i < RF_PATH_NUM_8852C; i++) 562 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 563 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 564 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 565 i, j, tssi->tssi_trim[i][j], 566 tssi_trim_addr[i] - j); 567 } 568 569 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 570 u8 *phycap_map) 571 { 572 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 573 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 574 u32 addr = rtwdev->chip->phycap_addr; 575 u8 i; 576 577 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 578 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 579 580 rtw89_debug(rtwdev, RTW89_DBG_RFK, 581 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 582 i, info->thermal_trim[i]); 583 584 if (info->thermal_trim[i] != 0xff) 585 info->pg_thermal_trim = true; 586 } 587 } 588 589 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 590 { 591 #define __thm_setting(raw) \ 592 ({ \ 593 u8 __v = (raw); \ 594 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 595 }) 596 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 597 u8 i, val; 598 599 if (!info->pg_thermal_trim) { 600 rtw89_debug(rtwdev, RTW89_DBG_RFK, 601 "[THERMAL][TRIM] no PG, do nothing\n"); 602 603 return; 604 } 605 606 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 607 val = __thm_setting(info->thermal_trim[i]); 608 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 609 610 rtw89_debug(rtwdev, RTW89_DBG_RFK, 611 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 612 i, val); 613 } 614 #undef __thm_setting 615 } 616 617 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 618 u8 *phycap_map) 619 { 620 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 621 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 622 u32 addr = rtwdev->chip->phycap_addr; 623 u8 i; 624 625 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 626 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 627 628 rtw89_debug(rtwdev, RTW89_DBG_RFK, 629 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 630 i, info->pa_bias_trim[i]); 631 632 if (info->pa_bias_trim[i] != 0xff) 633 info->pg_pa_bias_trim = true; 634 } 635 } 636 637 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 638 { 639 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 640 u8 pabias_2g, pabias_5g; 641 u8 i; 642 643 if (!info->pg_pa_bias_trim) { 644 rtw89_debug(rtwdev, RTW89_DBG_RFK, 645 "[PA_BIAS][TRIM] no PG, do nothing\n"); 646 647 return; 648 } 649 650 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 651 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 652 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 653 654 rtw89_debug(rtwdev, RTW89_DBG_RFK, 655 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 656 i, pabias_2g, pabias_5g); 657 658 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 659 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 660 } 661 } 662 663 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 664 { 665 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 666 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 667 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 668 669 return 0; 670 } 671 672 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 673 { 674 rtw8852c_thermal_trim(rtwdev); 675 rtw8852c_pa_bias_trim(rtwdev); 676 } 677 678 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 679 const struct rtw89_chan *chan, 680 u8 mac_idx) 681 { 682 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 683 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 684 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 685 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 686 u8 rf_mod_val = 0, chk_rate_mask = 0; 687 u32 txsc; 688 689 switch (chan->band_width) { 690 case RTW89_CHANNEL_WIDTH_160: 691 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 692 RTW89_CHANNEL_WIDTH_80); 693 fallthrough; 694 case RTW89_CHANNEL_WIDTH_80: 695 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 696 RTW89_CHANNEL_WIDTH_40); 697 fallthrough; 698 case RTW89_CHANNEL_WIDTH_40: 699 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 700 RTW89_CHANNEL_WIDTH_20); 701 break; 702 default: 703 break; 704 } 705 706 switch (chan->band_width) { 707 case RTW89_CHANNEL_WIDTH_160: 708 rf_mod_val = AX_WMAC_RFMOD_160M; 709 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 710 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 711 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 712 break; 713 case RTW89_CHANNEL_WIDTH_80: 714 rf_mod_val = AX_WMAC_RFMOD_80M; 715 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 716 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 717 break; 718 case RTW89_CHANNEL_WIDTH_40: 719 rf_mod_val = AX_WMAC_RFMOD_40M; 720 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 721 break; 722 case RTW89_CHANNEL_WIDTH_20: 723 default: 724 rf_mod_val = AX_WMAC_RFMOD_20M; 725 txsc = 0; 726 break; 727 } 728 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 729 rtw89_write32(rtwdev, sub_carr, txsc); 730 731 switch (chan->band_type) { 732 case RTW89_BAND_2G: 733 chk_rate_mask = B_AX_BAND_MODE; 734 break; 735 case RTW89_BAND_5G: 736 case RTW89_BAND_6G: 737 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 738 break; 739 default: 740 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 741 return; 742 } 743 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 744 B_AX_RTS_LIMIT_IN_OFDM6); 745 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 746 } 747 748 static const u32 rtw8852c_sco_barker_threshold[14] = { 749 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 750 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 751 }; 752 753 static const u32 rtw8852c_sco_cck_threshold[14] = { 754 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 755 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 756 }; 757 758 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 759 u8 primary_ch, enum rtw89_bandwidth bw) 760 { 761 u8 ch_element; 762 763 if (bw == RTW89_CHANNEL_WIDTH_20) { 764 ch_element = central_ch - 1; 765 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 766 if (primary_ch == 1) 767 ch_element = central_ch - 1 + 2; 768 else 769 ch_element = central_ch - 1 - 2; 770 } else { 771 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 772 return -EINVAL; 773 } 774 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 775 rtw8852c_sco_barker_threshold[ch_element]); 776 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 777 rtw8852c_sco_cck_threshold[ch_element]); 778 779 return 0; 780 } 781 782 struct rtw8852c_bb_gain { 783 u32 gain_g[BB_PATH_NUM_8852C]; 784 u32 gain_a[BB_PATH_NUM_8852C]; 785 u32 gain_mask; 786 }; 787 788 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 789 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 790 .gain_mask = 0x00ff0000 }, 791 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 792 .gain_mask = 0xff000000 }, 793 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 794 .gain_mask = 0x000000ff }, 795 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 796 .gain_mask = 0x0000ff00 }, 797 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 798 .gain_mask = 0x00ff0000 }, 799 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 800 .gain_mask = 0xff000000 }, 801 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 802 .gain_mask = 0x000000ff }, 803 }; 804 805 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 806 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 807 .gain_mask = 0x00ff0000 }, 808 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 809 .gain_mask = 0xff000000 }, 810 }; 811 812 struct rtw8852c_bb_gain_bypass { 813 u32 gain_g[BB_PATH_NUM_8852C]; 814 u32 gain_a[BB_PATH_NUM_8852C]; 815 u32 gain_mask_g; 816 u32 gain_mask_a; 817 }; 818 819 static 820 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 821 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 822 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 823 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 824 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 825 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 826 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 827 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 828 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 829 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 830 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 831 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 832 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 833 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 834 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 835 }; 836 837 struct rtw8852c_bb_gain_op1db { 838 struct { 839 u32 lna[BB_PATH_NUM_8852C]; 840 u32 tia_lna[BB_PATH_NUM_8852C]; 841 u32 mask; 842 } reg[LNA_GAIN_NUM]; 843 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 844 u32 mask_tia0_lna6; 845 }; 846 847 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 848 .reg = { 849 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 850 .mask = 0xff}, 851 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 852 .mask = 0xff00}, 853 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 854 .mask = 0xff0000}, 855 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 856 .mask = 0xff000000}, 857 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 858 .mask = 0xff}, 859 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 860 .mask = 0xff00}, 861 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 862 .mask = 0xff0000}, 863 }, 864 .reg_tia0_lna6 = {0x4674, 0x4758}, 865 .mask_tia0_lna6 = 0xff000000, 866 }; 867 868 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 869 enum rtw89_subband subband, 870 enum rtw89_rf_path path) 871 { 872 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 873 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 874 s32 val; 875 u32 reg; 876 u32 mask; 877 int i; 878 879 for (i = 0; i < LNA_GAIN_NUM; i++) { 880 if (subband == RTW89_CH_2G) 881 reg = bb_gain_lna[i].gain_g[path]; 882 else 883 reg = bb_gain_lna[i].gain_a[path]; 884 885 mask = bb_gain_lna[i].gain_mask; 886 val = gain->lna_gain[gain_band][path][i]; 887 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 888 889 if (subband == RTW89_CH_2G) { 890 reg = bb_gain_bypass_lna[i].gain_g[path]; 891 mask = bb_gain_bypass_lna[i].gain_mask_g; 892 } else { 893 reg = bb_gain_bypass_lna[i].gain_a[path]; 894 mask = bb_gain_bypass_lna[i].gain_mask_a; 895 } 896 897 val = gain->lna_gain_bypass[gain_band][path][i]; 898 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 899 900 if (subband != RTW89_CH_2G) { 901 reg = bb_gain_op1db_a.reg[i].lna[path]; 902 mask = bb_gain_op1db_a.reg[i].mask; 903 val = gain->lna_op1db[gain_band][path][i]; 904 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 905 906 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 907 mask = bb_gain_op1db_a.reg[i].mask; 908 val = gain->tia_lna_op1db[gain_band][path][i]; 909 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 910 } 911 } 912 913 if (subband != RTW89_CH_2G) { 914 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 915 mask = bb_gain_op1db_a.mask_tia0_lna6; 916 val = gain->tia_lna_op1db[gain_band][path][7]; 917 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 918 } 919 920 for (i = 0; i < TIA_GAIN_NUM; i++) { 921 if (subband == RTW89_CH_2G) 922 reg = bb_gain_tia[i].gain_g[path]; 923 else 924 reg = bb_gain_tia[i].gain_a[path]; 925 926 mask = bb_gain_tia[i].gain_mask; 927 val = gain->tia_gain[gain_band][path][i]; 928 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 929 } 930 } 931 932 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 933 const struct rtw89_chan *chan, 934 enum rtw89_phy_idx phy_idx, 935 enum rtw89_rf_path path) 936 { 937 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 938 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 939 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 940 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 941 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 942 enum rtw89_gain_offset gain_band; 943 s32 offset_q0, offset_base_q4; 944 s32 tmp = 0; 945 946 if (!efuse_gain->offset_valid) 947 return; 948 949 if (rtwdev->dbcc_en && path == RF_PATH_B) 950 phy_idx = RTW89_PHY_1; 951 952 if (chan->band_type == RTW89_BAND_2G) { 953 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 954 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 955 956 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 957 S8_MIN >> 1, S8_MAX >> 1); 958 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 959 } 960 961 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 962 963 offset_q0 = -efuse_gain->offset[path][gain_band]; 964 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 965 966 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 967 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 968 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 969 970 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 971 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 972 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 973 } 974 975 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 976 const struct rtw89_chan *chan, 977 enum rtw89_phy_idx phy_idx) 978 { 979 u8 sco; 980 u16 central_freq = chan->freq; 981 u8 central_ch = chan->channel; 982 u8 band = chan->band_type; 983 u8 subband = chan->subband_type; 984 bool is_2g = band == RTW89_BAND_2G; 985 u8 chan_idx; 986 987 if (!central_freq) { 988 rtw89_warn(rtwdev, "Invalid central_freq\n"); 989 return; 990 } 991 992 if (phy_idx == RTW89_PHY_0) { 993 /* Path A */ 994 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 995 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 996 997 if (is_2g) 998 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 999 B_PATH0_BAND_SEL_MSK_V1, 1, 1000 phy_idx); 1001 else 1002 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1003 B_PATH0_BAND_SEL_MSK_V1, 0, 1004 phy_idx); 1005 /* Path B */ 1006 if (!rtwdev->dbcc_en) { 1007 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1008 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1009 1010 if (is_2g) 1011 rtw89_phy_write32_idx(rtwdev, 1012 R_PATH1_BAND_SEL_V1, 1013 B_PATH1_BAND_SEL_MSK_V1, 1014 1, phy_idx); 1015 else 1016 rtw89_phy_write32_idx(rtwdev, 1017 R_PATH1_BAND_SEL_V1, 1018 B_PATH1_BAND_SEL_MSK_V1, 1019 0, phy_idx); 1020 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1021 } else { 1022 if (is_2g) 1023 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1024 else 1025 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1026 } 1027 /* SCO compensate FC setting */ 1028 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1029 central_freq, phy_idx); 1030 /* round_up((1/fc0)*pow(2,18)) */ 1031 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1032 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1033 phy_idx); 1034 } else { 1035 /* Path B */ 1036 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1037 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1038 1039 if (is_2g) 1040 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1041 B_PATH1_BAND_SEL_MSK_V1, 1042 1, phy_idx); 1043 else 1044 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1045 B_PATH1_BAND_SEL_MSK_V1, 1046 0, phy_idx); 1047 /* SCO compensate FC setting */ 1048 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1049 central_freq, phy_idx); 1050 /* round_up((1/fc0)*pow(2,18)) */ 1051 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1052 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1053 phy_idx); 1054 } 1055 /* CCK parameters */ 1056 if (band == RTW89_BAND_2G) { 1057 if (central_ch == 14) { 1058 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1059 B_PCOEFF01_MSK_V1, 0x3b13ff); 1060 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1061 B_PCOEFF23_MSK_V1, 0x1c42de); 1062 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1063 B_PCOEFF45_MSK_V1, 0xfdb0ad); 1064 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1065 B_PCOEFF67_MSK_V1, 0xf60f6e); 1066 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1067 B_PCOEFF89_MSK_V1, 0xfd8f92); 1068 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1069 B_PCOEFFAB_MSK_V1, 0x2d011); 1070 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1071 B_PCOEFFCD_MSK_V1, 0x1c02c); 1072 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1073 B_PCOEFFEF_MSK_V1, 0xfff00a); 1074 } else { 1075 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1076 B_PCOEFF01_MSK_V1, 0x3d23ff); 1077 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1078 B_PCOEFF23_MSK_V1, 0x29b354); 1079 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1080 B_PCOEFF45_MSK_V1, 0xfc1c8); 1081 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1082 B_PCOEFF67_MSK_V1, 0xfdb053); 1083 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1084 B_PCOEFF89_MSK_V1, 0xf86f9a); 1085 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1086 B_PCOEFFAB_MSK_V1, 0xfaef92); 1087 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1088 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1089 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1090 B_PCOEFFEF_MSK_V1, 0xffdff5); 1091 } 1092 } 1093 1094 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1095 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1096 } 1097 1098 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1099 { 1100 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1101 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1102 1103 switch (bw) { 1104 case RTW89_CHANNEL_WIDTH_5: 1105 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1106 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1107 break; 1108 case RTW89_CHANNEL_WIDTH_10: 1109 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1110 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1111 break; 1112 case RTW89_CHANNEL_WIDTH_20: 1113 case RTW89_CHANNEL_WIDTH_40: 1114 case RTW89_CHANNEL_WIDTH_80: 1115 case RTW89_CHANNEL_WIDTH_160: 1116 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1117 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1118 break; 1119 default: 1120 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1121 } 1122 } 1123 1124 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1125 enum rtw89_phy_idx phy_idx) 1126 { 1127 if (bw == RTW89_CHANNEL_WIDTH_20) { 1128 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1129 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1130 } else { 1131 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1132 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1133 } 1134 } 1135 1136 static void 1137 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1138 enum rtw89_phy_idx phy_idx) 1139 { 1140 u8 mod_sbw = 0; 1141 1142 switch (bw) { 1143 case RTW89_CHANNEL_WIDTH_5: 1144 case RTW89_CHANNEL_WIDTH_10: 1145 case RTW89_CHANNEL_WIDTH_20: 1146 if (bw == RTW89_CHANNEL_WIDTH_5) 1147 mod_sbw = 0x1; 1148 else if (bw == RTW89_CHANNEL_WIDTH_10) 1149 mod_sbw = 0x2; 1150 else if (bw == RTW89_CHANNEL_WIDTH_20) 1151 mod_sbw = 0x0; 1152 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1153 phy_idx); 1154 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1155 mod_sbw, phy_idx); 1156 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1157 phy_idx); 1158 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1159 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1160 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1161 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1162 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1163 B_PATH0_BW_SEL_MSK_V1, 0xf); 1164 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1165 B_PATH1_BW_SEL_MSK_V1, 0xf); 1166 break; 1167 case RTW89_CHANNEL_WIDTH_40: 1168 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1169 phy_idx); 1170 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1171 phy_idx); 1172 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1173 pri_ch, 1174 phy_idx); 1175 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1176 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1177 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1178 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1179 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1180 B_PATH0_BW_SEL_MSK_V1, 0xf); 1181 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1182 B_PATH1_BW_SEL_MSK_V1, 0xf); 1183 break; 1184 case RTW89_CHANNEL_WIDTH_80: 1185 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1186 phy_idx); 1187 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1188 phy_idx); 1189 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1190 pri_ch, 1191 phy_idx); 1192 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1193 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1194 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1195 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1196 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1197 B_PATH0_BW_SEL_MSK_V1, 0xd); 1198 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1199 B_PATH1_BW_SEL_MSK_V1, 0xd); 1200 break; 1201 case RTW89_CHANNEL_WIDTH_160: 1202 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1203 phy_idx); 1204 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1205 phy_idx); 1206 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1207 pri_ch, 1208 phy_idx); 1209 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1210 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1211 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1212 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1213 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1214 B_PATH0_BW_SEL_MSK_V1, 0xb); 1215 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1216 B_PATH1_BW_SEL_MSK_V1, 0xb); 1217 break; 1218 default: 1219 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1220 pri_ch); 1221 } 1222 1223 if (bw == RTW89_CHANNEL_WIDTH_40) { 1224 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1225 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1226 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1227 } else { 1228 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1229 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1230 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1231 } 1232 1233 if (phy_idx == RTW89_PHY_0) { 1234 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1235 if (!rtwdev->dbcc_en) 1236 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1237 } else { 1238 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1239 } 1240 1241 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1242 } 1243 1244 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1245 const struct rtw89_chan *chan) 1246 { 1247 u8 center_chan = chan->channel; 1248 u8 bw = chan->band_width; 1249 1250 switch (chan->band_type) { 1251 case RTW89_BAND_2G: 1252 if (bw == RTW89_CHANNEL_WIDTH_20) { 1253 if (center_chan >= 5 && center_chan <= 8) 1254 return 2440; 1255 if (center_chan == 13) 1256 return 2480; 1257 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1258 if (center_chan >= 3 && center_chan <= 10) 1259 return 2440; 1260 } 1261 break; 1262 case RTW89_BAND_5G: 1263 if (center_chan == 151 || center_chan == 153 || 1264 center_chan == 155 || center_chan == 163) 1265 return 5760; 1266 break; 1267 case RTW89_BAND_6G: 1268 if (center_chan == 195 || center_chan == 197 || 1269 center_chan == 199 || center_chan == 207) 1270 return 6920; 1271 break; 1272 default: 1273 break; 1274 } 1275 1276 return 0; 1277 } 1278 1279 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1280 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1281 #define MAX_TONE_NUM 2048 1282 1283 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1284 const struct rtw89_chan *chan, 1285 enum rtw89_phy_idx phy_idx) 1286 { 1287 u32 spur_freq; 1288 s32 freq_diff, csi_idx, csi_tone_idx; 1289 1290 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1291 if (spur_freq == 0) { 1292 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1293 return; 1294 } 1295 1296 freq_diff = (spur_freq - chan->freq) * 1000000; 1297 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1298 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1299 1300 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1301 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1302 } 1303 1304 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1305 [RF_PATH_A] = { 1306 .notch1_idx = {0x4C14, 0xFF}, 1307 .notch1_frac_idx = {0x4C14, 0xC00}, 1308 .notch1_en = {0x4C14, 0x1000}, 1309 .notch2_idx = {0x4C20, 0xFF}, 1310 .notch2_frac_idx = {0x4C20, 0xC00}, 1311 .notch2_en = {0x4C20, 0x1000}, 1312 }, 1313 [RF_PATH_B] = { 1314 .notch1_idx = {0x4CD8, 0xFF}, 1315 .notch1_frac_idx = {0x4CD8, 0xC00}, 1316 .notch1_en = {0x4CD8, 0x1000}, 1317 .notch2_idx = {0x4CE4, 0xFF}, 1318 .notch2_frac_idx = {0x4CE4, 0xC00}, 1319 .notch2_en = {0x4CE4, 0x1000}, 1320 }, 1321 }; 1322 1323 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1324 const struct rtw89_chan *chan, 1325 enum rtw89_rf_path path) 1326 { 1327 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1328 u32 spur_freq, fc; 1329 s32 freq_diff; 1330 s32 nbi_idx, nbi_tone_idx; 1331 s32 nbi_frac_idx, nbi_frac_tone_idx; 1332 bool notch2_chk = false; 1333 1334 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1335 if (spur_freq == 0) { 1336 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1337 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1338 return; 1339 } 1340 1341 fc = chan->freq; 1342 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1343 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1344 if ((fc > spur_freq && 1345 chan->channel < chan->primary_channel) || 1346 (fc < spur_freq && 1347 chan->channel > chan->primary_channel)) 1348 notch2_chk = true; 1349 } 1350 1351 freq_diff = (spur_freq - fc) * 1000000; 1352 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1353 1354 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1355 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1356 } else { 1357 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1358 128 : 256; 1359 1360 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1361 } 1362 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1363 1364 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1365 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1366 nbi->notch2_idx.mask, nbi_tone_idx); 1367 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1368 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1369 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1370 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1371 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1372 } else { 1373 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1374 nbi->notch1_idx.mask, nbi_tone_idx); 1375 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1376 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1377 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1378 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1379 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1380 } 1381 } 1382 1383 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1384 enum rtw89_phy_idx phy_idx) 1385 { 1386 u32 notch; 1387 u32 notch2; 1388 1389 if (phy_idx == RTW89_PHY_0) { 1390 notch = R_PATH0_NOTCH; 1391 notch2 = R_PATH0_NOTCH2; 1392 } else { 1393 notch = R_PATH1_NOTCH; 1394 notch2 = R_PATH1_NOTCH2; 1395 } 1396 1397 rtw89_phy_write32_mask(rtwdev, notch, 1398 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1399 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1400 rtw89_phy_write32_mask(rtwdev, notch2, 1401 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1402 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1403 } 1404 1405 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1406 const struct rtw89_chan *chan, 1407 u8 pri_ch_idx, 1408 enum rtw89_phy_idx phy_idx) 1409 { 1410 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1411 1412 if (phy_idx == RTW89_PHY_0) { 1413 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1414 (pri_ch_idx == RTW89_SC_20_LOWER || 1415 pri_ch_idx == RTW89_SC_20_UP3X)) { 1416 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1417 if (!rtwdev->dbcc_en) 1418 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1419 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1420 (pri_ch_idx == RTW89_SC_20_UPPER || 1421 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1422 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1423 if (!rtwdev->dbcc_en) 1424 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1425 } else { 1426 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1427 if (!rtwdev->dbcc_en) 1428 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1429 RF_PATH_B); 1430 } 1431 } else { 1432 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1433 (pri_ch_idx == RTW89_SC_20_LOWER || 1434 pri_ch_idx == RTW89_SC_20_UP3X)) { 1435 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1436 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1437 (pri_ch_idx == RTW89_SC_20_UPPER || 1438 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1439 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1440 } else { 1441 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1442 } 1443 } 1444 1445 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1446 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1447 else 1448 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1449 } 1450 1451 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1452 const struct rtw89_chan *chan, 1453 enum rtw89_phy_idx phy_idx) 1454 { 1455 u8 pri_ch = chan->pri_ch_idx; 1456 bool mask_5m_low; 1457 bool mask_5m_en; 1458 1459 switch (chan->band_width) { 1460 case RTW89_CHANNEL_WIDTH_40: 1461 mask_5m_en = true; 1462 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1463 break; 1464 case RTW89_CHANNEL_WIDTH_80: 1465 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1466 pri_ch == RTW89_SC_20_LOWEST; 1467 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1468 break; 1469 default: 1470 mask_5m_en = false; 1471 mask_5m_low = false; 1472 break; 1473 } 1474 1475 if (!mask_5m_en) { 1476 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1477 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1478 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1479 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1480 } else { 1481 if (mask_5m_low) { 1482 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1483 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1484 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1485 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1486 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1487 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1488 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1489 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1490 } else { 1491 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1492 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1493 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1494 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1495 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1496 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1497 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1498 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1499 } 1500 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1501 } 1502 } 1503 1504 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1505 enum rtw89_phy_idx phy_idx) 1506 { 1507 /*HW SI reset*/ 1508 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1509 0x7); 1510 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1511 0x7); 1512 1513 udelay(1); 1514 1515 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1516 phy_idx); 1517 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1518 phy_idx); 1519 /*HW SI reset*/ 1520 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1521 0x0); 1522 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1523 0x0); 1524 1525 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1526 phy_idx); 1527 } 1528 1529 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1530 enum rtw89_phy_idx phy_idx, bool en) 1531 { 1532 if (en) { 1533 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1534 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1535 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1536 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1537 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1538 phy_idx); 1539 if (band == RTW89_BAND_2G) 1540 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1541 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1542 } else { 1543 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1544 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1545 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1546 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1547 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1548 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1549 fsleep(1); 1550 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1551 phy_idx); 1552 } 1553 } 1554 1555 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1556 enum rtw89_phy_idx phy_idx) 1557 { 1558 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1559 } 1560 1561 static 1562 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1563 u8 tx_path_en, u8 trsw_tx, 1564 u8 trsw_rx, u8 trsw, u8 trsw_b) 1565 { 1566 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1567 u32 mask_ofst = 16; 1568 u32 cr; 1569 u32 val; 1570 1571 if (path >= ARRAY_SIZE(path_cr_bases)) 1572 return; 1573 1574 cr = path_cr_bases[path]; 1575 1576 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1577 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1578 1579 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1580 } 1581 1582 enum rtw8852c_rfe_src { 1583 PAPE_RFM, 1584 TRSW_RFM, 1585 LNAON_RFM, 1586 }; 1587 1588 static 1589 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1590 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1591 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1592 { 1593 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1594 static const u32 masks[] = {0, 8, 16}; 1595 u32 mask, mask_ofst; 1596 u32 cr; 1597 u32 val; 1598 1599 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1600 return; 1601 1602 mask_ofst = masks[src]; 1603 cr = path_cr_bases[path]; 1604 1605 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1606 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1607 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1608 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1609 mask = 0xff << mask_ofst; 1610 1611 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1612 } 1613 1614 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1615 { 1616 static const u32 cr_bases[] = {0x5800, 0x7800}; 1617 u32 addr; 1618 u8 i; 1619 1620 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1621 addr = cr_bases[i]; 1622 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1623 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1624 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1625 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1626 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1627 } 1628 1629 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1630 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1631 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1632 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1633 1634 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1635 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1636 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1637 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1638 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1639 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1640 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1641 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1642 1643 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1644 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1645 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1646 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1647 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1648 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1649 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1650 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1651 1652 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1653 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1654 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1655 1656 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1657 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1658 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1659 } 1660 1661 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1662 enum rtw89_phy_idx phy_idx) 1663 { 1664 u32 addr; 1665 1666 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1667 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1668 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1669 } 1670 1671 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1672 { 1673 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1674 1675 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1676 B_DBCC_80P80_SEL_EVM_RPT_EN); 1677 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1678 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1679 1680 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1681 rtw8852c_bb_gpio_init(rtwdev); 1682 1683 /* read these registers after loading BB parameters */ 1684 gain->offset_base[RTW89_PHY_0] = 1685 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1686 gain->offset_base[RTW89_PHY_1] = 1687 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1688 } 1689 1690 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1691 const struct rtw89_chan *chan, 1692 enum rtw89_phy_idx phy_idx) 1693 { 1694 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1695 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1696 struct rtw89_hal *hal = &rtwdev->hal; 1697 bool cck_en = chan->band_type == RTW89_BAND_2G; 1698 u8 pri_ch_idx = chan->pri_ch_idx; 1699 u32 mask, reg; 1700 u8 ntx_path; 1701 1702 if (chan->band_type == RTW89_BAND_2G) 1703 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1704 chan->primary_channel, 1705 chan->band_width); 1706 1707 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1708 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1709 if (cck_en) { 1710 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1711 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1712 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1713 B_PD_ARBITER_OFF, 0x0, phy_idx); 1714 } else { 1715 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1716 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1717 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1718 B_PD_ARBITER_OFF, 0x1, phy_idx); 1719 } 1720 1721 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1722 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G, 1723 RTW89_PHY_0); 1724 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1725 1726 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1727 rtwdev->hal.cv != CHIP_CAV) { 1728 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1729 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1730 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1731 if (chan->primary_channel > chan->channel) { 1732 rtw89_phy_write32_mask(rtwdev, 1733 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1734 ru_alloc_msk[phy_idx], 1); 1735 rtw89_write32_mask(rtwdev, reg, 1736 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1737 } else { 1738 rtw89_phy_write32_mask(rtwdev, 1739 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1740 ru_alloc_msk[phy_idx], 0); 1741 rtw89_write32_mask(rtwdev, reg, 1742 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1743 } 1744 } 1745 1746 if (chan->band_type == RTW89_BAND_6G && 1747 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1748 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1749 B_CDD_EVM_CHK_EN, 0, phy_idx); 1750 else 1751 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1752 B_CDD_EVM_CHK_EN, 1, phy_idx); 1753 1754 if (!rtwdev->dbcc_en) { 1755 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1756 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1757 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1758 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1759 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1760 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1761 } else { 1762 if (phy_idx == RTW89_PHY_0) { 1763 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1764 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1765 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1766 } else { 1767 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1768 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1769 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1770 } 1771 } 1772 1773 if (chan->band_type == RTW89_BAND_6G) 1774 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1775 else 1776 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1777 1778 if (hal->antenna_tx) 1779 ntx_path = hal->antenna_tx; 1780 else 1781 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1782 1783 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1784 1785 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1786 } 1787 1788 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1789 const struct rtw89_chan *chan, 1790 enum rtw89_mac_idx mac_idx, 1791 enum rtw89_phy_idx phy_idx) 1792 { 1793 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1794 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1795 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1796 } 1797 1798 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1799 { 1800 if (en) 1801 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1802 else 1803 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1804 } 1805 1806 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1807 { 1808 if (en) 1809 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1810 0x0); 1811 else 1812 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1813 0xf); 1814 } 1815 1816 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1817 struct rtw89_channel_help_params *p, 1818 const struct rtw89_chan *chan, 1819 enum rtw89_mac_idx mac_idx, 1820 enum rtw89_phy_idx phy_idx) 1821 { 1822 if (enter) { 1823 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1824 RTW89_SCH_TX_SEL_ALL); 1825 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1826 rtw8852c_dfs_en(rtwdev, false); 1827 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx, chan); 1828 rtw8852c_adc_en(rtwdev, false); 1829 fsleep(40); 1830 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1831 } else { 1832 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1833 rtw8852c_adc_en(rtwdev, true); 1834 rtw8852c_dfs_en(rtwdev, true); 1835 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx, chan); 1836 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1837 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1838 } 1839 } 1840 1841 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1842 { 1843 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1844 1845 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1846 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1847 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1848 rtw8852c_lck_init(rtwdev); 1849 rtw8852c_dpk_init(rtwdev); 1850 1851 rtw8852c_rck(rtwdev); 1852 rtw8852c_dack(rtwdev, RTW89_CHANCTX_0); 1853 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1854 } 1855 1856 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev, 1857 struct rtw89_vif_link *rtwvif_link) 1858 { 1859 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx; 1860 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 1861 1862 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1863 rtw89_btc_ntfy_conn_rfk(rtwdev, true); 1864 1865 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1866 rtw8852c_iqk(rtwdev, phy_idx, chanctx_idx); 1867 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1868 rtw8852c_tssi(rtwdev, phy_idx, chanctx_idx); 1869 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1870 rtw8852c_dpk(rtwdev, phy_idx, chanctx_idx); 1871 1872 rtw89_btc_ntfy_conn_rfk(rtwdev, false); 1873 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1874 } 1875 1876 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1877 enum rtw89_phy_idx phy_idx, 1878 const struct rtw89_chan *chan) 1879 { 1880 rtw8852c_tssi_scan(rtwdev, phy_idx, chan); 1881 } 1882 1883 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, 1884 struct rtw89_vif_link *rtwvif_link, 1885 bool start) 1886 { 1887 rtw8852c_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx); 1888 } 1889 1890 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1891 { 1892 rtw8852c_dpk_track(rtwdev); 1893 rtw8852c_lck_track(rtwdev); 1894 rtw8852c_rx_dck_track(rtwdev); 1895 } 1896 1897 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1898 enum rtw89_phy_idx phy_idx, 1899 s16 ref, u16 pwr_ofst_decrease) 1900 { 1901 u8 base_cw_0db = 0x27; 1902 u16 tssi_16dbm_cw = 0x12c; 1903 s16 pwr_s10_3 = 0; 1904 s16 rf_pwr_cw = 0; 1905 u16 bb_pwr_cw = 0; 1906 u32 pwr_cw = 0; 1907 u32 tssi_ofst_cw = 0; 1908 1909 pwr_s10_3 = (ref << 1) + (s16)(base_cw_0db << 3) - pwr_ofst_decrease; 1910 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1911 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1912 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1913 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1914 1915 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)) - 1916 pwr_ofst_decrease; 1917 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1918 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1919 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1920 1921 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1922 } 1923 1924 static 1925 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1926 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1927 { 1928 s8 pw_ofst_2tx; 1929 s8 val_1t; 1930 s8 val_2t; 1931 u32 reg; 1932 u8 i; 1933 1934 if (pw_ofst < -32 || pw_ofst > 31) { 1935 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1936 return; 1937 } 1938 val_1t = pw_ofst << 2; 1939 pw_ofst_2tx = max(pw_ofst - 3, -32); 1940 val_2t = pw_ofst_2tx << 2; 1941 1942 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1943 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1944 1945 for (i = 0; i < 4; i++) { 1946 /* 1TX */ 1947 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1948 rtw89_write32_mask(rtwdev, reg, 1949 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1950 val_1t); 1951 /* 2TX */ 1952 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1953 rtw89_write32_mask(rtwdev, reg, 1954 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1955 val_2t); 1956 } 1957 } 1958 1959 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1960 enum rtw89_phy_idx phy_idx, s16 pwr_ofst) 1961 { 1962 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1963 u16 ofst_dec[RF_PATH_NUM_8852C]; 1964 const u32 mask = 0x7FFFFFF; 1965 const u8 ofst_ofdm = 0x4; 1966 const u8 ofst_cck = 0x8; 1967 s16 ref_ofdm = 0; 1968 s16 ref_cck = 0; 1969 u32 val; 1970 u8 i; 1971 1972 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1973 1974 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1975 GENMASK(27, 10), 0x0); 1976 1977 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? 0 : abs(pwr_ofst); 1978 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ofst : 0; 1979 1980 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1981 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 1982 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm, ofst_dec[i]); 1983 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, phy_idx); 1984 } 1985 1986 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1987 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 1988 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck, ofst_dec[i]); 1989 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, phy_idx); 1990 } 1991 } 1992 1993 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1994 const struct rtw89_chan *chan, 1995 u8 tx_shape_idx, 1996 enum rtw89_phy_idx phy_idx) 1997 { 1998 #define __DFIR_CFG_MASK 0xffffff 1999 #define __DFIR_CFG_NR 8 2000 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 2001 static const u32 _prefix ## _ ## _name[] = {_val}; \ 2002 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 2003 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 2004 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 2005 2006 __DECL_DFIR_PARAM(flat, 2007 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 2008 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 2009 __DECL_DFIR_PARAM(sharp, 2010 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 2011 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 2012 __DECL_DFIR_PARAM(sharp_14, 2013 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 2014 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 2015 __DECL_DFIR_ADDR(filter, 2016 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 2017 0x45C4, 0x45C8); 2018 u8 ch = chan->channel; 2019 const u32 *param; 2020 int i; 2021 2022 if (ch > 14) { 2023 rtw89_warn(rtwdev, 2024 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 2025 return; 2026 } 2027 2028 if (ch == 14) 2029 param = param_sharp_14; 2030 else 2031 param = tx_shape_idx == 0 ? param_flat : param_sharp; 2032 2033 for (i = 0; i < __DFIR_CFG_NR; i++) { 2034 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2035 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 2036 param[i]); 2037 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 2038 param[i], phy_idx); 2039 } 2040 2041 #undef __DECL_DFIR_ADDR 2042 #undef __DECL_DFIR_PARAM 2043 #undef __DECL_DFIR_VAR 2044 #undef __DFIR_CFG_NR 2045 #undef __DFIR_CFG_MASK 2046 } 2047 2048 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 2049 const struct rtw89_chan *chan, 2050 enum rtw89_phy_idx phy_idx) 2051 { 2052 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2053 u8 band = chan->band_type; 2054 u8 regd = rtw89_regd_get(rtwdev, band); 2055 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 2056 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 2057 2058 if (band == RTW89_BAND_2G) 2059 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 2060 2061 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2062 (enum rtw89_mac_idx)phy_idx, 2063 tx_shape_ofdm); 2064 2065 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN, 2066 B_P0_DAC_COMP_POST_DPD_EN); 2067 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN, 2068 B_P1_DAC_COMP_POST_DPD_EN); 2069 } 2070 2071 static void rtw8852c_set_txpwr_diff(struct rtw89_dev *rtwdev, 2072 const struct rtw89_chan *chan, 2073 enum rtw89_phy_idx phy_idx) 2074 { 2075 s16 pwr_ofst; 2076 2077 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan); 2078 rtw8852c_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst); 2079 } 2080 2081 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 2082 const struct rtw89_chan *chan, 2083 enum rtw89_phy_idx phy_idx) 2084 { 2085 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 2086 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 2087 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 2088 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 2089 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 2090 rtw8852c_set_txpwr_diff(rtwdev, chan, phy_idx); 2091 } 2092 2093 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 2094 enum rtw89_phy_idx phy_idx) 2095 { 2096 rtw8852c_set_txpwr_ref(rtwdev, phy_idx, 0); 2097 } 2098 2099 static void 2100 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2101 { 2102 static const struct rtw89_reg2_def ctrl_ini[] = { 2103 {0xD938, 0x00010100}, 2104 {0xD93C, 0x0500D500}, 2105 {0xD940, 0x00000500}, 2106 {0xD944, 0x00000005}, 2107 {0xD94C, 0x00220000}, 2108 {0xD950, 0x00030000}, 2109 }; 2110 u32 addr; 2111 int i; 2112 2113 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2114 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2115 2116 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2117 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2118 ctrl_ini[i].data); 2119 2120 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2121 (enum rtw89_mac_idx)phy_idx, 2122 RTW89_TSSI_BANDEDGE_FLAT); 2123 } 2124 2125 static int 2126 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2127 { 2128 int ret; 2129 2130 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2131 if (ret) 2132 return ret; 2133 2134 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2135 if (ret) 2136 return ret; 2137 2138 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2139 if (ret) 2140 return ret; 2141 2142 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2143 RTW89_MAC_1 : 2144 RTW89_MAC_0); 2145 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2146 2147 return 0; 2148 } 2149 2150 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2151 { 2152 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 2153 u8 band = chan->band_type; 2154 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2155 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2156 2157 if (rtwdev->dbcc_en) { 2158 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2159 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2160 RTW89_PHY_1); 2161 2162 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2163 1); 2164 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2165 1); 2166 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2167 RTW89_PHY_1); 2168 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2169 RTW89_PHY_1); 2170 2171 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2172 B_RXHT_MCS_LIMIT, 0); 2173 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2174 B_RXVHT_MCS_LIMIT, 0); 2175 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2176 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2177 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2178 2179 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2180 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2181 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2182 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2183 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2184 RTW89_PHY_1); 2185 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2186 RTW89_PHY_1); 2187 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2188 RTW89_PHY_1); 2189 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2190 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2191 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2192 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2193 } else { 2194 if (rx_path == RF_PATH_A) { 2195 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2196 B_ANT_RX_SEG0, 1); 2197 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2198 B_ANT_RX_1RCCA_SEG0, 1); 2199 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2200 B_ANT_RX_1RCCA_SEG1, 1); 2201 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2202 B_RXHT_MCS_LIMIT, 0); 2203 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2204 B_RXVHT_MCS_LIMIT, 0); 2205 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2206 0); 2207 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2208 0); 2209 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2210 rst_mask0, 1); 2211 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2212 rst_mask0, 3); 2213 } else if (rx_path == RF_PATH_B) { 2214 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2215 B_ANT_RX_SEG0, 2); 2216 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2217 B_ANT_RX_1RCCA_SEG0, 2); 2218 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2219 B_ANT_RX_1RCCA_SEG1, 2); 2220 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2221 B_RXHT_MCS_LIMIT, 0); 2222 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2223 B_RXVHT_MCS_LIMIT, 0); 2224 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2225 0); 2226 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2227 0); 2228 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2229 rst_mask1, 1); 2230 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2231 rst_mask1, 3); 2232 } else { 2233 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2234 B_ANT_RX_SEG0, 3); 2235 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2236 B_ANT_RX_1RCCA_SEG0, 3); 2237 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2238 B_ANT_RX_1RCCA_SEG1, 3); 2239 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2240 B_RXHT_MCS_LIMIT, 1); 2241 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2242 B_RXVHT_MCS_LIMIT, 1); 2243 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2244 1); 2245 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2246 1); 2247 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G, 2248 RTW89_PHY_0); 2249 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2250 rst_mask0, 1); 2251 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2252 rst_mask0, 3); 2253 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2254 rst_mask1, 1); 2255 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2256 rst_mask1, 3); 2257 } 2258 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2259 } 2260 } 2261 2262 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2263 enum rtw89_mac_idx mac_idx) 2264 { 2265 struct rtw89_reg2_def path_com[] = { 2266 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2267 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2268 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2269 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2270 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2271 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2272 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2273 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2274 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2275 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2276 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2277 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2278 }; 2279 u32 addr; 2280 u32 reg; 2281 u8 cr_size = ARRAY_SIZE(path_com); 2282 u8 i = 0; 2283 2284 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2285 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2286 2287 for (addr = R_AX_MACID_ANT_TABLE; 2288 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2289 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2290 rtw89_write32(rtwdev, reg, 0); 2291 } 2292 2293 if (tx_path == RF_A) { 2294 path_com[0].data = AX_PATH_COM0_PATHA; 2295 path_com[1].data = AX_PATH_COM1_PATHA; 2296 path_com[2].data = AX_PATH_COM2_PATHA; 2297 path_com[7].data = AX_PATH_COM7_PATHA; 2298 path_com[8].data = AX_PATH_COM8_PATHA; 2299 } else if (tx_path == RF_B) { 2300 path_com[0].data = AX_PATH_COM0_PATHB; 2301 path_com[1].data = AX_PATH_COM1_PATHB; 2302 path_com[2].data = AX_PATH_COM2_PATHB; 2303 path_com[7].data = AX_PATH_COM7_PATHB; 2304 path_com[8].data = AX_PATH_COM8_PATHB; 2305 } else if (tx_path == RF_AB) { 2306 path_com[0].data = AX_PATH_COM0_PATHAB; 2307 path_com[1].data = AX_PATH_COM1_PATHAB; 2308 path_com[2].data = AX_PATH_COM2_PATHAB; 2309 path_com[7].data = AX_PATH_COM7_PATHAB; 2310 path_com[8].data = AX_PATH_COM8_PATHAB; 2311 } else { 2312 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2313 return; 2314 } 2315 2316 for (i = 0; i < cr_size; i++) { 2317 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2318 path_com[i].addr, path_com[i].data); 2319 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2320 rtw89_write32(rtwdev, reg, path_com[i].data); 2321 } 2322 } 2323 2324 static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 2325 enum rtw89_phy_idx phy_idx) 2326 { 2327 if (en) { 2328 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2329 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2330 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2331 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2332 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2333 B_PATH0_RXBB_MSK_V1, 0xf); 2334 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2335 B_PATH1_RXBB_MSK_V1, 0xf); 2336 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2337 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2338 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2339 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2340 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2341 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2342 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2343 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2344 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2345 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2346 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2347 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2348 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2349 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2350 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2351 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2352 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2353 B_P0_BACKOFF_IBADC_V1, 0x34); 2354 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2355 B_P1_BACKOFF_IBADC_V1, 0x34); 2356 } else { 2357 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2358 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2359 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2360 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2361 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2362 B_PATH0_RXBB_MSK_V1, 0x60); 2363 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2364 B_PATH1_RXBB_MSK_V1, 0x60); 2365 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2366 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2367 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2368 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2369 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2370 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2371 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2372 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2373 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2374 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2375 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2376 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2377 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2378 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2379 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2380 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2381 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2382 B_P0_BACKOFF_IBADC_V1, 0x26); 2383 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2384 B_P1_BACKOFF_IBADC_V1, 0x26); 2385 } 2386 } 2387 2388 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2389 { 2390 struct rtw89_hal *hal = &rtwdev->hal; 2391 2392 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2393 2394 if (hal->rx_nss == 1) { 2395 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2396 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2397 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2398 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2399 } else { 2400 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2401 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2402 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2403 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2404 } 2405 } 2406 2407 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2408 { 2409 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2410 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2411 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2412 2413 fsleep(200); 2414 2415 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2416 } 2417 2418 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2419 { 2420 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2421 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 2422 2423 if (ver->fcxinit == 7) { 2424 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 2425 md->md_v7.kt_ver = rtwdev->hal.cv; 2426 md->md_v7.bt_solo = 0; 2427 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 2428 2429 if (md->md_v7.rfe_type > 0) 2430 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 2431 else 2432 md->md_v7.ant.num = 2; 2433 2434 md->md_v7.ant.diversity = 0; 2435 md->md_v7.ant.isolation = 10; 2436 2437 if (md->md_v7.ant.num == 3) { 2438 md->md_v7.ant.type = BTC_ANT_DEDICATED; 2439 md->md_v7.bt_pos = BTC_BT_ALONE; 2440 } else { 2441 md->md_v7.ant.type = BTC_ANT_SHARED; 2442 md->md_v7.bt_pos = BTC_BT_BTG; 2443 } 2444 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 2445 rtwdev->btc.ant_type = md->md_v7.ant.type; 2446 } else { 2447 md->md.rfe_type = rtwdev->efuse.rfe_type; 2448 md->md.cv = rtwdev->hal.cv; 2449 md->md.bt_solo = 0; 2450 md->md.switch_type = BTC_SWITCH_INTERNAL; 2451 2452 if (md->md.rfe_type > 0) 2453 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 2454 else 2455 md->md.ant.num = 2; 2456 2457 md->md.ant.diversity = 0; 2458 md->md.ant.isolation = 10; 2459 2460 if (md->md.ant.num == 3) { 2461 md->md.ant.type = BTC_ANT_DEDICATED; 2462 md->md.bt_pos = BTC_BT_ALONE; 2463 } else { 2464 md->md.ant.type = BTC_ANT_SHARED; 2465 md->md.bt_pos = BTC_BT_BTG; 2466 } 2467 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2468 rtwdev->btc.ant_type = md->md.ant.type; 2469 } 2470 } 2471 2472 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 2473 enum rtw89_phy_idx phy_idx) 2474 { 2475 if (en) { 2476 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2477 B_PATH0_BT_SHARE_V1, 0x1); 2478 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2479 B_PATH0_BTG_PATH_V1, 0x0); 2480 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2481 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2482 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2483 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2484 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2485 B_PATH1_BT_SHARE_V1, 0x1); 2486 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2487 B_PATH1_BTG_PATH_V1, 0x1); 2488 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2489 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2490 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2491 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2492 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2493 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2494 0x1); 2495 } else { 2496 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2497 B_PATH0_BT_SHARE_V1, 0x0); 2498 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2499 B_PATH0_BTG_PATH_V1, 0x0); 2500 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2501 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2502 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2503 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2504 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2505 B_PATH1_BT_SHARE_V1, 0x0); 2506 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2507 B_PATH1_BTG_PATH_V1, 0x0); 2508 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2509 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2510 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2511 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2512 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2513 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2514 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2515 0x0); 2516 } 2517 } 2518 2519 static 2520 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2521 { 2522 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2523 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2524 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2525 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2526 } 2527 2528 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2529 { 2530 struct rtw89_btc *btc = &rtwdev->btc; 2531 const struct rtw89_chip_info *chip = rtwdev->chip; 2532 const struct rtw89_mac_ax_coex coex_params = { 2533 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2534 .direction = RTW89_MAC_AX_COEX_INNER, 2535 }; 2536 2537 /* PTA init */ 2538 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2539 2540 /* set WL Tx response = Hi-Pri */ 2541 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2542 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2543 2544 /* set rf gnt debug off */ 2545 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2546 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2547 2548 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2549 if (btc->ant_type == BTC_ANT_SHARED) { 2550 rtw8852c_set_trx_mask(rtwdev, 2551 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2552 rtw8852c_set_trx_mask(rtwdev, 2553 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2554 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2555 rtw8852c_set_trx_mask(rtwdev, 2556 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2557 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2558 rtw8852c_set_trx_mask(rtwdev, 2559 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2560 rtw8852c_set_trx_mask(rtwdev, 2561 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2562 } 2563 2564 /* set PTA break table */ 2565 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2566 2567 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2568 rtw89_write32_set(rtwdev, 2569 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2570 B_AX_BT_CNT_RST_V1); 2571 btc->cx.wl.status.map.init_ok = true; 2572 } 2573 2574 static 2575 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2576 { 2577 u32 bitmap = 0; 2578 u32 reg = 0; 2579 2580 switch (map) { 2581 case BTC_PRI_MASK_TX_RESP: 2582 reg = R_BTC_COEX_WL_REQ; 2583 bitmap = B_BTC_RSP_ACK_HI; 2584 break; 2585 case BTC_PRI_MASK_BEACON: 2586 reg = R_BTC_COEX_WL_REQ; 2587 bitmap = B_BTC_TX_BCN_HI; 2588 break; 2589 default: 2590 return; 2591 } 2592 2593 if (state) 2594 rtw89_write32_set(rtwdev, reg, bitmap); 2595 else 2596 rtw89_write32_clr(rtwdev, reg, bitmap); 2597 } 2598 2599 union rtw8852c_btc_wl_txpwr_ctrl { 2600 u32 txpwr_val; 2601 struct { 2602 union { 2603 u16 ctrl_all_time; 2604 struct { 2605 s16 data:9; 2606 u16 rsvd:6; 2607 u16 flag:1; 2608 } all_time; 2609 }; 2610 union { 2611 u16 ctrl_gnt_bt; 2612 struct { 2613 s16 data:9; 2614 u16 rsvd:7; 2615 } gnt_bt; 2616 }; 2617 }; 2618 } __packed; 2619 2620 static void 2621 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2622 { 2623 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2624 s32 val; 2625 2626 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2627 do { \ 2628 u32 _wrt = FIELD_PREP(_msk, _val); \ 2629 BUILD_BUG_ON((_msk & _en) != 0); \ 2630 if (_cond) \ 2631 _wrt |= _en; \ 2632 else \ 2633 _wrt &= ~_en; \ 2634 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2635 _msk | _en, _wrt); \ 2636 } while (0) 2637 2638 switch (arg.ctrl_all_time) { 2639 case 0xffff: 2640 val = 0; 2641 break; 2642 default: 2643 val = arg.all_time.data; 2644 break; 2645 } 2646 2647 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2648 val, B_AX_FORCE_PWR_BY_RATE_EN, 2649 arg.ctrl_all_time != 0xffff); 2650 2651 switch (arg.ctrl_gnt_bt) { 2652 case 0xffff: 2653 val = 0; 2654 break; 2655 default: 2656 val = arg.gnt_bt.data; 2657 break; 2658 } 2659 2660 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2661 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2662 2663 #undef __write_ctrl 2664 } 2665 2666 static 2667 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2668 { 2669 /* +6 for compensate offset */ 2670 return clamp_t(s8, val + 6, -100, 0) + 100; 2671 } 2672 2673 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2674 {255, 0, 0, 7}, /* 0 -> original */ 2675 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2676 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2677 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2678 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2679 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2680 {6, 1, 0, 7}, 2681 {13, 1, 0, 7}, 2682 {13, 1, 0, 7} 2683 }; 2684 2685 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2686 {255, 0, 0, 7}, /* 0 -> original */ 2687 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2688 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2689 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2690 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2691 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2692 {255, 1, 0, 7}, 2693 {255, 1, 0, 7}, 2694 {255, 1, 0, 7} 2695 }; 2696 2697 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2698 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2699 2700 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2701 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2702 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2703 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2704 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2705 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2706 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2707 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2708 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2709 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2710 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2711 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2712 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2713 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2714 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2715 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2716 }; 2717 2718 static 2719 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2720 { 2721 /* Feature move to firmware */ 2722 } 2723 2724 static 2725 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2726 { 2727 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2728 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2729 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2730 2731 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2732 if (state) 2733 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2734 RFREG_MASK, 0x179c); 2735 else 2736 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2737 RFREG_MASK, 0x208); 2738 2739 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2740 } 2741 2742 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2743 { 2744 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2745 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2746 * To improve BT ACI in co-rx 2747 */ 2748 2749 switch (level) { 2750 case 0: /* default */ 2751 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2752 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2753 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2754 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2755 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2756 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2757 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2758 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2759 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2760 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2761 break; 2762 case 1: /* Fix LNA2=5 */ 2763 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2764 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2765 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2766 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2767 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2768 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2769 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2770 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2771 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2772 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2773 break; 2774 } 2775 } 2776 2777 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2778 { 2779 struct rtw89_btc *btc = &rtwdev->btc; 2780 2781 switch (level) { 2782 case 0: /* original */ 2783 default: 2784 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2785 btc->dm.wl_lna2 = 0; 2786 break; 2787 case 1: /* for FDD free-run */ 2788 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2789 btc->dm.wl_lna2 = 0; 2790 break; 2791 case 2: /* for BTG Co-Rx*/ 2792 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2793 btc->dm.wl_lna2 = 1; 2794 break; 2795 } 2796 2797 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2798 } 2799 2800 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2801 struct rtw89_rx_phy_ppdu *phy_ppdu, 2802 struct ieee80211_rx_status *status) 2803 { 2804 u8 chan_idx = phy_ppdu->chan_idx; 2805 enum nl80211_band band; 2806 u8 ch; 2807 2808 if (chan_idx == 0) 2809 return; 2810 2811 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2812 status->freq = ieee80211_channel_to_frequency(ch, band); 2813 status->band = band; 2814 } 2815 2816 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2817 struct rtw89_rx_phy_ppdu *phy_ppdu, 2818 struct ieee80211_rx_status *status) 2819 { 2820 u8 path; 2821 u8 *rx_power = phy_ppdu->rssi; 2822 2823 if (!status->signal) 2824 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], 2825 rx_power[RF_PATH_B])); 2826 2827 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2828 status->chains |= BIT(path); 2829 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2830 } 2831 if (phy_ppdu->valid) 2832 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2833 } 2834 2835 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2836 { 2837 int ret; 2838 2839 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2840 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2841 2842 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2843 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2844 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2845 2846 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2847 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2848 2849 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2850 if (ret) 2851 return ret; 2852 2853 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2854 if (ret) 2855 return ret; 2856 2857 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2858 if (ret) 2859 return ret; 2860 2861 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2862 if (ret) 2863 return ret; 2864 2865 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2866 if (ret) 2867 return ret; 2868 2869 return 0; 2870 } 2871 2872 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2873 { 2874 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2875 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2876 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2877 2878 return 0; 2879 } 2880 2881 static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = { 2882 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb, 2883 }; 2884 2885 #ifdef CONFIG_PM 2886 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2887 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT | 2888 WIPHY_WOWLAN_NET_DETECT, 2889 .n_patterns = RTW89_MAX_PATTERN_NUM, 2890 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2891 .pattern_min_len = 1, 2892 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID, 2893 }; 2894 #endif 2895 2896 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2897 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2898 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2899 .bb_preinit = NULL, 2900 .bb_postinit = NULL, 2901 .bb_reset = rtw8852c_bb_reset, 2902 .bb_sethw = rtw8852c_bb_sethw, 2903 .read_rf = rtw89_phy_read_rf_v1, 2904 .write_rf = rtw89_phy_write_rf_v1, 2905 .set_channel = rtw8852c_set_channel, 2906 .set_channel_help = rtw8852c_set_channel_help, 2907 .read_efuse = rtw8852c_read_efuse, 2908 .read_phycap = rtw8852c_read_phycap, 2909 .fem_setup = NULL, 2910 .rfe_gpio = NULL, 2911 .rfk_hw_init = NULL, 2912 .rfk_init = rtw8852c_rfk_init, 2913 .rfk_init_late = NULL, 2914 .rfk_channel = rtw8852c_rfk_channel, 2915 .rfk_band_changed = rtw8852c_rfk_band_changed, 2916 .rfk_scan = rtw8852c_rfk_scan, 2917 .rfk_track = rtw8852c_rfk_track, 2918 .power_trim = rtw8852c_power_trim, 2919 .set_txpwr = rtw8852c_set_txpwr, 2920 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2921 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2922 .get_thermal = rtw8852c_get_thermal, 2923 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx, 2924 .query_ppdu = rtw8852c_query_ppdu, 2925 .convert_rpl_to_rssi = NULL, 2926 .phy_rpt_to_rssi = NULL, 2927 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx, 2928 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2929 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2930 .digital_pwr_comp = NULL, 2931 .pwr_on_func = rtw8852c_pwr_on_func, 2932 .pwr_off_func = rtw8852c_pwr_off_func, 2933 .query_rxdesc = rtw89_core_query_rxdesc, 2934 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2935 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2936 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2937 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2938 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2939 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2940 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2941 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2942 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2943 .h2c_ampdu_cmac_tbl = NULL, 2944 .h2c_default_dmac_tbl = NULL, 2945 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2946 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2947 2948 .btc_set_rfe = rtw8852c_btc_set_rfe, 2949 .btc_init_cfg = rtw8852c_btc_init_cfg, 2950 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2951 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2952 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2953 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2954 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2955 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2956 .btc_set_policy = rtw89_btc_set_policy_v1, 2957 }; 2958 2959 const struct rtw89_chip_info rtw8852c_chip_info = { 2960 .chip_id = RTL8852C, 2961 .chip_gen = RTW89_CHIP_AX, 2962 .ops = &rtw8852c_chip_ops, 2963 .mac_def = &rtw89_mac_gen_ax, 2964 .phy_def = &rtw89_phy_gen_ax, 2965 .fw_basename = RTW8852C_FW_BASENAME, 2966 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2967 .try_ce_fw = false, 2968 .bbmcu_nr = 0, 2969 .needed_fw_elms = 0, 2970 .fifo_size = 458752, 2971 .small_fifo_size = false, 2972 .dle_scc_rsvd_size = 0, 2973 .max_amsdu_limit = 8000, 2974 .dis_2g_40m_ul_ofdma = false, 2975 .rsvd_ple_ofst = 0x6f800, 2976 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2977 .dle_mem = rtw8852c_dle_mem_pcie, 2978 .wde_qempty_acq_grpnum = 16, 2979 .wde_qempty_mgq_grpsel = 16, 2980 .rf_base_addr = {0xe000, 0xf000}, 2981 .thermal_th = {0x32, 0x35}, 2982 .pwr_on_seq = NULL, 2983 .pwr_off_seq = NULL, 2984 .bb_table = &rtw89_8852c_phy_bb_table, 2985 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2986 .rf_table = {&rtw89_8852c_phy_radiob_table, 2987 &rtw89_8852c_phy_radioa_table,}, 2988 .nctl_table = &rtw89_8852c_phy_nctl_table, 2989 .nctl_post_table = NULL, 2990 .dflt_parms = &rtw89_8852c_dflt_parms, 2991 .rfe_parms_conf = NULL, 2992 .chanctx_listener = &rtw8852c_chanctx_listener, 2993 .txpwr_factor_bb = 3, 2994 .txpwr_factor_rf = 2, 2995 .txpwr_factor_mac = 1, 2996 .dig_table = NULL, 2997 .dig_regs = &rtw8852c_dig_regs, 2998 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2999 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 3000 .support_link_num = 0, 3001 .support_chanctx_num = 2, 3002 .support_rnr = false, 3003 .support_bands = BIT(NL80211_BAND_2GHZ) | 3004 BIT(NL80211_BAND_5GHZ) | 3005 BIT(NL80211_BAND_6GHZ), 3006 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 3007 BIT(NL80211_CHAN_WIDTH_40) | 3008 BIT(NL80211_CHAN_WIDTH_80) | 3009 BIT(NL80211_CHAN_WIDTH_160), 3010 .support_unii4 = true, 3011 .support_ant_gain = true, 3012 .ul_tb_waveform_ctrl = false, 3013 .ul_tb_pwr_diff = true, 3014 .hw_sec_hdr = true, 3015 .hw_mgmt_tx_encrypt = true, 3016 .rf_path_num = 2, 3017 .tx_nss = 2, 3018 .rx_nss = 2, 3019 .acam_num = 128, 3020 .bcam_num = 20, 3021 .scam_num = 128, 3022 .bacam_num = 8, 3023 .bacam_dynamic_num = 8, 3024 .bacam_ver = RTW89_BACAM_V0_EXT, 3025 .ppdu_max_usr = 8, 3026 .sec_ctrl_efuse_size = 4, 3027 .physical_efuse_size = 1216, 3028 .logical_efuse_size = 2048, 3029 .limit_efuse_size = 1280, 3030 .dav_phy_efuse_size = 96, 3031 .dav_log_efuse_size = 16, 3032 .efuse_blocks = NULL, 3033 .phycap_addr = 0x590, 3034 .phycap_size = 0x60, 3035 .para_ver = 0x1, 3036 .wlcx_desired = 0x06000000, 3037 .btcx_desired = 0x7, 3038 .scbd = 0x1, 3039 .mailbox = 0x1, 3040 3041 .afh_guard_ch = 6, 3042 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 3043 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 3044 .rssi_tol = 2, 3045 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 3046 .mon_reg = rtw89_btc_8852c_mon_reg, 3047 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 3048 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 3049 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 3050 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 3051 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 3052 BIT(RTW89_PS_MODE_CLK_GATED) | 3053 BIT(RTW89_PS_MODE_PWR_GATED), 3054 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 3055 BIT(RTW89_PS_MODE_PWR_GATED), 3056 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 3057 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 3058 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 3059 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 3060 .txwd_info_size = sizeof(struct rtw89_txwd_info), 3061 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 3062 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 3063 .h2c_regs = rtw8852c_h2c_regs, 3064 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 3065 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 3066 .c2h_regs = rtw8852c_c2h_regs, 3067 .page_regs = &rtw8852c_page_regs, 3068 .wow_reason_reg = rtw8852c_wow_wakeup_regs, 3069 .cfo_src_fd = false, 3070 .cfo_hw_comp = false, 3071 .dcfo_comp = &rtw8852c_dcfo_comp, 3072 .dcfo_comp_sft = 12, 3073 .imr_info = &rtw8852c_imr_info, 3074 .imr_dmac_table = NULL, 3075 .imr_cmac_table = NULL, 3076 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 3077 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 3078 .bss_clr_map_reg = R_BSS_CLR_MAP, 3079 .rfkill_init = &rtw8852c_rfkill_regs, 3080 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 3081 .dma_ch_mask = 0, 3082 .edcca_regs = &rtw8852c_edcca_regs, 3083 #ifdef CONFIG_PM 3084 .wowlan_stub = &rtw_wowlan_stub_8852c, 3085 #endif 3086 .xtal_info = NULL, 3087 }; 3088 EXPORT_SYMBOL(rtw8852c_chip_info); 3089 3090 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 3091 MODULE_AUTHOR("Realtek Corporation"); 3092 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 3093 MODULE_LICENSE("Dual BSD/GPL"); 3094