1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2024 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852bt.h" 11 12 #define RTW8852BT_FW_FORMAT_MAX 0 13 #define RTW8852BT_FW_BASENAME "rtw89/rtw8852bt_fw" 14 #define RTW8852BT_MODULE_FIRMWARE \ 15 RTW8852BT_FW_BASENAME ".bin" 16 17 static const struct rtw89_hfc_ch_cfg rtw8852bt_hfc_chcfg_pcie[] = { 18 {16, 742, grp_0}, /* ACH 0 */ 19 {16, 742, grp_0}, /* ACH 1 */ 20 {16, 742, grp_0}, /* ACH 2 */ 21 {16, 742, grp_0}, /* ACH 3 */ 22 {0, 0, grp_0}, /* ACH 4 */ 23 {0, 0, grp_0}, /* ACH 5 */ 24 {0, 0, grp_0}, /* ACH 6 */ 25 {0, 0, grp_0}, /* ACH 7 */ 26 {15, 743, grp_0}, /* B0MGQ */ 27 {15, 743, grp_0}, /* B0HIQ */ 28 {0, 0, grp_0}, /* B1MGQ */ 29 {0, 0, grp_0}, /* B1HIQ */ 30 {40, 0, 0} /* FWCMDQ */ 31 }; 32 33 static const struct rtw89_hfc_pub_cfg rtw8852bt_hfc_pubcfg_pcie = { 34 958, /* Group 0 */ 35 0, /* Group 1 */ 36 958, /* Public Max */ 37 0 /* WP threshold */ 38 }; 39 40 static const struct rtw89_hfc_param_ini rtw8852bt_hfc_param_ini_pcie[] = { 41 [RTW89_QTA_SCC] = {rtw8852bt_hfc_chcfg_pcie, &rtw8852bt_hfc_pubcfg_pcie, 42 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 43 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 44 RTW89_HCIFC_POH}, 45 [RTW89_QTA_INVALID] = {NULL}, 46 }; 47 48 static const struct rtw89_dle_mem rtw8852bt_dle_mem_pcie[] = { 49 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size23, 50 &rtw89_mac_size.ple_size9, &rtw89_mac_size.wde_qt23, 51 &rtw89_mac_size.wde_qt23, &rtw89_mac_size.ple_qt57, 52 &rtw89_mac_size.ple_qt59}, 53 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size23, 54 &rtw89_mac_size.ple_size9, &rtw89_mac_size.wde_qt23, 55 &rtw89_mac_size.wde_qt23, &rtw89_mac_size.ple_qt57, 56 &rtw89_mac_size.ple_qt_52bt_wow}, 57 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 58 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 59 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 60 &rtw89_mac_size.ple_qt13}, 61 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 62 NULL}, 63 }; 64 65 static const u32 rtw8852bt_h2c_regs[RTW89_H2CREG_MAX] = { 66 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 67 R_AX_H2CREG_DATA3 68 }; 69 70 static const u32 rtw8852bt_c2h_regs[RTW89_C2HREG_MAX] = { 71 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 72 R_AX_C2HREG_DATA3 73 }; 74 75 static const u32 rtw8852bt_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 76 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 77 }; 78 79 static const struct rtw89_page_regs rtw8852bt_page_regs = { 80 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 81 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 82 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 83 .ach_page_info = R_AX_ACH0_PAGE_INFO, 84 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 85 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 86 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 87 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 88 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 89 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 90 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 91 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 92 }; 93 94 static const struct rtw89_reg_def rtw8852bt_dcfo_comp = { 95 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 96 }; 97 98 static const struct rtw89_imr_info rtw8852bt_imr_info = { 99 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 100 .wsec_imr_reg = R_AX_SEC_DEBUG, 101 .wsec_imr_set = B_AX_IMR_ERROR, 102 .mpdu_tx_imr_set = 0, 103 .mpdu_rx_imr_set = 0, 104 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 105 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 106 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 107 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 108 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 109 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 110 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 111 .wde_imr_clr = B_AX_WDE_IMR_CLR_V01, 112 .wde_imr_set = B_AX_WDE_IMR_SET_V01, 113 .ple_imr_clr = B_AX_PLE_IMR_CLR, 114 .ple_imr_set = B_AX_PLE_IMR_SET, 115 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 116 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V01, 117 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 118 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 119 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 120 .other_disp_imr_set = 0, 121 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 122 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 123 .bbrpt_err_imr_set = 0, 124 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 125 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 126 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 127 .cdma_imr_0_reg = R_AX_DLE_CTRL, 128 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 129 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 130 .cdma_imr_1_reg = 0, 131 .cdma_imr_1_clr = 0, 132 .cdma_imr_1_set = 0, 133 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 134 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_EN_ALL, 135 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET, 136 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 137 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 138 .rmac_imr_set = B_AX_RMAC_IMR_SET, 139 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 140 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 141 .tmac_imr_set = B_AX_TMAC_IMR_SET, 142 }; 143 144 static const struct rtw89_rrsr_cfgs rtw8852bt_rrsr_cfgs = { 145 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 146 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 147 }; 148 149 static const struct rtw89_dig_regs rtw8852bt_dig_regs = { 150 .seg0_pd_reg = R_SEG0R_PD_V1, 151 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 152 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 153 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 154 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 155 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 156 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 157 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 158 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 159 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 160 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 161 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 162 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 163 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 164 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 165 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 166 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 167 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 168 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 169 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 170 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 171 }; 172 173 static const struct rtw89_edcca_regs rtw8852bt_edcca_regs = { 174 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 175 .edcca_mask = B_EDCCA_LVL_MSK0, 176 .edcca_p_mask = B_EDCCA_LVL_MSK1, 177 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 178 .ppdu_mask = B_EDCCA_LVL_MSK3, 179 .rpt_a = R_EDCCA_RPT_A, 180 .rpt_b = R_EDCCA_RPT_B, 181 .rpt_sel = R_EDCCA_RPT_SEL, 182 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 183 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 184 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 185 }; 186 187 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_ul[] = { 188 {255, 0, 0, 7}, /* 0 -> original */ 189 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 190 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 191 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 192 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 193 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 194 {6, 1, 0, 7}, 195 {13, 1, 0, 7}, 196 {13, 1, 0, 7} 197 }; 198 199 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_dl[] = { 200 {255, 0, 0, 7}, /* 0 -> original */ 201 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 202 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 203 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 204 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 205 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 206 {255, 1, 0, 7}, 207 {255, 1, 0, 7}, 208 {255, 1, 0, 7} 209 }; 210 211 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852bt_mon_reg[] = { 212 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 213 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 214 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 215 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 216 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 217 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 218 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 219 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 220 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 221 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 222 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 223 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 224 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 225 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 226 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 227 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 228 }; 229 230 static const u8 rtw89_btc_8852bt_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 231 static const u8 rtw89_btc_8852bt_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 232 233 static const struct rtw89_chip_ops rtw8852bt_chip_ops = { 234 }; 235 236 #ifdef CONFIG_PM 237 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852bt = { 238 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 239 .n_patterns = RTW89_MAX_PATTERN_NUM, 240 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 241 .pattern_min_len = 1, 242 }; 243 #endif 244 245 const struct rtw89_chip_info rtw8852bt_chip_info = { 246 .chip_id = RTL8852BT, 247 .chip_gen = RTW89_CHIP_AX, 248 .ops = &rtw8852bt_chip_ops, 249 .mac_def = &rtw89_mac_gen_ax, 250 .phy_def = &rtw89_phy_gen_ax, 251 .fw_basename = RTW8852BT_FW_BASENAME, 252 .fw_format_max = RTW8852BT_FW_FORMAT_MAX, 253 .try_ce_fw = true, 254 .bbmcu_nr = 0, 255 .needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ, 256 .fifo_size = 458752, 257 .small_fifo_size = true, 258 .dle_scc_rsvd_size = 98304, 259 .max_amsdu_limit = 5000, 260 .dis_2g_40m_ul_ofdma = true, 261 .rsvd_ple_ofst = 0x6f800, 262 .hfc_param_ini = rtw8852bt_hfc_param_ini_pcie, 263 .dle_mem = rtw8852bt_dle_mem_pcie, 264 .wde_qempty_acq_grpnum = 4, 265 .wde_qempty_mgq_grpsel = 4, 266 .rf_base_addr = {0xe000, 0xf000}, 267 .pwr_on_seq = NULL, 268 .pwr_off_seq = NULL, 269 .bb_table = NULL, 270 .bb_gain_table = NULL, 271 .rf_table = {}, 272 .nctl_table = NULL, 273 .nctl_post_table = NULL, 274 .dflt_parms = NULL, 275 .rfe_parms_conf = NULL, 276 .txpwr_factor_rf = 2, 277 .txpwr_factor_mac = 1, 278 .dig_table = NULL, 279 .dig_regs = &rtw8852bt_dig_regs, 280 .tssi_dbw_table = NULL, 281 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 282 .support_chanctx_num = 1, 283 .support_rnr = false, 284 .support_bands = BIT(NL80211_BAND_2GHZ) | 285 BIT(NL80211_BAND_5GHZ), 286 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 287 BIT(NL80211_CHAN_WIDTH_40) | 288 BIT(NL80211_CHAN_WIDTH_80), 289 .support_unii4 = true, 290 .ul_tb_waveform_ctrl = true, 291 .ul_tb_pwr_diff = false, 292 .hw_sec_hdr = false, 293 .rf_path_num = 2, 294 .tx_nss = 2, 295 .rx_nss = 2, 296 .acam_num = 128, 297 .bcam_num = 10, 298 .scam_num = 128, 299 .bacam_num = 2, 300 .bacam_dynamic_num = 4, 301 .bacam_ver = RTW89_BACAM_V0, 302 .ppdu_max_usr = 4, 303 .sec_ctrl_efuse_size = 4, 304 .physical_efuse_size = 1216, 305 .logical_efuse_size = 2048, 306 .limit_efuse_size = 1280, 307 .dav_phy_efuse_size = 96, 308 .dav_log_efuse_size = 16, 309 .efuse_blocks = NULL, 310 .phycap_addr = 0x580, 311 .phycap_size = 128, 312 .para_ver = 0, 313 .wlcx_desired = 0x070e0000, 314 .btcx_desired = 0x7, 315 .scbd = 0x1, 316 .mailbox = 0x1, 317 318 .afh_guard_ch = 6, 319 .wl_rssi_thres = rtw89_btc_8852bt_wl_rssi_thres, 320 .bt_rssi_thres = rtw89_btc_8852bt_bt_rssi_thres, 321 .rssi_tol = 2, 322 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852bt_mon_reg), 323 .mon_reg = rtw89_btc_8852bt_mon_reg, 324 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_ul), 325 .rf_para_ulink = rtw89_btc_8852bt_rf_ul, 326 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_dl), 327 .rf_para_dlink = rtw89_btc_8852bt_rf_dl, 328 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 329 BIT(RTW89_PS_MODE_CLK_GATED) | 330 BIT(RTW89_PS_MODE_PWR_GATED), 331 .low_power_hci_modes = 0, 332 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 333 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 334 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 335 .txwd_body_size = sizeof(struct rtw89_txwd_body), 336 .txwd_info_size = sizeof(struct rtw89_txwd_info), 337 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 338 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 339 .h2c_regs = rtw8852bt_h2c_regs, 340 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 341 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 342 .c2h_regs = rtw8852bt_c2h_regs, 343 .page_regs = &rtw8852bt_page_regs, 344 .wow_reason_reg = rtw8852bt_wow_wakeup_regs, 345 .cfo_src_fd = true, 346 .cfo_hw_comp = true, 347 .dcfo_comp = &rtw8852bt_dcfo_comp, 348 .dcfo_comp_sft = 10, 349 .imr_info = &rtw8852bt_imr_info, 350 .imr_dmac_table = NULL, 351 .imr_cmac_table = NULL, 352 .rrsr_cfgs = &rtw8852bt_rrsr_cfgs, 353 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 354 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 355 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 356 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 357 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 358 .edcca_regs = &rtw8852bt_edcca_regs, 359 #ifdef CONFIG_PM 360 .wowlan_stub = &rtw_wowlan_stub_8852bt, 361 #endif 362 .xtal_info = NULL, 363 }; 364 EXPORT_SYMBOL(rtw8852bt_chip_info); 365 366 MODULE_FIRMWARE(RTW8852BT_MODULE_FIRMWARE); 367 MODULE_AUTHOR("Realtek Corporation"); 368 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BT driver"); 369 MODULE_LICENSE("Dual BSD/GPL"); 370