1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2024 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852bt.h" 11 #include "rtw8852bt_rfk.h" 12 #include "rtw8852b_common.h" 13 14 #define RTW8852BT_FW_FORMAT_MAX 0 15 #define RTW8852BT_FW_BASENAME "rtw89/rtw8852bt_fw" 16 #define RTW8852BT_MODULE_FIRMWARE \ 17 RTW8852BT_FW_BASENAME ".bin" 18 19 static const struct rtw89_hfc_ch_cfg rtw8852bt_hfc_chcfg_pcie[] = { 20 {16, 742, grp_0}, /* ACH 0 */ 21 {16, 742, grp_0}, /* ACH 1 */ 22 {16, 742, grp_0}, /* ACH 2 */ 23 {16, 742, grp_0}, /* ACH 3 */ 24 {0, 0, grp_0}, /* ACH 4 */ 25 {0, 0, grp_0}, /* ACH 5 */ 26 {0, 0, grp_0}, /* ACH 6 */ 27 {0, 0, grp_0}, /* ACH 7 */ 28 {15, 743, grp_0}, /* B0MGQ */ 29 {15, 743, grp_0}, /* B0HIQ */ 30 {0, 0, grp_0}, /* B1MGQ */ 31 {0, 0, grp_0}, /* B1HIQ */ 32 {40, 0, 0} /* FWCMDQ */ 33 }; 34 35 static const struct rtw89_hfc_pub_cfg rtw8852bt_hfc_pubcfg_pcie = { 36 958, /* Group 0 */ 37 0, /* Group 1 */ 38 958, /* Public Max */ 39 0 /* WP threshold */ 40 }; 41 42 static const struct rtw89_hfc_param_ini rtw8852bt_hfc_param_ini_pcie[] = { 43 [RTW89_QTA_SCC] = {rtw8852bt_hfc_chcfg_pcie, &rtw8852bt_hfc_pubcfg_pcie, 44 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 45 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 46 RTW89_HCIFC_POH}, 47 [RTW89_QTA_INVALID] = {NULL}, 48 }; 49 50 static const struct rtw89_dle_mem rtw8852bt_dle_mem_pcie[] = { 51 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size23, 52 &rtw89_mac_size.ple_size9, &rtw89_mac_size.wde_qt23, 53 &rtw89_mac_size.wde_qt23, &rtw89_mac_size.ple_qt57, 54 &rtw89_mac_size.ple_qt59}, 55 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size23, 56 &rtw89_mac_size.ple_size9, &rtw89_mac_size.wde_qt23, 57 &rtw89_mac_size.wde_qt23, &rtw89_mac_size.ple_qt57, 58 &rtw89_mac_size.ple_qt_52bt_wow}, 59 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 60 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 61 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 62 &rtw89_mac_size.ple_qt13}, 63 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 64 NULL}, 65 }; 66 67 static const u32 rtw8852bt_h2c_regs[RTW89_H2CREG_MAX] = { 68 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 69 R_AX_H2CREG_DATA3 70 }; 71 72 static const u32 rtw8852bt_c2h_regs[RTW89_C2HREG_MAX] = { 73 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 74 R_AX_C2HREG_DATA3 75 }; 76 77 static const u32 rtw8852bt_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 78 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 79 }; 80 81 static const struct rtw89_page_regs rtw8852bt_page_regs = { 82 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 83 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 84 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 85 .ach_page_info = R_AX_ACH0_PAGE_INFO, 86 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 87 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 88 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 89 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 90 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 91 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 92 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 93 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 94 }; 95 96 static const struct rtw89_reg_def rtw8852bt_dcfo_comp = { 97 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 98 }; 99 100 static const struct rtw89_imr_info rtw8852bt_imr_info = { 101 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 102 .wsec_imr_reg = R_AX_SEC_DEBUG, 103 .wsec_imr_set = B_AX_IMR_ERROR, 104 .mpdu_tx_imr_set = 0, 105 .mpdu_rx_imr_set = 0, 106 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 107 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 108 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 109 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 110 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 111 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 112 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 113 .wde_imr_clr = B_AX_WDE_IMR_CLR_V01, 114 .wde_imr_set = B_AX_WDE_IMR_SET_V01, 115 .ple_imr_clr = B_AX_PLE_IMR_CLR, 116 .ple_imr_set = B_AX_PLE_IMR_SET, 117 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 118 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V01, 119 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 120 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 121 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 122 .other_disp_imr_set = 0, 123 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 124 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 125 .bbrpt_err_imr_set = 0, 126 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 127 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 128 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 129 .cdma_imr_0_reg = R_AX_DLE_CTRL, 130 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 131 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 132 .cdma_imr_1_reg = 0, 133 .cdma_imr_1_clr = 0, 134 .cdma_imr_1_set = 0, 135 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 136 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_EN_ALL, 137 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET, 138 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 139 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 140 .rmac_imr_set = B_AX_RMAC_IMR_SET, 141 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 142 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 143 .tmac_imr_set = B_AX_TMAC_IMR_SET, 144 }; 145 146 static const struct rtw89_rrsr_cfgs rtw8852bt_rrsr_cfgs = { 147 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 148 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 149 }; 150 151 static const struct rtw89_rfkill_regs rtw8852bt_rfkill_regs = { 152 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 153 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 154 0xf}, 155 .mode = {R_AX_GPIO_EXT_CTRL + 2, 156 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 157 0x0}, 158 }; 159 160 static const struct rtw89_dig_regs rtw8852bt_dig_regs = { 161 .seg0_pd_reg = R_SEG0R_PD_V1, 162 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 163 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 164 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 165 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 166 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 167 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 168 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 169 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 170 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 171 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 172 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 173 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 174 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 175 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 176 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 177 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 178 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 179 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 180 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 181 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 182 }; 183 184 static const struct rtw89_edcca_regs rtw8852bt_edcca_regs = { 185 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 186 .edcca_mask = B_EDCCA_LVL_MSK0, 187 .edcca_p_mask = B_EDCCA_LVL_MSK1, 188 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 189 .ppdu_mask = B_EDCCA_LVL_MSK3, 190 .rpt_a = R_EDCCA_RPT_A, 191 .rpt_b = R_EDCCA_RPT_B, 192 .rpt_sel = R_EDCCA_RPT_SEL, 193 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 194 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 195 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 196 }; 197 198 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_ul[] = { 199 {255, 0, 0, 7}, /* 0 -> original */ 200 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 201 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 202 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 203 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 204 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 205 {6, 1, 0, 7}, 206 {13, 1, 0, 7}, 207 {13, 1, 0, 7} 208 }; 209 210 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_dl[] = { 211 {255, 0, 0, 7}, /* 0 -> original */ 212 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 213 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 214 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 215 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 216 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 217 {255, 1, 0, 7}, 218 {255, 1, 0, 7}, 219 {255, 1, 0, 7} 220 }; 221 222 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852bt_mon_reg[] = { 223 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 224 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 225 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 226 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 227 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 228 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 229 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 230 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 231 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 232 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 233 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 234 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 235 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 236 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 237 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 238 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 239 }; 240 241 static const u8 rtw89_btc_8852bt_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 242 static const u8 rtw89_btc_8852bt_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 243 244 static int rtw8852bt_pwr_on_func(struct rtw89_dev *rtwdev) 245 { 246 u32 val32; 247 u32 ret; 248 249 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 250 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 251 B_AX_AFSM_PCIE_SUS_EN); 252 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 253 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 254 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 255 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 256 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_OCP_L1_MASK, 7); 257 258 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 259 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 260 if (ret) 261 return ret; 262 263 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 264 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 265 266 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 267 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 268 if (ret) 269 return ret; 270 271 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 272 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 273 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 274 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 275 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 276 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 277 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 278 279 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 280 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 281 if (ret) 282 return ret; 283 284 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 285 286 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 287 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 288 if (ret) 289 return ret; 290 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 291 XTAL_SI_OFF_WEI); 292 if (ret) 293 return ret; 294 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 295 XTAL_SI_OFF_EI); 296 if (ret) 297 return ret; 298 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 299 if (ret) 300 return ret; 301 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 302 XTAL_SI_PON_WEI); 303 if (ret) 304 return ret; 305 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 306 XTAL_SI_PON_EI); 307 if (ret) 308 return ret; 309 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 310 if (ret) 311 return ret; 312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 313 if (ret) 314 return ret; 315 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 316 if (ret) 317 return ret; 318 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 319 if (ret) 320 return ret; 321 322 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 323 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 324 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 325 326 fsleep(1000); 327 328 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 329 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 330 331 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) 332 goto func_en; 333 334 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); 335 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); 336 337 func_en: 338 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 339 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 340 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 341 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 342 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 343 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 344 B_AX_DMACREG_GCKEN); 345 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 346 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 347 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 348 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 349 B_AX_RMAC_EN); 350 351 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, 352 B_AX_PINMUX_EESK_FUNC_SEL_MASK, 0x1); 353 354 return 0; 355 } 356 357 static int rtw8852bt_pwr_off_func(struct rtw89_dev *rtwdev) 358 { 359 u32 val32; 360 u32 ret; 361 362 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 363 XTAL_SI_RFC2RF); 364 if (ret) 365 return ret; 366 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 367 if (ret) 368 return ret; 369 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 370 if (ret) 371 return ret; 372 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 373 if (ret) 374 return ret; 375 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 376 if (ret) 377 return ret; 378 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 379 XTAL_SI_SRAM2RFC); 380 if (ret) 381 return ret; 382 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 383 if (ret) 384 return ret; 385 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 386 if (ret) 387 return ret; 388 389 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 390 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 391 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 392 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 393 394 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 395 if (ret) 396 return ret; 397 398 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 399 400 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 401 if (ret) 402 return ret; 403 404 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 405 406 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 407 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 408 if (ret) 409 return ret; 410 411 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 412 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 413 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); 414 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 415 416 return 0; 417 } 418 419 static void rtw8852bt_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 420 enum rtw89_phy_idx phy_idx, bool en) 421 { 422 if (en) { 423 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 424 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 425 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 426 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 427 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 428 if (band == RTW89_BAND_2G) 429 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 430 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 431 } else { 432 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 433 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 434 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 435 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 436 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 437 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 438 fsleep(1); 439 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 440 } 441 } 442 443 static void rtw8852bt_bb_reset(struct rtw89_dev *rtwdev, 444 enum rtw89_phy_idx phy_idx) 445 { 446 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 447 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1); 448 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 449 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 450 B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI, 0x1); 451 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 452 rtw8852bx_bb_reset_all(rtwdev, phy_idx); 453 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 454 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 3); 455 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 456 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 457 B_P1_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3); 458 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 459 } 460 461 static void rtw8852bt_set_channel(struct rtw89_dev *rtwdev, 462 const struct rtw89_chan *chan, 463 enum rtw89_mac_idx mac_idx, 464 enum rtw89_phy_idx phy_idx) 465 { 466 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx); 467 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx); 468 rtw8852bt_set_channel_rf(rtwdev, chan, phy_idx); 469 } 470 471 static void rtw8852bt_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 472 enum rtw89_rf_path path) 473 { 474 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; 475 476 if (en) 477 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0); 478 else 479 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1); 480 } 481 482 static void rtw8852bt_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 483 u8 phy_idx, const struct rtw89_chan *chan) 484 { 485 if (!rtwdev->dbcc_en) { 486 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_A); 487 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_B); 488 rtw8852bt_tssi_scan(rtwdev, phy_idx, chan); 489 } else { 490 if (phy_idx == RTW89_PHY_0) 491 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_A); 492 else 493 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_B); 494 } 495 } 496 497 static void rtw8852bt_adc_en(struct rtw89_dev *rtwdev, bool en) 498 { 499 if (en) 500 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 501 else 502 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 503 } 504 505 static void rtw8852bt_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 506 struct rtw89_channel_help_params *p, 507 const struct rtw89_chan *chan, 508 enum rtw89_mac_idx mac_idx, 509 enum rtw89_phy_idx phy_idx) 510 { 511 if (enter) { 512 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 513 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 514 rtw8852bt_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0, chan); 515 rtw8852bt_adc_en(rtwdev, false); 516 fsleep(40); 517 rtw8852bt_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 518 } else { 519 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 520 rtw8852bt_adc_en(rtwdev, true); 521 rtw8852bt_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0, chan); 522 rtw8852bt_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 523 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 524 } 525 } 526 527 static void rtw8852bt_rfk_init(struct rtw89_dev *rtwdev) 528 { 529 rtwdev->is_tssi_mode[RF_PATH_A] = false; 530 rtwdev->is_tssi_mode[RF_PATH_B] = false; 531 532 rtw8852bt_dpk_init(rtwdev); 533 rtw8852bt_rck(rtwdev); 534 rtw8852bt_dack(rtwdev, RTW89_CHANCTX_0); 535 rtw8852bt_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0); 536 } 537 538 static void rtw8852bt_rfk_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 539 { 540 enum rtw89_chanctx_idx chanctx_idx = rtwvif->chanctx_idx; 541 enum rtw89_phy_idx phy_idx = rtwvif->phy_idx; 542 543 rtw8852bt_rx_dck(rtwdev, phy_idx, chanctx_idx); 544 rtw8852bt_iqk(rtwdev, phy_idx, chanctx_idx); 545 rtw8852bt_tssi(rtwdev, phy_idx, true, chanctx_idx); 546 rtw8852bt_dpk(rtwdev, phy_idx, chanctx_idx); 547 } 548 549 static void rtw8852bt_rfk_band_changed(struct rtw89_dev *rtwdev, 550 enum rtw89_phy_idx phy_idx, 551 const struct rtw89_chan *chan) 552 { 553 rtw8852bt_tssi_scan(rtwdev, phy_idx, chan); 554 } 555 556 static void rtw8852bt_rfk_scan(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 557 bool start) 558 { 559 rtw8852bt_wifi_scan_notify(rtwdev, start, rtwvif->phy_idx, rtwvif->chanctx_idx); 560 } 561 562 static void rtw8852bt_rfk_track(struct rtw89_dev *rtwdev) 563 { 564 rtw8852bt_dpk_track(rtwdev); 565 } 566 567 static void rtw8852bt_btc_set_rfe(struct rtw89_dev *rtwdev) 568 { 569 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 570 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 571 572 if (ver->fcxinit == 7) { 573 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 574 md->md_v7.kt_ver = rtwdev->hal.cv; 575 md->md_v7.kt_ver_adie = rtwdev->hal.acv; 576 md->md_v7.bt_solo = 0; 577 md->md_v7.bt_pos = BTC_BT_BTG; 578 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 579 md->md_v7.wa_type = 0; 580 581 md->md_v7.ant.type = BTC_ANT_SHARED; 582 md->md_v7.ant.num = 2; 583 md->md_v7.ant.isolation = 10; 584 md->md_v7.ant.diversity = 0; 585 /* WL 1-stream+1-Ant is located at 0:s0(path-A) or 1:s1(path-B) */ 586 md->md_v7.ant.single_pos = RF_PATH_A; 587 md->md_v7.ant.btg_pos = RF_PATH_B; 588 589 if (md->md_v7.rfe_type == 0) { 590 rtwdev->btc.dm.error.map.rfe_type0 = true; 591 return; 592 } 593 594 md->md_v7.ant.num = (md->md_v7.rfe_type % 2) ? 2 : 3; 595 md->md_v7.ant.stream_cnt = 2; 596 md->md_v7.wa_type |= BTC_WA_INIT_SCAN; 597 598 if (md->md_v7.ant.num == 2) { 599 md->md_v7.ant.type = BTC_ANT_SHARED; 600 md->md_v7.bt_pos = BTC_BT_BTG; 601 md->md_v7.wa_type |= BTC_WA_HFP_LAG; 602 } else { 603 md->md_v7.ant.type = BTC_ANT_DEDICATED; 604 md->md_v7.bt_pos = BTC_BT_ALONE; 605 } 606 } else { 607 return; 608 } 609 } 610 611 static void 612 rtw8852bt_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 613 { 614 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0)); 615 u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16)); 616 617 switch (ctrl_all_time) { 618 case 0xffff: 619 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL, 620 B_AX_FORCE_PWR_BY_RATE_EN, 0x0); 621 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL, 622 B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 0x0); 623 break; 624 default: 625 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL, 626 B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 627 ctrl_all_time); 628 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL, 629 B_AX_FORCE_PWR_BY_RATE_EN, 0x1); 630 break; 631 } 632 633 switch (ctrl_gnt_bt) { 634 case 0xffff: 635 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL, 636 B_AX_TXAGC_BT_EN, 0x0); 637 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL, 638 B_AX_TXAGC_BT_MASK, 0x0); 639 break; 640 default: 641 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL, 642 B_AX_TXAGC_BT_MASK, ctrl_gnt_bt); 643 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL, 644 B_AX_TXAGC_BT_EN, 0x1); 645 break; 646 } 647 } 648 649 static const struct rtw89_chip_ops rtw8852bt_chip_ops = { 650 .enable_bb_rf = rtw8852bx_mac_enable_bb_rf, 651 .disable_bb_rf = rtw8852bx_mac_disable_bb_rf, 652 .bb_preinit = NULL, 653 .bb_postinit = NULL, 654 .bb_reset = rtw8852bt_bb_reset, 655 .bb_sethw = rtw8852bx_bb_sethw, 656 .read_rf = rtw89_phy_read_rf_v1, 657 .write_rf = rtw89_phy_write_rf_v1, 658 .set_channel = rtw8852bt_set_channel, 659 .set_channel_help = rtw8852bt_set_channel_help, 660 .read_efuse = rtw8852bx_read_efuse, 661 .read_phycap = rtw8852bx_read_phycap, 662 .fem_setup = NULL, 663 .rfe_gpio = NULL, 664 .rfk_hw_init = NULL, 665 .rfk_init = rtw8852bt_rfk_init, 666 .rfk_init_late = NULL, 667 .rfk_channel = rtw8852bt_rfk_channel, 668 .rfk_band_changed = rtw8852bt_rfk_band_changed, 669 .rfk_scan = rtw8852bt_rfk_scan, 670 .rfk_track = rtw8852bt_rfk_track, 671 .power_trim = rtw8852bx_power_trim, 672 .set_txpwr = rtw8852bx_set_txpwr, 673 .set_txpwr_ctrl = rtw8852bx_set_txpwr_ctrl, 674 .init_txpwr_unit = rtw8852bx_init_txpwr_unit, 675 .get_thermal = rtw8852bx_get_thermal, 676 .ctrl_btg_bt_rx = rtw8852bx_ctrl_btg_bt_rx, 677 .query_ppdu = rtw8852bx_query_ppdu, 678 .convert_rpl_to_rssi = rtw8852bx_convert_rpl_to_rssi, 679 .ctrl_nbtg_bt_tx = rtw8852bx_ctrl_nbtg_bt_tx, 680 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, 681 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, 682 .digital_pwr_comp = NULL, 683 .pwr_on_func = rtw8852bt_pwr_on_func, 684 .pwr_off_func = rtw8852bt_pwr_off_func, 685 .query_rxdesc = rtw89_core_query_rxdesc, 686 .fill_txdesc = rtw89_core_fill_txdesc, 687 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 688 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 689 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 690 .stop_sch_tx = rtw89_mac_stop_sch_tx, 691 .resume_sch_tx = rtw89_mac_resume_sch_tx, 692 .h2c_dctl_sec_cam = NULL, 693 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 694 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 695 .h2c_ampdu_cmac_tbl = NULL, 696 .h2c_default_dmac_tbl = NULL, 697 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 698 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 699 700 .btc_set_rfe = rtw8852bt_btc_set_rfe, 701 .btc_init_cfg = rtw8852bx_btc_init_cfg, 702 .btc_set_wl_pri = rtw8852bx_btc_set_wl_pri, 703 .btc_set_wl_txpwr_ctrl = rtw8852bt_btc_set_wl_txpwr_ctrl, 704 .btc_get_bt_rssi = rtw8852bx_btc_get_bt_rssi, 705 .btc_update_bt_cnt = rtw8852bx_btc_update_bt_cnt, 706 .btc_wl_s1_standby = rtw8852bx_btc_wl_s1_standby, 707 .btc_set_wl_rx_gain = rtw8852bx_btc_set_wl_rx_gain, 708 .btc_set_policy = rtw89_btc_set_policy_v1, 709 }; 710 711 #ifdef CONFIG_PM 712 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852bt = { 713 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 714 .n_patterns = RTW89_MAX_PATTERN_NUM, 715 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 716 .pattern_min_len = 1, 717 }; 718 #endif 719 720 const struct rtw89_chip_info rtw8852bt_chip_info = { 721 .chip_id = RTL8852BT, 722 .chip_gen = RTW89_CHIP_AX, 723 .ops = &rtw8852bt_chip_ops, 724 .mac_def = &rtw89_mac_gen_ax, 725 .phy_def = &rtw89_phy_gen_ax, 726 .fw_basename = RTW8852BT_FW_BASENAME, 727 .fw_format_max = RTW8852BT_FW_FORMAT_MAX, 728 .try_ce_fw = true, 729 .bbmcu_nr = 0, 730 .needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ, 731 .fifo_size = 458752, 732 .small_fifo_size = true, 733 .dle_scc_rsvd_size = 98304, 734 .max_amsdu_limit = 5000, 735 .dis_2g_40m_ul_ofdma = true, 736 .rsvd_ple_ofst = 0x6f800, 737 .hfc_param_ini = rtw8852bt_hfc_param_ini_pcie, 738 .dle_mem = rtw8852bt_dle_mem_pcie, 739 .wde_qempty_acq_grpnum = 4, 740 .wde_qempty_mgq_grpsel = 4, 741 .rf_base_addr = {0xe000, 0xf000}, 742 .pwr_on_seq = NULL, 743 .pwr_off_seq = NULL, 744 .bb_table = NULL, 745 .bb_gain_table = NULL, 746 .rf_table = {}, 747 .nctl_table = NULL, 748 .nctl_post_table = NULL, 749 .dflt_parms = NULL, 750 .rfe_parms_conf = NULL, 751 .txpwr_factor_rf = 2, 752 .txpwr_factor_mac = 1, 753 .dig_table = NULL, 754 .dig_regs = &rtw8852bt_dig_regs, 755 .tssi_dbw_table = NULL, 756 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 757 .support_link_num = 0, 758 .support_chanctx_num = 1, 759 .support_rnr = false, 760 .support_bands = BIT(NL80211_BAND_2GHZ) | 761 BIT(NL80211_BAND_5GHZ), 762 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 763 BIT(NL80211_CHAN_WIDTH_40) | 764 BIT(NL80211_CHAN_WIDTH_80), 765 .support_unii4 = true, 766 .ul_tb_waveform_ctrl = true, 767 .ul_tb_pwr_diff = false, 768 .hw_sec_hdr = false, 769 .hw_mgmt_tx_encrypt = false, 770 .rf_path_num = 2, 771 .tx_nss = 2, 772 .rx_nss = 2, 773 .acam_num = 128, 774 .bcam_num = 10, 775 .scam_num = 128, 776 .bacam_num = 2, 777 .bacam_dynamic_num = 4, 778 .bacam_ver = RTW89_BACAM_V0, 779 .ppdu_max_usr = 4, 780 .sec_ctrl_efuse_size = 4, 781 .physical_efuse_size = 1216, 782 .logical_efuse_size = 2048, 783 .limit_efuse_size = 1280, 784 .dav_phy_efuse_size = 96, 785 .dav_log_efuse_size = 16, 786 .efuse_blocks = NULL, 787 .phycap_addr = 0x580, 788 .phycap_size = 128, 789 .para_ver = 0, 790 .wlcx_desired = 0x070e0000, 791 .btcx_desired = 0x7, 792 .scbd = 0x1, 793 .mailbox = 0x1, 794 795 .afh_guard_ch = 6, 796 .wl_rssi_thres = rtw89_btc_8852bt_wl_rssi_thres, 797 .bt_rssi_thres = rtw89_btc_8852bt_bt_rssi_thres, 798 .rssi_tol = 2, 799 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852bt_mon_reg), 800 .mon_reg = rtw89_btc_8852bt_mon_reg, 801 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_ul), 802 .rf_para_ulink = rtw89_btc_8852bt_rf_ul, 803 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_dl), 804 .rf_para_dlink = rtw89_btc_8852bt_rf_dl, 805 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 806 BIT(RTW89_PS_MODE_CLK_GATED) | 807 BIT(RTW89_PS_MODE_PWR_GATED), 808 .low_power_hci_modes = 0, 809 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 810 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 811 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 812 .txwd_body_size = sizeof(struct rtw89_txwd_body), 813 .txwd_info_size = sizeof(struct rtw89_txwd_info), 814 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 815 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 816 .h2c_regs = rtw8852bt_h2c_regs, 817 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 818 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 819 .c2h_regs = rtw8852bt_c2h_regs, 820 .page_regs = &rtw8852bt_page_regs, 821 .wow_reason_reg = rtw8852bt_wow_wakeup_regs, 822 .cfo_src_fd = true, 823 .cfo_hw_comp = true, 824 .dcfo_comp = &rtw8852bt_dcfo_comp, 825 .dcfo_comp_sft = 10, 826 .imr_info = &rtw8852bt_imr_info, 827 .imr_dmac_table = NULL, 828 .imr_cmac_table = NULL, 829 .rrsr_cfgs = &rtw8852bt_rrsr_cfgs, 830 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 831 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 832 .rfkill_init = &rtw8852bt_rfkill_regs, 833 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 834 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 835 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 836 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 837 .edcca_regs = &rtw8852bt_edcca_regs, 838 #ifdef CONFIG_PM 839 .wowlan_stub = &rtw_wowlan_stub_8852bt, 840 #endif 841 .xtal_info = NULL, 842 }; 843 EXPORT_SYMBOL(rtw8852bt_chip_info); 844 845 MODULE_FIRMWARE(RTW8852BT_MODULE_FIRMWARE); 846 MODULE_AUTHOR("Realtek Corporation"); 847 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BT driver"); 848 MODULE_LICENSE("Dual BSD/GPL"); 849