1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_8852B_H__ 6 #define __RTW89_8852B_H__ 7 8 #include "core.h" 9 10 #define RF_PATH_NUM_8852B 2 11 #define BB_PATH_NUM_8852B 2 12 13 enum rtw8852b_pmac_mode { 14 NONE_TEST, 15 PKTS_TX, 16 PKTS_RX, 17 CONT_TX 18 }; 19 20 struct rtw8852b_u_efuse { 21 u8 rsvd[0x88]; 22 u8 mac_addr[ETH_ALEN]; 23 }; 24 25 struct rtw8852b_e_efuse { 26 u8 mac_addr[ETH_ALEN]; 27 }; 28 29 struct rtw8852b_tssi_offset { 30 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; 31 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; 32 u8 rsvd[7]; 33 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; 34 } __packed; 35 36 struct rtw8852b_efuse { 37 u8 rsvd[0x210]; 38 struct rtw8852b_tssi_offset path_a_tssi; 39 u8 rsvd1[10]; 40 struct rtw8852b_tssi_offset path_b_tssi; 41 u8 rsvd2[94]; 42 u8 channel_plan; 43 u8 xtal_k; 44 u8 rsvd3; 45 u8 iqk_lck; 46 u8 rsvd4[5]; 47 u8 reg_setting:2; 48 u8 tx_diversity:1; 49 u8 rx_diversity:2; 50 u8 ac_mode:1; 51 u8 module_type:2; 52 u8 rsvd5; 53 u8 shared_ant:1; 54 u8 coex_type:3; 55 u8 ant_iso:1; 56 u8 radio_on_off:1; 57 u8 rsvd6:2; 58 u8 eeprom_version; 59 u8 customer_id; 60 u8 tx_bb_swing_2g; 61 u8 tx_bb_swing_5g; 62 u8 tx_cali_pwr_trk_mode; 63 u8 trx_path_selection; 64 u8 rfe_type; 65 u8 country_code[2]; 66 u8 rsvd7[3]; 67 u8 path_a_therm; 68 u8 path_b_therm; 69 u8 rsvd8[2]; 70 u8 rx_gain_2g_ofdm; 71 u8 rsvd9; 72 u8 rx_gain_2g_cck; 73 u8 rsvd10; 74 u8 rx_gain_5g_low; 75 u8 rsvd11; 76 u8 rx_gain_5g_mid; 77 u8 rsvd12; 78 u8 rx_gain_5g_high; 79 u8 rsvd13[35]; 80 u8 path_a_cck_pwr_idx[6]; 81 u8 path_a_bw40_1tx_pwr_idx[5]; 82 u8 path_a_ofdm_1tx_pwr_idx_diff:4; 83 u8 path_a_bw20_1tx_pwr_idx_diff:4; 84 u8 path_a_bw20_2tx_pwr_idx_diff:4; 85 u8 path_a_bw40_2tx_pwr_idx_diff:4; 86 u8 path_a_cck_2tx_pwr_idx_diff:4; 87 u8 path_a_ofdm_2tx_pwr_idx_diff:4; 88 u8 rsvd14[0xf2]; 89 union { 90 struct rtw8852b_u_efuse u; 91 struct rtw8852b_e_efuse e; 92 }; 93 } __packed; 94 95 struct rtw8852b_bb_pmac_info { 96 u8 en_pmac_tx:1; 97 u8 is_cck:1; 98 u8 mode:3; 99 u8 rsvd:3; 100 u16 tx_cnt; 101 u16 period; 102 u16 tx_time; 103 u8 duty_cycle; 104 }; 105 106 struct rtw8852b_bb_tssi_bak { 107 u8 tx_path; 108 u8 rx_path; 109 u32 p0_rfmode; 110 u32 p0_rfmode_ftm; 111 u32 p1_rfmode; 112 u32 p1_rfmode_ftm; 113 s16 tx_pwr; /* S9 */ 114 }; 115 116 extern const struct rtw89_chip_info rtw8852b_chip_info; 117 118 void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev); 119 void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 120 struct rtw8852b_bb_pmac_info *tx_info, 121 enum rtw89_phy_idx idx); 122 void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 123 u16 tx_cnt, u16 period, u16 tx_time, 124 enum rtw89_phy_idx idx); 125 void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 126 enum rtw89_phy_idx idx); 127 void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path); 128 void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 129 enum rtw89_rf_path_bit rx_path); 130 void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 131 enum rtw89_phy_idx idx, u8 mode); 132 void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 133 struct rtw8852b_bb_tssi_bak *bak); 134 void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 135 const struct rtw8852b_bb_tssi_bak *bak); 136 137 #endif 138