1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852b.h" 11 #include "rtw8852b_common.h" 12 #include "rtw8852b_rfk.h" 13 #include "rtw8852b_table.h" 14 #include "txrx.h" 15 16 #define RTW8852B_FW_FORMAT_MAX 1 17 #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw" 18 #define RTW8852B_MODULE_FIRMWARE \ 19 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" 20 21 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { 22 {5, 341, grp_0}, /* ACH 0 */ 23 {5, 341, grp_0}, /* ACH 1 */ 24 {4, 342, grp_0}, /* ACH 2 */ 25 {4, 342, grp_0}, /* ACH 3 */ 26 {0, 0, grp_0}, /* ACH 4 */ 27 {0, 0, grp_0}, /* ACH 5 */ 28 {0, 0, grp_0}, /* ACH 6 */ 29 {0, 0, grp_0}, /* ACH 7 */ 30 {4, 342, grp_0}, /* B0MGQ */ 31 {4, 342, grp_0}, /* B0HIQ */ 32 {0, 0, grp_0}, /* B1MGQ */ 33 {0, 0, grp_0}, /* B1HIQ */ 34 {40, 0, 0} /* FWCMDQ */ 35 }; 36 37 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { 38 446, /* Group 0 */ 39 0, /* Group 1 */ 40 446, /* Public Max */ 41 0 /* WP threshold */ 42 }; 43 44 static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = { 45 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie, 46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 48 RTW89_HCIFC_POH}, 49 [RTW89_QTA_INVALID] = {NULL}, 50 }; 51 52 static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { 53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7, 54 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 55 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 56 &rtw89_mac_size.ple_qt58}, 57 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7, 58 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 59 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 60 &rtw89_mac_size.ple_qt_52b_wow}, 61 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 62 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 63 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 64 &rtw89_mac_size.ple_qt13}, 65 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 66 NULL}, 67 }; 68 69 static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = { 70 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 71 R_AX_H2CREG_DATA3 72 }; 73 74 static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = { 75 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 76 R_AX_C2HREG_DATA3 77 }; 78 79 static const u32 rtw8852b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 80 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 81 }; 82 83 static const struct rtw89_page_regs rtw8852b_page_regs = { 84 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 85 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 86 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 87 .ach_page_info = R_AX_ACH0_PAGE_INFO, 88 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 89 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 90 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 91 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 92 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 93 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 94 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 95 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 96 }; 97 98 static const struct rtw89_reg_def rtw8852b_dcfo_comp = { 99 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 100 }; 101 102 static const struct rtw89_imr_info rtw8852b_imr_info = { 103 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 104 .wsec_imr_reg = R_AX_SEC_DEBUG, 105 .wsec_imr_set = B_AX_IMR_ERROR, 106 .mpdu_tx_imr_set = 0, 107 .mpdu_rx_imr_set = 0, 108 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 109 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 110 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 111 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 112 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 113 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 114 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 115 .wde_imr_clr = B_AX_WDE_IMR_CLR, 116 .wde_imr_set = B_AX_WDE_IMR_SET, 117 .ple_imr_clr = B_AX_PLE_IMR_CLR, 118 .ple_imr_set = B_AX_PLE_IMR_SET, 119 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 120 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 121 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 122 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 123 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 124 .other_disp_imr_set = 0, 125 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 126 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 127 .bbrpt_err_imr_set = 0, 128 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 129 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 130 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 131 .cdma_imr_0_reg = R_AX_DLE_CTRL, 132 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 133 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 134 .cdma_imr_1_reg = 0, 135 .cdma_imr_1_clr = 0, 136 .cdma_imr_1_set = 0, 137 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 138 .phy_intf_imr_clr = 0, 139 .phy_intf_imr_set = 0, 140 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 141 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 142 .rmac_imr_set = B_AX_RMAC_IMR_SET, 143 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 144 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 145 .tmac_imr_set = B_AX_TMAC_IMR_SET, 146 }; 147 148 static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = { 149 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 150 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 151 }; 152 153 static const struct rtw89_dig_regs rtw8852b_dig_regs = { 154 .seg0_pd_reg = R_SEG0R_PD_V1, 155 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 156 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 157 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 158 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 159 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 160 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 161 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 162 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 163 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 164 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 165 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 166 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 167 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 168 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 169 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 170 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 171 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 172 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 173 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 174 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 175 }; 176 177 static const struct rtw89_edcca_regs rtw8852b_edcca_regs = { 178 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 179 .edcca_mask = B_EDCCA_LVL_MSK0, 180 .edcca_p_mask = B_EDCCA_LVL_MSK1, 181 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 182 .ppdu_mask = B_EDCCA_LVL_MSK3, 183 .rpt_a = R_EDCCA_RPT_A, 184 .rpt_b = R_EDCCA_RPT_B, 185 .rpt_sel = R_EDCCA_RPT_SEL, 186 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 187 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 188 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 189 }; 190 191 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = { 192 {255, 0, 0, 7}, /* 0 -> original */ 193 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 194 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 195 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 196 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 197 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 198 {6, 1, 0, 7}, 199 {13, 1, 0, 7}, 200 {13, 1, 0, 7} 201 }; 202 203 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = { 204 {255, 0, 0, 7}, /* 0 -> original */ 205 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 206 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 207 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 208 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 209 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 210 {255, 1, 0, 7}, 211 {255, 1, 0, 7}, 212 {255, 1, 0, 7} 213 }; 214 215 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { 216 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 217 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 218 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 219 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 220 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 221 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 222 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 223 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 224 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 225 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 226 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 227 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 228 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 229 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), 230 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), 231 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), 232 }; 233 234 static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 235 static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 236 237 static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev) 238 { 239 struct rtw89_efuse *efuse = &rtwdev->efuse; 240 241 if (efuse->rfe_type == 0x5) 242 rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA); 243 } 244 245 static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev) 246 { 247 u32 val32; 248 u32 ret; 249 250 rtw8852b_pwr_sps_ana(rtwdev); 251 252 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 253 B_AX_AFSM_PCIE_SUS_EN); 254 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 255 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 256 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 257 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 258 259 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 260 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 261 if (ret) 262 return ret; 263 264 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN); 265 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN, 266 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL); 267 if (ret) 268 return ret; 269 270 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); 271 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); 272 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 273 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 274 275 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 276 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 277 if (ret) 278 return ret; 279 280 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 281 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 282 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 283 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 284 285 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 286 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 287 288 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 289 290 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 291 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 292 if (ret) 293 return ret; 294 295 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 296 297 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 298 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 299 if (ret) 300 return ret; 301 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 302 XTAL_SI_OFF_WEI); 303 if (ret) 304 return ret; 305 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 306 XTAL_SI_OFF_EI); 307 if (ret) 308 return ret; 309 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 310 if (ret) 311 return ret; 312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 313 XTAL_SI_PON_WEI); 314 if (ret) 315 return ret; 316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 317 XTAL_SI_PON_EI); 318 if (ret) 319 return ret; 320 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 321 if (ret) 322 return ret; 323 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 324 if (ret) 325 return ret; 326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 327 if (ret) 328 return ret; 329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 330 if (ret) 331 return ret; 332 333 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 334 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 335 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 336 337 fsleep(1000); 338 339 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 340 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 341 342 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) 343 goto func_en; 344 345 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); 346 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); 347 348 if (rtwdev->hal.cv == CHIP_CBV) { 349 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 350 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA); 351 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 352 } 353 354 func_en: 355 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 356 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 357 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 358 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 359 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 360 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 361 B_AX_DMACREG_GCKEN); 362 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 363 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 364 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 365 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 366 B_AX_RMAC_EN); 367 368 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, 369 PINMUX_EESK_FUNC_SEL_BT_LOG); 370 371 return 0; 372 } 373 374 static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev) 375 { 376 u32 val32; 377 u32 ret; 378 379 rtw8852b_pwr_sps_ana(rtwdev); 380 381 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 382 XTAL_SI_RFC2RF); 383 if (ret) 384 return ret; 385 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 386 if (ret) 387 return ret; 388 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 389 if (ret) 390 return ret; 391 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 392 if (ret) 393 return ret; 394 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 395 if (ret) 396 return ret; 397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 398 XTAL_SI_SRAM2RFC); 399 if (ret) 400 return ret; 401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 402 if (ret) 403 return ret; 404 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 405 if (ret) 406 return ret; 407 408 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 409 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 410 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 411 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 412 413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 414 if (ret) 415 return ret; 416 417 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 418 419 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 420 if (ret) 421 return ret; 422 423 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 424 425 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 426 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 427 if (ret) 428 return ret; 429 430 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 431 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 432 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); 433 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 434 435 return 0; 436 } 437 438 static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 439 enum rtw89_phy_idx phy_idx, bool en) 440 { 441 if (en) { 442 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 443 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 444 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 445 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 446 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 447 if (band == RTW89_BAND_2G) 448 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 449 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 450 } else { 451 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 452 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 453 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 454 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 455 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 456 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 457 fsleep(1); 458 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 459 } 460 } 461 462 static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev, 463 enum rtw89_phy_idx phy_idx) 464 { 465 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 466 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 467 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 468 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 469 rtw8852bx_bb_reset_all(rtwdev, phy_idx); 470 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 471 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 472 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 473 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 474 } 475 476 static void rtw8852b_set_channel(struct rtw89_dev *rtwdev, 477 const struct rtw89_chan *chan, 478 enum rtw89_mac_idx mac_idx, 479 enum rtw89_phy_idx phy_idx) 480 { 481 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx); 482 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx); 483 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx); 484 } 485 486 static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 487 enum rtw89_rf_path path) 488 { 489 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; 490 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; 491 492 if (en) { 493 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0); 494 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0); 495 } else { 496 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1); 497 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1); 498 } 499 } 500 501 static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 502 u8 phy_idx) 503 { 504 if (!rtwdev->dbcc_en) { 505 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 506 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 507 } else { 508 if (phy_idx == RTW89_PHY_0) 509 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 510 else 511 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 512 } 513 } 514 515 static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en) 516 { 517 if (en) 518 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 519 else 520 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 521 } 522 523 static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 524 struct rtw89_channel_help_params *p, 525 const struct rtw89_chan *chan, 526 enum rtw89_mac_idx mac_idx, 527 enum rtw89_phy_idx phy_idx) 528 { 529 if (enter) { 530 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 531 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 532 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 533 rtw8852b_adc_en(rtwdev, false); 534 fsleep(40); 535 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 536 } else { 537 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 538 rtw8852b_adc_en(rtwdev, true); 539 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 540 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 541 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 542 } 543 } 544 545 static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev) 546 { 547 rtwdev->is_tssi_mode[RF_PATH_A] = false; 548 rtwdev->is_tssi_mode[RF_PATH_B] = false; 549 550 rtw8852b_dpk_init(rtwdev); 551 rtw8852b_rck(rtwdev); 552 rtw8852b_dack(rtwdev); 553 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0); 554 } 555 556 static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev) 557 { 558 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 559 560 rtw8852b_rx_dck(rtwdev, phy_idx); 561 rtw8852b_iqk(rtwdev, phy_idx); 562 rtw8852b_tssi(rtwdev, phy_idx, true); 563 rtw8852b_dpk(rtwdev, phy_idx); 564 } 565 566 static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev, 567 enum rtw89_phy_idx phy_idx) 568 { 569 rtw8852b_tssi_scan(rtwdev, phy_idx); 570 } 571 572 static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start) 573 { 574 rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 575 } 576 577 static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev) 578 { 579 rtw8852b_dpk_track(rtwdev); 580 } 581 582 static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) 583 { 584 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 585 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 586 587 if (ver->fcxinit == 7) { 588 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 589 md->md_v7.kt_ver = rtwdev->hal.cv; 590 md->md_v7.bt_solo = 0; 591 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 592 593 if (md->md_v7.rfe_type > 0) 594 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 595 else 596 md->md_v7.ant.num = 2; 597 598 md->md_v7.ant.diversity = 0; 599 md->md_v7.ant.isolation = 10; 600 601 if (md->md_v7.ant.num == 3) { 602 md->md_v7.ant.type = BTC_ANT_DEDICATED; 603 md->md_v7.bt_pos = BTC_BT_ALONE; 604 } else { 605 md->md_v7.ant.type = BTC_ANT_SHARED; 606 md->md_v7.bt_pos = BTC_BT_BTG; 607 } 608 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 609 rtwdev->btc.ant_type = md->md_v7.ant.type; 610 } else { 611 md->md.rfe_type = rtwdev->efuse.rfe_type; 612 md->md.cv = rtwdev->hal.cv; 613 md->md.bt_solo = 0; 614 md->md.switch_type = BTC_SWITCH_INTERNAL; 615 616 if (md->md.rfe_type > 0) 617 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 618 else 619 md->md.ant.num = 2; 620 621 md->md.ant.diversity = 0; 622 md->md.ant.isolation = 10; 623 624 if (md->md.ant.num == 3) { 625 md->md.ant.type = BTC_ANT_DEDICATED; 626 md->md.bt_pos = BTC_BT_ALONE; 627 } else { 628 md->md.ant.type = BTC_ANT_SHARED; 629 md->md.bt_pos = BTC_BT_BTG; 630 } 631 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 632 rtwdev->btc.ant_type = md->md.ant.type; 633 } 634 } 635 636 union rtw8852b_btc_wl_txpwr_ctrl { 637 u32 txpwr_val; 638 struct { 639 union { 640 u16 ctrl_all_time; 641 struct { 642 s16 data:9; 643 u16 rsvd:6; 644 u16 flag:1; 645 } all_time; 646 }; 647 union { 648 u16 ctrl_gnt_bt; 649 struct { 650 s16 data:9; 651 u16 rsvd:7; 652 } gnt_bt; 653 }; 654 }; 655 } __packed; 656 657 static void 658 rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 659 { 660 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 661 s32 val; 662 663 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 664 do { \ 665 u32 _wrt = FIELD_PREP(_msk, _val); \ 666 BUILD_BUG_ON(!!(_msk & _en)); \ 667 if (_cond) \ 668 _wrt |= _en; \ 669 else \ 670 _wrt &= ~_en; \ 671 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 672 _msk | _en, _wrt); \ 673 } while (0) 674 675 switch (arg.ctrl_all_time) { 676 case 0xffff: 677 val = 0; 678 break; 679 default: 680 val = arg.all_time.data; 681 break; 682 } 683 684 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 685 val, B_AX_FORCE_PWR_BY_RATE_EN, 686 arg.ctrl_all_time != 0xffff); 687 688 switch (arg.ctrl_gnt_bt) { 689 case 0xffff: 690 val = 0; 691 break; 692 default: 693 val = arg.gnt_bt.data; 694 break; 695 } 696 697 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 698 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 699 700 #undef __write_ctrl 701 } 702 703 static const struct rtw89_chip_ops rtw8852b_chip_ops = { 704 .enable_bb_rf = rtw8852bx_mac_enable_bb_rf, 705 .disable_bb_rf = rtw8852bx_mac_disable_bb_rf, 706 .bb_preinit = NULL, 707 .bb_postinit = NULL, 708 .bb_reset = rtw8852b_bb_reset, 709 .bb_sethw = rtw8852bx_bb_sethw, 710 .read_rf = rtw89_phy_read_rf_v1, 711 .write_rf = rtw89_phy_write_rf_v1, 712 .set_channel = rtw8852b_set_channel, 713 .set_channel_help = rtw8852b_set_channel_help, 714 .read_efuse = rtw8852bx_read_efuse, 715 .read_phycap = rtw8852bx_read_phycap, 716 .fem_setup = NULL, 717 .rfe_gpio = NULL, 718 .rfk_hw_init = NULL, 719 .rfk_init = rtw8852b_rfk_init, 720 .rfk_init_late = NULL, 721 .rfk_channel = rtw8852b_rfk_channel, 722 .rfk_band_changed = rtw8852b_rfk_band_changed, 723 .rfk_scan = rtw8852b_rfk_scan, 724 .rfk_track = rtw8852b_rfk_track, 725 .power_trim = rtw8852bx_power_trim, 726 .set_txpwr = rtw8852bx_set_txpwr, 727 .set_txpwr_ctrl = rtw8852bx_set_txpwr_ctrl, 728 .init_txpwr_unit = rtw8852bx_init_txpwr_unit, 729 .get_thermal = rtw8852bx_get_thermal, 730 .ctrl_btg_bt_rx = rtw8852bx_ctrl_btg_bt_rx, 731 .query_ppdu = rtw8852bx_query_ppdu, 732 .ctrl_nbtg_bt_tx = rtw8852bx_ctrl_nbtg_bt_tx, 733 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, 734 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, 735 .pwr_on_func = rtw8852b_pwr_on_func, 736 .pwr_off_func = rtw8852b_pwr_off_func, 737 .query_rxdesc = rtw89_core_query_rxdesc, 738 .fill_txdesc = rtw89_core_fill_txdesc, 739 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 740 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 741 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 742 .stop_sch_tx = rtw89_mac_stop_sch_tx, 743 .resume_sch_tx = rtw89_mac_resume_sch_tx, 744 .h2c_dctl_sec_cam = NULL, 745 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 746 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 747 .h2c_ampdu_cmac_tbl = NULL, 748 .h2c_default_dmac_tbl = NULL, 749 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 750 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 751 752 .btc_set_rfe = rtw8852b_btc_set_rfe, 753 .btc_init_cfg = rtw8852bx_btc_init_cfg, 754 .btc_set_wl_pri = rtw8852bx_btc_set_wl_pri, 755 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl, 756 .btc_get_bt_rssi = rtw8852bx_btc_get_bt_rssi, 757 .btc_update_bt_cnt = rtw8852bx_btc_update_bt_cnt, 758 .btc_wl_s1_standby = rtw8852bx_btc_wl_s1_standby, 759 .btc_set_wl_rx_gain = rtw8852bx_btc_set_wl_rx_gain, 760 .btc_set_policy = rtw89_btc_set_policy_v1, 761 }; 762 763 #ifdef CONFIG_PM 764 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = { 765 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 766 .n_patterns = RTW89_MAX_PATTERN_NUM, 767 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 768 .pattern_min_len = 1, 769 }; 770 #endif 771 772 const struct rtw89_chip_info rtw8852b_chip_info = { 773 .chip_id = RTL8852B, 774 .chip_gen = RTW89_CHIP_AX, 775 .ops = &rtw8852b_chip_ops, 776 .mac_def = &rtw89_mac_gen_ax, 777 .phy_def = &rtw89_phy_gen_ax, 778 .fw_basename = RTW8852B_FW_BASENAME, 779 .fw_format_max = RTW8852B_FW_FORMAT_MAX, 780 .try_ce_fw = true, 781 .bbmcu_nr = 0, 782 .needed_fw_elms = 0, 783 .fifo_size = 196608, 784 .small_fifo_size = true, 785 .dle_scc_rsvd_size = 98304, 786 .max_amsdu_limit = 5000, 787 .dis_2g_40m_ul_ofdma = true, 788 .rsvd_ple_ofst = 0x2f800, 789 .hfc_param_ini = rtw8852b_hfc_param_ini_pcie, 790 .dle_mem = rtw8852b_dle_mem_pcie, 791 .wde_qempty_acq_grpnum = 4, 792 .wde_qempty_mgq_grpsel = 4, 793 .rf_base_addr = {0xe000, 0xf000}, 794 .pwr_on_seq = NULL, 795 .pwr_off_seq = NULL, 796 .bb_table = &rtw89_8852b_phy_bb_table, 797 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table, 798 .rf_table = {&rtw89_8852b_phy_radioa_table, 799 &rtw89_8852b_phy_radiob_table,}, 800 .nctl_table = &rtw89_8852b_phy_nctl_table, 801 .nctl_post_table = NULL, 802 .dflt_parms = &rtw89_8852b_dflt_parms, 803 .rfe_parms_conf = NULL, 804 .txpwr_factor_rf = 2, 805 .txpwr_factor_mac = 1, 806 .dig_table = NULL, 807 .dig_regs = &rtw8852b_dig_regs, 808 .tssi_dbw_table = NULL, 809 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 810 .support_chanctx_num = 0, 811 .support_rnr = false, 812 .support_bands = BIT(NL80211_BAND_2GHZ) | 813 BIT(NL80211_BAND_5GHZ), 814 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 815 BIT(NL80211_CHAN_WIDTH_40) | 816 BIT(NL80211_CHAN_WIDTH_80), 817 .support_unii4 = true, 818 .ul_tb_waveform_ctrl = true, 819 .ul_tb_pwr_diff = false, 820 .hw_sec_hdr = false, 821 .rf_path_num = 2, 822 .tx_nss = 2, 823 .rx_nss = 2, 824 .acam_num = 128, 825 .bcam_num = 10, 826 .scam_num = 128, 827 .bacam_num = 2, 828 .bacam_dynamic_num = 4, 829 .bacam_ver = RTW89_BACAM_V0, 830 .ppdu_max_usr = 4, 831 .sec_ctrl_efuse_size = 4, 832 .physical_efuse_size = 1216, 833 .logical_efuse_size = 2048, 834 .limit_efuse_size = 1280, 835 .dav_phy_efuse_size = 96, 836 .dav_log_efuse_size = 16, 837 .efuse_blocks = NULL, 838 .phycap_addr = 0x580, 839 .phycap_size = 128, 840 .para_ver = 0, 841 .wlcx_desired = 0x05050000, 842 .btcx_desired = 0x5, 843 .scbd = 0x1, 844 .mailbox = 0x1, 845 846 .afh_guard_ch = 6, 847 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres, 848 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres, 849 .rssi_tol = 2, 850 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg), 851 .mon_reg = rtw89_btc_8852b_mon_reg, 852 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul), 853 .rf_para_ulink = rtw89_btc_8852b_rf_ul, 854 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl), 855 .rf_para_dlink = rtw89_btc_8852b_rf_dl, 856 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 857 BIT(RTW89_PS_MODE_CLK_GATED) | 858 BIT(RTW89_PS_MODE_PWR_GATED), 859 .low_power_hci_modes = 0, 860 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 861 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 862 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 863 .txwd_body_size = sizeof(struct rtw89_txwd_body), 864 .txwd_info_size = sizeof(struct rtw89_txwd_info), 865 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 866 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 867 .h2c_regs = rtw8852b_h2c_regs, 868 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 869 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 870 .c2h_regs = rtw8852b_c2h_regs, 871 .page_regs = &rtw8852b_page_regs, 872 .wow_reason_reg = rtw8852b_wow_wakeup_regs, 873 .cfo_src_fd = true, 874 .cfo_hw_comp = true, 875 .dcfo_comp = &rtw8852b_dcfo_comp, 876 .dcfo_comp_sft = 10, 877 .imr_info = &rtw8852b_imr_info, 878 .imr_dmac_table = NULL, 879 .imr_cmac_table = NULL, 880 .rrsr_cfgs = &rtw8852b_rrsr_cfgs, 881 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 882 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 883 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 884 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 885 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 886 .edcca_regs = &rtw8852b_edcca_regs, 887 #ifdef CONFIG_PM 888 .wowlan_stub = &rtw_wowlan_stub_8852b, 889 #endif 890 .xtal_info = NULL, 891 }; 892 EXPORT_SYMBOL(rtw8852b_chip_info); 893 894 MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE); 895 MODULE_AUTHOR("Realtek Corporation"); 896 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver"); 897 MODULE_LICENSE("Dual BSD/GPL"); 898