1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852b.h" 11 #include "rtw8852b_rfk.h" 12 #include "rtw8852b_table.h" 13 #include "txrx.h" 14 15 #define RTW8852B_FW_FORMAT_MAX 1 16 #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw" 17 #define RTW8852B_MODULE_FIRMWARE \ 18 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { 21 {5, 341, grp_0}, /* ACH 0 */ 22 {5, 341, grp_0}, /* ACH 1 */ 23 {4, 342, grp_0}, /* ACH 2 */ 24 {4, 342, grp_0}, /* ACH 3 */ 25 {0, 0, grp_0}, /* ACH 4 */ 26 {0, 0, grp_0}, /* ACH 5 */ 27 {0, 0, grp_0}, /* ACH 6 */ 28 {0, 0, grp_0}, /* ACH 7 */ 29 {4, 342, grp_0}, /* B0MGQ */ 30 {4, 342, grp_0}, /* B0HIQ */ 31 {0, 0, grp_0}, /* B1MGQ */ 32 {0, 0, grp_0}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { 37 446, /* Group 0 */ 38 0, /* Group 1 */ 39 446, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7, 53 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 54 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 55 &rtw89_mac_size.ple_qt58}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7, 57 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 58 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 59 &rtw89_mac_size.ple_qt_52b_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 61 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = { 69 {0x4580, 0x0000ffff, 0x0}, 70 {0x4580, 0xffff0000, 0x0}, 71 {0x4584, 0x0000ffff, 0x0}, 72 {0x4584, 0xffff0000, 0x0}, 73 {0x4580, 0x0000ffff, 0x1}, 74 {0x4578, 0x00ffffff, 0x2018b}, 75 {0x4570, 0x03ffffff, 0x7}, 76 {0x4574, 0x03ffffff, 0x32407}, 77 {0x45b8, 0x00000010, 0x0}, 78 {0x45b8, 0x00000100, 0x0}, 79 {0x45b8, 0x00000080, 0x0}, 80 {0x45b8, 0x00000008, 0x0}, 81 {0x45a0, 0x0000ff00, 0x0}, 82 {0x45a0, 0xff000000, 0x1}, 83 {0x45a4, 0x0000ff00, 0x2}, 84 {0x45a4, 0xff000000, 0x3}, 85 {0x45b8, 0x00000020, 0x0}, 86 {0x4568, 0xe0000000, 0x0}, 87 {0x45b8, 0x00000002, 0x1}, 88 {0x456c, 0xe0000000, 0x0}, 89 {0x45b4, 0x00006000, 0x0}, 90 {0x45b4, 0x00001800, 0x1}, 91 {0x45b8, 0x00000040, 0x0}, 92 {0x45b8, 0x00000004, 0x0}, 93 {0x45b8, 0x00000200, 0x0}, 94 {0x4598, 0xf8000000, 0x0}, 95 {0x45b8, 0x00100000, 0x0}, 96 {0x45a8, 0x00000fc0, 0x0}, 97 {0x45b8, 0x00200000, 0x0}, 98 {0x45b0, 0x00000038, 0x0}, 99 {0x45b0, 0x000001c0, 0x0}, 100 {0x45a0, 0x000000ff, 0x0}, 101 {0x45b8, 0x00400000, 0x0}, 102 {0x4590, 0x000007ff, 0x0}, 103 {0x45b0, 0x00000e00, 0x0}, 104 {0x45ac, 0x0000001f, 0x0}, 105 {0x45b8, 0x00800000, 0x0}, 106 {0x45a8, 0x0003f000, 0x0}, 107 {0x45b8, 0x01000000, 0x0}, 108 {0x45b0, 0x00007000, 0x0}, 109 {0x45b0, 0x00038000, 0x0}, 110 {0x45a0, 0x00ff0000, 0x0}, 111 {0x45b8, 0x02000000, 0x0}, 112 {0x4590, 0x003ff800, 0x0}, 113 {0x45b0, 0x001c0000, 0x0}, 114 {0x45ac, 0x000003e0, 0x0}, 115 {0x45b8, 0x04000000, 0x0}, 116 {0x45a8, 0x00fc0000, 0x0}, 117 {0x45b8, 0x08000000, 0x0}, 118 {0x45b0, 0x00e00000, 0x0}, 119 {0x45b0, 0x07000000, 0x0}, 120 {0x45a4, 0x000000ff, 0x0}, 121 {0x45b8, 0x10000000, 0x0}, 122 {0x4594, 0x000007ff, 0x0}, 123 {0x45b0, 0x38000000, 0x0}, 124 {0x45ac, 0x00007c00, 0x0}, 125 {0x45b8, 0x20000000, 0x0}, 126 {0x45a8, 0x3f000000, 0x0}, 127 {0x45b8, 0x40000000, 0x0}, 128 {0x45b4, 0x00000007, 0x0}, 129 {0x45b4, 0x00000038, 0x0}, 130 {0x45a4, 0x00ff0000, 0x0}, 131 {0x45b8, 0x80000000, 0x0}, 132 {0x4594, 0x003ff800, 0x0}, 133 {0x45b4, 0x000001c0, 0x0}, 134 {0x4598, 0xf8000000, 0x0}, 135 {0x45b8, 0x00100000, 0x0}, 136 {0x45a8, 0x00000fc0, 0x7}, 137 {0x45b8, 0x00200000, 0x0}, 138 {0x45b0, 0x00000038, 0x0}, 139 {0x45b0, 0x000001c0, 0x0}, 140 {0x45a0, 0x000000ff, 0x0}, 141 {0x45b4, 0x06000000, 0x0}, 142 {0x45b0, 0x00000007, 0x0}, 143 {0x45b8, 0x00080000, 0x0}, 144 {0x45a8, 0x0000003f, 0x0}, 145 {0x457c, 0xffe00000, 0x1}, 146 {0x4530, 0xffffffff, 0x0}, 147 {0x4588, 0x00003fff, 0x0}, 148 {0x4598, 0x000001ff, 0x0}, 149 {0x4534, 0xffffffff, 0x0}, 150 {0x4538, 0xffffffff, 0x0}, 151 {0x453c, 0xffffffff, 0x0}, 152 {0x4588, 0x0fffc000, 0x0}, 153 {0x4598, 0x0003fe00, 0x0}, 154 {0x4540, 0xffffffff, 0x0}, 155 {0x4544, 0xffffffff, 0x0}, 156 {0x4548, 0xffffffff, 0x0}, 157 {0x458c, 0x00003fff, 0x0}, 158 {0x4598, 0x07fc0000, 0x0}, 159 {0x454c, 0xffffffff, 0x0}, 160 {0x4550, 0xffffffff, 0x0}, 161 {0x4554, 0xffffffff, 0x0}, 162 {0x458c, 0x0fffc000, 0x0}, 163 {0x459c, 0x000001ff, 0x0}, 164 {0x4558, 0xffffffff, 0x0}, 165 {0x455c, 0xffffffff, 0x0}, 166 {0x4530, 0xffffffff, 0x4e790001}, 167 {0x4588, 0x00003fff, 0x0}, 168 {0x4598, 0x000001ff, 0x1}, 169 {0x4534, 0xffffffff, 0x0}, 170 {0x4538, 0xffffffff, 0x4b}, 171 {0x45ac, 0x38000000, 0x7}, 172 {0x4588, 0xf0000000, 0x0}, 173 {0x459c, 0x7e000000, 0x0}, 174 {0x45b8, 0x00040000, 0x0}, 175 {0x45b8, 0x00020000, 0x0}, 176 {0x4590, 0xffc00000, 0x0}, 177 {0x45b8, 0x00004000, 0x0}, 178 {0x4578, 0xff000000, 0x0}, 179 {0x45b8, 0x00000400, 0x0}, 180 {0x45b8, 0x00000800, 0x0}, 181 {0x45b8, 0x00001000, 0x0}, 182 {0x45b8, 0x00002000, 0x0}, 183 {0x45b4, 0x00018000, 0x0}, 184 {0x45ac, 0x07800000, 0x0}, 185 {0x45b4, 0x00000600, 0x2}, 186 {0x459c, 0x0001fe00, 0x80}, 187 {0x45ac, 0x00078000, 0x3}, 188 {0x459c, 0x01fe0000, 0x1}, 189 }; 190 191 static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = { 192 {0x46D0, GENMASK(1, 0), 0x3}, 193 {0x4790, GENMASK(1, 0), 0x3}, 194 {0x4AD4, GENMASK(31, 0), 0xf}, 195 {0x4AE0, GENMASK(31, 0), 0xf}, 196 {0x4688, GENMASK(31, 24), 0x80}, 197 {0x476C, GENMASK(31, 24), 0x80}, 198 {0x4694, GENMASK(7, 0), 0x80}, 199 {0x4694, GENMASK(15, 8), 0x80}, 200 {0x4778, GENMASK(7, 0), 0x80}, 201 {0x4778, GENMASK(15, 8), 0x80}, 202 {0x4AE4, GENMASK(23, 0), 0x780D1E}, 203 {0x4AEC, GENMASK(23, 0), 0x780D1E}, 204 {0x469C, GENMASK(31, 26), 0x34}, 205 {0x49F0, GENMASK(31, 26), 0x34}, 206 }; 207 208 static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs); 209 210 static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = { 211 {0x46D0, GENMASK(1, 0), 0x0}, 212 {0x4790, GENMASK(1, 0), 0x0}, 213 {0x4AD4, GENMASK(31, 0), 0x60}, 214 {0x4AE0, GENMASK(31, 0), 0x60}, 215 {0x4688, GENMASK(31, 24), 0x1a}, 216 {0x476C, GENMASK(31, 24), 0x1a}, 217 {0x4694, GENMASK(7, 0), 0x2a}, 218 {0x4694, GENMASK(15, 8), 0x2a}, 219 {0x4778, GENMASK(7, 0), 0x2a}, 220 {0x4778, GENMASK(15, 8), 0x2a}, 221 {0x4AE4, GENMASK(23, 0), 0x79E99E}, 222 {0x4AEC, GENMASK(23, 0), 0x79E99E}, 223 {0x469C, GENMASK(31, 26), 0x26}, 224 {0x49F0, GENMASK(31, 26), 0x26}, 225 }; 226 227 static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs); 228 229 static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = { 230 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 231 R_AX_H2CREG_DATA3 232 }; 233 234 static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = { 235 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 236 R_AX_C2HREG_DATA3 237 }; 238 239 static const struct rtw89_page_regs rtw8852b_page_regs = { 240 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 241 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 242 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 243 .ach_page_info = R_AX_ACH0_PAGE_INFO, 244 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 245 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 246 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 247 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 248 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 249 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 250 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 251 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 252 }; 253 254 static const struct rtw89_reg_def rtw8852b_dcfo_comp = { 255 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 256 }; 257 258 static const struct rtw89_imr_info rtw8852b_imr_info = { 259 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 260 .wsec_imr_reg = R_AX_SEC_DEBUG, 261 .wsec_imr_set = B_AX_IMR_ERROR, 262 .mpdu_tx_imr_set = 0, 263 .mpdu_rx_imr_set = 0, 264 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 265 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 266 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 267 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 268 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 269 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 270 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 271 .wde_imr_clr = B_AX_WDE_IMR_CLR, 272 .wde_imr_set = B_AX_WDE_IMR_SET, 273 .ple_imr_clr = B_AX_PLE_IMR_CLR, 274 .ple_imr_set = B_AX_PLE_IMR_SET, 275 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 276 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 277 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 278 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 279 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 280 .other_disp_imr_set = 0, 281 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 282 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 283 .bbrpt_err_imr_set = 0, 284 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 285 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 286 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 287 .cdma_imr_0_reg = R_AX_DLE_CTRL, 288 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 289 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 290 .cdma_imr_1_reg = 0, 291 .cdma_imr_1_clr = 0, 292 .cdma_imr_1_set = 0, 293 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 294 .phy_intf_imr_clr = 0, 295 .phy_intf_imr_set = 0, 296 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 297 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 298 .rmac_imr_set = B_AX_RMAC_IMR_SET, 299 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 300 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 301 .tmac_imr_set = B_AX_TMAC_IMR_SET, 302 }; 303 304 static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = { 305 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 306 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 307 }; 308 309 static const struct rtw89_dig_regs rtw8852b_dig_regs = { 310 .seg0_pd_reg = R_SEG0R_PD_V1, 311 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 312 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 313 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 314 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 315 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 316 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 317 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 318 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 319 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 320 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 321 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 322 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 323 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 324 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 325 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 326 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 327 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 328 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 329 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 330 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 331 }; 332 333 static const struct rtw89_edcca_regs rtw8852b_edcca_regs = { 334 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 335 .edcca_mask = B_EDCCA_LVL_MSK0, 336 .edcca_p_mask = B_EDCCA_LVL_MSK1, 337 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 338 .ppdu_mask = B_EDCCA_LVL_MSK3, 339 .rpt_a = R_EDCCA_RPT_A, 340 .rpt_b = R_EDCCA_RPT_B, 341 .rpt_sel = R_EDCCA_RPT_SEL, 342 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 343 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 344 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 345 }; 346 347 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = { 348 {255, 0, 0, 7}, /* 0 -> original */ 349 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 350 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 351 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 352 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 353 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 354 {6, 1, 0, 7}, 355 {13, 1, 0, 7}, 356 {13, 1, 0, 7} 357 }; 358 359 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = { 360 {255, 0, 0, 7}, /* 0 -> original */ 361 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 362 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 363 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 364 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 365 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 366 {255, 1, 0, 7}, 367 {255, 1, 0, 7}, 368 {255, 1, 0, 7} 369 }; 370 371 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { 372 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 373 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 374 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 375 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 376 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 377 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 378 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 379 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 380 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 381 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 382 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 383 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 384 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 385 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), 386 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), 387 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), 388 }; 389 390 static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 391 static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 392 393 static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev) 394 { 395 struct rtw89_efuse *efuse = &rtwdev->efuse; 396 397 if (efuse->rfe_type == 0x5) 398 rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA); 399 } 400 401 static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev) 402 { 403 u32 val32; 404 u32 ret; 405 406 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 407 B_AX_AFSM_PCIE_SUS_EN); 408 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 409 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 410 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 411 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 412 413 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 414 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 415 if (ret) 416 return ret; 417 418 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN); 419 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN, 420 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL); 421 if (ret) 422 return ret; 423 424 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); 425 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); 426 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 427 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 428 429 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 430 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 431 if (ret) 432 return ret; 433 434 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 435 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 436 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 437 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 438 439 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 440 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 441 442 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 443 444 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 445 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 446 if (ret) 447 return ret; 448 449 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 450 451 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 452 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 453 if (ret) 454 return ret; 455 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 456 XTAL_SI_OFF_WEI); 457 if (ret) 458 return ret; 459 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 460 XTAL_SI_OFF_EI); 461 if (ret) 462 return ret; 463 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 464 if (ret) 465 return ret; 466 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 467 XTAL_SI_PON_WEI); 468 if (ret) 469 return ret; 470 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 471 XTAL_SI_PON_EI); 472 if (ret) 473 return ret; 474 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 475 if (ret) 476 return ret; 477 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 478 if (ret) 479 return ret; 480 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 481 if (ret) 482 return ret; 483 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 484 if (ret) 485 return ret; 486 487 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 488 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 489 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 490 491 fsleep(1000); 492 493 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 494 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 495 496 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) 497 goto func_en; 498 499 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); 500 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); 501 502 if (rtwdev->hal.cv == CHIP_CBV) { 503 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 504 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA); 505 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 506 } 507 508 func_en: 509 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 510 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 511 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 512 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 513 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 514 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 515 B_AX_DMACREG_GCKEN); 516 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 517 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 518 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 519 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 520 B_AX_RMAC_EN); 521 522 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, 523 PINMUX_EESK_FUNC_SEL_BT_LOG); 524 525 return 0; 526 } 527 528 static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev) 529 { 530 u32 val32; 531 u32 ret; 532 533 /* Only do once during probe stage after reading efuse */ 534 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 535 rtw8852b_pwr_sps_ana(rtwdev); 536 537 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 538 XTAL_SI_RFC2RF); 539 if (ret) 540 return ret; 541 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 542 if (ret) 543 return ret; 544 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 545 if (ret) 546 return ret; 547 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 548 if (ret) 549 return ret; 550 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 551 if (ret) 552 return ret; 553 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 554 XTAL_SI_SRAM2RFC); 555 if (ret) 556 return ret; 557 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 558 if (ret) 559 return ret; 560 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 561 if (ret) 562 return ret; 563 564 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 565 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 566 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 567 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 568 569 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 570 if (ret) 571 return ret; 572 573 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 574 575 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 576 if (ret) 577 return ret; 578 579 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 580 581 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 582 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 583 if (ret) 584 return ret; 585 586 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 587 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 588 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); 589 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 590 591 return 0; 592 } 593 594 static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse, 595 struct rtw8852b_efuse *map) 596 { 597 ether_addr_copy(efuse->addr, map->e.mac_addr); 598 efuse->rfe_type = map->rfe_type; 599 efuse->xtal_cap = map->xtal_k; 600 } 601 602 static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 603 struct rtw8852b_efuse *map) 604 { 605 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 606 struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 607 u8 i, j; 608 609 tssi->thermal[RF_PATH_A] = map->path_a_therm; 610 tssi->thermal[RF_PATH_B] = map->path_b_therm; 611 612 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 613 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 614 sizeof(ofst[i]->cck_tssi)); 615 616 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 617 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 618 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 619 i, j, tssi->tssi_cck[i][j]); 620 621 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 622 sizeof(ofst[i]->bw40_tssi)); 623 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 624 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 625 626 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 627 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 628 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 629 i, j, tssi->tssi_mcs[i][j]); 630 } 631 } 632 633 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 634 { 635 if (high) 636 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 637 if (low) 638 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 639 640 return data != 0xff; 641 } 642 643 static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 644 struct rtw8852b_efuse *map) 645 { 646 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 647 bool valid = false; 648 649 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 650 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 651 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 652 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 653 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 654 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 655 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 656 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 657 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 658 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 659 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 660 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 661 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 662 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 663 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 664 665 gain->offset_valid = valid; 666 } 667 668 static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 669 enum rtw89_efuse_block block) 670 { 671 struct rtw89_efuse *efuse = &rtwdev->efuse; 672 struct rtw8852b_efuse *map; 673 674 map = (struct rtw8852b_efuse *)log_map; 675 676 efuse->country_code[0] = map->country_code[0]; 677 efuse->country_code[1] = map->country_code[1]; 678 rtw8852b_efuse_parsing_tssi(rtwdev, map); 679 rtw8852b_efuse_parsing_gain_offset(rtwdev, map); 680 681 switch (rtwdev->hci.type) { 682 case RTW89_HCI_TYPE_PCIE: 683 rtw8852be_efuse_parsing(efuse, map); 684 break; 685 default: 686 return -EOPNOTSUPP; 687 } 688 689 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 690 691 return 0; 692 } 693 694 static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map) 695 { 696 #define PWR_K_CHK_OFFSET 0x5E9 697 #define PWR_K_CHK_VALUE 0xAA 698 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr; 699 700 if (phycap_map[offset] == PWR_K_CHK_VALUE) 701 rtwdev->efuse.power_k_valid = true; 702 } 703 704 static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 705 { 706 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 707 static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB}; 708 u32 addr = rtwdev->chip->phycap_addr; 709 bool pg = false; 710 u32 ofst; 711 u8 i, j; 712 713 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 714 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 715 /* addrs are in decreasing order */ 716 ofst = tssi_trim_addr[i] - addr - j; 717 tssi->tssi_trim[i][j] = phycap_map[ofst]; 718 719 if (phycap_map[ofst] != 0xff) 720 pg = true; 721 } 722 } 723 724 if (!pg) { 725 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 726 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 727 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 728 } 729 730 for (i = 0; i < RF_PATH_NUM_8852B; i++) 731 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 732 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 733 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 734 i, j, tssi->tssi_trim[i][j], 735 tssi_trim_addr[i] - j); 736 } 737 738 static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 739 u8 *phycap_map) 740 { 741 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 742 static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC}; 743 u32 addr = rtwdev->chip->phycap_addr; 744 u8 i; 745 746 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 747 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 748 749 rtw89_debug(rtwdev, RTW89_DBG_RFK, 750 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 751 i, info->thermal_trim[i]); 752 753 if (info->thermal_trim[i] != 0xff) 754 info->pg_thermal_trim = true; 755 } 756 } 757 758 static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev) 759 { 760 #define __thm_setting(raw) \ 761 ({ \ 762 u8 __v = (raw); \ 763 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 764 }) 765 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 766 u8 i, val; 767 768 if (!info->pg_thermal_trim) { 769 rtw89_debug(rtwdev, RTW89_DBG_RFK, 770 "[THERMAL][TRIM] no PG, do nothing\n"); 771 772 return; 773 } 774 775 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 776 val = __thm_setting(info->thermal_trim[i]); 777 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 778 779 rtw89_debug(rtwdev, RTW89_DBG_RFK, 780 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 781 i, val); 782 } 783 #undef __thm_setting 784 } 785 786 static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 787 u8 *phycap_map) 788 { 789 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 790 static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB}; 791 u32 addr = rtwdev->chip->phycap_addr; 792 u8 i; 793 794 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 795 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 796 797 rtw89_debug(rtwdev, RTW89_DBG_RFK, 798 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 799 i, info->pa_bias_trim[i]); 800 801 if (info->pa_bias_trim[i] != 0xff) 802 info->pg_pa_bias_trim = true; 803 } 804 } 805 806 static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev) 807 { 808 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 809 u8 pabias_2g, pabias_5g; 810 u8 i; 811 812 if (!info->pg_pa_bias_trim) { 813 rtw89_debug(rtwdev, RTW89_DBG_RFK, 814 "[PA_BIAS][TRIM] no PG, do nothing\n"); 815 816 return; 817 } 818 819 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 820 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 821 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 822 823 rtw89_debug(rtwdev, RTW89_DBG_RFK, 824 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 825 i, pabias_2g, pabias_5g); 826 827 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 828 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 829 } 830 } 831 832 static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) 833 { 834 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { 835 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, 836 {0x590, 0x58F, 0, 0x58E, 0x58D}, 837 }; 838 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 839 u32 phycap_addr = rtwdev->chip->phycap_addr; 840 bool valid = false; 841 int path, i; 842 u8 data; 843 844 for (path = 0; path < 2; path++) 845 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { 846 if (comp_addrs[path][i] == 0) 847 continue; 848 849 data = phycap_map[comp_addrs[path][i] - phycap_addr]; 850 valid |= _decode_efuse_gain(data, NULL, 851 &gain->comp[path][i]); 852 } 853 854 gain->comp_valid = valid; 855 } 856 857 static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 858 { 859 rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map); 860 rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map); 861 rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map); 862 rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 863 rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map); 864 865 return 0; 866 } 867 868 static void rtw8852b_power_trim(struct rtw89_dev *rtwdev) 869 { 870 rtw8852b_thermal_trim(rtwdev); 871 rtw8852b_pa_bias_trim(rtwdev); 872 } 873 874 static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev, 875 const struct rtw89_chan *chan, 876 u8 mac_idx) 877 { 878 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 879 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 880 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 881 u8 txsc20 = 0, txsc40 = 0; 882 883 switch (chan->band_width) { 884 case RTW89_CHANNEL_WIDTH_80: 885 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); 886 fallthrough; 887 case RTW89_CHANNEL_WIDTH_40: 888 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); 889 break; 890 default: 891 break; 892 } 893 894 switch (chan->band_width) { 895 case RTW89_CHANNEL_WIDTH_80: 896 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 897 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 898 break; 899 case RTW89_CHANNEL_WIDTH_40: 900 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 901 rtw89_write32(rtwdev, sub_carr, txsc20); 902 break; 903 case RTW89_CHANNEL_WIDTH_20: 904 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 905 rtw89_write32(rtwdev, sub_carr, 0); 906 break; 907 default: 908 break; 909 } 910 911 if (chan->channel > 14) { 912 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); 913 rtw89_write8_set(rtwdev, chk_rate, 914 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 915 } else { 916 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); 917 rtw89_write8_clr(rtwdev, chk_rate, 918 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 919 } 920 } 921 922 static const u32 rtw8852b_sco_barker_threshold[14] = { 923 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 924 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 925 }; 926 927 static const u32 rtw8852b_sco_cck_threshold[14] = { 928 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 929 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 930 }; 931 932 static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) 933 { 934 u8 ch_element = primary_ch - 1; 935 936 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 937 rtw8852b_sco_barker_threshold[ch_element]); 938 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 939 rtw8852b_sco_cck_threshold[ch_element]); 940 } 941 942 static u8 rtw8852b_sco_mapping(u8 central_ch) 943 { 944 if (central_ch == 1) 945 return 109; 946 else if (central_ch >= 2 && central_ch <= 6) 947 return 108; 948 else if (central_ch >= 7 && central_ch <= 10) 949 return 107; 950 else if (central_ch >= 11 && central_ch <= 14) 951 return 106; 952 else if (central_ch == 36 || central_ch == 38) 953 return 51; 954 else if (central_ch >= 40 && central_ch <= 58) 955 return 50; 956 else if (central_ch >= 60 && central_ch <= 64) 957 return 49; 958 else if (central_ch == 100 || central_ch == 102) 959 return 48; 960 else if (central_ch >= 104 && central_ch <= 126) 961 return 47; 962 else if (central_ch >= 128 && central_ch <= 151) 963 return 46; 964 else if (central_ch >= 153 && central_ch <= 177) 965 return 45; 966 else 967 return 0; 968 } 969 970 struct rtw8852b_bb_gain { 971 u32 gain_g[BB_PATH_NUM_8852B]; 972 u32 gain_a[BB_PATH_NUM_8852B]; 973 u32 gain_mask; 974 }; 975 976 static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 977 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 978 .gain_mask = 0x00ff0000 }, 979 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 980 .gain_mask = 0xff000000 }, 981 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 982 .gain_mask = 0x000000ff }, 983 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 984 .gain_mask = 0x0000ff00 }, 985 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 986 .gain_mask = 0x00ff0000 }, 987 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 988 .gain_mask = 0xff000000 }, 989 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 990 .gain_mask = 0x000000ff }, 991 }; 992 993 static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 994 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 995 .gain_mask = 0x00ff0000 }, 996 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 997 .gain_mask = 0xff000000 }, 998 }; 999 1000 static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev, 1001 enum rtw89_subband subband, 1002 enum rtw89_rf_path path) 1003 { 1004 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1005 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 1006 s32 val; 1007 u32 reg; 1008 u32 mask; 1009 int i; 1010 1011 for (i = 0; i < LNA_GAIN_NUM; i++) { 1012 if (subband == RTW89_CH_2G) 1013 reg = bb_gain_lna[i].gain_g[path]; 1014 else 1015 reg = bb_gain_lna[i].gain_a[path]; 1016 1017 mask = bb_gain_lna[i].gain_mask; 1018 val = gain->lna_gain[gain_band][path][i]; 1019 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 1020 } 1021 1022 for (i = 0; i < TIA_GAIN_NUM; i++) { 1023 if (subband == RTW89_CH_2G) 1024 reg = bb_gain_tia[i].gain_g[path]; 1025 else 1026 reg = bb_gain_tia[i].gain_a[path]; 1027 1028 mask = bb_gain_tia[i].gain_mask; 1029 val = gain->tia_gain[gain_band][path][i]; 1030 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 1031 } 1032 } 1033 1034 static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev, 1035 enum rtw89_subband subband, 1036 enum rtw89_phy_idx phy_idx) 1037 { 1038 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD}; 1039 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1, 1040 R_PATH1_G_TIA1_LNA6_OP1DB_V1}; 1041 struct rtw89_hal *hal = &rtwdev->hal; 1042 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 1043 enum rtw89_gain_offset gain_ofdm_band; 1044 s32 offset_a, offset_b; 1045 s32 offset_ofdm, offset_cck; 1046 s32 tmp; 1047 u8 path; 1048 1049 if (!efuse_gain->comp_valid) 1050 goto next; 1051 1052 for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) { 1053 tmp = efuse_gain->comp[path][subband]; 1054 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); 1055 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); 1056 } 1057 1058 next: 1059 if (!efuse_gain->offset_valid) 1060 return; 1061 1062 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); 1063 1064 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 1065 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 1066 1067 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 1068 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1069 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); 1070 1071 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 1072 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1073 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp); 1074 1075 if (hal->antenna_rx == RF_B) { 1076 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 1077 offset_cck = -efuse_gain->offset[RF_PATH_B][0]; 1078 } else { 1079 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 1080 offset_cck = -efuse_gain->offset[RF_PATH_A][0]; 1081 } 1082 1083 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; 1084 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1085 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 1086 1087 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; 1088 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1089 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 1090 1091 if (subband == RTW89_CH_2G) { 1092 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); 1093 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); 1094 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, 1095 B_RX_RPL_OFST_CCK_MASK, tmp); 1096 } 1097 } 1098 1099 static 1100 void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) 1101 { 1102 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1103 u8 band = rtw89_subband_to_bb_gain_band(subband); 1104 u32 val; 1105 1106 val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] + 1107 gain->rpl_ofst_20[band][RF_PATH_B]) / 2) | 1108 FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] + 1109 gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) | 1110 FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] + 1111 gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2); 1112 val >>= B_P0_RPL1_SHIFT; 1113 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); 1114 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); 1115 1116 val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] + 1117 gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) | 1118 FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] + 1119 gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) | 1120 FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] + 1121 gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) | 1122 FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] + 1123 gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2); 1124 rtw89_phy_write32(rtwdev, R_P0_RPL2, val); 1125 rtw89_phy_write32(rtwdev, R_P1_RPL2, val); 1126 1127 val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] + 1128 gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) | 1129 FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] + 1130 gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) | 1131 FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] + 1132 gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) | 1133 FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] + 1134 gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2); 1135 rtw89_phy_write32(rtwdev, R_P0_RPL3, val); 1136 rtw89_phy_write32(rtwdev, R_P1_RPL3, val); 1137 } 1138 1139 static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev, 1140 const struct rtw89_chan *chan, 1141 enum rtw89_phy_idx phy_idx) 1142 { 1143 u8 central_ch = chan->channel; 1144 u8 subband = chan->subband_type; 1145 u8 sco_comp; 1146 bool is_2g = central_ch <= 14; 1147 1148 /* Path A */ 1149 if (is_2g) 1150 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1151 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); 1152 else 1153 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1154 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); 1155 1156 /* Path B */ 1157 if (is_2g) 1158 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1159 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx); 1160 else 1161 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1162 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx); 1163 1164 /* SCO compensate FC setting */ 1165 sco_comp = rtw8852b_sco_mapping(central_ch); 1166 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); 1167 1168 if (chan->band_type == RTW89_BAND_6G) 1169 return; 1170 1171 /* CCK parameters */ 1172 if (central_ch == 14) { 1173 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); 1174 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); 1175 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); 1176 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); 1177 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); 1178 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 1179 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 1180 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); 1181 } else { 1182 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); 1183 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); 1184 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 1185 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); 1186 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); 1187 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); 1188 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); 1189 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); 1190 } 1191 1192 rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_A); 1193 rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_B); 1194 rtw8852b_set_gain_offset(rtwdev, subband, phy_idx); 1195 rtw8852b_set_rxsc_rpl_comp(rtwdev, subband); 1196 } 1197 1198 static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1199 { 1200 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1201 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1202 1203 switch (bw) { 1204 case RTW89_CHANNEL_WIDTH_5: 1205 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1206 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1207 break; 1208 case RTW89_CHANNEL_WIDTH_10: 1209 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1210 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1211 break; 1212 case RTW89_CHANNEL_WIDTH_20: 1213 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1214 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1215 break; 1216 case RTW89_CHANNEL_WIDTH_40: 1217 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1218 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1219 break; 1220 case RTW89_CHANNEL_WIDTH_80: 1221 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1222 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1223 break; 1224 default: 1225 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1226 } 1227 } 1228 1229 static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1230 enum rtw89_phy_idx phy_idx) 1231 { 1232 u32 rx_path_0; 1233 1234 switch (bw) { 1235 case RTW89_CHANNEL_WIDTH_5: 1236 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1237 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); 1238 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1239 1240 /*Set RF mode at 3 */ 1241 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1242 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1243 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1244 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1245 break; 1246 case RTW89_CHANNEL_WIDTH_10: 1247 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1248 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); 1249 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1250 1251 /*Set RF mode at 3 */ 1252 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1253 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1254 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1255 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1256 break; 1257 case RTW89_CHANNEL_WIDTH_20: 1258 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1259 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1260 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1261 1262 /*Set RF mode at 3 */ 1263 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1264 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1265 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1266 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1267 break; 1268 case RTW89_CHANNEL_WIDTH_40: 1269 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); 1270 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1271 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1272 pri_ch, phy_idx); 1273 1274 /*Set RF mode at 3 */ 1275 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1276 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1277 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1278 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1279 /*CCK primary channel */ 1280 if (pri_ch == RTW89_SC_20_UPPER) 1281 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1282 else 1283 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1284 1285 break; 1286 case RTW89_CHANNEL_WIDTH_80: 1287 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); 1288 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1289 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1290 pri_ch, phy_idx); 1291 1292 /*Set RF mode at A */ 1293 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1294 B_P0_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx); 1295 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1296 B_P1_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx); 1297 break; 1298 default: 1299 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1300 pri_ch); 1301 } 1302 1303 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A); 1304 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B); 1305 1306 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1307 phy_idx); 1308 if (rx_path_0 == 0x1) 1309 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1310 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1311 else if (rx_path_0 == 0x2) 1312 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1313 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1314 } 1315 1316 static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) 1317 { 1318 if (cck_en) { 1319 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1320 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1321 } else { 1322 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1323 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1324 } 1325 } 1326 1327 static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1328 enum rtw89_phy_idx phy_idx) 1329 { 1330 u8 pri_ch = chan->pri_ch_idx; 1331 bool mask_5m_low; 1332 bool mask_5m_en; 1333 1334 switch (chan->band_width) { 1335 case RTW89_CHANNEL_WIDTH_40: 1336 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ 1337 mask_5m_en = true; 1338 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1339 break; 1340 case RTW89_CHANNEL_WIDTH_80: 1341 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ 1342 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1343 pri_ch == RTW89_SC_20_LOWEST; 1344 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1345 break; 1346 default: 1347 mask_5m_en = false; 1348 break; 1349 } 1350 1351 if (!mask_5m_en) { 1352 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); 1353 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0); 1354 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1355 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); 1356 return; 1357 } 1358 1359 if (mask_5m_low) { 1360 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1361 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1362 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); 1363 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); 1364 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1365 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1366 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0); 1367 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1); 1368 } else { 1369 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1370 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1371 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); 1372 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); 1373 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1374 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1375 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1); 1376 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0); 1377 } 1378 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1379 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); 1380 } 1381 1382 static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1383 { 1384 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1385 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1386 fsleep(1); 1387 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1388 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1389 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1390 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1391 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1392 } 1393 1394 static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1395 enum rtw89_phy_idx phy_idx, bool en) 1396 { 1397 if (en) { 1398 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1399 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1400 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1401 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1402 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1403 if (band == RTW89_BAND_2G) 1404 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 1405 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1406 } else { 1407 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 1408 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1409 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1410 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1411 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1412 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1413 fsleep(1); 1414 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1415 } 1416 } 1417 1418 static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev, 1419 enum rtw89_phy_idx phy_idx) 1420 { 1421 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1422 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1423 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1424 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1425 rtw8852b_bb_reset_all(rtwdev, phy_idx); 1426 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1427 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1428 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1429 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1430 } 1431 1432 static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1433 enum rtw89_phy_idx phy_idx) 1434 { 1435 u32 addr; 1436 1437 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1438 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1439 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1440 } 1441 1442 static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev) 1443 { 1444 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1445 1446 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1447 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1448 1449 rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1450 1451 /* read these registers after loading BB parameters */ 1452 gain->offset_base[RTW89_PHY_0] = 1453 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); 1454 gain->rssi_base[RTW89_PHY_0] = 1455 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); 1456 } 1457 1458 static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev) 1459 { 1460 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) 1461 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN); 1462 } 1463 1464 static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1465 enum rtw89_phy_idx phy_idx) 1466 { 1467 bool cck_en = chan->channel <= 14; 1468 u8 pri_ch_idx = chan->pri_ch_idx; 1469 u8 band = chan->band_type, chan_idx; 1470 1471 if (cck_en) 1472 rtw8852b_ctrl_sco_cck(rtwdev, chan->primary_channel); 1473 1474 rtw8852b_ctrl_ch(rtwdev, chan, phy_idx); 1475 rtw8852b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1476 rtw8852b_ctrl_cck_en(rtwdev, cck_en); 1477 if (chan->band_type == RTW89_BAND_5G) { 1478 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1479 B_PATH0_BT_SHARE_V1, 0x0); 1480 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1481 B_PATH0_BTG_PATH_V1, 0x0); 1482 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1483 B_PATH1_BT_SHARE_V1, 0x0); 1484 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1485 B_PATH1_BTG_PATH_V1, 0x0); 1486 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1487 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1488 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1489 B_BT_DYN_DC_EST_EN_MSK, 0x0); 1490 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1491 } 1492 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1493 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); 1494 rtw8852b_5m_mask(rtwdev, chan, phy_idx); 1495 rtw8852b_bb_set_pop(rtwdev); 1496 rtw8852b_bb_reset_all(rtwdev, phy_idx); 1497 } 1498 1499 static void rtw8852b_set_channel(struct rtw89_dev *rtwdev, 1500 const struct rtw89_chan *chan, 1501 enum rtw89_mac_idx mac_idx, 1502 enum rtw89_phy_idx phy_idx) 1503 { 1504 rtw8852b_set_channel_mac(rtwdev, chan, mac_idx); 1505 rtw8852b_set_channel_bb(rtwdev, chan, phy_idx); 1506 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx); 1507 } 1508 1509 static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1510 enum rtw89_rf_path path) 1511 { 1512 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; 1513 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; 1514 1515 if (en) { 1516 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0); 1517 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0); 1518 } else { 1519 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1); 1520 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1); 1521 } 1522 } 1523 1524 static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1525 u8 phy_idx) 1526 { 1527 if (!rtwdev->dbcc_en) { 1528 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 1529 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 1530 } else { 1531 if (phy_idx == RTW89_PHY_0) 1532 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 1533 else 1534 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 1535 } 1536 } 1537 1538 static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en) 1539 { 1540 if (en) 1541 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 1542 else 1543 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 1544 } 1545 1546 static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1547 struct rtw89_channel_help_params *p, 1548 const struct rtw89_chan *chan, 1549 enum rtw89_mac_idx mac_idx, 1550 enum rtw89_phy_idx phy_idx) 1551 { 1552 if (enter) { 1553 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1554 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1555 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1556 rtw8852b_adc_en(rtwdev, false); 1557 fsleep(40); 1558 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1559 } else { 1560 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1561 rtw8852b_adc_en(rtwdev, true); 1562 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1563 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1564 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1565 } 1566 } 1567 1568 static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev) 1569 { 1570 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1571 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1572 1573 rtw8852b_dpk_init(rtwdev); 1574 rtw8852b_rck(rtwdev); 1575 rtw8852b_dack(rtwdev); 1576 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0); 1577 } 1578 1579 static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev) 1580 { 1581 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1582 1583 rtw8852b_rx_dck(rtwdev, phy_idx); 1584 rtw8852b_iqk(rtwdev, phy_idx); 1585 rtw8852b_tssi(rtwdev, phy_idx, true); 1586 rtw8852b_dpk(rtwdev, phy_idx); 1587 } 1588 1589 static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev, 1590 enum rtw89_phy_idx phy_idx) 1591 { 1592 rtw8852b_tssi_scan(rtwdev, phy_idx); 1593 } 1594 1595 static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1596 { 1597 rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1598 } 1599 1600 static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev) 1601 { 1602 rtw8852b_dpk_track(rtwdev); 1603 } 1604 1605 static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1606 enum rtw89_phy_idx phy_idx, s16 ref) 1607 { 1608 const u16 tssi_16dbm_cw = 0x12c; 1609 const u8 base_cw_0db = 0x27; 1610 const s8 ofst_int = 0; 1611 s16 pwr_s10_3; 1612 s16 rf_pwr_cw; 1613 u16 bb_pwr_cw; 1614 u32 pwr_cw; 1615 u32 tssi_ofst_cw; 1616 1617 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1618 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1619 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1620 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1621 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1622 1623 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1624 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1625 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1626 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1627 1628 return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) | 1629 FIELD_PREP(B_DPD_PWR_CW, pwr_cw) | 1630 FIELD_PREP(B_DPD_REF, ref); 1631 } 1632 1633 static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev, 1634 enum rtw89_phy_idx phy_idx) 1635 { 1636 static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800}; 1637 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; 1638 const u8 ofst_ofdm = 0x4; 1639 const u8 ofst_cck = 0x8; 1640 const s16 ref_ofdm = 0; 1641 const s16 ref_cck = 0; 1642 u32 val; 1643 u8 i; 1644 1645 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1646 1647 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1648 B_AX_PWR_REF, 0x0); 1649 1650 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1651 val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1652 1653 for (i = 0; i < RF_PATH_NUM_8852B; i++) 1654 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1655 phy_idx); 1656 1657 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1658 val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1659 1660 for (i = 0; i < RF_PATH_NUM_8852B; i++) 1661 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1662 phy_idx); 1663 } 1664 1665 static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1666 const struct rtw89_chan *chan, 1667 u8 tx_shape_idx, 1668 enum rtw89_phy_idx phy_idx) 1669 { 1670 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) 1671 #define __DFIR_CFG_MASK 0xffffffff 1672 #define __DFIR_CFG_NR 8 1673 #define __DECL_DFIR_PARAM(_name, _val...) \ 1674 static const u32 param_ ## _name[] = {_val}; \ 1675 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) 1676 1677 __DECL_DFIR_PARAM(flat, 1678 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1679 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1680 __DECL_DFIR_PARAM(sharp, 1681 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1682 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); 1683 __DECL_DFIR_PARAM(sharp_14, 1684 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1685 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); 1686 u8 ch = chan->channel; 1687 const u32 *param; 1688 u32 addr; 1689 int i; 1690 1691 if (ch > 14) { 1692 rtw89_warn(rtwdev, 1693 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1694 return; 1695 } 1696 1697 if (ch == 14) 1698 param = param_sharp_14; 1699 else 1700 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1701 1702 for (i = 0; i < __DFIR_CFG_NR; i++) { 1703 addr = __DFIR_CFG_ADDR(i); 1704 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1705 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); 1706 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], 1707 phy_idx); 1708 } 1709 1710 #undef __DECL_DFIR_PARAM 1711 #undef __DFIR_CFG_NR 1712 #undef __DFIR_CFG_MASK 1713 #undef __DECL_CFG_ADDR 1714 } 1715 1716 static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev, 1717 const struct rtw89_chan *chan, 1718 enum rtw89_phy_idx phy_idx) 1719 { 1720 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1721 u8 band = chan->band_type; 1722 u8 regd = rtw89_regd_get(rtwdev, band); 1723 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 1724 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 1725 1726 if (band == RTW89_BAND_2G) 1727 rtw8852b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1728 1729 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, 1730 tx_shape_ofdm); 1731 } 1732 1733 static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev, 1734 const struct rtw89_chan *chan, 1735 enum rtw89_phy_idx phy_idx) 1736 { 1737 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1738 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1739 rtw8852b_set_tx_shape(rtwdev, chan, phy_idx); 1740 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1741 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1742 } 1743 1744 static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1745 enum rtw89_phy_idx phy_idx) 1746 { 1747 rtw8852b_set_txpwr_ref(rtwdev, phy_idx); 1748 } 1749 1750 static 1751 void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1752 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1753 { 1754 u32 reg; 1755 1756 if (pw_ofst < -16 || pw_ofst > 15) { 1757 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1758 return; 1759 } 1760 1761 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1762 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1763 1764 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1765 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); 1766 1767 pw_ofst = max_t(s8, pw_ofst - 3, -16); 1768 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1769 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); 1770 } 1771 1772 static int 1773 rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1774 { 1775 int ret; 1776 1777 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1778 if (ret) 1779 return ret; 1780 1781 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 1782 if (ret) 1783 return ret; 1784 1785 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1786 if (ret) 1787 return ret; 1788 1789 rtw8852b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 1790 RTW89_MAC_1 : RTW89_MAC_0); 1791 1792 return 0; 1793 } 1794 1795 void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1796 { 1797 const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl; 1798 u8 i; 1799 1800 for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++) 1801 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 1802 } 1803 1804 static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev, 1805 struct rtw8852b_bb_pmac_info *tx_info, 1806 enum rtw89_phy_idx idx) 1807 { 1808 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1809 if (tx_info->mode == CONT_TX) 1810 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx); 1811 else if (tx_info->mode == PKTS_TX) 1812 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx); 1813 } 1814 1815 static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev, 1816 struct rtw8852b_bb_pmac_info *tx_info, 1817 enum rtw89_phy_idx idx) 1818 { 1819 enum rtw8852b_pmac_mode mode = tx_info->mode; 1820 u32 pkt_cnt = tx_info->tx_cnt; 1821 u16 period = tx_info->period; 1822 1823 if (mode == CONT_TX && !tx_info->is_cck) { 1824 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx); 1825 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1826 } else if (mode == PKTS_TX) { 1827 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx); 1828 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1829 B_PMAC_TX_PRD_MSK, period, idx); 1830 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1831 pkt_cnt, idx); 1832 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1833 } 1834 1835 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1836 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1837 } 1838 1839 void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1840 struct rtw8852b_bb_pmac_info *tx_info, 1841 enum rtw89_phy_idx idx) 1842 { 1843 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1844 1845 if (!tx_info->en_pmac_tx) { 1846 rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx); 1847 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1848 if (chan->band_type == RTW89_BAND_2G) 1849 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1850 return; 1851 } 1852 1853 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1854 1855 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1856 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1857 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx); 1858 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1859 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1860 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1861 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1862 1863 rtw8852b_start_pmac_tx(rtwdev, tx_info, idx); 1864 } 1865 1866 void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1867 u16 tx_cnt, u16 period, u16 tx_time, 1868 enum rtw89_phy_idx idx) 1869 { 1870 struct rtw8852b_bb_pmac_info tx_info = {0}; 1871 1872 tx_info.en_pmac_tx = enable; 1873 tx_info.is_cck = 0; 1874 tx_info.mode = PKTS_TX; 1875 tx_info.tx_cnt = tx_cnt; 1876 tx_info.period = period; 1877 tx_info.tx_time = tx_time; 1878 1879 rtw8852b_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1880 } 1881 1882 void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1883 enum rtw89_phy_idx idx) 1884 { 1885 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1886 1887 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1888 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1889 } 1890 1891 void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1892 { 1893 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1894 1895 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1896 1897 if (tx_path == RF_PATH_A) { 1898 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1); 1899 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1900 } else if (tx_path == RF_PATH_B) { 1901 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2); 1902 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1903 } else if (tx_path == RF_PATH_AB) { 1904 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3); 1905 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4); 1906 } else { 1907 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1908 } 1909 } 1910 1911 void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1912 enum rtw89_phy_idx idx, u8 mode) 1913 { 1914 if (mode != 0) 1915 return; 1916 1917 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1918 1919 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1920 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1921 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1922 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1923 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1924 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1925 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1926 } 1927 1928 void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1929 struct rtw8852b_bb_tssi_bak *bak) 1930 { 1931 s32 tmp; 1932 1933 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx); 1934 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx); 1935 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx); 1936 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx); 1937 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx); 1938 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx); 1939 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx); 1940 bak->tx_pwr = sign_extend32(tmp, 8); 1941 } 1942 1943 void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1944 const struct rtw8852b_bb_tssi_bak *bak) 1945 { 1946 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx); 1947 if (bak->tx_path == RF_AB) 1948 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4); 1949 else 1950 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0); 1951 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx); 1952 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1953 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx); 1954 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx); 1955 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx); 1956 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx); 1957 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx); 1958 } 1959 1960 static void rtw8852b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1961 enum rtw89_phy_idx phy_idx) 1962 { 1963 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852b_btc_preagc_en_defs_tbl : 1964 &rtw8852b_btc_preagc_dis_defs_tbl); 1965 } 1966 1967 static void rtw8852b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1968 enum rtw89_phy_idx phy_idx) 1969 { 1970 if (en) { 1971 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1972 B_PATH0_BT_SHARE_V1, 0x1); 1973 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1974 B_PATH0_BTG_PATH_V1, 0x0); 1975 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1976 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 1977 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1978 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 1979 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1980 B_PATH1_BT_SHARE_V1, 0x1); 1981 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1982 B_PATH1_BTG_PATH_V1, 0x1); 1983 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1984 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); 1985 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2); 1986 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1987 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1988 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); 1989 } else { 1990 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1991 B_PATH0_BT_SHARE_V1, 0x0); 1992 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1993 B_PATH0_BTG_PATH_V1, 0x0); 1994 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1995 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 1996 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1997 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1998 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1999 B_PATH1_BT_SHARE_V1, 0x0); 2000 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2001 B_PATH1_BTG_PATH_V1, 0x0); 2002 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); 2003 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 2004 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 2005 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 2006 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2007 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 2008 } 2009 } 2010 2011 void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 2012 enum rtw89_rf_path_bit rx_path) 2013 { 2014 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2015 u32 rst_mask0; 2016 u32 rst_mask1; 2017 2018 if (rx_path == RF_A) { 2019 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); 2020 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); 2021 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); 2022 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2023 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2024 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 2025 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2026 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2027 } else if (rx_path == RF_B) { 2028 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2); 2029 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2); 2030 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2); 2031 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2032 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2033 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 2034 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2035 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2036 } else if (rx_path == RF_AB) { 2037 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3); 2038 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3); 2039 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3); 2040 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2041 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2042 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 2043 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2044 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2045 } 2046 2047 rtw8852b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); 2048 2049 if (chan->band_type == RTW89_BAND_2G && 2050 (rx_path == RF_B || rx_path == RF_AB)) 2051 rtw8852b_ctrl_btg_bt_rx(rtwdev, true, RTW89_PHY_0); 2052 else 2053 rtw8852b_ctrl_btg_bt_rx(rtwdev, false, RTW89_PHY_0); 2054 2055 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2056 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2057 if (rx_path == RF_A) { 2058 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2059 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2060 } else { 2061 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2062 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2063 } 2064 } 2065 2066 static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev, 2067 enum rtw89_rf_path_bit rx_path) 2068 { 2069 if (rx_path == RF_A) { 2070 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 2071 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2072 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 2073 B_P0_RFMODE_FTM_RX, 0x333); 2074 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 2075 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 2076 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 2077 B_P1_RFMODE_FTM_RX, 0x111); 2078 } else if (rx_path == RF_B) { 2079 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 2080 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 2081 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 2082 B_P0_RFMODE_FTM_RX, 0x111); 2083 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 2084 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2085 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 2086 B_P1_RFMODE_FTM_RX, 0x333); 2087 } else if (rx_path == RF_AB) { 2088 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 2089 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2090 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 2091 B_P0_RFMODE_FTM_RX, 0x333); 2092 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 2093 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2094 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 2095 B_P1_RFMODE_FTM_RX, 0x333); 2096 } 2097 } 2098 2099 static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2100 { 2101 struct rtw89_hal *hal = &rtwdev->hal; 2102 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB; 2103 2104 rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path); 2105 rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path); 2106 2107 if (rtwdev->hal.rx_nss == 1) { 2108 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2109 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2110 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2111 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2112 } else { 2113 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2114 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2115 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2116 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2117 } 2118 2119 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 2120 } 2121 2122 static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2123 { 2124 if (rtwdev->is_tssi_mode[rf_path]) { 2125 u32 addr = 0x1c10 + (rf_path << 13); 2126 2127 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 2128 } 2129 2130 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2131 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2132 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2133 2134 fsleep(200); 2135 2136 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2137 } 2138 2139 static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) 2140 { 2141 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2142 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 2143 2144 if (ver->fcxinit == 7) { 2145 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 2146 md->md_v7.kt_ver = rtwdev->hal.cv; 2147 md->md_v7.bt_solo = 0; 2148 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 2149 2150 if (md->md_v7.rfe_type > 0) 2151 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 2152 else 2153 md->md_v7.ant.num = 2; 2154 2155 md->md_v7.ant.diversity = 0; 2156 md->md_v7.ant.isolation = 10; 2157 2158 if (md->md_v7.ant.num == 3) { 2159 md->md_v7.ant.type = BTC_ANT_DEDICATED; 2160 md->md_v7.bt_pos = BTC_BT_ALONE; 2161 } else { 2162 md->md_v7.ant.type = BTC_ANT_SHARED; 2163 md->md_v7.bt_pos = BTC_BT_BTG; 2164 } 2165 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 2166 rtwdev->btc.ant_type = md->md_v7.ant.type; 2167 } else { 2168 md->md.rfe_type = rtwdev->efuse.rfe_type; 2169 md->md.cv = rtwdev->hal.cv; 2170 md->md.bt_solo = 0; 2171 md->md.switch_type = BTC_SWITCH_INTERNAL; 2172 2173 if (md->md.rfe_type > 0) 2174 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 2175 else 2176 md->md.ant.num = 2; 2177 2178 md->md.ant.diversity = 0; 2179 md->md.ant.isolation = 10; 2180 2181 if (md->md.ant.num == 3) { 2182 md->md.ant.type = BTC_ANT_DEDICATED; 2183 md->md.bt_pos = BTC_BT_ALONE; 2184 } else { 2185 md->md.ant.type = BTC_ANT_SHARED; 2186 md->md.bt_pos = BTC_BT_BTG; 2187 } 2188 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2189 rtwdev->btc.ant_type = md->md.ant.type; 2190 } 2191 } 2192 2193 static 2194 void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2195 { 2196 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2197 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2198 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2199 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2200 } 2201 2202 static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev) 2203 { 2204 struct rtw89_btc *btc = &rtwdev->btc; 2205 const struct rtw89_chip_info *chip = rtwdev->chip; 2206 const struct rtw89_mac_ax_coex coex_params = { 2207 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2208 .direction = RTW89_MAC_AX_COEX_INNER, 2209 }; 2210 2211 /* PTA init */ 2212 rtw89_mac_coex_init(rtwdev, &coex_params); 2213 2214 /* set WL Tx response = Hi-Pri */ 2215 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2216 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2217 2218 /* set rf gnt debug off */ 2219 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2220 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2221 2222 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2223 if (btc->ant_type == BTC_ANT_SHARED) { 2224 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2225 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2226 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2227 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2228 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f); 2229 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2230 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2231 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2232 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2233 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff); 2234 } 2235 2236 /* set PTA break table */ 2237 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 2238 2239 /* enable BT counter 0xda40[16,2] = 2b'11 */ 2240 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 2241 btc->cx.wl.status.map.init_ok = true; 2242 } 2243 2244 static 2245 void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2246 { 2247 u32 bitmap; 2248 u32 reg; 2249 2250 switch (map) { 2251 case BTC_PRI_MASK_TX_RESP: 2252 reg = R_BTC_BT_COEX_MSK_TABLE; 2253 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 2254 break; 2255 case BTC_PRI_MASK_BEACON: 2256 reg = R_AX_WL_PRI_MSK; 2257 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 2258 break; 2259 case BTC_PRI_MASK_RX_CCK: 2260 reg = R_BTC_BT_COEX_MSK_TABLE; 2261 bitmap = B_BTC_PRI_MASK_RXCCK_V1; 2262 break; 2263 default: 2264 return; 2265 } 2266 2267 if (state) 2268 rtw89_write32_set(rtwdev, reg, bitmap); 2269 else 2270 rtw89_write32_clr(rtwdev, reg, bitmap); 2271 } 2272 2273 union rtw8852b_btc_wl_txpwr_ctrl { 2274 u32 txpwr_val; 2275 struct { 2276 union { 2277 u16 ctrl_all_time; 2278 struct { 2279 s16 data:9; 2280 u16 rsvd:6; 2281 u16 flag:1; 2282 } all_time; 2283 }; 2284 union { 2285 u16 ctrl_gnt_bt; 2286 struct { 2287 s16 data:9; 2288 u16 rsvd:7; 2289 } gnt_bt; 2290 }; 2291 }; 2292 } __packed; 2293 2294 static void 2295 rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2296 { 2297 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2298 s32 val; 2299 2300 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2301 do { \ 2302 u32 _wrt = FIELD_PREP(_msk, _val); \ 2303 BUILD_BUG_ON(!!(_msk & _en)); \ 2304 if (_cond) \ 2305 _wrt |= _en; \ 2306 else \ 2307 _wrt &= ~_en; \ 2308 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2309 _msk | _en, _wrt); \ 2310 } while (0) 2311 2312 switch (arg.ctrl_all_time) { 2313 case 0xffff: 2314 val = 0; 2315 break; 2316 default: 2317 val = arg.all_time.data; 2318 break; 2319 } 2320 2321 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2322 val, B_AX_FORCE_PWR_BY_RATE_EN, 2323 arg.ctrl_all_time != 0xffff); 2324 2325 switch (arg.ctrl_gnt_bt) { 2326 case 0xffff: 2327 val = 0; 2328 break; 2329 default: 2330 val = arg.gnt_bt.data; 2331 break; 2332 } 2333 2334 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2335 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2336 2337 #undef __write_ctrl 2338 } 2339 2340 static 2341 s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2342 { 2343 /* +6 for compensate offset */ 2344 return clamp_t(s8, val + 6, -100, 0) + 100; 2345 } 2346 2347 static 2348 void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2349 { 2350 /* Feature move to firmware */ 2351 } 2352 2353 static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2354 { 2355 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2356 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2357 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31); 2358 2359 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2360 if (state) 2361 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179); 2362 else 2363 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20); 2364 2365 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2366 } 2367 2368 static void rtw8852b_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2369 { 2370 switch (level) { 2371 case 0: /* default */ 2372 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2373 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2374 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2375 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2376 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2377 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2378 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2379 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2380 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2381 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2382 break; 2383 case 1: /* Fix LNA2=5 */ 2384 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2385 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2386 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2387 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2388 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2389 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2390 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2391 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2392 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2393 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2394 break; 2395 } 2396 } 2397 2398 static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2399 { 2400 struct rtw89_btc *btc = &rtwdev->btc; 2401 2402 switch (level) { 2403 case 0: /* original */ 2404 default: 2405 rtw8852b_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2406 btc->dm.wl_lna2 = 0; 2407 break; 2408 case 1: /* for FDD free-run */ 2409 rtw8852b_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2410 btc->dm.wl_lna2 = 0; 2411 break; 2412 case 2: /* for BTG Co-Rx*/ 2413 rtw8852b_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2414 btc->dm.wl_lna2 = 1; 2415 break; 2416 } 2417 2418 rtw8852b_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2419 } 2420 2421 static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2422 struct rtw89_rx_phy_ppdu *phy_ppdu, 2423 struct ieee80211_rx_status *status) 2424 { 2425 u16 chan = phy_ppdu->chan_idx; 2426 enum nl80211_band band; 2427 u8 ch; 2428 2429 if (chan == 0) 2430 return; 2431 2432 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); 2433 status->freq = ieee80211_channel_to_frequency(ch, band); 2434 status->band = band; 2435 } 2436 2437 static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev, 2438 struct rtw89_rx_phy_ppdu *phy_ppdu, 2439 struct ieee80211_rx_status *status) 2440 { 2441 u8 path; 2442 u8 *rx_power = phy_ppdu->rssi; 2443 2444 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2445 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2446 status->chains |= BIT(path); 2447 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2448 } 2449 if (phy_ppdu->valid) 2450 rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2451 } 2452 2453 static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2454 { 2455 int ret; 2456 2457 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2458 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2459 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); 2460 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2461 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2462 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2463 2464 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, 2465 FULL_BIT_MASK); 2466 if (ret) 2467 return ret; 2468 2469 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, 2470 FULL_BIT_MASK); 2471 if (ret) 2472 return ret; 2473 2474 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); 2475 2476 return 0; 2477 } 2478 2479 static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2480 { 2481 u8 wl_rfc_s0; 2482 u8 wl_rfc_s1; 2483 int ret; 2484 2485 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2486 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2487 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2488 2489 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); 2490 if (ret) 2491 return ret; 2492 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; 2493 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, 2494 FULL_BIT_MASK); 2495 if (ret) 2496 return ret; 2497 2498 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); 2499 if (ret) 2500 return ret; 2501 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; 2502 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, 2503 FULL_BIT_MASK); 2504 return ret; 2505 } 2506 2507 static const struct rtw89_chip_ops rtw8852b_chip_ops = { 2508 .enable_bb_rf = rtw8852b_mac_enable_bb_rf, 2509 .disable_bb_rf = rtw8852b_mac_disable_bb_rf, 2510 .bb_preinit = NULL, 2511 .bb_postinit = NULL, 2512 .bb_reset = rtw8852b_bb_reset, 2513 .bb_sethw = rtw8852b_bb_sethw, 2514 .read_rf = rtw89_phy_read_rf_v1, 2515 .write_rf = rtw89_phy_write_rf_v1, 2516 .set_channel = rtw8852b_set_channel, 2517 .set_channel_help = rtw8852b_set_channel_help, 2518 .read_efuse = rtw8852b_read_efuse, 2519 .read_phycap = rtw8852b_read_phycap, 2520 .fem_setup = NULL, 2521 .rfe_gpio = NULL, 2522 .rfk_hw_init = NULL, 2523 .rfk_init = rtw8852b_rfk_init, 2524 .rfk_init_late = NULL, 2525 .rfk_channel = rtw8852b_rfk_channel, 2526 .rfk_band_changed = rtw8852b_rfk_band_changed, 2527 .rfk_scan = rtw8852b_rfk_scan, 2528 .rfk_track = rtw8852b_rfk_track, 2529 .power_trim = rtw8852b_power_trim, 2530 .set_txpwr = rtw8852b_set_txpwr, 2531 .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl, 2532 .init_txpwr_unit = rtw8852b_init_txpwr_unit, 2533 .get_thermal = rtw8852b_get_thermal, 2534 .ctrl_btg_bt_rx = rtw8852b_ctrl_btg_bt_rx, 2535 .query_ppdu = rtw8852b_query_ppdu, 2536 .ctrl_nbtg_bt_tx = rtw8852b_ctrl_nbtg_bt_tx, 2537 .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path, 2538 .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset, 2539 .pwr_on_func = rtw8852b_pwr_on_func, 2540 .pwr_off_func = rtw8852b_pwr_off_func, 2541 .query_rxdesc = rtw89_core_query_rxdesc, 2542 .fill_txdesc = rtw89_core_fill_txdesc, 2543 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2544 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2545 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2546 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2547 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2548 .h2c_dctl_sec_cam = NULL, 2549 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2550 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2551 .h2c_ampdu_cmac_tbl = NULL, 2552 .h2c_default_dmac_tbl = NULL, 2553 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2554 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2555 2556 .btc_set_rfe = rtw8852b_btc_set_rfe, 2557 .btc_init_cfg = rtw8852b_btc_init_cfg, 2558 .btc_set_wl_pri = rtw8852b_btc_set_wl_pri, 2559 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl, 2560 .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi, 2561 .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt, 2562 .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby, 2563 .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain, 2564 .btc_set_policy = rtw89_btc_set_policy_v1, 2565 }; 2566 2567 #ifdef CONFIG_PM 2568 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = { 2569 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2570 .n_patterns = RTW89_MAX_PATTERN_NUM, 2571 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2572 .pattern_min_len = 1, 2573 }; 2574 #endif 2575 2576 const struct rtw89_chip_info rtw8852b_chip_info = { 2577 .chip_id = RTL8852B, 2578 .chip_gen = RTW89_CHIP_AX, 2579 .ops = &rtw8852b_chip_ops, 2580 .mac_def = &rtw89_mac_gen_ax, 2581 .phy_def = &rtw89_phy_gen_ax, 2582 .fw_basename = RTW8852B_FW_BASENAME, 2583 .fw_format_max = RTW8852B_FW_FORMAT_MAX, 2584 .try_ce_fw = true, 2585 .bbmcu_nr = 0, 2586 .needed_fw_elms = 0, 2587 .fifo_size = 196608, 2588 .small_fifo_size = true, 2589 .dle_scc_rsvd_size = 98304, 2590 .max_amsdu_limit = 3500, 2591 .dis_2g_40m_ul_ofdma = true, 2592 .rsvd_ple_ofst = 0x2f800, 2593 .hfc_param_ini = rtw8852b_hfc_param_ini_pcie, 2594 .dle_mem = rtw8852b_dle_mem_pcie, 2595 .wde_qempty_acq_grpnum = 4, 2596 .wde_qempty_mgq_grpsel = 4, 2597 .rf_base_addr = {0xe000, 0xf000}, 2598 .pwr_on_seq = NULL, 2599 .pwr_off_seq = NULL, 2600 .bb_table = &rtw89_8852b_phy_bb_table, 2601 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table, 2602 .rf_table = {&rtw89_8852b_phy_radioa_table, 2603 &rtw89_8852b_phy_radiob_table,}, 2604 .nctl_table = &rtw89_8852b_phy_nctl_table, 2605 .nctl_post_table = NULL, 2606 .dflt_parms = &rtw89_8852b_dflt_parms, 2607 .rfe_parms_conf = NULL, 2608 .txpwr_factor_rf = 2, 2609 .txpwr_factor_mac = 1, 2610 .dig_table = NULL, 2611 .dig_regs = &rtw8852b_dig_regs, 2612 .tssi_dbw_table = NULL, 2613 .support_chanctx_num = 0, 2614 .support_rnr = false, 2615 .support_bands = BIT(NL80211_BAND_2GHZ) | 2616 BIT(NL80211_BAND_5GHZ), 2617 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2618 BIT(NL80211_CHAN_WIDTH_40) | 2619 BIT(NL80211_CHAN_WIDTH_80), 2620 .support_unii4 = true, 2621 .ul_tb_waveform_ctrl = true, 2622 .ul_tb_pwr_diff = false, 2623 .hw_sec_hdr = false, 2624 .rf_path_num = 2, 2625 .tx_nss = 2, 2626 .rx_nss = 2, 2627 .acam_num = 128, 2628 .bcam_num = 10, 2629 .scam_num = 128, 2630 .bacam_num = 2, 2631 .bacam_dynamic_num = 4, 2632 .bacam_ver = RTW89_BACAM_V0, 2633 .ppdu_max_usr = 4, 2634 .sec_ctrl_efuse_size = 4, 2635 .physical_efuse_size = 1216, 2636 .logical_efuse_size = 2048, 2637 .limit_efuse_size = 1280, 2638 .dav_phy_efuse_size = 96, 2639 .dav_log_efuse_size = 16, 2640 .efuse_blocks = NULL, 2641 .phycap_addr = 0x580, 2642 .phycap_size = 128, 2643 .para_ver = 0, 2644 .wlcx_desired = 0x05050000, 2645 .btcx_desired = 0x5, 2646 .scbd = 0x1, 2647 .mailbox = 0x1, 2648 2649 .afh_guard_ch = 6, 2650 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres, 2651 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres, 2652 .rssi_tol = 2, 2653 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg), 2654 .mon_reg = rtw89_btc_8852b_mon_reg, 2655 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul), 2656 .rf_para_ulink = rtw89_btc_8852b_rf_ul, 2657 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl), 2658 .rf_para_dlink = rtw89_btc_8852b_rf_dl, 2659 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2660 BIT(RTW89_PS_MODE_CLK_GATED) | 2661 BIT(RTW89_PS_MODE_PWR_GATED), 2662 .low_power_hci_modes = 0, 2663 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2664 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2665 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2666 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2667 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2668 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2669 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2670 .h2c_regs = rtw8852b_h2c_regs, 2671 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2672 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2673 .c2h_regs = rtw8852b_c2h_regs, 2674 .page_regs = &rtw8852b_page_regs, 2675 .wow_reason_reg = R_AX_C2HREG_DATA3 + 3, 2676 .cfo_src_fd = true, 2677 .cfo_hw_comp = true, 2678 .dcfo_comp = &rtw8852b_dcfo_comp, 2679 .dcfo_comp_sft = 10, 2680 .imr_info = &rtw8852b_imr_info, 2681 .imr_dmac_table = NULL, 2682 .imr_cmac_table = NULL, 2683 .rrsr_cfgs = &rtw8852b_rrsr_cfgs, 2684 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 2685 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 2686 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 2687 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 2688 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 2689 .edcca_regs = &rtw8852b_edcca_regs, 2690 #ifdef CONFIG_PM 2691 .wowlan_stub = &rtw_wowlan_stub_8852b, 2692 #endif 2693 .xtal_info = NULL, 2694 }; 2695 EXPORT_SYMBOL(rtw8852b_chip_info); 2696 2697 MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE); 2698 MODULE_AUTHOR("Realtek Corporation"); 2699 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver"); 2700 MODULE_LICENSE("Dual BSD/GPL"); 2701