1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852b.h" 11 #include "rtw8852b_common.h" 12 #include "rtw8852b_rfk.h" 13 #include "rtw8852b_table.h" 14 #include "txrx.h" 15 16 #define RTW8852B_FW_FORMAT_MAX 1 17 #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw" 18 #define RTW8852B_MODULE_FIRMWARE \ 19 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" 20 21 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { 22 {5, 341, grp_0}, /* ACH 0 */ 23 {5, 341, grp_0}, /* ACH 1 */ 24 {4, 342, grp_0}, /* ACH 2 */ 25 {4, 342, grp_0}, /* ACH 3 */ 26 {0, 0, grp_0}, /* ACH 4 */ 27 {0, 0, grp_0}, /* ACH 5 */ 28 {0, 0, grp_0}, /* ACH 6 */ 29 {0, 0, grp_0}, /* ACH 7 */ 30 {4, 342, grp_0}, /* B0MGQ */ 31 {4, 342, grp_0}, /* B0HIQ */ 32 {0, 0, grp_0}, /* B1MGQ */ 33 {0, 0, grp_0}, /* B1HIQ */ 34 {40, 0, 0} /* FWCMDQ */ 35 }; 36 37 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { 38 446, /* Group 0 */ 39 0, /* Group 1 */ 40 446, /* Public Max */ 41 0 /* WP threshold */ 42 }; 43 44 static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = { 45 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie, 46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 48 RTW89_HCIFC_POH}, 49 [RTW89_QTA_INVALID] = {NULL}, 50 }; 51 52 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_usb[] = { 53 {18, 152, grp_0}, /* ACH 0 */ 54 {18, 152, grp_0}, /* ACH 1 */ 55 {18, 152, grp_0}, /* ACH 2 */ 56 {18, 152, grp_0}, /* ACH 3 */ 57 {0, 0, grp_0}, /* ACH 4 */ 58 {0, 0, grp_0}, /* ACH 5 */ 59 {0, 0, grp_0}, /* ACH 6 */ 60 {0, 0, grp_0}, /* ACH 7 */ 61 {18, 152, grp_0}, /* B0MGQ */ 62 {18, 152, grp_0}, /* B0HIQ */ 63 {0, 0, grp_0}, /* B1MGQ */ 64 {0, 0, grp_0}, /* B1HIQ */ 65 {0, 0, 0} /* FWCMDQ */ 66 }; 67 68 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_usb = { 69 152, /* Group 0 */ 70 0, /* Group 1 */ 71 152, /* Public Max */ 72 0 /* WP threshold */ 73 }; 74 75 static const struct rtw89_hfc_prec_cfg rtw8852b_hfc_preccfg_usb = { 76 9, /* CH 0-11 pre-cost */ 77 32, /* H2C pre-cost */ 78 64, /* WP CH 0-7 pre-cost */ 79 24, /* WP CH 8-11 pre-cost */ 80 1, /* CH 0-11 full condition */ 81 1, /* H2C full condition */ 82 1, /* WP CH 0-7 full condition */ 83 1, /* WP CH 8-11 full condition */ 84 }; 85 86 static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_usb[] = { 87 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_usb, &rtw8852b_hfc_pubcfg_usb, 88 &rtw8852b_hfc_preccfg_usb, RTW89_HCIFC_STF}, 89 [RTW89_QTA_DLFW] = {NULL, NULL, 90 &rtw8852b_hfc_preccfg_usb, RTW89_HCIFC_STF}, 91 [RTW89_QTA_INVALID] = {NULL}, 92 }; 93 94 static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { 95 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7, 96 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 97 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 98 &rtw89_mac_size.ple_qt58}, 99 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7, 100 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 101 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 102 &rtw89_mac_size.ple_qt_52b_wow}, 103 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 104 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 105 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 106 &rtw89_mac_size.ple_qt13}, 107 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 108 NULL}, 109 }; 110 111 static const struct rtw89_dle_mem rtw8852b_dle_mem_usb3[] = { 112 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25, 113 &rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25, 114 &rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74, 115 &rtw89_mac_size.ple_qt75}, 116 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 117 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 118 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 119 &rtw89_mac_size.ple_qt13}, 120 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 121 NULL}, 122 }; 123 124 static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = { 125 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 126 R_AX_H2CREG_DATA3 127 }; 128 129 static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = { 130 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 131 R_AX_C2HREG_DATA3 132 }; 133 134 static const u32 rtw8852b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 135 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 136 }; 137 138 static const struct rtw89_page_regs rtw8852b_page_regs = { 139 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 140 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 141 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 142 .ach_page_info = R_AX_ACH0_PAGE_INFO, 143 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 144 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 145 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 146 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 147 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 148 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 149 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 150 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 151 }; 152 153 static const struct rtw89_reg_def rtw8852b_dcfo_comp = { 154 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 155 }; 156 157 static const struct rtw89_imr_info rtw8852b_imr_info = { 158 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 159 .wsec_imr_reg = R_AX_SEC_DEBUG, 160 .wsec_imr_set = B_AX_IMR_ERROR, 161 .mpdu_tx_imr_set = 0, 162 .mpdu_rx_imr_set = 0, 163 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 164 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 165 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 166 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 167 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 168 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 169 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 170 .wde_imr_clr = B_AX_WDE_IMR_CLR, 171 .wde_imr_set = B_AX_WDE_IMR_SET, 172 .ple_imr_clr = B_AX_PLE_IMR_CLR, 173 .ple_imr_set = B_AX_PLE_IMR_SET, 174 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 175 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 176 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 177 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 178 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 179 .other_disp_imr_set = 0, 180 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 181 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 182 .bbrpt_err_imr_set = 0, 183 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 184 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 185 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 186 .cdma_imr_0_reg = R_AX_DLE_CTRL, 187 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 188 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 189 .cdma_imr_1_reg = 0, 190 .cdma_imr_1_clr = 0, 191 .cdma_imr_1_set = 0, 192 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 193 .phy_intf_imr_clr = 0, 194 .phy_intf_imr_set = 0, 195 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 196 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 197 .rmac_imr_set = B_AX_RMAC_IMR_SET, 198 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 199 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 200 .tmac_imr_set = B_AX_TMAC_IMR_SET, 201 }; 202 203 static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = { 204 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 205 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 206 }; 207 208 static const struct rtw89_rfkill_regs rtw8852b_rfkill_regs = { 209 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 210 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 211 0xf}, 212 .mode = {R_AX_GPIO_EXT_CTRL + 2, 213 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 214 0x0}, 215 }; 216 217 static const struct rtw89_dig_regs rtw8852b_dig_regs = { 218 .seg0_pd_reg = R_SEG0R_PD_V1, 219 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 220 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 221 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 222 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 223 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 224 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 225 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 226 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 227 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 228 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 229 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 230 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 231 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 232 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 233 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 234 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 235 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 236 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 237 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 238 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 239 }; 240 241 static const struct rtw89_edcca_regs rtw8852b_edcca_regs = { 242 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 243 .edcca_mask = B_EDCCA_LVL_MSK0, 244 .edcca_p_mask = B_EDCCA_LVL_MSK1, 245 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 246 .ppdu_mask = B_EDCCA_LVL_MSK3, 247 .p = {{ 248 .rpt_a = R_EDCCA_RPT_A, 249 .rpt_b = R_EDCCA_RPT_B, 250 .rpt_sel = R_EDCCA_RPT_SEL, 251 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 252 }, { 253 .rpt_a = R_EDCCA_RPT_P1_A, 254 .rpt_b = R_EDCCA_RPT_P1_B, 255 .rpt_sel = R_EDCCA_RPT_SEL, 256 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK, 257 }}, 258 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 259 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 260 }; 261 262 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = { 263 {255, 0, 0, 7}, /* 0 -> original */ 264 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 265 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 266 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 267 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 268 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 269 {6, 1, 0, 7}, 270 {13, 1, 0, 7}, 271 {13, 1, 0, 7} 272 }; 273 274 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = { 275 {255, 0, 0, 7}, /* 0 -> original */ 276 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 277 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 278 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 279 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 280 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 281 {255, 1, 0, 7}, 282 {255, 1, 0, 7}, 283 {255, 1, 0, 7} 284 }; 285 286 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { 287 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 288 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 289 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 290 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 291 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 292 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 293 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 294 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 295 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 296 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 297 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 298 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 299 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 300 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), 301 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), 302 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), 303 }; 304 305 static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 306 static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 307 308 static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev) 309 { 310 struct rtw89_efuse *efuse = &rtwdev->efuse; 311 312 if (efuse->rfe_type == 0x5) 313 rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA); 314 } 315 316 static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev) 317 { 318 u32 val32; 319 int ret; 320 321 rtw8852b_pwr_sps_ana(rtwdev); 322 323 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 324 B_AX_AFSM_PCIE_SUS_EN); 325 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 326 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 327 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 328 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 329 330 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 331 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 332 if (ret) 333 return ret; 334 335 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN); 336 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN, 337 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL); 338 if (ret) 339 return ret; 340 341 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); 342 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); 343 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 344 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 345 346 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 347 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 348 if (ret) 349 return ret; 350 351 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 352 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 353 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 354 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 355 356 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 357 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 358 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 359 360 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 361 362 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 363 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 364 if (ret) 365 return ret; 366 367 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 368 369 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 370 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 371 if (ret) 372 return ret; 373 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 374 XTAL_SI_OFF_WEI); 375 if (ret) 376 return ret; 377 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 378 XTAL_SI_OFF_EI); 379 if (ret) 380 return ret; 381 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 382 if (ret) 383 return ret; 384 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 385 XTAL_SI_PON_WEI); 386 if (ret) 387 return ret; 388 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 389 XTAL_SI_PON_EI); 390 if (ret) 391 return ret; 392 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 393 if (ret) 394 return ret; 395 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 396 if (ret) 397 return ret; 398 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 399 if (ret) 400 return ret; 401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 402 if (ret) 403 return ret; 404 405 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 406 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 407 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 408 409 fsleep(1000); 410 411 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 412 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 413 414 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) 415 goto func_en; 416 417 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); 418 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); 419 420 if (rtwdev->hal.cv == CHIP_CBV && rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 421 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 422 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA); 423 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 424 } 425 426 func_en: 427 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 428 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 429 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 430 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 431 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 432 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 433 B_AX_DMACREG_GCKEN); 434 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 435 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 436 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 437 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 438 B_AX_RMAC_EN); 439 440 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, 441 PINMUX_EESK_FUNC_SEL_BT_LOG); 442 443 return 0; 444 } 445 446 static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev) 447 { 448 u32 val32; 449 int ret; 450 451 rtw8852b_pwr_sps_ana(rtwdev); 452 453 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 454 XTAL_SI_RFC2RF); 455 if (ret) 456 return ret; 457 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 458 if (ret) 459 return ret; 460 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 461 if (ret) 462 return ret; 463 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 464 if (ret) 465 return ret; 466 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 467 if (ret) 468 return ret; 469 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 470 XTAL_SI_SRAM2RFC); 471 if (ret) 472 return ret; 473 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 474 if (ret) 475 return ret; 476 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 477 if (ret) 478 return ret; 479 480 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 481 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 482 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 483 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 484 485 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 486 if (ret) 487 return ret; 488 489 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 490 491 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 492 if (ret) 493 return ret; 494 495 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 496 497 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 498 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 499 if (ret) 500 return ret; 501 502 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 503 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 504 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 505 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR); 506 507 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 508 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); 509 510 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 511 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 512 } else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) { 513 val32 = rtw89_read32(rtwdev, R_AX_SYS_PW_CTRL); 514 val32 &= ~B_AX_AFSM_PCIE_SUS_EN; 515 val32 |= B_AX_AFSM_WLSUS_EN; 516 rtw89_write32(rtwdev, R_AX_SYS_PW_CTRL, val32); 517 } 518 519 return 0; 520 } 521 522 static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 523 enum rtw89_phy_idx phy_idx, bool en) 524 { 525 if (en) { 526 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 527 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 528 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 529 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 530 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 531 if (band == RTW89_BAND_2G) 532 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 533 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 534 } else { 535 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 536 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 537 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 538 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 539 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 540 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 541 fsleep(1); 542 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 543 } 544 } 545 546 static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev, 547 enum rtw89_phy_idx phy_idx) 548 { 549 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 550 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 551 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 552 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 553 rtw8852bx_bb_reset_all(rtwdev, phy_idx); 554 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 555 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 556 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 557 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 558 } 559 560 static void rtw8852b_set_channel(struct rtw89_dev *rtwdev, 561 const struct rtw89_chan *chan, 562 enum rtw89_mac_idx mac_idx, 563 enum rtw89_phy_idx phy_idx) 564 { 565 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx); 566 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx); 567 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx); 568 } 569 570 static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 571 enum rtw89_rf_path path) 572 { 573 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; 574 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; 575 576 if (en) { 577 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0); 578 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0); 579 } else { 580 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1); 581 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1); 582 } 583 } 584 585 static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 586 u8 phy_idx) 587 { 588 if (!rtwdev->dbcc_en) { 589 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 590 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 591 } else { 592 if (phy_idx == RTW89_PHY_0) 593 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 594 else 595 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 596 } 597 } 598 599 static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en) 600 { 601 if (en) 602 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 603 else 604 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 605 } 606 607 static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 608 struct rtw89_channel_help_params *p, 609 const struct rtw89_chan *chan, 610 enum rtw89_mac_idx mac_idx, 611 enum rtw89_phy_idx phy_idx) 612 { 613 if (enter) { 614 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 615 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 616 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 617 rtw8852b_adc_en(rtwdev, false); 618 fsleep(40); 619 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 620 } else { 621 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 622 rtw8852b_adc_en(rtwdev, true); 623 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 624 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 625 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 626 } 627 } 628 629 static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev) 630 { 631 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 632 633 rtwdev->is_tssi_mode[RF_PATH_A] = false; 634 rtwdev->is_tssi_mode[RF_PATH_B] = false; 635 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 636 637 rtw8852b_dpk_init(rtwdev); 638 rtw8852b_rck(rtwdev); 639 rtw8852b_dack(rtwdev, RTW89_CHANCTX_0); 640 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0); 641 } 642 643 static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev, 644 struct rtw89_vif_link *rtwvif_link) 645 { 646 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx; 647 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 648 649 rtw8852b_mcc_get_ch_info(rtwdev, phy_idx); 650 rtw89_btc_ntfy_conn_rfk(rtwdev, true); 651 652 rtw8852b_rx_dck(rtwdev, phy_idx, chanctx_idx); 653 rtw8852b_iqk(rtwdev, phy_idx, chanctx_idx); 654 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 655 rtw8852b_tssi(rtwdev, phy_idx, true, chanctx_idx); 656 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 657 rtw8852b_dpk(rtwdev, phy_idx, chanctx_idx); 658 659 rtw89_btc_ntfy_conn_rfk(rtwdev, false); 660 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 661 } 662 663 static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev, 664 enum rtw89_phy_idx phy_idx, 665 const struct rtw89_chan *chan) 666 { 667 rtw8852b_tssi_scan(rtwdev, phy_idx, chan); 668 } 669 670 static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, 671 struct rtw89_vif_link *rtwvif_link, 672 bool start) 673 { 674 rtw8852b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx, 675 rtwvif_link->chanctx_idx); 676 } 677 678 static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev) 679 { 680 rtw8852b_dpk_track(rtwdev); 681 } 682 683 static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) 684 { 685 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 686 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 687 688 if (ver->fcxinit == 7) { 689 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 690 md->md_v7.kt_ver = rtwdev->hal.cv; 691 md->md_v7.bt_solo = 0; 692 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 693 694 if (md->md_v7.rfe_type > 0) 695 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 696 else 697 md->md_v7.ant.num = 2; 698 699 md->md_v7.ant.diversity = 0; 700 md->md_v7.ant.isolation = 10; 701 702 if (md->md_v7.ant.num == 3) { 703 md->md_v7.ant.type = BTC_ANT_DEDICATED; 704 md->md_v7.bt_pos = BTC_BT_ALONE; 705 } else { 706 md->md_v7.ant.type = BTC_ANT_SHARED; 707 md->md_v7.bt_pos = BTC_BT_BTG; 708 } 709 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 710 rtwdev->btc.ant_type = md->md_v7.ant.type; 711 } else { 712 md->md.rfe_type = rtwdev->efuse.rfe_type; 713 md->md.cv = rtwdev->hal.cv; 714 md->md.bt_solo = 0; 715 md->md.switch_type = BTC_SWITCH_INTERNAL; 716 717 if (md->md.rfe_type > 0) 718 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 719 else 720 md->md.ant.num = 2; 721 722 md->md.ant.diversity = 0; 723 md->md.ant.isolation = 10; 724 725 if (md->md.ant.num == 3) { 726 md->md.ant.type = BTC_ANT_DEDICATED; 727 md->md.bt_pos = BTC_BT_ALONE; 728 } else { 729 md->md.ant.type = BTC_ANT_SHARED; 730 md->md.bt_pos = BTC_BT_BTG; 731 } 732 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 733 rtwdev->btc.ant_type = md->md.ant.type; 734 } 735 } 736 737 union rtw8852b_btc_wl_txpwr_ctrl { 738 u32 txpwr_val; 739 struct { 740 union { 741 u16 ctrl_all_time; 742 struct { 743 s16 data:9; 744 u16 rsvd:6; 745 u16 flag:1; 746 } all_time; 747 }; 748 union { 749 u16 ctrl_gnt_bt; 750 struct { 751 s16 data:9; 752 u16 rsvd:7; 753 } gnt_bt; 754 }; 755 }; 756 } __packed; 757 758 static void 759 rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 760 { 761 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 762 s32 val; 763 764 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 765 do { \ 766 u32 _wrt = FIELD_PREP(_msk, _val); \ 767 BUILD_BUG_ON(!!(_msk & _en)); \ 768 if (_cond) \ 769 _wrt |= _en; \ 770 else \ 771 _wrt &= ~_en; \ 772 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 773 _msk | _en, _wrt); \ 774 } while (0) 775 776 switch (arg.ctrl_all_time) { 777 case 0xffff: 778 val = 0; 779 break; 780 default: 781 val = arg.all_time.data; 782 break; 783 } 784 785 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 786 val, B_AX_FORCE_PWR_BY_RATE_EN, 787 arg.ctrl_all_time != 0xffff); 788 789 switch (arg.ctrl_gnt_bt) { 790 case 0xffff: 791 val = 0; 792 break; 793 default: 794 val = arg.gnt_bt.data; 795 break; 796 } 797 798 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 799 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 800 801 #undef __write_ctrl 802 } 803 804 static const struct rtw89_chip_ops rtw8852b_chip_ops = { 805 .enable_bb_rf = rtw8852bx_mac_enable_bb_rf, 806 .disable_bb_rf = rtw8852bx_mac_disable_bb_rf, 807 .bb_preinit = NULL, 808 .bb_postinit = NULL, 809 .bb_reset = rtw8852b_bb_reset, 810 .bb_sethw = rtw8852bx_bb_sethw, 811 .read_rf = rtw89_phy_read_rf_v1, 812 .write_rf = rtw89_phy_write_rf_v1, 813 .set_channel = rtw8852b_set_channel, 814 .set_channel_help = rtw8852b_set_channel_help, 815 .read_efuse = rtw8852bx_read_efuse, 816 .read_phycap = rtw8852bx_read_phycap, 817 .fem_setup = NULL, 818 .rfe_gpio = NULL, 819 .rfk_hw_init = NULL, 820 .rfk_init = rtw8852b_rfk_init, 821 .rfk_init_late = NULL, 822 .rfk_channel = rtw8852b_rfk_channel, 823 .rfk_band_changed = rtw8852b_rfk_band_changed, 824 .rfk_scan = rtw8852b_rfk_scan, 825 .rfk_track = rtw8852b_rfk_track, 826 .power_trim = rtw8852bx_power_trim, 827 .set_txpwr = rtw8852bx_set_txpwr, 828 .set_txpwr_ctrl = rtw8852bx_set_txpwr_ctrl, 829 .init_txpwr_unit = rtw8852bx_init_txpwr_unit, 830 .get_thermal = rtw8852bx_get_thermal, 831 .chan_to_rf18_val = NULL, 832 .ctrl_btg_bt_rx = rtw8852bx_ctrl_btg_bt_rx, 833 .query_ppdu = rtw8852bx_query_ppdu, 834 .convert_rpl_to_rssi = rtw8852bx_convert_rpl_to_rssi, 835 .phy_rpt_to_rssi = NULL, 836 .ctrl_nbtg_bt_tx = rtw8852bx_ctrl_nbtg_bt_tx, 837 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, 838 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, 839 .digital_pwr_comp = NULL, 840 .pwr_on_func = rtw8852b_pwr_on_func, 841 .pwr_off_func = rtw8852b_pwr_off_func, 842 .query_rxdesc = rtw89_core_query_rxdesc, 843 .fill_txdesc = rtw89_core_fill_txdesc, 844 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 845 .get_ch_dma = rtw89_core_get_ch_dma, 846 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 847 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 848 .stop_sch_tx = rtw89_mac_stop_sch_tx, 849 .resume_sch_tx = rtw89_mac_resume_sch_tx, 850 .h2c_dctl_sec_cam = NULL, 851 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 852 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 853 .h2c_ampdu_cmac_tbl = NULL, 854 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl, 855 .h2c_punctured_cmac_tbl = NULL, 856 .h2c_default_dmac_tbl = NULL, 857 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 858 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 859 860 .btc_set_rfe = rtw8852b_btc_set_rfe, 861 .btc_init_cfg = rtw8852bx_btc_init_cfg, 862 .btc_set_wl_pri = rtw8852bx_btc_set_wl_pri, 863 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl, 864 .btc_get_bt_rssi = rtw8852bx_btc_get_bt_rssi, 865 .btc_update_bt_cnt = rtw8852bx_btc_update_bt_cnt, 866 .btc_wl_s1_standby = rtw8852bx_btc_wl_s1_standby, 867 .btc_set_wl_rx_gain = rtw8852bx_btc_set_wl_rx_gain, 868 .btc_set_policy = rtw89_btc_set_policy_v1, 869 }; 870 871 static const struct rtw89_chanctx_listener rtw8852b_chanctx_listener = { 872 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852b_rfk_chanctx_cb, 873 }; 874 875 #ifdef CONFIG_PM 876 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = { 877 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 878 .n_patterns = RTW89_MAX_PATTERN_NUM, 879 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 880 .pattern_min_len = 1, 881 }; 882 #endif 883 884 const struct rtw89_chip_info rtw8852b_chip_info = { 885 .chip_id = RTL8852B, 886 .chip_gen = RTW89_CHIP_AX, 887 .ops = &rtw8852b_chip_ops, 888 .mac_def = &rtw89_mac_gen_ax, 889 .phy_def = &rtw89_phy_gen_ax, 890 .fw_basename = RTW8852B_FW_BASENAME, 891 .fw_format_max = RTW8852B_FW_FORMAT_MAX, 892 .try_ce_fw = true, 893 .bbmcu_nr = 0, 894 .needed_fw_elms = 0, 895 .fw_blacklist = &rtw89_fw_blacklist_default, 896 .fifo_size = 196608, 897 .small_fifo_size = true, 898 .dle_scc_rsvd_size = 98304, 899 .max_amsdu_limit = 5000, 900 .dis_2g_40m_ul_ofdma = true, 901 .rsvd_ple_ofst = 0x2f800, 902 .hfc_param_ini = {rtw8852b_hfc_param_ini_pcie, 903 rtw8852b_hfc_param_ini_usb, 904 NULL}, 905 .dle_mem = {rtw8852b_dle_mem_pcie, 906 rtw8852b_dle_mem_usb3, 907 rtw8852b_dle_mem_usb3, 908 NULL}, 909 .wde_qempty_acq_grpnum = 4, 910 .wde_qempty_mgq_grpsel = 4, 911 .rf_base_addr = {0xe000, 0xf000}, 912 .thermal_th = {0x32, 0x35}, 913 .pwr_on_seq = NULL, 914 .pwr_off_seq = NULL, 915 .bb_table = &rtw89_8852b_phy_bb_table, 916 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table, 917 .rf_table = {&rtw89_8852b_phy_radioa_table, 918 &rtw89_8852b_phy_radiob_table,}, 919 .nctl_table = &rtw89_8852b_phy_nctl_table, 920 .nctl_post_table = NULL, 921 .dflt_parms = &rtw89_8852b_dflt_parms, 922 .rfe_parms_conf = NULL, 923 .chanctx_listener = &rtw8852b_chanctx_listener, 924 .txpwr_factor_bb = 3, 925 .txpwr_factor_rf = 2, 926 .txpwr_factor_mac = 1, 927 .dig_table = NULL, 928 .dig_regs = &rtw8852b_dig_regs, 929 .tssi_dbw_table = NULL, 930 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 931 .support_link_num = 0, 932 .support_chanctx_num = 2, 933 .support_rnr = false, 934 .support_bands = BIT(NL80211_BAND_2GHZ) | 935 BIT(NL80211_BAND_5GHZ), 936 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 937 BIT(NL80211_CHAN_WIDTH_40) | 938 BIT(NL80211_CHAN_WIDTH_80), 939 .support_unii4 = true, 940 .support_ant_gain = true, 941 .support_tas = false, 942 .support_sar_by_ant = true, 943 .support_noise = false, 944 .ul_tb_waveform_ctrl = true, 945 .ul_tb_pwr_diff = false, 946 .rx_freq_frome_ie = true, 947 .hw_sec_hdr = false, 948 .hw_mgmt_tx_encrypt = false, 949 .hw_tkip_crypto = false, 950 .hw_mlo_bmc_crypto = false, 951 .rf_path_num = 2, 952 .tx_nss = 2, 953 .rx_nss = 2, 954 .acam_num = 128, 955 .bcam_num = 10, 956 .scam_num = 128, 957 .bacam_num = 2, 958 .bacam_dynamic_num = 4, 959 .bacam_ver = RTW89_BACAM_V0, 960 .ppdu_max_usr = 4, 961 .sec_ctrl_efuse_size = 4, 962 .physical_efuse_size = 1216, 963 .logical_efuse_size = 2048, 964 .limit_efuse_size = 1280, 965 .dav_phy_efuse_size = 96, 966 .dav_log_efuse_size = 16, 967 .efuse_blocks = NULL, 968 .phycap_addr = 0x580, 969 .phycap_size = 128, 970 .para_ver = 0, 971 .wlcx_desired = 0x05050000, 972 .scbd = 0x1, 973 .mailbox = 0x1, 974 975 .afh_guard_ch = 6, 976 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres, 977 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres, 978 .rssi_tol = 2, 979 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg), 980 .mon_reg = rtw89_btc_8852b_mon_reg, 981 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul), 982 .rf_para_ulink = rtw89_btc_8852b_rf_ul, 983 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl), 984 .rf_para_dlink = rtw89_btc_8852b_rf_dl, 985 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 986 BIT(RTW89_PS_MODE_CLK_GATED) | 987 BIT(RTW89_PS_MODE_PWR_GATED), 988 .low_power_hci_modes = 0, 989 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 990 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 991 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 992 .txwd_body_size = sizeof(struct rtw89_txwd_body), 993 .txwd_info_size = sizeof(struct rtw89_txwd_info), 994 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 995 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 996 .h2c_regs = rtw8852b_h2c_regs, 997 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 998 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 999 .c2h_regs = rtw8852b_c2h_regs, 1000 .page_regs = &rtw8852b_page_regs, 1001 .wow_reason_reg = rtw8852b_wow_wakeup_regs, 1002 .cfo_src_fd = true, 1003 .cfo_hw_comp = true, 1004 .dcfo_comp = &rtw8852b_dcfo_comp, 1005 .dcfo_comp_sft = 10, 1006 .nhm_report = NULL, 1007 .nhm_th = NULL, 1008 .imr_info = &rtw8852b_imr_info, 1009 .imr_dmac_table = NULL, 1010 .imr_cmac_table = NULL, 1011 .rrsr_cfgs = &rtw8852b_rrsr_cfgs, 1012 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 1013 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 1014 .rfkill_init = &rtw8852b_rfkill_regs, 1015 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 1016 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 1017 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 1018 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 1019 .edcca_regs = &rtw8852b_edcca_regs, 1020 #ifdef CONFIG_PM 1021 .wowlan_stub = &rtw_wowlan_stub_8852b, 1022 #endif 1023 .xtal_info = NULL, 1024 }; 1025 EXPORT_SYMBOL(rtw8852b_chip_info); 1026 1027 MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE); 1028 MODULE_AUTHOR("Realtek Corporation"); 1029 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver"); 1030 MODULE_LICENSE("Dual BSD/GPL"); 1031