1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_8852A_H__ 6 #define __RTW89_8852A_H__ 7 8 #include "core.h" 9 10 #define RF_PATH_NUM_8852A 2 11 12 enum rtw8852a_pmac_mode { 13 NONE_TEST, 14 PKTS_TX, 15 PKTS_RX, 16 CONT_TX 17 }; 18 19 struct rtw8852au_efuse { 20 u8 rsvd[0x38]; 21 u8 mac_addr[ETH_ALEN]; 22 }; 23 24 struct rtw8852ae_efuse { 25 u8 mac_addr[ETH_ALEN]; 26 }; 27 28 struct rtw8852a_tssi_offset { 29 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; 30 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; 31 u8 rsvd[7]; 32 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; 33 } __packed; 34 35 struct rtw8852a_efuse { 36 u8 rsvd[0x210]; 37 struct rtw8852a_tssi_offset path_a_tssi; 38 u8 rsvd1[10]; 39 struct rtw8852a_tssi_offset path_b_tssi; 40 u8 rsvd2[94]; 41 u8 channel_plan; 42 u8 xtal_k; 43 u8 rsvd3; 44 u8 iqk_lck; 45 u8 rsvd4[5]; 46 u8 reg_setting:2; 47 u8 tx_diversity:1; 48 u8 rx_diversity:2; 49 u8 ac_mode:1; 50 u8 module_type:2; 51 u8 rsvd5; 52 u8 shared_ant:1; 53 u8 coex_type:3; 54 u8 ant_iso:1; 55 u8 radio_on_off:1; 56 u8 rsvd6:2; 57 u8 eeprom_version; 58 u8 customer_id; 59 u8 tx_bb_swing_2g; 60 u8 tx_bb_swing_5g; 61 u8 tx_cali_pwr_trk_mode; 62 u8 trx_path_selection; 63 u8 rfe_type; 64 u8 country_code[2]; 65 u8 rsvd7[3]; 66 u8 path_a_therm; 67 u8 path_b_therm; 68 u8 rsvd8[46]; 69 u8 path_a_cck_pwr_idx[6]; 70 u8 path_a_bw40_1tx_pwr_idx[5]; 71 u8 path_a_ofdm_1tx_pwr_idx_diff:4; 72 u8 path_a_bw20_1tx_pwr_idx_diff:4; 73 u8 path_a_bw20_2tx_pwr_idx_diff:4; 74 u8 path_a_bw40_2tx_pwr_idx_diff:4; 75 u8 path_a_cck_2tx_pwr_idx_diff:4; 76 u8 path_a_ofdm_2tx_pwr_idx_diff:4; 77 u8 rsvd9[0xf2]; 78 union { 79 struct rtw8852au_efuse u; 80 struct rtw8852ae_efuse e; 81 }; 82 } __packed; 83 84 struct rtw8852a_bb_pmac_info { 85 u8 en_pmac_tx:1; 86 u8 is_cck:1; 87 u8 mode:3; 88 u8 rsvd:3; 89 u16 tx_cnt; 90 u16 period; 91 u16 tx_time; 92 u8 duty_cycle; 93 }; 94 95 extern const struct rtw89_chip_info rtw8852a_chip_info; 96 97 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev); 98 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 99 struct rtw8852a_bb_pmac_info *tx_info, 100 enum rtw89_phy_idx idx); 101 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 102 u16 tx_cnt, u16 period, u16 tx_time, 103 enum rtw89_phy_idx idx); 104 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 105 enum rtw89_phy_idx idx); 106 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path); 107 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 108 enum rtw89_phy_idx idx, u8 mode); 109 110 #endif 111