1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 #define RTW8852A_FW_FORMAT_MAX 0 16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17 #define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 55 &rtw89_mac_size.ple_qt5}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 59 &rtw89_mac_size.ple_qt_52a_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 69 {0x44AC, 0x00000000}, 70 {0x44B0, 0x00000000}, 71 {0x44B4, 0x00000000}, 72 {0x44B8, 0x00000000}, 73 {0x44BC, 0x00000000}, 74 {0x44C0, 0x00000000}, 75 {0x44C4, 0x00000000}, 76 {0x44C8, 0x00000000}, 77 {0x44CC, 0x00000000}, 78 {0x44D0, 0x00000000}, 79 {0x44D4, 0x00000000}, 80 {0x44D8, 0x00000000}, 81 {0x44DC, 0x00000000}, 82 {0x44E0, 0x00000000}, 83 {0x44E4, 0x00000000}, 84 {0x44E8, 0x00000000}, 85 {0x44EC, 0x00000000}, 86 {0x44F0, 0x00000000}, 87 {0x44F4, 0x00000000}, 88 {0x44F8, 0x00000000}, 89 {0x44FC, 0x00000000}, 90 {0x4500, 0x00000000}, 91 {0x4504, 0x00000000}, 92 {0x4508, 0x00000000}, 93 {0x450C, 0x00000000}, 94 {0x4510, 0x00000000}, 95 {0x4514, 0x00000000}, 96 {0x4518, 0x00000000}, 97 {0x451C, 0x00000000}, 98 {0x4520, 0x00000000}, 99 {0x4524, 0x00000000}, 100 {0x4528, 0x00000000}, 101 {0x452C, 0x00000000}, 102 {0x4530, 0x4E1F3E81}, 103 {0x4534, 0x00000000}, 104 {0x4538, 0x0000005A}, 105 {0x453C, 0x00000000}, 106 {0x4540, 0x00000000}, 107 {0x4544, 0x00000000}, 108 {0x4548, 0x00000000}, 109 {0x454C, 0x00000000}, 110 {0x4550, 0x00000000}, 111 {0x4554, 0x00000000}, 112 {0x4558, 0x00000000}, 113 {0x455C, 0x00000000}, 114 {0x4560, 0x4060001A}, 115 {0x4564, 0x40000000}, 116 {0x4568, 0x00000000}, 117 {0x456C, 0x00000000}, 118 {0x4570, 0x04000007}, 119 {0x4574, 0x0000DC87}, 120 {0x4578, 0x00000BAB}, 121 {0x457C, 0x03E00000}, 122 {0x4580, 0x00000048}, 123 {0x4584, 0x00000000}, 124 {0x4588, 0x000003E8}, 125 {0x458C, 0x30000000}, 126 {0x4590, 0x00000000}, 127 {0x4594, 0x10000000}, 128 {0x4598, 0x00000001}, 129 {0x459C, 0x00030000}, 130 {0x45A0, 0x01000000}, 131 {0x45A4, 0x03000200}, 132 {0x45A8, 0xC00001C0}, 133 {0x45AC, 0x78018000}, 134 {0x45B0, 0x80000000}, 135 {0x45B4, 0x01C80600}, 136 {0x45B8, 0x00000002}, 137 {0x4594, 0x10000000} 138 }; 139 140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 141 {0x4624, GENMASK(20, 14), 0x40}, 142 {0x46f8, GENMASK(20, 14), 0x40}, 143 {0x4674, GENMASK(20, 19), 0x2}, 144 {0x4748, GENMASK(20, 19), 0x2}, 145 {0x4650, GENMASK(14, 10), 0x18}, 146 {0x4724, GENMASK(14, 10), 0x18}, 147 {0x4688, GENMASK(1, 0), 0x3}, 148 {0x475c, GENMASK(1, 0), 0x3}, 149 }; 150 151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 152 153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 154 {0x4624, GENMASK(20, 14), 0x1a}, 155 {0x46f8, GENMASK(20, 14), 0x1a}, 156 {0x4674, GENMASK(20, 19), 0x1}, 157 {0x4748, GENMASK(20, 19), 0x1}, 158 {0x4650, GENMASK(14, 10), 0x12}, 159 {0x4724, GENMASK(14, 10), 0x12}, 160 {0x4688, GENMASK(1, 0), 0x0}, 161 {0x475c, GENMASK(1, 0), 0x0}, 162 }; 163 164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 165 166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 167 {0x00C6, 168 PWR_CV_MSK_B, 169 PWR_INTF_MSK_PCIE, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(6), BIT(6)}, 172 {0x1086, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_SDIO, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(0), 0}, 177 {0x1086, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_SDIO, 180 PWR_BASE_MAC, 181 PWR_CMD_POLL, BIT(1), BIT(1)}, 182 {0x0005, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 187 {0x0005, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(7), 0}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(2), 0}, 197 {0x0006, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(1), BIT(1)}, 202 {0x0006, 203 PWR_CV_MSK_ALL, 204 PWR_INTF_MSK_ALL, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(0), BIT(0)}, 207 {0x0005, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0005, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_POLL, BIT(0), 0}, 217 {0x106D, 218 PWR_CV_MSK_B | PWR_CV_MSK_C, 219 PWR_INTF_MSK_USB, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(6), 0}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), BIT(0)}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x0088, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(0), BIT(0)}, 237 {0x0088, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(0), 0}, 242 {0x0088, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(0), BIT(0)}, 247 {0x0083, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(6), 0}, 252 {0x0080, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(5), BIT(5)}, 257 {0x0024, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 262 {0x02A0, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(1), BIT(1)}, 267 {0x02A2, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 272 {0x0071, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_PCIE, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(4), 0}, 277 {0x0010, 278 PWR_CV_MSK_A, 279 PWR_INTF_MSK_PCIE, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(2), BIT(2)}, 282 {0x02A0, 283 PWR_CV_MSK_A, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 287 {0xFFFF, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 0, 291 PWR_CMD_END, 0, 0}, 292 }; 293 294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 295 {0x02F0, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, 0xFF, 0}, 300 {0x02F1, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, 0xFF, 0}, 305 {0x0006, 306 PWR_CV_MSK_ALL, 307 PWR_INTF_MSK_ALL, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(0), BIT(0)}, 310 {0x0002, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 315 {0x0082, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 320 {0x106D, 321 PWR_CV_MSK_B | PWR_CV_MSK_C, 322 PWR_INTF_MSK_USB, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(6), BIT(6)}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_ALL, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(1), BIT(1)}, 330 {0x0005, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_ALL, 333 PWR_BASE_MAC, 334 PWR_CMD_POLL, BIT(1), 0}, 335 {0x0091, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_PCIE, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(0), 0}, 340 {0x0005, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_PCIE, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(2), BIT(2)}, 345 {0x0007, 346 PWR_CV_MSK_ALL, 347 PWR_INTF_MSK_USB, 348 PWR_BASE_MAC, 349 PWR_CMD_WRITE, BIT(4), 0}, 350 {0x0007, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_SDIO, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 355 {0x0005, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 360 {0x0005, 361 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 362 PWR_CV_MSK_G, 363 PWR_INTF_MSK_USB, 364 PWR_BASE_MAC, 365 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 366 {0x1086, 367 PWR_CV_MSK_ALL, 368 PWR_INTF_MSK_SDIO, 369 PWR_BASE_MAC, 370 PWR_CMD_WRITE, BIT(0), BIT(0)}, 371 {0x1086, 372 PWR_CV_MSK_ALL, 373 PWR_INTF_MSK_SDIO, 374 PWR_BASE_MAC, 375 PWR_CMD_POLL, BIT(1), 0}, 376 {0xFFFF, 377 PWR_CV_MSK_ALL, 378 PWR_INTF_MSK_ALL, 379 0, 380 PWR_CMD_END, 0, 0}, 381 }; 382 383 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 384 rtw8852a_pwron, NULL 385 }; 386 387 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 388 rtw8852a_pwroff, NULL 389 }; 390 391 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 392 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 393 R_AX_H2CREG_DATA3 394 }; 395 396 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 397 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 398 R_AX_C2HREG_DATA3 399 }; 400 401 static const struct rtw89_page_regs rtw8852a_page_regs = { 402 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 403 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 404 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 405 .ach_page_info = R_AX_ACH0_PAGE_INFO, 406 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 407 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 408 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 409 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 410 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 411 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 412 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 413 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 414 }; 415 416 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 417 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 418 }; 419 420 static const struct rtw89_imr_info rtw8852a_imr_info = { 421 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 422 .wsec_imr_reg = R_AX_SEC_DEBUG, 423 .wsec_imr_set = B_AX_IMR_ERROR, 424 .mpdu_tx_imr_set = 0, 425 .mpdu_rx_imr_set = 0, 426 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 427 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 428 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 429 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 430 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 431 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 432 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 433 .wde_imr_clr = B_AX_WDE_IMR_CLR, 434 .wde_imr_set = B_AX_WDE_IMR_SET, 435 .ple_imr_clr = B_AX_PLE_IMR_CLR, 436 .ple_imr_set = B_AX_PLE_IMR_SET, 437 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 438 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 439 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 440 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 441 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 442 .other_disp_imr_set = 0, 443 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 444 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 445 .bbrpt_err_imr_set = 0, 446 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 447 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 448 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 449 .cdma_imr_0_reg = R_AX_DLE_CTRL, 450 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 451 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 452 .cdma_imr_1_reg = 0, 453 .cdma_imr_1_clr = 0, 454 .cdma_imr_1_set = 0, 455 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 456 .phy_intf_imr_clr = 0, 457 .phy_intf_imr_set = 0, 458 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 459 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 460 .rmac_imr_set = B_AX_RMAC_IMR_SET, 461 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 462 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 463 .tmac_imr_set = B_AX_TMAC_IMR_SET, 464 }; 465 466 static const struct rtw89_xtal_info rtw8852a_xtal_info = { 467 .xcap_reg = R_AX_XTAL_ON_CTRL0, 468 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK, 469 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK, 470 }; 471 472 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 473 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 474 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 475 }; 476 477 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 478 .seg0_pd_reg = R_SEG0R_PD, 479 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 480 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 481 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 482 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 483 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 484 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 485 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 486 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 487 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 488 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 489 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 490 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 491 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 492 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 493 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 494 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 495 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 496 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 497 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 498 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 499 }; 500 501 static const struct rtw89_edcca_regs rtw8852a_edcca_regs = { 502 .edcca_level = R_SEG0R_EDCCA_LVL, 503 .edcca_mask = B_EDCCA_LVL_MSK0, 504 .edcca_p_mask = B_EDCCA_LVL_MSK1, 505 .ppdu_level = R_SEG0R_EDCCA_LVL, 506 .ppdu_mask = B_EDCCA_LVL_MSK3, 507 .rpt_a = R_EDCCA_RPT_A, 508 .rpt_b = R_EDCCA_RPT_B, 509 .rpt_sel = R_EDCCA_RPT_SEL, 510 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 511 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 512 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 513 }; 514 515 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 516 struct rtw8852a_efuse *map) 517 { 518 ether_addr_copy(efuse->addr, map->e.mac_addr); 519 efuse->rfe_type = map->rfe_type; 520 efuse->xtal_cap = map->xtal_k; 521 } 522 523 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 524 struct rtw8852a_efuse *map) 525 { 526 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 527 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 528 u8 i, j; 529 530 tssi->thermal[RF_PATH_A] = map->path_a_therm; 531 tssi->thermal[RF_PATH_B] = map->path_b_therm; 532 533 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 534 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 535 sizeof(ofst[i]->cck_tssi)); 536 537 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 538 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 539 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 540 i, j, tssi->tssi_cck[i][j]); 541 542 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 543 sizeof(ofst[i]->bw40_tssi)); 544 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 545 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 546 547 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 548 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 549 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 550 i, j, tssi->tssi_mcs[i][j]); 551 } 552 } 553 554 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 555 enum rtw89_efuse_block block) 556 { 557 struct rtw89_efuse *efuse = &rtwdev->efuse; 558 struct rtw8852a_efuse *map; 559 560 map = (struct rtw8852a_efuse *)log_map; 561 562 efuse->country_code[0] = map->country_code[0]; 563 efuse->country_code[1] = map->country_code[1]; 564 rtw8852a_efuse_parsing_tssi(rtwdev, map); 565 566 switch (rtwdev->hci.type) { 567 case RTW89_HCI_TYPE_PCIE: 568 rtw8852ae_efuse_parsing(efuse, map); 569 break; 570 default: 571 return -ENOTSUPP; 572 } 573 574 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 575 576 return 0; 577 } 578 579 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 580 { 581 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 582 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 583 u32 addr = rtwdev->chip->phycap_addr; 584 bool pg = false; 585 u32 ofst; 586 u8 i, j; 587 588 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 589 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 590 /* addrs are in decreasing order */ 591 ofst = tssi_trim_addr[i] - addr - j; 592 tssi->tssi_trim[i][j] = phycap_map[ofst]; 593 594 if (phycap_map[ofst] != 0xff) 595 pg = true; 596 } 597 } 598 599 if (!pg) { 600 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 601 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 602 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 603 } 604 605 for (i = 0; i < RF_PATH_NUM_8852A; i++) 606 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 607 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 608 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 609 i, j, tssi->tssi_trim[i][j], 610 tssi_trim_addr[i] - j); 611 } 612 613 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 614 u8 *phycap_map) 615 { 616 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 617 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 618 u32 addr = rtwdev->chip->phycap_addr; 619 u8 i; 620 621 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 622 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 623 624 rtw89_debug(rtwdev, RTW89_DBG_RFK, 625 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 626 i, info->thermal_trim[i]); 627 628 if (info->thermal_trim[i] != 0xff) 629 info->pg_thermal_trim = true; 630 } 631 } 632 633 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 634 { 635 #define __thm_setting(raw) \ 636 ({ \ 637 u8 __v = (raw); \ 638 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 639 }) 640 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 641 u8 i, val; 642 643 if (!info->pg_thermal_trim) { 644 rtw89_debug(rtwdev, RTW89_DBG_RFK, 645 "[THERMAL][TRIM] no PG, do nothing\n"); 646 647 return; 648 } 649 650 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 651 val = __thm_setting(info->thermal_trim[i]); 652 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 653 654 rtw89_debug(rtwdev, RTW89_DBG_RFK, 655 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 656 i, val); 657 } 658 #undef __thm_setting 659 } 660 661 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 662 u8 *phycap_map) 663 { 664 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 665 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 666 u32 addr = rtwdev->chip->phycap_addr; 667 u8 i; 668 669 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 670 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 671 672 rtw89_debug(rtwdev, RTW89_DBG_RFK, 673 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 674 i, info->pa_bias_trim[i]); 675 676 if (info->pa_bias_trim[i] != 0xff) 677 info->pg_pa_bias_trim = true; 678 } 679 } 680 681 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 682 { 683 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 684 u8 pabias_2g, pabias_5g; 685 u8 i; 686 687 if (!info->pg_pa_bias_trim) { 688 rtw89_debug(rtwdev, RTW89_DBG_RFK, 689 "[PA_BIAS][TRIM] no PG, do nothing\n"); 690 691 return; 692 } 693 694 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 695 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 696 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 697 698 rtw89_debug(rtwdev, RTW89_DBG_RFK, 699 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 700 i, pabias_2g, pabias_5g); 701 702 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 703 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 704 } 705 } 706 707 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 708 { 709 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 710 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 711 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 712 713 return 0; 714 } 715 716 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 717 { 718 rtw8852a_thermal_trim(rtwdev); 719 rtw8852a_pa_bias_trim(rtwdev); 720 } 721 722 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 723 const struct rtw89_chan *chan, 724 u8 mac_idx) 725 { 726 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 727 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 728 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 729 u8 txsc20 = 0, txsc40 = 0; 730 731 switch (chan->band_width) { 732 case RTW89_CHANNEL_WIDTH_80: 733 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 734 RTW89_CHANNEL_WIDTH_40); 735 fallthrough; 736 case RTW89_CHANNEL_WIDTH_40: 737 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 738 RTW89_CHANNEL_WIDTH_20); 739 break; 740 default: 741 break; 742 } 743 744 switch (chan->band_width) { 745 case RTW89_CHANNEL_WIDTH_80: 746 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 747 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 748 break; 749 case RTW89_CHANNEL_WIDTH_40: 750 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 751 rtw89_write32(rtwdev, sub_carr, txsc20); 752 break; 753 case RTW89_CHANNEL_WIDTH_20: 754 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 755 rtw89_write32(rtwdev, sub_carr, 0); 756 break; 757 default: 758 break; 759 } 760 761 if (chan->channel > 14) 762 rtw89_write8_set(rtwdev, chk_rate, 763 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 764 else 765 rtw89_write8_clr(rtwdev, chk_rate, 766 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 767 } 768 769 static const u32 rtw8852a_sco_barker_threshold[14] = { 770 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 771 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 772 }; 773 774 static const u32 rtw8852a_sco_cck_threshold[14] = { 775 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 776 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 777 }; 778 779 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 780 u8 primary_ch, enum rtw89_bandwidth bw) 781 { 782 u8 ch_element; 783 784 if (bw == RTW89_CHANNEL_WIDTH_20) { 785 ch_element = central_ch - 1; 786 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 787 if (primary_ch == 1) 788 ch_element = central_ch - 1 + 2; 789 else 790 ch_element = central_ch - 1 - 2; 791 } else { 792 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 793 return -EINVAL; 794 } 795 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 796 rtw8852a_sco_barker_threshold[ch_element]); 797 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 798 rtw8852a_sco_cck_threshold[ch_element]); 799 800 return 0; 801 } 802 803 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 804 u8 path) 805 { 806 u32 val; 807 808 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 809 if (val == INV_RF_DATA) { 810 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 811 return; 812 } 813 val &= ~0x303ff; 814 val |= central_ch; 815 if (central_ch > 14) 816 val |= (BIT(16) | BIT(8)); 817 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 818 } 819 820 static u8 rtw8852a_sco_mapping(u8 central_ch) 821 { 822 if (central_ch == 1) 823 return 109; 824 else if (central_ch >= 2 && central_ch <= 6) 825 return 108; 826 else if (central_ch >= 7 && central_ch <= 10) 827 return 107; 828 else if (central_ch >= 11 && central_ch <= 14) 829 return 106; 830 else if (central_ch == 36 || central_ch == 38) 831 return 51; 832 else if (central_ch >= 40 && central_ch <= 58) 833 return 50; 834 else if (central_ch >= 60 && central_ch <= 64) 835 return 49; 836 else if (central_ch == 100 || central_ch == 102) 837 return 48; 838 else if (central_ch >= 104 && central_ch <= 126) 839 return 47; 840 else if (central_ch >= 128 && central_ch <= 151) 841 return 46; 842 else if (central_ch >= 153 && central_ch <= 177) 843 return 45; 844 else 845 return 0; 846 } 847 848 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 849 enum rtw89_phy_idx phy_idx) 850 { 851 u8 sco_comp; 852 bool is_2g = central_ch <= 14; 853 854 if (phy_idx == RTW89_PHY_0) { 855 /* Path A */ 856 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 857 if (is_2g) 858 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 859 B_PATH0_TIA_ERR_G1_SEL, 1, 860 phy_idx); 861 else 862 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 863 B_PATH0_TIA_ERR_G1_SEL, 0, 864 phy_idx); 865 866 /* Path B */ 867 if (!rtwdev->dbcc_en) { 868 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 869 if (is_2g) 870 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 871 B_P1_MODE_SEL, 872 1, phy_idx); 873 else 874 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 875 B_P1_MODE_SEL, 876 0, phy_idx); 877 } else { 878 if (is_2g) 879 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 880 B_2P4G_BAND_SEL); 881 else 882 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 883 B_2P4G_BAND_SEL); 884 } 885 /* SCO compensate FC setting */ 886 sco_comp = rtw8852a_sco_mapping(central_ch); 887 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 888 sco_comp, phy_idx); 889 } else { 890 /* Path B */ 891 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 892 if (is_2g) 893 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 894 B_P1_MODE_SEL, 895 1, phy_idx); 896 else 897 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 898 B_P1_MODE_SEL, 899 0, phy_idx); 900 /* SCO compensate FC setting */ 901 sco_comp = rtw8852a_sco_mapping(central_ch); 902 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 903 sco_comp, phy_idx); 904 } 905 906 /* Band edge */ 907 if (is_2g) 908 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 909 phy_idx); 910 else 911 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 912 phy_idx); 913 914 /* CCK parameters */ 915 if (central_ch == 14) { 916 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 917 0x3b13ff); 918 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 919 0x1c42de); 920 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 921 0xfdb0ad); 922 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 923 0xf60f6e); 924 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 925 0xfd8f92); 926 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 927 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 928 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 929 0xfff00a); 930 } else { 931 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 932 0x3d23ff); 933 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 934 0x29b354); 935 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 936 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 937 0xfdb053); 938 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 939 0xf86f9a); 940 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 941 0xfaef92); 942 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 943 0xfe5fcc); 944 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 945 0xffdff5); 946 } 947 } 948 949 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 950 { 951 u32 val = 0; 952 u32 adc_sel[2] = {0x12d0, 0x32d0}; 953 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 954 955 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 956 if (val == INV_RF_DATA) { 957 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 958 return; 959 } 960 val &= ~(BIT(11) | BIT(10)); 961 switch (bw) { 962 case RTW89_CHANNEL_WIDTH_5: 963 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 964 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 965 val |= (BIT(11) | BIT(10)); 966 break; 967 case RTW89_CHANNEL_WIDTH_10: 968 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 969 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 970 val |= (BIT(11) | BIT(10)); 971 break; 972 case RTW89_CHANNEL_WIDTH_20: 973 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 974 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 975 val |= (BIT(11) | BIT(10)); 976 break; 977 case RTW89_CHANNEL_WIDTH_40: 978 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 979 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 980 val |= BIT(11); 981 break; 982 case RTW89_CHANNEL_WIDTH_80: 983 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 984 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 985 val |= BIT(10); 986 break; 987 default: 988 rtw89_warn(rtwdev, "Fail to set ADC\n"); 989 } 990 991 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 992 } 993 994 static void 995 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 996 enum rtw89_phy_idx phy_idx) 997 { 998 /* Switch bandwidth */ 999 switch (bw) { 1000 case RTW89_CHANNEL_WIDTH_5: 1001 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1002 phy_idx); 1003 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 1004 phy_idx); 1005 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1006 0x0, phy_idx); 1007 break; 1008 case RTW89_CHANNEL_WIDTH_10: 1009 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1010 phy_idx); 1011 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 1012 phy_idx); 1013 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1014 0x0, phy_idx); 1015 break; 1016 case RTW89_CHANNEL_WIDTH_20: 1017 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1018 phy_idx); 1019 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1020 phy_idx); 1021 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1022 0x0, phy_idx); 1023 break; 1024 case RTW89_CHANNEL_WIDTH_40: 1025 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1026 phy_idx); 1027 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1028 phy_idx); 1029 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1030 pri_ch, 1031 phy_idx); 1032 if (pri_ch == RTW89_SC_20_UPPER) 1033 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1034 else 1035 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1036 break; 1037 case RTW89_CHANNEL_WIDTH_80: 1038 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1039 phy_idx); 1040 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1041 phy_idx); 1042 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1043 pri_ch, 1044 phy_idx); 1045 break; 1046 default: 1047 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1048 pri_ch); 1049 } 1050 1051 if (phy_idx == RTW89_PHY_0) { 1052 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1053 if (!rtwdev->dbcc_en) 1054 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1055 } else { 1056 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1057 } 1058 } 1059 1060 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1061 { 1062 if (central_ch == 153) { 1063 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1064 0x210); 1065 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1066 0x210); 1067 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1068 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1069 B_P0_NBIIDX_NOTCH_EN, 0x1); 1070 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1071 B_P1_NBIIDX_NOTCH_EN, 0x1); 1072 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1073 0x1); 1074 } else if (central_ch == 151) { 1075 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1076 0x210); 1077 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1078 0x210); 1079 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1080 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1081 B_P0_NBIIDX_NOTCH_EN, 0x1); 1082 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1083 B_P1_NBIIDX_NOTCH_EN, 0x1); 1084 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1085 0x1); 1086 } else if (central_ch == 155) { 1087 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1088 0x2d0); 1089 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1090 0x2d0); 1091 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1092 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1093 B_P0_NBIIDX_NOTCH_EN, 0x1); 1094 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1095 B_P1_NBIIDX_NOTCH_EN, 0x1); 1096 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1097 0x1); 1098 } else { 1099 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1100 B_P0_NBIIDX_NOTCH_EN, 0x0); 1101 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1102 B_P1_NBIIDX_NOTCH_EN, 0x0); 1103 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1104 0x0); 1105 } 1106 } 1107 1108 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1109 enum rtw89_phy_idx phy_idx) 1110 { 1111 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1112 phy_idx); 1113 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1114 phy_idx); 1115 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1116 phy_idx); 1117 } 1118 1119 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1120 enum rtw89_phy_idx phy_idx, bool en) 1121 { 1122 if (en) 1123 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1124 1, 1125 phy_idx); 1126 else 1127 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1128 0, 1129 phy_idx); 1130 } 1131 1132 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1133 enum rtw89_phy_idx phy_idx) 1134 { 1135 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1136 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1137 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1138 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1139 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1140 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1141 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1142 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1143 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1144 } 1145 1146 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1147 enum rtw89_phy_idx phy_idx) 1148 { 1149 u32 addr; 1150 1151 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1152 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1153 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1154 } 1155 1156 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1157 { 1158 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1159 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1160 1161 if (rtwdev->hal.cv <= CHIP_CCV) { 1162 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1163 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1164 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1165 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1166 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1167 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1168 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1169 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1170 } 1171 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1172 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1173 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1174 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1175 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1176 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1177 1178 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1179 } 1180 1181 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1182 enum rtw89_phy_idx phy_idx) 1183 { 1184 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1185 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1186 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1187 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1188 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1189 udelay(1); 1190 } 1191 1192 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1193 const struct rtw89_chan *chan, 1194 enum rtw89_phy_idx phy_idx) 1195 { 1196 bool cck_en = chan->channel <= 14; 1197 u8 pri_ch_idx = chan->pri_ch_idx; 1198 1199 if (cck_en) 1200 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1201 chan->primary_channel, 1202 chan->band_width); 1203 1204 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1205 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1206 if (cck_en) { 1207 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1208 } else { 1209 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1210 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1211 } 1212 rtw8852a_spur_elimination(rtwdev, chan->channel); 1213 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1214 chan->primary_channel); 1215 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1216 } 1217 1218 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1219 const struct rtw89_chan *chan, 1220 enum rtw89_mac_idx mac_idx, 1221 enum rtw89_phy_idx phy_idx) 1222 { 1223 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1224 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1225 } 1226 1227 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1228 { 1229 if (en) 1230 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1231 else 1232 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1233 } 1234 1235 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1236 enum rtw89_rf_path path) 1237 { 1238 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1239 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1240 1241 if (en) { 1242 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1243 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1244 } else { 1245 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1246 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1247 } 1248 } 1249 1250 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1251 u8 phy_idx) 1252 { 1253 if (!rtwdev->dbcc_en) { 1254 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1255 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1256 } else { 1257 if (phy_idx == RTW89_PHY_0) 1258 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1259 else 1260 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1261 } 1262 } 1263 1264 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1265 { 1266 if (en) 1267 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1268 0x0); 1269 else 1270 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1271 0xf); 1272 } 1273 1274 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1275 struct rtw89_channel_help_params *p, 1276 const struct rtw89_chan *chan, 1277 enum rtw89_mac_idx mac_idx, 1278 enum rtw89_phy_idx phy_idx) 1279 { 1280 if (enter) { 1281 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1282 RTW89_SCH_TX_SEL_ALL); 1283 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1284 rtw8852a_dfs_en(rtwdev, false); 1285 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1286 rtw8852a_adc_en(rtwdev, false); 1287 fsleep(40); 1288 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1289 } else { 1290 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1291 rtw8852a_adc_en(rtwdev, true); 1292 rtw8852a_dfs_en(rtwdev, true); 1293 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1294 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1295 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1296 } 1297 } 1298 1299 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1300 { 1301 struct rtw89_efuse *efuse = &rtwdev->efuse; 1302 1303 switch (efuse->rfe_type) { 1304 case 11: 1305 case 12: 1306 case 17: 1307 case 18: 1308 case 51: 1309 case 53: 1310 rtwdev->fem.epa_2g = true; 1311 rtwdev->fem.elna_2g = true; 1312 fallthrough; 1313 case 9: 1314 case 10: 1315 case 15: 1316 case 16: 1317 rtwdev->fem.epa_5g = true; 1318 rtwdev->fem.elna_5g = true; 1319 break; 1320 default: 1321 break; 1322 } 1323 } 1324 1325 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1326 { 1327 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1328 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1329 1330 rtw8852a_rck(rtwdev); 1331 rtw8852a_dack(rtwdev); 1332 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1333 } 1334 1335 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1336 { 1337 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1338 1339 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1340 rtw8852a_iqk(rtwdev, phy_idx); 1341 rtw8852a_tssi(rtwdev, phy_idx); 1342 rtw8852a_dpk(rtwdev, phy_idx); 1343 } 1344 1345 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1346 enum rtw89_phy_idx phy_idx) 1347 { 1348 rtw8852a_tssi_scan(rtwdev, phy_idx); 1349 } 1350 1351 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1352 { 1353 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1354 } 1355 1356 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1357 { 1358 rtw8852a_dpk_track(rtwdev); 1359 rtw8852a_tssi_track(rtwdev); 1360 } 1361 1362 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1363 enum rtw89_phy_idx phy_idx, s16 ref) 1364 { 1365 s8 ofst_int = 0; 1366 u8 base_cw_0db = 0x27; 1367 u16 tssi_16dbm_cw = 0x12c; 1368 s16 pwr_s10_3 = 0; 1369 s16 rf_pwr_cw = 0; 1370 u16 bb_pwr_cw = 0; 1371 u32 pwr_cw = 0; 1372 u32 tssi_ofst_cw = 0; 1373 1374 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1375 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1376 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1377 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1378 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1379 1380 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1381 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1382 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1383 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1384 1385 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1386 } 1387 1388 static 1389 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1390 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1391 { 1392 s8 val_1t = 0; 1393 s8 val_2t = 0; 1394 u32 reg; 1395 1396 if (pw_ofst < -16 || pw_ofst > 15) { 1397 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1398 pw_ofst); 1399 return; 1400 } 1401 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1402 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1403 val_1t = pw_ofst; 1404 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1405 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1406 val_2t = max(val_1t - 3, -16); 1407 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1408 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1409 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1410 val_1t, val_2t); 1411 } 1412 1413 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1414 enum rtw89_phy_idx phy_idx) 1415 { 1416 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1417 const u32 mask = 0x7FFFFFF; 1418 const u8 ofst_ofdm = 0x4; 1419 const u8 ofst_cck = 0x8; 1420 s16 ref_ofdm = 0; 1421 s16 ref_cck = 0; 1422 u32 val; 1423 u8 i; 1424 1425 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1426 1427 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1428 GENMASK(27, 10), 0x0); 1429 1430 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1431 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1432 1433 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1434 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1435 phy_idx); 1436 1437 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1438 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1439 1440 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1441 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1442 phy_idx); 1443 } 1444 1445 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1446 const struct rtw89_chan *chan, 1447 enum rtw89_phy_idx phy_idx) 1448 { 1449 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1450 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1451 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1452 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1453 } 1454 1455 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1456 enum rtw89_phy_idx phy_idx) 1457 { 1458 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1459 } 1460 1461 static int 1462 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1463 { 1464 int ret; 1465 1466 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1467 if (ret) 1468 return ret; 1469 1470 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1471 if (ret) 1472 return ret; 1473 1474 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1475 if (ret) 1476 return ret; 1477 1478 return 0; 1479 } 1480 1481 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1482 { 1483 u8 i = 0; 1484 u32 addr, val; 1485 1486 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1487 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1488 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1489 rtw89_phy_write32(rtwdev, addr, val); 1490 } 1491 } 1492 1493 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1494 struct rtw8852a_bb_pmac_info *tx_info, 1495 enum rtw89_phy_idx idx) 1496 { 1497 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1498 if (tx_info->mode == CONT_TX) 1499 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1500 idx); 1501 else if (tx_info->mode == PKTS_TX) 1502 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1503 idx); 1504 } 1505 1506 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1507 struct rtw8852a_bb_pmac_info *tx_info, 1508 enum rtw89_phy_idx idx) 1509 { 1510 enum rtw8852a_pmac_mode mode = tx_info->mode; 1511 u32 pkt_cnt = tx_info->tx_cnt; 1512 u16 period = tx_info->period; 1513 1514 if (mode == CONT_TX && !tx_info->is_cck) { 1515 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1516 idx); 1517 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1518 } else if (mode == PKTS_TX) { 1519 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1520 idx); 1521 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1522 B_PMAC_TX_PRD_MSK, period, idx); 1523 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1524 pkt_cnt, idx); 1525 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1526 } 1527 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1528 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1529 } 1530 1531 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1532 struct rtw8852a_bb_pmac_info *tx_info, 1533 enum rtw89_phy_idx idx) 1534 { 1535 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1536 1537 if (!tx_info->en_pmac_tx) { 1538 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1539 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1540 if (chan->band_type == RTW89_BAND_2G) 1541 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1542 return; 1543 } 1544 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1545 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1546 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1547 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1548 idx); 1549 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1550 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1551 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1552 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1553 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1554 } 1555 1556 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1557 u16 tx_cnt, u16 period, u16 tx_time, 1558 enum rtw89_phy_idx idx) 1559 { 1560 struct rtw8852a_bb_pmac_info tx_info = {0}; 1561 1562 tx_info.en_pmac_tx = enable; 1563 tx_info.is_cck = 0; 1564 tx_info.mode = PKTS_TX; 1565 tx_info.tx_cnt = tx_cnt; 1566 tx_info.period = period; 1567 tx_info.tx_time = tx_time; 1568 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1569 } 1570 1571 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1572 enum rtw89_phy_idx idx) 1573 { 1574 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1575 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1576 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1577 } 1578 1579 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1580 { 1581 u32 rst_mask0 = 0; 1582 u32 rst_mask1 = 0; 1583 1584 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1585 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1586 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1587 if (!rtwdev->dbcc_en) { 1588 if (tx_path == RF_PATH_A) { 1589 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1590 B_TXPATH_SEL_MSK, 1); 1591 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1592 B_TXNSS_MAP_MSK, 0); 1593 } else if (tx_path == RF_PATH_B) { 1594 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1595 B_TXPATH_SEL_MSK, 2); 1596 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1597 B_TXNSS_MAP_MSK, 0); 1598 } else if (tx_path == RF_PATH_AB) { 1599 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1600 B_TXPATH_SEL_MSK, 3); 1601 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1602 B_TXNSS_MAP_MSK, 4); 1603 } else { 1604 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1605 } 1606 } else { 1607 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1608 1); 1609 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1610 RTW89_PHY_1); 1611 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1612 0); 1613 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1614 RTW89_PHY_1); 1615 } 1616 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1617 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1618 if (tx_path == RF_PATH_A) { 1619 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1620 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1621 } else { 1622 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1623 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1624 } 1625 } 1626 1627 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1628 enum rtw89_phy_idx idx, u8 mode) 1629 { 1630 if (mode != 0) 1631 return; 1632 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1633 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1634 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1635 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1636 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1637 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1638 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1639 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1640 } 1641 1642 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1643 enum rtw89_phy_idx phy_idx) 1644 { 1645 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl : 1646 &rtw8852a_btc_preagc_dis_defs_tbl); 1647 } 1648 1649 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1650 { 1651 if (rtwdev->is_tssi_mode[rf_path]) { 1652 u32 addr = 0x1c10 + (rf_path << 13); 1653 1654 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1655 } 1656 1657 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1658 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1659 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1660 1661 fsleep(200); 1662 1663 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1664 } 1665 1666 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1667 { 1668 struct rtw89_btc *btc = &rtwdev->btc; 1669 struct rtw89_btc_module *module = &btc->mdinfo; 1670 1671 module->rfe_type = rtwdev->efuse.rfe_type; 1672 module->cv = rtwdev->hal.cv; 1673 module->bt_solo = 0; 1674 module->switch_type = BTC_SWITCH_INTERNAL; 1675 1676 if (module->rfe_type > 0) 1677 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1678 else 1679 module->ant.num = 2; 1680 1681 module->ant.diversity = 0; 1682 module->ant.isolation = 10; 1683 1684 if (module->ant.num == 3) { 1685 module->ant.type = BTC_ANT_DEDICATED; 1686 module->bt_pos = BTC_BT_ALONE; 1687 } else { 1688 module->ant.type = BTC_ANT_SHARED; 1689 module->bt_pos = BTC_BT_BTG; 1690 } 1691 } 1692 1693 static 1694 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1695 { 1696 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1697 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1698 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1699 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1700 } 1701 1702 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1703 enum rtw89_phy_idx phy_idx) 1704 { 1705 if (en) { 1706 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1707 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1708 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1709 } else { 1710 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1711 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1712 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1713 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1714 } 1715 } 1716 1717 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1718 { 1719 struct rtw89_btc *btc = &rtwdev->btc; 1720 struct rtw89_btc_module *module = &btc->mdinfo; 1721 const struct rtw89_chip_info *chip = rtwdev->chip; 1722 const struct rtw89_mac_ax_coex coex_params = { 1723 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1724 .direction = RTW89_MAC_AX_COEX_INNER, 1725 }; 1726 1727 /* PTA init */ 1728 rtw89_mac_coex_init(rtwdev, &coex_params); 1729 1730 /* set WL Tx response = Hi-Pri */ 1731 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1732 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1733 1734 /* set rf gnt debug off */ 1735 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1736 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1737 1738 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1739 if (module->ant.type == BTC_ANT_SHARED) { 1740 rtw8852a_set_trx_mask(rtwdev, 1741 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1742 rtw8852a_set_trx_mask(rtwdev, 1743 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1744 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1745 rtw8852a_set_trx_mask(rtwdev, 1746 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1747 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1748 rtw8852a_set_trx_mask(rtwdev, 1749 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1750 rtw8852a_set_trx_mask(rtwdev, 1751 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1752 } 1753 1754 /* set PTA break table */ 1755 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1756 1757 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1758 rtw89_write32_set(rtwdev, 1759 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1760 btc->cx.wl.status.map.init_ok = true; 1761 } 1762 1763 static 1764 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1765 { 1766 u32 bitmap = 0; 1767 u32 reg = 0; 1768 1769 switch (map) { 1770 case BTC_PRI_MASK_TX_RESP: 1771 reg = R_BTC_BT_COEX_MSK_TABLE; 1772 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1773 break; 1774 case BTC_PRI_MASK_BEACON: 1775 reg = R_AX_WL_PRI_MSK; 1776 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1777 break; 1778 default: 1779 return; 1780 } 1781 1782 if (state) 1783 rtw89_write32_set(rtwdev, reg, bitmap); 1784 else 1785 rtw89_write32_clr(rtwdev, reg, bitmap); 1786 } 1787 1788 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1789 { 1790 return FIELD_GET(GENMASK(15, 0), ctrl); 1791 } 1792 1793 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1794 { 1795 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1796 } 1797 1798 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1799 { 1800 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1801 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1802 1803 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1804 } 1805 1806 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1807 { 1808 return FIELD_GET(GENMASK(31, 16), ctrl); 1809 } 1810 1811 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1812 { 1813 return cur & ~B_AX_TXAGC_BT_EN; 1814 } 1815 1816 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1817 { 1818 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1819 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1820 1821 return ov | iv | B_AX_TXAGC_BT_EN; 1822 } 1823 1824 static void 1825 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1826 { 1827 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1828 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1829 1830 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1831 #define __handle(_case) \ 1832 do { \ 1833 const u32 _reg = __btc_cr_ ## _case; \ 1834 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1835 u32 _cur, _wrt; \ 1836 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1837 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1838 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1839 break; \ 1840 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1841 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1842 _wrt = __do_clr(_val) ? \ 1843 __btc_ctrl_rst_ ## _case(_cur) : \ 1844 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1845 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1846 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1847 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1848 } while (0) 1849 1850 __handle(all_time); 1851 __handle(gnt_bt); 1852 1853 #undef __handle 1854 #undef __do_clr 1855 } 1856 1857 static 1858 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1859 { 1860 /* +6 for compensate offset */ 1861 return clamp_t(s8, val + 6, -100, 0) + 100; 1862 } 1863 1864 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1865 {255, 0, 0, 7}, /* 0 -> original */ 1866 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1867 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1868 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1869 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1870 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1871 {6, 1, 0, 7}, 1872 {13, 1, 0, 7}, 1873 {13, 1, 0, 7} 1874 }; 1875 1876 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1877 {255, 0, 0, 7}, /* 0 -> original */ 1878 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1879 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1880 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1881 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1882 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1883 {255, 1, 0, 7}, 1884 {255, 1, 0, 7}, 1885 {255, 1, 0, 7} 1886 }; 1887 1888 static const 1889 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1890 static const 1891 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1892 1893 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1894 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1895 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1896 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1897 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1898 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1899 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1900 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1901 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1902 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1903 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1904 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1905 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1906 }; 1907 1908 static 1909 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1910 { 1911 struct rtw89_btc *btc = &rtwdev->btc; 1912 const struct rtw89_btc_ver *ver = btc->ver; 1913 struct rtw89_btc_cx *cx = &btc->cx; 1914 u32 val; 1915 1916 if (ver->fcxbtcrpt != 1) 1917 return; 1918 1919 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1920 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1921 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1922 1923 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1924 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1925 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1926 1927 /* clock-gate off before reset counter*/ 1928 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1929 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1930 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1931 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1932 } 1933 1934 static 1935 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1936 { 1937 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1938 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1939 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1940 1941 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1942 if (state) 1943 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1944 RFREG_MASK, 0xa2d7c); 1945 else 1946 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1947 RFREG_MASK, 0xa2020); 1948 1949 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1950 } 1951 1952 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1953 { 1954 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 1955 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 1956 * To improve BT ACI in co-rx 1957 */ 1958 1959 switch (level) { 1960 case 0: /* default */ 1961 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1962 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1963 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1964 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1965 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1966 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1967 break; 1968 case 1: /* Fix LNA2=5 */ 1969 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1970 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1971 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 1972 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1973 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1974 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1975 break; 1976 } 1977 } 1978 1979 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 1980 { 1981 struct rtw89_btc *btc = &rtwdev->btc; 1982 1983 switch (level) { 1984 case 0: /* original */ 1985 default: 1986 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 1987 btc->dm.wl_lna2 = 0; 1988 break; 1989 case 1: /* for FDD free-run */ 1990 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 1991 btc->dm.wl_lna2 = 0; 1992 break; 1993 case 2: /* for BTG Co-Rx*/ 1994 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 1995 btc->dm.wl_lna2 = 1; 1996 break; 1997 } 1998 1999 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2000 } 2001 2002 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2003 struct rtw89_rx_phy_ppdu *phy_ppdu, 2004 struct ieee80211_rx_status *status) 2005 { 2006 u16 chan = phy_ppdu->chan_idx; 2007 u8 band; 2008 2009 if (chan == 0) 2010 return; 2011 2012 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2013 status->freq = ieee80211_channel_to_frequency(chan, band); 2014 status->band = band; 2015 } 2016 2017 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2018 struct rtw89_rx_phy_ppdu *phy_ppdu, 2019 struct ieee80211_rx_status *status) 2020 { 2021 u8 path; 2022 u8 *rx_power = phy_ppdu->rssi; 2023 2024 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2025 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2026 status->chains |= BIT(path); 2027 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2028 } 2029 if (phy_ppdu->valid) 2030 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2031 } 2032 2033 #ifdef CONFIG_PM 2034 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2035 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2036 .n_patterns = RTW89_MAX_PATTERN_NUM, 2037 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2038 .pattern_min_len = 1, 2039 }; 2040 #endif 2041 2042 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2043 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2044 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2045 .bb_preinit = NULL, 2046 .bb_reset = rtw8852a_bb_reset, 2047 .bb_sethw = rtw8852a_bb_sethw, 2048 .read_rf = rtw89_phy_read_rf, 2049 .write_rf = rtw89_phy_write_rf, 2050 .set_channel = rtw8852a_set_channel, 2051 .set_channel_help = rtw8852a_set_channel_help, 2052 .read_efuse = rtw8852a_read_efuse, 2053 .read_phycap = rtw8852a_read_phycap, 2054 .fem_setup = rtw8852a_fem_setup, 2055 .rfe_gpio = NULL, 2056 .rfk_init = rtw8852a_rfk_init, 2057 .rfk_channel = rtw8852a_rfk_channel, 2058 .rfk_band_changed = rtw8852a_rfk_band_changed, 2059 .rfk_scan = rtw8852a_rfk_scan, 2060 .rfk_track = rtw8852a_rfk_track, 2061 .power_trim = rtw8852a_power_trim, 2062 .set_txpwr = rtw8852a_set_txpwr, 2063 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2064 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2065 .get_thermal = rtw8852a_get_thermal, 2066 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx, 2067 .query_ppdu = rtw8852a_query_ppdu, 2068 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx, 2069 .cfg_txrx_path = NULL, 2070 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2071 .pwr_on_func = NULL, 2072 .pwr_off_func = NULL, 2073 .query_rxdesc = rtw89_core_query_rxdesc, 2074 .fill_txdesc = rtw89_core_fill_txdesc, 2075 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2076 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2077 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2078 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2079 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2080 .h2c_dctl_sec_cam = NULL, 2081 2082 .btc_set_rfe = rtw8852a_btc_set_rfe, 2083 .btc_init_cfg = rtw8852a_btc_init_cfg, 2084 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2085 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2086 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2087 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2088 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2089 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2090 .btc_set_policy = rtw89_btc_set_policy, 2091 }; 2092 2093 const struct rtw89_chip_info rtw8852a_chip_info = { 2094 .chip_id = RTL8852A, 2095 .chip_gen = RTW89_CHIP_AX, 2096 .ops = &rtw8852a_chip_ops, 2097 .mac_def = &rtw89_mac_gen_ax, 2098 .phy_def = &rtw89_phy_gen_ax, 2099 .fw_basename = RTW8852A_FW_BASENAME, 2100 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2101 .try_ce_fw = false, 2102 .bbmcu_nr = 0, 2103 .needed_fw_elms = 0, 2104 .fifo_size = 458752, 2105 .small_fifo_size = false, 2106 .dle_scc_rsvd_size = 0, 2107 .max_amsdu_limit = 3500, 2108 .dis_2g_40m_ul_ofdma = true, 2109 .rsvd_ple_ofst = 0x6f800, 2110 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2111 .dle_mem = rtw8852a_dle_mem_pcie, 2112 .wde_qempty_acq_grpnum = 16, 2113 .wde_qempty_mgq_grpsel = 16, 2114 .rf_base_addr = {0xc000, 0xd000}, 2115 .pwr_on_seq = pwr_on_seq_8852a, 2116 .pwr_off_seq = pwr_off_seq_8852a, 2117 .bb_table = &rtw89_8852a_phy_bb_table, 2118 .bb_gain_table = NULL, 2119 .rf_table = {&rtw89_8852a_phy_radioa_table, 2120 &rtw89_8852a_phy_radiob_table,}, 2121 .nctl_table = &rtw89_8852a_phy_nctl_table, 2122 .nctl_post_table = NULL, 2123 .dflt_parms = &rtw89_8852a_dflt_parms, 2124 .rfe_parms_conf = NULL, 2125 .txpwr_factor_rf = 2, 2126 .txpwr_factor_mac = 1, 2127 .dig_table = &rtw89_8852a_phy_dig_table, 2128 .dig_regs = &rtw8852a_dig_regs, 2129 .tssi_dbw_table = NULL, 2130 .support_chanctx_num = 1, 2131 .support_bands = BIT(NL80211_BAND_2GHZ) | 2132 BIT(NL80211_BAND_5GHZ), 2133 .support_bw160 = false, 2134 .support_unii4 = false, 2135 .ul_tb_waveform_ctrl = false, 2136 .ul_tb_pwr_diff = false, 2137 .hw_sec_hdr = false, 2138 .rf_path_num = 2, 2139 .tx_nss = 2, 2140 .rx_nss = 2, 2141 .acam_num = 128, 2142 .bcam_num = 10, 2143 .scam_num = 128, 2144 .bacam_num = 2, 2145 .bacam_dynamic_num = 4, 2146 .bacam_ver = RTW89_BACAM_V0, 2147 .ppdu_max_usr = 4, 2148 .sec_ctrl_efuse_size = 4, 2149 .physical_efuse_size = 1216, 2150 .logical_efuse_size = 1536, 2151 .limit_efuse_size = 1152, 2152 .dav_phy_efuse_size = 0, 2153 .dav_log_efuse_size = 0, 2154 .efuse_blocks = NULL, 2155 .phycap_addr = 0x580, 2156 .phycap_size = 128, 2157 .para_ver = 0x0, 2158 .wlcx_desired = 0x06000000, 2159 .btcx_desired = 0x7, 2160 .scbd = 0x1, 2161 .mailbox = 0x1, 2162 2163 .afh_guard_ch = 6, 2164 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2165 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2166 .rssi_tol = 2, 2167 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2168 .mon_reg = rtw89_btc_8852a_mon_reg, 2169 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2170 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2171 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2172 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2173 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2174 BIT(RTW89_PS_MODE_CLK_GATED) | 2175 BIT(RTW89_PS_MODE_PWR_GATED), 2176 .low_power_hci_modes = 0, 2177 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2178 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2179 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2180 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2181 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2182 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2183 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2184 .h2c_regs = rtw8852a_h2c_regs, 2185 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2186 .c2h_regs = rtw8852a_c2h_regs, 2187 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2188 .page_regs = &rtw8852a_page_regs, 2189 .cfo_src_fd = false, 2190 .cfo_hw_comp = false, 2191 .dcfo_comp = &rtw8852a_dcfo_comp, 2192 .dcfo_comp_sft = 10, 2193 .imr_info = &rtw8852a_imr_info, 2194 .imr_dmac_table = NULL, 2195 .imr_cmac_table = NULL, 2196 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2197 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2198 .bss_clr_map_reg = R_BSS_CLR_MAP, 2199 .dma_ch_mask = 0, 2200 .edcca_regs = &rtw8852a_edcca_regs, 2201 #ifdef CONFIG_PM 2202 .wowlan_stub = &rtw_wowlan_stub_8852a, 2203 #endif 2204 .xtal_info = &rtw8852a_xtal_info, 2205 }; 2206 EXPORT_SYMBOL(rtw8852a_chip_info); 2207 2208 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2209 MODULE_AUTHOR("Realtek Corporation"); 2210 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2211 MODULE_LICENSE("Dual BSD/GPL"); 2212