1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 #define RTW8852A_FW_FORMAT_MAX 0 16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17 #define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 55 &rtw89_mac_size.ple_qt5}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 59 &rtw89_mac_size.ple_qt_52a_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 69 {0x44AC, 0x00000000}, 70 {0x44B0, 0x00000000}, 71 {0x44B4, 0x00000000}, 72 {0x44B8, 0x00000000}, 73 {0x44BC, 0x00000000}, 74 {0x44C0, 0x00000000}, 75 {0x44C4, 0x00000000}, 76 {0x44C8, 0x00000000}, 77 {0x44CC, 0x00000000}, 78 {0x44D0, 0x00000000}, 79 {0x44D4, 0x00000000}, 80 {0x44D8, 0x00000000}, 81 {0x44DC, 0x00000000}, 82 {0x44E0, 0x00000000}, 83 {0x44E4, 0x00000000}, 84 {0x44E8, 0x00000000}, 85 {0x44EC, 0x00000000}, 86 {0x44F0, 0x00000000}, 87 {0x44F4, 0x00000000}, 88 {0x44F8, 0x00000000}, 89 {0x44FC, 0x00000000}, 90 {0x4500, 0x00000000}, 91 {0x4504, 0x00000000}, 92 {0x4508, 0x00000000}, 93 {0x450C, 0x00000000}, 94 {0x4510, 0x00000000}, 95 {0x4514, 0x00000000}, 96 {0x4518, 0x00000000}, 97 {0x451C, 0x00000000}, 98 {0x4520, 0x00000000}, 99 {0x4524, 0x00000000}, 100 {0x4528, 0x00000000}, 101 {0x452C, 0x00000000}, 102 {0x4530, 0x4E1F3E81}, 103 {0x4534, 0x00000000}, 104 {0x4538, 0x0000005A}, 105 {0x453C, 0x00000000}, 106 {0x4540, 0x00000000}, 107 {0x4544, 0x00000000}, 108 {0x4548, 0x00000000}, 109 {0x454C, 0x00000000}, 110 {0x4550, 0x00000000}, 111 {0x4554, 0x00000000}, 112 {0x4558, 0x00000000}, 113 {0x455C, 0x00000000}, 114 {0x4560, 0x4060001A}, 115 {0x4564, 0x40000000}, 116 {0x4568, 0x00000000}, 117 {0x456C, 0x00000000}, 118 {0x4570, 0x04000007}, 119 {0x4574, 0x0000DC87}, 120 {0x4578, 0x00000BAB}, 121 {0x457C, 0x03E00000}, 122 {0x4580, 0x00000048}, 123 {0x4584, 0x00000000}, 124 {0x4588, 0x000003E8}, 125 {0x458C, 0x30000000}, 126 {0x4590, 0x00000000}, 127 {0x4594, 0x10000000}, 128 {0x4598, 0x00000001}, 129 {0x459C, 0x00030000}, 130 {0x45A0, 0x01000000}, 131 {0x45A4, 0x03000200}, 132 {0x45A8, 0xC00001C0}, 133 {0x45AC, 0x78018000}, 134 {0x45B0, 0x80000000}, 135 {0x45B4, 0x01C80600}, 136 {0x45B8, 0x00000002}, 137 {0x4594, 0x10000000} 138 }; 139 140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 141 {0x4624, GENMASK(20, 14), 0x40}, 142 {0x46f8, GENMASK(20, 14), 0x40}, 143 {0x4674, GENMASK(20, 19), 0x2}, 144 {0x4748, GENMASK(20, 19), 0x2}, 145 {0x4650, GENMASK(14, 10), 0x18}, 146 {0x4724, GENMASK(14, 10), 0x18}, 147 {0x4688, GENMASK(1, 0), 0x3}, 148 {0x475c, GENMASK(1, 0), 0x3}, 149 }; 150 151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 152 153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 154 {0x4624, GENMASK(20, 14), 0x1a}, 155 {0x46f8, GENMASK(20, 14), 0x1a}, 156 {0x4674, GENMASK(20, 19), 0x1}, 157 {0x4748, GENMASK(20, 19), 0x1}, 158 {0x4650, GENMASK(14, 10), 0x12}, 159 {0x4724, GENMASK(14, 10), 0x12}, 160 {0x4688, GENMASK(1, 0), 0x0}, 161 {0x475c, GENMASK(1, 0), 0x0}, 162 }; 163 164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 165 166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 167 {0x00C6, 168 PWR_CV_MSK_B, 169 PWR_INTF_MSK_PCIE, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(6), BIT(6)}, 172 {0x1086, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_SDIO, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(0), 0}, 177 {0x1086, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_SDIO, 180 PWR_BASE_MAC, 181 PWR_CMD_POLL, BIT(1), BIT(1)}, 182 {0x0005, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 187 {0x0005, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(7), 0}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(2), 0}, 197 {0x0006, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(1), BIT(1)}, 202 {0x0006, 203 PWR_CV_MSK_ALL, 204 PWR_INTF_MSK_ALL, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(0), BIT(0)}, 207 {0x0005, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0005, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_POLL, BIT(0), 0}, 217 {0x106D, 218 PWR_CV_MSK_B | PWR_CV_MSK_C, 219 PWR_INTF_MSK_USB, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(6), 0}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), BIT(0)}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x0088, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(0), BIT(0)}, 237 {0x0088, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(0), 0}, 242 {0x0088, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(0), BIT(0)}, 247 {0x0083, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(6), 0}, 252 {0x0080, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(5), BIT(5)}, 257 {0x0024, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 262 {0x02A0, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(1), BIT(1)}, 267 {0x02A2, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 272 {0x0071, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_PCIE, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(4), 0}, 277 {0x0010, 278 PWR_CV_MSK_A, 279 PWR_INTF_MSK_PCIE, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(2), BIT(2)}, 282 {0x02A0, 283 PWR_CV_MSK_A, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 287 {0xFFFF, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 0, 291 PWR_CMD_END, 0, 0}, 292 }; 293 294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 295 {0x02F0, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, 0xFF, 0}, 300 {0x02F1, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, 0xFF, 0}, 305 {0x0006, 306 PWR_CV_MSK_ALL, 307 PWR_INTF_MSK_ALL, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(0), BIT(0)}, 310 {0x0002, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 315 {0x0082, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 320 {0x106D, 321 PWR_CV_MSK_B | PWR_CV_MSK_C, 322 PWR_INTF_MSK_USB, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(6), BIT(6)}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_ALL, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(1), BIT(1)}, 330 {0x0005, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_ALL, 333 PWR_BASE_MAC, 334 PWR_CMD_POLL, BIT(1), 0}, 335 {0x0091, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_PCIE, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(0), 0}, 340 {0x0005, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_PCIE, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(2), BIT(2)}, 345 {0x0007, 346 PWR_CV_MSK_ALL, 347 PWR_INTF_MSK_USB, 348 PWR_BASE_MAC, 349 PWR_CMD_WRITE, BIT(4), 0}, 350 {0x0007, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_SDIO, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 355 {0x0005, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 360 {0x0005, 361 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 362 PWR_CV_MSK_G, 363 PWR_INTF_MSK_USB, 364 PWR_BASE_MAC, 365 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 366 {0x1086, 367 PWR_CV_MSK_ALL, 368 PWR_INTF_MSK_SDIO, 369 PWR_BASE_MAC, 370 PWR_CMD_WRITE, BIT(0), BIT(0)}, 371 {0x1086, 372 PWR_CV_MSK_ALL, 373 PWR_INTF_MSK_SDIO, 374 PWR_BASE_MAC, 375 PWR_CMD_POLL, BIT(1), 0}, 376 {0xFFFF, 377 PWR_CV_MSK_ALL, 378 PWR_INTF_MSK_ALL, 379 0, 380 PWR_CMD_END, 0, 0}, 381 }; 382 383 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 384 rtw8852a_pwron, NULL 385 }; 386 387 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 388 rtw8852a_pwroff, NULL 389 }; 390 391 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 392 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 393 R_AX_H2CREG_DATA3 394 }; 395 396 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 397 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 398 R_AX_C2HREG_DATA3 399 }; 400 401 static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 402 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 403 }; 404 405 static const struct rtw89_page_regs rtw8852a_page_regs = { 406 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 407 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 408 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 409 .ach_page_info = R_AX_ACH0_PAGE_INFO, 410 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 411 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 412 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 413 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 414 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 415 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 416 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 417 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 418 }; 419 420 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 421 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 422 }; 423 424 static const struct rtw89_imr_info rtw8852a_imr_info = { 425 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 426 .wsec_imr_reg = R_AX_SEC_DEBUG, 427 .wsec_imr_set = B_AX_IMR_ERROR, 428 .mpdu_tx_imr_set = 0, 429 .mpdu_rx_imr_set = 0, 430 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 431 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 432 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 433 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 434 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 435 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 436 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 437 .wde_imr_clr = B_AX_WDE_IMR_CLR, 438 .wde_imr_set = B_AX_WDE_IMR_SET, 439 .ple_imr_clr = B_AX_PLE_IMR_CLR, 440 .ple_imr_set = B_AX_PLE_IMR_SET, 441 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 442 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 443 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 444 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 445 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 446 .other_disp_imr_set = 0, 447 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 448 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 449 .bbrpt_err_imr_set = 0, 450 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 451 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 452 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 453 .cdma_imr_0_reg = R_AX_DLE_CTRL, 454 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 455 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 456 .cdma_imr_1_reg = 0, 457 .cdma_imr_1_clr = 0, 458 .cdma_imr_1_set = 0, 459 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 460 .phy_intf_imr_clr = 0, 461 .phy_intf_imr_set = 0, 462 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 463 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 464 .rmac_imr_set = B_AX_RMAC_IMR_SET, 465 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 466 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 467 .tmac_imr_set = B_AX_TMAC_IMR_SET, 468 }; 469 470 static const struct rtw89_xtal_info rtw8852a_xtal_info = { 471 .xcap_reg = R_AX_XTAL_ON_CTRL0, 472 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK, 473 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK, 474 }; 475 476 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 477 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 478 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 479 }; 480 481 static const struct rtw89_rfkill_regs rtw8852a_rfkill_regs = { 482 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 483 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 484 0xf}, 485 .mode = {R_AX_GPIO_EXT_CTRL + 2, 486 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 487 0x0}, 488 }; 489 490 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 491 .seg0_pd_reg = R_SEG0R_PD, 492 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 493 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 494 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 495 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 496 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 497 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 498 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 499 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 500 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 501 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 502 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 503 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 504 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 505 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 506 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 507 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 508 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 509 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 510 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 511 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 512 }; 513 514 static const struct rtw89_edcca_regs rtw8852a_edcca_regs = { 515 .edcca_level = R_SEG0R_EDCCA_LVL, 516 .edcca_mask = B_EDCCA_LVL_MSK0, 517 .edcca_p_mask = B_EDCCA_LVL_MSK1, 518 .ppdu_level = R_SEG0R_EDCCA_LVL, 519 .ppdu_mask = B_EDCCA_LVL_MSK3, 520 .rpt_a = R_EDCCA_RPT_A, 521 .rpt_b = R_EDCCA_RPT_B, 522 .rpt_sel = R_EDCCA_RPT_SEL, 523 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 524 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 525 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 526 }; 527 528 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 529 struct rtw8852a_efuse *map) 530 { 531 ether_addr_copy(efuse->addr, map->e.mac_addr); 532 efuse->rfe_type = map->rfe_type; 533 efuse->xtal_cap = map->xtal_k; 534 } 535 536 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 537 struct rtw8852a_efuse *map) 538 { 539 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 540 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 541 u8 i, j; 542 543 tssi->thermal[RF_PATH_A] = map->path_a_therm; 544 tssi->thermal[RF_PATH_B] = map->path_b_therm; 545 546 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 547 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 548 sizeof(ofst[i]->cck_tssi)); 549 550 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 551 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 552 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 553 i, j, tssi->tssi_cck[i][j]); 554 555 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 556 sizeof(ofst[i]->bw40_tssi)); 557 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 558 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 559 560 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 561 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 562 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 563 i, j, tssi->tssi_mcs[i][j]); 564 } 565 } 566 567 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 568 enum rtw89_efuse_block block) 569 { 570 struct rtw89_efuse *efuse = &rtwdev->efuse; 571 struct rtw8852a_efuse *map; 572 573 map = (struct rtw8852a_efuse *)log_map; 574 575 efuse->country_code[0] = map->country_code[0]; 576 efuse->country_code[1] = map->country_code[1]; 577 rtw8852a_efuse_parsing_tssi(rtwdev, map); 578 579 switch (rtwdev->hci.type) { 580 case RTW89_HCI_TYPE_PCIE: 581 rtw8852ae_efuse_parsing(efuse, map); 582 break; 583 default: 584 return -ENOTSUPP; 585 } 586 587 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 588 589 return 0; 590 } 591 592 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 593 { 594 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 595 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 596 u32 addr = rtwdev->chip->phycap_addr; 597 bool pg = false; 598 u32 ofst; 599 u8 i, j; 600 601 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 602 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 603 /* addrs are in decreasing order */ 604 ofst = tssi_trim_addr[i] - addr - j; 605 tssi->tssi_trim[i][j] = phycap_map[ofst]; 606 607 if (phycap_map[ofst] != 0xff) 608 pg = true; 609 } 610 } 611 612 if (!pg) { 613 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 614 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 615 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 616 } 617 618 for (i = 0; i < RF_PATH_NUM_8852A; i++) 619 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 620 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 621 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 622 i, j, tssi->tssi_trim[i][j], 623 tssi_trim_addr[i] - j); 624 } 625 626 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 627 u8 *phycap_map) 628 { 629 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 630 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 631 u32 addr = rtwdev->chip->phycap_addr; 632 u8 i; 633 634 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 635 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 636 637 rtw89_debug(rtwdev, RTW89_DBG_RFK, 638 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 639 i, info->thermal_trim[i]); 640 641 if (info->thermal_trim[i] != 0xff) 642 info->pg_thermal_trim = true; 643 } 644 } 645 646 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 647 { 648 #define __thm_setting(raw) \ 649 ({ \ 650 u8 __v = (raw); \ 651 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 652 }) 653 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 654 u8 i, val; 655 656 if (!info->pg_thermal_trim) { 657 rtw89_debug(rtwdev, RTW89_DBG_RFK, 658 "[THERMAL][TRIM] no PG, do nothing\n"); 659 660 return; 661 } 662 663 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 664 val = __thm_setting(info->thermal_trim[i]); 665 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 666 667 rtw89_debug(rtwdev, RTW89_DBG_RFK, 668 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 669 i, val); 670 } 671 #undef __thm_setting 672 } 673 674 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 675 u8 *phycap_map) 676 { 677 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 678 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 679 u32 addr = rtwdev->chip->phycap_addr; 680 u8 i; 681 682 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 683 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 684 685 rtw89_debug(rtwdev, RTW89_DBG_RFK, 686 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 687 i, info->pa_bias_trim[i]); 688 689 if (info->pa_bias_trim[i] != 0xff) 690 info->pg_pa_bias_trim = true; 691 } 692 } 693 694 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 695 { 696 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 697 u8 pabias_2g, pabias_5g; 698 u8 i; 699 700 if (!info->pg_pa_bias_trim) { 701 rtw89_debug(rtwdev, RTW89_DBG_RFK, 702 "[PA_BIAS][TRIM] no PG, do nothing\n"); 703 704 return; 705 } 706 707 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 708 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 709 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 710 711 rtw89_debug(rtwdev, RTW89_DBG_RFK, 712 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 713 i, pabias_2g, pabias_5g); 714 715 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 716 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 717 } 718 } 719 720 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 721 { 722 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 723 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 724 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 725 726 return 0; 727 } 728 729 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 730 { 731 rtw8852a_thermal_trim(rtwdev); 732 rtw8852a_pa_bias_trim(rtwdev); 733 } 734 735 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 736 const struct rtw89_chan *chan, 737 u8 mac_idx) 738 { 739 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 740 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 741 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 742 u8 txsc20 = 0, txsc40 = 0; 743 744 switch (chan->band_width) { 745 case RTW89_CHANNEL_WIDTH_80: 746 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 747 RTW89_CHANNEL_WIDTH_40); 748 fallthrough; 749 case RTW89_CHANNEL_WIDTH_40: 750 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 751 RTW89_CHANNEL_WIDTH_20); 752 break; 753 default: 754 break; 755 } 756 757 switch (chan->band_width) { 758 case RTW89_CHANNEL_WIDTH_80: 759 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 760 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 761 break; 762 case RTW89_CHANNEL_WIDTH_40: 763 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 764 rtw89_write32(rtwdev, sub_carr, txsc20); 765 break; 766 case RTW89_CHANNEL_WIDTH_20: 767 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 768 rtw89_write32(rtwdev, sub_carr, 0); 769 break; 770 default: 771 break; 772 } 773 774 if (chan->channel > 14) 775 rtw89_write8_set(rtwdev, chk_rate, 776 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 777 else 778 rtw89_write8_clr(rtwdev, chk_rate, 779 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 780 } 781 782 static const u32 rtw8852a_sco_barker_threshold[14] = { 783 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 784 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 785 }; 786 787 static const u32 rtw8852a_sco_cck_threshold[14] = { 788 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 789 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 790 }; 791 792 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 793 u8 primary_ch, enum rtw89_bandwidth bw) 794 { 795 u8 ch_element; 796 797 if (bw == RTW89_CHANNEL_WIDTH_20) { 798 ch_element = central_ch - 1; 799 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 800 if (primary_ch == 1) 801 ch_element = central_ch - 1 + 2; 802 else 803 ch_element = central_ch - 1 - 2; 804 } else { 805 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 806 return -EINVAL; 807 } 808 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 809 rtw8852a_sco_barker_threshold[ch_element]); 810 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 811 rtw8852a_sco_cck_threshold[ch_element]); 812 813 return 0; 814 } 815 816 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 817 u8 path) 818 { 819 u32 val; 820 821 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 822 if (val == INV_RF_DATA) { 823 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 824 return; 825 } 826 val &= ~0x303ff; 827 val |= central_ch; 828 if (central_ch > 14) 829 val |= (BIT(16) | BIT(8)); 830 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 831 } 832 833 static u8 rtw8852a_sco_mapping(u8 central_ch) 834 { 835 if (central_ch == 1) 836 return 109; 837 else if (central_ch >= 2 && central_ch <= 6) 838 return 108; 839 else if (central_ch >= 7 && central_ch <= 10) 840 return 107; 841 else if (central_ch >= 11 && central_ch <= 14) 842 return 106; 843 else if (central_ch == 36 || central_ch == 38) 844 return 51; 845 else if (central_ch >= 40 && central_ch <= 58) 846 return 50; 847 else if (central_ch >= 60 && central_ch <= 64) 848 return 49; 849 else if (central_ch == 100 || central_ch == 102) 850 return 48; 851 else if (central_ch >= 104 && central_ch <= 126) 852 return 47; 853 else if (central_ch >= 128 && central_ch <= 151) 854 return 46; 855 else if (central_ch >= 153 && central_ch <= 177) 856 return 45; 857 else 858 return 0; 859 } 860 861 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 862 enum rtw89_phy_idx phy_idx) 863 { 864 u8 sco_comp; 865 bool is_2g = central_ch <= 14; 866 867 if (phy_idx == RTW89_PHY_0) { 868 /* Path A */ 869 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 870 if (is_2g) 871 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 872 B_PATH0_TIA_ERR_G1_SEL, 1, 873 phy_idx); 874 else 875 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 876 B_PATH0_TIA_ERR_G1_SEL, 0, 877 phy_idx); 878 879 /* Path B */ 880 if (!rtwdev->dbcc_en) { 881 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 882 if (is_2g) 883 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 884 B_P1_MODE_SEL, 885 1, phy_idx); 886 else 887 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 888 B_P1_MODE_SEL, 889 0, phy_idx); 890 } else { 891 if (is_2g) 892 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 893 B_2P4G_BAND_SEL); 894 else 895 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 896 B_2P4G_BAND_SEL); 897 } 898 /* SCO compensate FC setting */ 899 sco_comp = rtw8852a_sco_mapping(central_ch); 900 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 901 sco_comp, phy_idx); 902 } else { 903 /* Path B */ 904 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 905 if (is_2g) 906 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 907 B_P1_MODE_SEL, 908 1, phy_idx); 909 else 910 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 911 B_P1_MODE_SEL, 912 0, phy_idx); 913 /* SCO compensate FC setting */ 914 sco_comp = rtw8852a_sco_mapping(central_ch); 915 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 916 sco_comp, phy_idx); 917 } 918 919 /* Band edge */ 920 if (is_2g) 921 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 922 phy_idx); 923 else 924 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 925 phy_idx); 926 927 /* CCK parameters */ 928 if (central_ch == 14) { 929 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 930 0x3b13ff); 931 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 932 0x1c42de); 933 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 934 0xfdb0ad); 935 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 936 0xf60f6e); 937 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 938 0xfd8f92); 939 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 940 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 941 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 942 0xfff00a); 943 } else { 944 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 945 0x3d23ff); 946 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 947 0x29b354); 948 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 949 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 950 0xfdb053); 951 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 952 0xf86f9a); 953 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 954 0xfaef92); 955 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 956 0xfe5fcc); 957 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 958 0xffdff5); 959 } 960 } 961 962 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 963 { 964 u32 val = 0; 965 u32 adc_sel[2] = {0x12d0, 0x32d0}; 966 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 967 968 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 969 if (val == INV_RF_DATA) { 970 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 971 return; 972 } 973 val &= ~(BIT(11) | BIT(10)); 974 switch (bw) { 975 case RTW89_CHANNEL_WIDTH_5: 976 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 977 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 978 val |= (BIT(11) | BIT(10)); 979 break; 980 case RTW89_CHANNEL_WIDTH_10: 981 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 982 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 983 val |= (BIT(11) | BIT(10)); 984 break; 985 case RTW89_CHANNEL_WIDTH_20: 986 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 987 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 988 val |= (BIT(11) | BIT(10)); 989 break; 990 case RTW89_CHANNEL_WIDTH_40: 991 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 992 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 993 val |= BIT(11); 994 break; 995 case RTW89_CHANNEL_WIDTH_80: 996 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 997 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 998 val |= BIT(10); 999 break; 1000 default: 1001 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1002 } 1003 1004 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 1005 } 1006 1007 static void 1008 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1009 enum rtw89_phy_idx phy_idx) 1010 { 1011 /* Switch bandwidth */ 1012 switch (bw) { 1013 case RTW89_CHANNEL_WIDTH_5: 1014 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1015 phy_idx); 1016 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 1017 phy_idx); 1018 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1019 0x0, phy_idx); 1020 break; 1021 case RTW89_CHANNEL_WIDTH_10: 1022 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1023 phy_idx); 1024 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 1025 phy_idx); 1026 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1027 0x0, phy_idx); 1028 break; 1029 case RTW89_CHANNEL_WIDTH_20: 1030 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1031 phy_idx); 1032 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1033 phy_idx); 1034 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1035 0x0, phy_idx); 1036 break; 1037 case RTW89_CHANNEL_WIDTH_40: 1038 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1039 phy_idx); 1040 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1041 phy_idx); 1042 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1043 pri_ch, 1044 phy_idx); 1045 if (pri_ch == RTW89_SC_20_UPPER) 1046 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1047 else 1048 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1049 break; 1050 case RTW89_CHANNEL_WIDTH_80: 1051 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1052 phy_idx); 1053 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1054 phy_idx); 1055 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1056 pri_ch, 1057 phy_idx); 1058 break; 1059 default: 1060 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1061 pri_ch); 1062 } 1063 1064 if (phy_idx == RTW89_PHY_0) { 1065 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1066 if (!rtwdev->dbcc_en) 1067 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1068 } else { 1069 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1070 } 1071 } 1072 1073 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1074 { 1075 if (central_ch == 153) { 1076 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1077 0x210); 1078 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1079 0x210); 1080 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1081 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1082 B_P0_NBIIDX_NOTCH_EN, 0x1); 1083 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1084 B_P1_NBIIDX_NOTCH_EN, 0x1); 1085 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1086 0x1); 1087 } else if (central_ch == 151) { 1088 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1089 0x210); 1090 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1091 0x210); 1092 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1093 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1094 B_P0_NBIIDX_NOTCH_EN, 0x1); 1095 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1096 B_P1_NBIIDX_NOTCH_EN, 0x1); 1097 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1098 0x1); 1099 } else if (central_ch == 155) { 1100 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1101 0x2d0); 1102 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1103 0x2d0); 1104 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1105 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1106 B_P0_NBIIDX_NOTCH_EN, 0x1); 1107 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1108 B_P1_NBIIDX_NOTCH_EN, 0x1); 1109 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1110 0x1); 1111 } else { 1112 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1113 B_P0_NBIIDX_NOTCH_EN, 0x0); 1114 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1115 B_P1_NBIIDX_NOTCH_EN, 0x0); 1116 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1117 0x0); 1118 } 1119 } 1120 1121 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1122 enum rtw89_phy_idx phy_idx) 1123 { 1124 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1125 phy_idx); 1126 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1127 phy_idx); 1128 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1129 phy_idx); 1130 } 1131 1132 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1133 enum rtw89_phy_idx phy_idx, bool en) 1134 { 1135 if (en) 1136 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1137 1, 1138 phy_idx); 1139 else 1140 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1141 0, 1142 phy_idx); 1143 } 1144 1145 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1146 enum rtw89_phy_idx phy_idx) 1147 { 1148 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1149 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1150 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1151 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1152 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1153 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1154 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1155 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1156 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1157 } 1158 1159 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1160 enum rtw89_phy_idx phy_idx) 1161 { 1162 u32 addr; 1163 1164 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1165 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1166 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1167 } 1168 1169 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1170 { 1171 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1172 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1173 1174 if (rtwdev->hal.cv <= CHIP_CCV) { 1175 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1176 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1177 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1178 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1179 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1180 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1181 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1182 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1183 } 1184 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1185 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1186 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1187 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1188 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1189 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1190 1191 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1192 } 1193 1194 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1195 enum rtw89_phy_idx phy_idx) 1196 { 1197 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1198 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1199 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1200 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1201 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1202 udelay(1); 1203 } 1204 1205 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1206 const struct rtw89_chan *chan, 1207 enum rtw89_phy_idx phy_idx) 1208 { 1209 bool cck_en = chan->channel <= 14; 1210 u8 pri_ch_idx = chan->pri_ch_idx; 1211 1212 if (cck_en) 1213 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1214 chan->primary_channel, 1215 chan->band_width); 1216 1217 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1218 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1219 if (cck_en) { 1220 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1221 } else { 1222 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1223 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1224 } 1225 rtw8852a_spur_elimination(rtwdev, chan->channel); 1226 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1227 chan->primary_channel); 1228 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1229 } 1230 1231 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1232 const struct rtw89_chan *chan, 1233 enum rtw89_mac_idx mac_idx, 1234 enum rtw89_phy_idx phy_idx) 1235 { 1236 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1237 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1238 } 1239 1240 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1241 { 1242 if (en) 1243 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1244 else 1245 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1246 } 1247 1248 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1249 enum rtw89_rf_path path) 1250 { 1251 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1252 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1253 1254 if (en) { 1255 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1256 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1257 } else { 1258 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1259 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1260 } 1261 } 1262 1263 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1264 u8 phy_idx) 1265 { 1266 if (!rtwdev->dbcc_en) { 1267 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1268 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1269 } else { 1270 if (phy_idx == RTW89_PHY_0) 1271 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1272 else 1273 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1274 } 1275 } 1276 1277 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1278 { 1279 if (en) 1280 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1281 0x0); 1282 else 1283 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1284 0xf); 1285 } 1286 1287 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1288 struct rtw89_channel_help_params *p, 1289 const struct rtw89_chan *chan, 1290 enum rtw89_mac_idx mac_idx, 1291 enum rtw89_phy_idx phy_idx) 1292 { 1293 if (enter) { 1294 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1295 RTW89_SCH_TX_SEL_ALL); 1296 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1297 rtw8852a_dfs_en(rtwdev, false); 1298 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1299 rtw8852a_adc_en(rtwdev, false); 1300 fsleep(40); 1301 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1302 } else { 1303 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1304 rtw8852a_adc_en(rtwdev, true); 1305 rtw8852a_dfs_en(rtwdev, true); 1306 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1307 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1308 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1309 } 1310 } 1311 1312 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1313 { 1314 struct rtw89_efuse *efuse = &rtwdev->efuse; 1315 1316 switch (efuse->rfe_type) { 1317 case 11: 1318 case 12: 1319 case 17: 1320 case 18: 1321 case 51: 1322 case 53: 1323 rtwdev->fem.epa_2g = true; 1324 rtwdev->fem.elna_2g = true; 1325 fallthrough; 1326 case 9: 1327 case 10: 1328 case 15: 1329 case 16: 1330 rtwdev->fem.epa_5g = true; 1331 rtwdev->fem.elna_5g = true; 1332 break; 1333 default: 1334 break; 1335 } 1336 } 1337 1338 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1339 { 1340 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1341 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1342 1343 rtw8852a_rck(rtwdev); 1344 rtw8852a_dack(rtwdev); 1345 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1346 } 1347 1348 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 1349 { 1350 enum rtw89_phy_idx phy_idx = rtwvif->phy_idx; 1351 1352 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1353 rtw8852a_iqk(rtwdev, phy_idx); 1354 rtw8852a_tssi(rtwdev, phy_idx); 1355 rtw8852a_dpk(rtwdev, phy_idx); 1356 } 1357 1358 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1359 enum rtw89_phy_idx phy_idx) 1360 { 1361 rtw8852a_tssi_scan(rtwdev, phy_idx); 1362 } 1363 1364 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1365 bool start) 1366 { 1367 rtw8852a_wifi_scan_notify(rtwdev, start, rtwvif->phy_idx); 1368 } 1369 1370 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1371 { 1372 rtw8852a_dpk_track(rtwdev); 1373 rtw8852a_tssi_track(rtwdev); 1374 } 1375 1376 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1377 enum rtw89_phy_idx phy_idx, s16 ref) 1378 { 1379 s8 ofst_int = 0; 1380 u8 base_cw_0db = 0x27; 1381 u16 tssi_16dbm_cw = 0x12c; 1382 s16 pwr_s10_3 = 0; 1383 s16 rf_pwr_cw = 0; 1384 u16 bb_pwr_cw = 0; 1385 u32 pwr_cw = 0; 1386 u32 tssi_ofst_cw = 0; 1387 1388 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1389 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1390 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1391 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1392 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1393 1394 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1395 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1396 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1397 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1398 1399 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1400 } 1401 1402 static 1403 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1404 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1405 { 1406 s8 val_1t = 0; 1407 s8 val_2t = 0; 1408 u32 reg; 1409 1410 if (pw_ofst < -16 || pw_ofst > 15) { 1411 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1412 pw_ofst); 1413 return; 1414 } 1415 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1416 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1417 val_1t = pw_ofst; 1418 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1419 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1420 val_2t = max(val_1t - 3, -16); 1421 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1422 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1423 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1424 val_1t, val_2t); 1425 } 1426 1427 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1428 enum rtw89_phy_idx phy_idx) 1429 { 1430 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1431 const u32 mask = 0x7FFFFFF; 1432 const u8 ofst_ofdm = 0x4; 1433 const u8 ofst_cck = 0x8; 1434 s16 ref_ofdm = 0; 1435 s16 ref_cck = 0; 1436 u32 val; 1437 u8 i; 1438 1439 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1440 1441 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1442 GENMASK(27, 10), 0x0); 1443 1444 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1445 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1446 1447 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1448 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1449 phy_idx); 1450 1451 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1452 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1453 1454 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1455 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1456 phy_idx); 1457 } 1458 1459 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1460 const struct rtw89_chan *chan, 1461 enum rtw89_phy_idx phy_idx) 1462 { 1463 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1464 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1465 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1466 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1467 } 1468 1469 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1470 enum rtw89_phy_idx phy_idx) 1471 { 1472 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1473 } 1474 1475 static int 1476 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1477 { 1478 int ret; 1479 1480 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1481 if (ret) 1482 return ret; 1483 1484 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1485 if (ret) 1486 return ret; 1487 1488 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1489 if (ret) 1490 return ret; 1491 1492 return 0; 1493 } 1494 1495 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1496 { 1497 u8 i = 0; 1498 u32 addr, val; 1499 1500 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1501 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1502 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1503 rtw89_phy_write32(rtwdev, addr, val); 1504 } 1505 } 1506 1507 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1508 struct rtw8852a_bb_pmac_info *tx_info, 1509 enum rtw89_phy_idx idx) 1510 { 1511 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1512 if (tx_info->mode == CONT_TX) 1513 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1514 idx); 1515 else if (tx_info->mode == PKTS_TX) 1516 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1517 idx); 1518 } 1519 1520 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1521 struct rtw8852a_bb_pmac_info *tx_info, 1522 enum rtw89_phy_idx idx) 1523 { 1524 enum rtw8852a_pmac_mode mode = tx_info->mode; 1525 u32 pkt_cnt = tx_info->tx_cnt; 1526 u16 period = tx_info->period; 1527 1528 if (mode == CONT_TX && !tx_info->is_cck) { 1529 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1530 idx); 1531 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1532 } else if (mode == PKTS_TX) { 1533 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1534 idx); 1535 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1536 B_PMAC_TX_PRD_MSK, period, idx); 1537 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1538 pkt_cnt, idx); 1539 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1540 } 1541 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1542 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1543 } 1544 1545 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1546 struct rtw8852a_bb_pmac_info *tx_info, 1547 enum rtw89_phy_idx idx) 1548 { 1549 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 1550 1551 if (!tx_info->en_pmac_tx) { 1552 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1553 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1554 if (chan->band_type == RTW89_BAND_2G) 1555 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1556 return; 1557 } 1558 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1559 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1560 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1561 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1562 idx); 1563 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1564 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1565 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1566 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1567 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1568 } 1569 1570 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1571 u16 tx_cnt, u16 period, u16 tx_time, 1572 enum rtw89_phy_idx idx) 1573 { 1574 struct rtw8852a_bb_pmac_info tx_info = {0}; 1575 1576 tx_info.en_pmac_tx = enable; 1577 tx_info.is_cck = 0; 1578 tx_info.mode = PKTS_TX; 1579 tx_info.tx_cnt = tx_cnt; 1580 tx_info.period = period; 1581 tx_info.tx_time = tx_time; 1582 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1583 } 1584 1585 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1586 enum rtw89_phy_idx idx) 1587 { 1588 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1589 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1590 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1591 } 1592 1593 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1594 { 1595 u32 rst_mask0 = 0; 1596 u32 rst_mask1 = 0; 1597 1598 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1599 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1600 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1601 if (!rtwdev->dbcc_en) { 1602 if (tx_path == RF_PATH_A) { 1603 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1604 B_TXPATH_SEL_MSK, 1); 1605 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1606 B_TXNSS_MAP_MSK, 0); 1607 } else if (tx_path == RF_PATH_B) { 1608 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1609 B_TXPATH_SEL_MSK, 2); 1610 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1611 B_TXNSS_MAP_MSK, 0); 1612 } else if (tx_path == RF_PATH_AB) { 1613 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1614 B_TXPATH_SEL_MSK, 3); 1615 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1616 B_TXNSS_MAP_MSK, 4); 1617 } else { 1618 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1619 } 1620 } else { 1621 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1622 1); 1623 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1624 RTW89_PHY_1); 1625 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1626 0); 1627 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1628 RTW89_PHY_1); 1629 } 1630 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1631 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1632 if (tx_path == RF_PATH_A) { 1633 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1634 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1635 } else { 1636 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1637 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1638 } 1639 } 1640 1641 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1642 enum rtw89_phy_idx idx, u8 mode) 1643 { 1644 if (mode != 0) 1645 return; 1646 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1647 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1648 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1649 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1650 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1651 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1652 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1653 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1654 } 1655 1656 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1657 enum rtw89_phy_idx phy_idx) 1658 { 1659 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl : 1660 &rtw8852a_btc_preagc_dis_defs_tbl); 1661 } 1662 1663 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1664 { 1665 if (rtwdev->is_tssi_mode[rf_path]) { 1666 u32 addr = 0x1c10 + (rf_path << 13); 1667 1668 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1669 } 1670 1671 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1672 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1673 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1674 1675 fsleep(200); 1676 1677 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1678 } 1679 1680 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1681 { 1682 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 1683 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 1684 1685 if (ver->fcxinit == 7) { 1686 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 1687 md->md_v7.kt_ver = rtwdev->hal.cv; 1688 md->md_v7.bt_solo = 0; 1689 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 1690 1691 if (md->md_v7.rfe_type > 0) 1692 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 1693 else 1694 md->md_v7.ant.num = 2; 1695 1696 md->md_v7.ant.diversity = 0; 1697 md->md_v7.ant.isolation = 10; 1698 1699 if (md->md_v7.ant.num == 3) { 1700 md->md_v7.ant.type = BTC_ANT_DEDICATED; 1701 md->md_v7.bt_pos = BTC_BT_ALONE; 1702 } else { 1703 md->md_v7.ant.type = BTC_ANT_SHARED; 1704 md->md_v7.bt_pos = BTC_BT_BTG; 1705 } 1706 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 1707 rtwdev->btc.ant_type = md->md_v7.ant.type; 1708 } else { 1709 md->md.rfe_type = rtwdev->efuse.rfe_type; 1710 md->md.cv = rtwdev->hal.cv; 1711 md->md.bt_solo = 0; 1712 md->md.switch_type = BTC_SWITCH_INTERNAL; 1713 1714 if (md->md.rfe_type > 0) 1715 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 1716 else 1717 md->md.ant.num = 2; 1718 1719 md->md.ant.diversity = 0; 1720 md->md.ant.isolation = 10; 1721 1722 if (md->md.ant.num == 3) { 1723 md->md.ant.type = BTC_ANT_DEDICATED; 1724 md->md.bt_pos = BTC_BT_ALONE; 1725 } else { 1726 md->md.ant.type = BTC_ANT_SHARED; 1727 md->md.bt_pos = BTC_BT_BTG; 1728 } 1729 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 1730 rtwdev->btc.ant_type = md->md.ant.type; 1731 } 1732 } 1733 1734 static 1735 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1736 { 1737 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1738 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1739 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1740 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1741 } 1742 1743 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1744 enum rtw89_phy_idx phy_idx) 1745 { 1746 if (en) { 1747 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1748 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1749 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1750 } else { 1751 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1752 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1753 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1754 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1755 } 1756 } 1757 1758 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1759 { 1760 struct rtw89_btc *btc = &rtwdev->btc; 1761 const struct rtw89_chip_info *chip = rtwdev->chip; 1762 const struct rtw89_mac_ax_coex coex_params = { 1763 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1764 .direction = RTW89_MAC_AX_COEX_INNER, 1765 }; 1766 1767 /* PTA init */ 1768 rtw89_mac_coex_init(rtwdev, &coex_params); 1769 1770 /* set WL Tx response = Hi-Pri */ 1771 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1772 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1773 1774 /* set rf gnt debug off */ 1775 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1776 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1777 1778 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1779 if (btc->ant_type == BTC_ANT_SHARED) { 1780 rtw8852a_set_trx_mask(rtwdev, 1781 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1782 rtw8852a_set_trx_mask(rtwdev, 1783 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1784 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1785 rtw8852a_set_trx_mask(rtwdev, 1786 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1787 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1788 rtw8852a_set_trx_mask(rtwdev, 1789 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1790 rtw8852a_set_trx_mask(rtwdev, 1791 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1792 } 1793 1794 /* set PTA break table */ 1795 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1796 1797 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1798 rtw89_write32_set(rtwdev, 1799 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1800 btc->cx.wl.status.map.init_ok = true; 1801 } 1802 1803 static 1804 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1805 { 1806 u32 bitmap = 0; 1807 u32 reg = 0; 1808 1809 switch (map) { 1810 case BTC_PRI_MASK_TX_RESP: 1811 reg = R_BTC_BT_COEX_MSK_TABLE; 1812 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1813 break; 1814 case BTC_PRI_MASK_BEACON: 1815 reg = R_AX_WL_PRI_MSK; 1816 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1817 break; 1818 default: 1819 return; 1820 } 1821 1822 if (state) 1823 rtw89_write32_set(rtwdev, reg, bitmap); 1824 else 1825 rtw89_write32_clr(rtwdev, reg, bitmap); 1826 } 1827 1828 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1829 { 1830 return FIELD_GET(GENMASK(15, 0), ctrl); 1831 } 1832 1833 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1834 { 1835 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1836 } 1837 1838 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1839 { 1840 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1841 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1842 1843 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1844 } 1845 1846 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1847 { 1848 return FIELD_GET(GENMASK(31, 16), ctrl); 1849 } 1850 1851 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1852 { 1853 return cur & ~B_AX_TXAGC_BT_EN; 1854 } 1855 1856 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1857 { 1858 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1859 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1860 1861 return ov | iv | B_AX_TXAGC_BT_EN; 1862 } 1863 1864 static void 1865 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1866 { 1867 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1868 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1869 1870 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1871 #define __handle(_case) \ 1872 do { \ 1873 const u32 _reg = __btc_cr_ ## _case; \ 1874 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1875 u32 _cur, _wrt; \ 1876 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1877 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1878 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1879 break; \ 1880 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1881 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1882 _wrt = __do_clr(_val) ? \ 1883 __btc_ctrl_rst_ ## _case(_cur) : \ 1884 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1885 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1886 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1887 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1888 } while (0) 1889 1890 __handle(all_time); 1891 __handle(gnt_bt); 1892 1893 #undef __handle 1894 #undef __do_clr 1895 } 1896 1897 static 1898 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1899 { 1900 /* +6 for compensate offset */ 1901 return clamp_t(s8, val + 6, -100, 0) + 100; 1902 } 1903 1904 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1905 {255, 0, 0, 7}, /* 0 -> original */ 1906 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1907 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1908 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1909 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1910 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1911 {6, 1, 0, 7}, 1912 {13, 1, 0, 7}, 1913 {13, 1, 0, 7} 1914 }; 1915 1916 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1917 {255, 0, 0, 7}, /* 0 -> original */ 1918 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1919 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1920 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1921 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1922 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1923 {255, 1, 0, 7}, 1924 {255, 1, 0, 7}, 1925 {255, 1, 0, 7} 1926 }; 1927 1928 static const 1929 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1930 static const 1931 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1932 1933 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1934 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1935 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1936 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1937 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1938 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1939 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1940 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1941 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1942 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1943 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1944 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1945 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1946 }; 1947 1948 static 1949 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1950 { 1951 struct rtw89_btc *btc = &rtwdev->btc; 1952 const struct rtw89_btc_ver *ver = btc->ver; 1953 struct rtw89_btc_cx *cx = &btc->cx; 1954 u32 val; 1955 1956 if (ver->fcxbtcrpt != 1) 1957 return; 1958 1959 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1960 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1961 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1962 1963 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1964 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1965 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1966 1967 /* clock-gate off before reset counter*/ 1968 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1969 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1970 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1971 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1972 } 1973 1974 static 1975 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1976 { 1977 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1978 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1979 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1980 1981 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1982 if (state) 1983 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1984 RFREG_MASK, 0xa2d7c); 1985 else 1986 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1987 RFREG_MASK, 0xa2020); 1988 1989 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1990 } 1991 1992 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1993 { 1994 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 1995 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 1996 * To improve BT ACI in co-rx 1997 */ 1998 1999 switch (level) { 2000 case 0: /* default */ 2001 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2002 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2003 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2004 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2005 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2006 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2007 break; 2008 case 1: /* Fix LNA2=5 */ 2009 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2010 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2011 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2012 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2013 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2014 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2015 break; 2016 } 2017 } 2018 2019 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2020 { 2021 struct rtw89_btc *btc = &rtwdev->btc; 2022 2023 switch (level) { 2024 case 0: /* original */ 2025 default: 2026 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2027 btc->dm.wl_lna2 = 0; 2028 break; 2029 case 1: /* for FDD free-run */ 2030 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2031 btc->dm.wl_lna2 = 0; 2032 break; 2033 case 2: /* for BTG Co-Rx*/ 2034 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2035 btc->dm.wl_lna2 = 1; 2036 break; 2037 } 2038 2039 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2040 } 2041 2042 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2043 struct rtw89_rx_phy_ppdu *phy_ppdu, 2044 struct ieee80211_rx_status *status) 2045 { 2046 u16 chan = phy_ppdu->chan_idx; 2047 u8 band; 2048 2049 if (chan == 0) 2050 return; 2051 2052 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2053 status->freq = ieee80211_channel_to_frequency(chan, band); 2054 status->band = band; 2055 } 2056 2057 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2058 struct rtw89_rx_phy_ppdu *phy_ppdu, 2059 struct ieee80211_rx_status *status) 2060 { 2061 u8 path; 2062 u8 *rx_power = phy_ppdu->rssi; 2063 2064 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2065 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2066 status->chains |= BIT(path); 2067 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2068 } 2069 if (phy_ppdu->valid) 2070 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2071 } 2072 2073 #ifdef CONFIG_PM 2074 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2075 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2076 .n_patterns = RTW89_MAX_PATTERN_NUM, 2077 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2078 .pattern_min_len = 1, 2079 }; 2080 #endif 2081 2082 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2083 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2084 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2085 .bb_preinit = NULL, 2086 .bb_postinit = NULL, 2087 .bb_reset = rtw8852a_bb_reset, 2088 .bb_sethw = rtw8852a_bb_sethw, 2089 .read_rf = rtw89_phy_read_rf, 2090 .write_rf = rtw89_phy_write_rf, 2091 .set_channel = rtw8852a_set_channel, 2092 .set_channel_help = rtw8852a_set_channel_help, 2093 .read_efuse = rtw8852a_read_efuse, 2094 .read_phycap = rtw8852a_read_phycap, 2095 .fem_setup = rtw8852a_fem_setup, 2096 .rfe_gpio = NULL, 2097 .rfk_hw_init = NULL, 2098 .rfk_init = rtw8852a_rfk_init, 2099 .rfk_init_late = NULL, 2100 .rfk_channel = rtw8852a_rfk_channel, 2101 .rfk_band_changed = rtw8852a_rfk_band_changed, 2102 .rfk_scan = rtw8852a_rfk_scan, 2103 .rfk_track = rtw8852a_rfk_track, 2104 .power_trim = rtw8852a_power_trim, 2105 .set_txpwr = rtw8852a_set_txpwr, 2106 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2107 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2108 .get_thermal = rtw8852a_get_thermal, 2109 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx, 2110 .query_ppdu = rtw8852a_query_ppdu, 2111 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx, 2112 .cfg_txrx_path = NULL, 2113 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2114 .pwr_on_func = NULL, 2115 .pwr_off_func = NULL, 2116 .query_rxdesc = rtw89_core_query_rxdesc, 2117 .fill_txdesc = rtw89_core_fill_txdesc, 2118 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2119 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2120 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2121 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2122 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2123 .h2c_dctl_sec_cam = NULL, 2124 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2125 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2126 .h2c_ampdu_cmac_tbl = NULL, 2127 .h2c_default_dmac_tbl = NULL, 2128 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2129 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2130 2131 .btc_set_rfe = rtw8852a_btc_set_rfe, 2132 .btc_init_cfg = rtw8852a_btc_init_cfg, 2133 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2134 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2135 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2136 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2137 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2138 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2139 .btc_set_policy = rtw89_btc_set_policy, 2140 }; 2141 2142 const struct rtw89_chip_info rtw8852a_chip_info = { 2143 .chip_id = RTL8852A, 2144 .chip_gen = RTW89_CHIP_AX, 2145 .ops = &rtw8852a_chip_ops, 2146 .mac_def = &rtw89_mac_gen_ax, 2147 .phy_def = &rtw89_phy_gen_ax, 2148 .fw_basename = RTW8852A_FW_BASENAME, 2149 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2150 .try_ce_fw = false, 2151 .bbmcu_nr = 0, 2152 .needed_fw_elms = 0, 2153 .fifo_size = 458752, 2154 .small_fifo_size = false, 2155 .dle_scc_rsvd_size = 0, 2156 .max_amsdu_limit = 3500, 2157 .dis_2g_40m_ul_ofdma = true, 2158 .rsvd_ple_ofst = 0x6f800, 2159 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2160 .dle_mem = rtw8852a_dle_mem_pcie, 2161 .wde_qempty_acq_grpnum = 16, 2162 .wde_qempty_mgq_grpsel = 16, 2163 .rf_base_addr = {0xc000, 0xd000}, 2164 .pwr_on_seq = pwr_on_seq_8852a, 2165 .pwr_off_seq = pwr_off_seq_8852a, 2166 .bb_table = &rtw89_8852a_phy_bb_table, 2167 .bb_gain_table = NULL, 2168 .rf_table = {&rtw89_8852a_phy_radioa_table, 2169 &rtw89_8852a_phy_radiob_table,}, 2170 .nctl_table = &rtw89_8852a_phy_nctl_table, 2171 .nctl_post_table = NULL, 2172 .dflt_parms = &rtw89_8852a_dflt_parms, 2173 .rfe_parms_conf = NULL, 2174 .txpwr_factor_rf = 2, 2175 .txpwr_factor_mac = 1, 2176 .dig_table = &rtw89_8852a_phy_dig_table, 2177 .dig_regs = &rtw8852a_dig_regs, 2178 .tssi_dbw_table = NULL, 2179 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2180 .support_chanctx_num = 1, 2181 .support_rnr = false, 2182 .support_bands = BIT(NL80211_BAND_2GHZ) | 2183 BIT(NL80211_BAND_5GHZ), 2184 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2185 BIT(NL80211_CHAN_WIDTH_40) | 2186 BIT(NL80211_CHAN_WIDTH_80), 2187 .support_unii4 = false, 2188 .ul_tb_waveform_ctrl = false, 2189 .ul_tb_pwr_diff = false, 2190 .hw_sec_hdr = false, 2191 .hw_mgmt_tx_encrypt = false, 2192 .rf_path_num = 2, 2193 .tx_nss = 2, 2194 .rx_nss = 2, 2195 .acam_num = 128, 2196 .bcam_num = 10, 2197 .scam_num = 128, 2198 .bacam_num = 2, 2199 .bacam_dynamic_num = 4, 2200 .bacam_ver = RTW89_BACAM_V0, 2201 .ppdu_max_usr = 4, 2202 .sec_ctrl_efuse_size = 4, 2203 .physical_efuse_size = 1216, 2204 .logical_efuse_size = 1536, 2205 .limit_efuse_size = 1152, 2206 .dav_phy_efuse_size = 0, 2207 .dav_log_efuse_size = 0, 2208 .efuse_blocks = NULL, 2209 .phycap_addr = 0x580, 2210 .phycap_size = 128, 2211 .para_ver = 0x0, 2212 .wlcx_desired = 0x06000000, 2213 .btcx_desired = 0x7, 2214 .scbd = 0x1, 2215 .mailbox = 0x1, 2216 2217 .afh_guard_ch = 6, 2218 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2219 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2220 .rssi_tol = 2, 2221 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2222 .mon_reg = rtw89_btc_8852a_mon_reg, 2223 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2224 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2225 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2226 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2227 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2228 BIT(RTW89_PS_MODE_CLK_GATED) | 2229 BIT(RTW89_PS_MODE_PWR_GATED), 2230 .low_power_hci_modes = 0, 2231 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2232 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2233 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2234 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2235 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2236 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2237 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2238 .h2c_regs = rtw8852a_h2c_regs, 2239 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2240 .c2h_regs = rtw8852a_c2h_regs, 2241 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2242 .page_regs = &rtw8852a_page_regs, 2243 .wow_reason_reg = rtw8852a_wow_wakeup_regs, 2244 .cfo_src_fd = false, 2245 .cfo_hw_comp = false, 2246 .dcfo_comp = &rtw8852a_dcfo_comp, 2247 .dcfo_comp_sft = 10, 2248 .imr_info = &rtw8852a_imr_info, 2249 .imr_dmac_table = NULL, 2250 .imr_cmac_table = NULL, 2251 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2252 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2253 .bss_clr_map_reg = R_BSS_CLR_MAP, 2254 .rfkill_init = &rtw8852a_rfkill_regs, 2255 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 2256 .dma_ch_mask = 0, 2257 .edcca_regs = &rtw8852a_edcca_regs, 2258 #ifdef CONFIG_PM 2259 .wowlan_stub = &rtw_wowlan_stub_8852a, 2260 #endif 2261 .xtal_info = &rtw8852a_xtal_info, 2262 }; 2263 EXPORT_SYMBOL(rtw8852a_chip_info); 2264 2265 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2266 MODULE_AUTHOR("Realtek Corporation"); 2267 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2268 MODULE_LICENSE("Dual BSD/GPL"); 2269