1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 #define RTW8852A_FW_FORMAT_MAX 0 16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17 #define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 55 &rtw89_mac_size.ple_qt5}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 59 &rtw89_mac_size.ple_qt_52a_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 69 {0x44AC, 0x00000000}, 70 {0x44B0, 0x00000000}, 71 {0x44B4, 0x00000000}, 72 {0x44B8, 0x00000000}, 73 {0x44BC, 0x00000000}, 74 {0x44C0, 0x00000000}, 75 {0x44C4, 0x00000000}, 76 {0x44C8, 0x00000000}, 77 {0x44CC, 0x00000000}, 78 {0x44D0, 0x00000000}, 79 {0x44D4, 0x00000000}, 80 {0x44D8, 0x00000000}, 81 {0x44DC, 0x00000000}, 82 {0x44E0, 0x00000000}, 83 {0x44E4, 0x00000000}, 84 {0x44E8, 0x00000000}, 85 {0x44EC, 0x00000000}, 86 {0x44F0, 0x00000000}, 87 {0x44F4, 0x00000000}, 88 {0x44F8, 0x00000000}, 89 {0x44FC, 0x00000000}, 90 {0x4500, 0x00000000}, 91 {0x4504, 0x00000000}, 92 {0x4508, 0x00000000}, 93 {0x450C, 0x00000000}, 94 {0x4510, 0x00000000}, 95 {0x4514, 0x00000000}, 96 {0x4518, 0x00000000}, 97 {0x451C, 0x00000000}, 98 {0x4520, 0x00000000}, 99 {0x4524, 0x00000000}, 100 {0x4528, 0x00000000}, 101 {0x452C, 0x00000000}, 102 {0x4530, 0x4E1F3E81}, 103 {0x4534, 0x00000000}, 104 {0x4538, 0x0000005A}, 105 {0x453C, 0x00000000}, 106 {0x4540, 0x00000000}, 107 {0x4544, 0x00000000}, 108 {0x4548, 0x00000000}, 109 {0x454C, 0x00000000}, 110 {0x4550, 0x00000000}, 111 {0x4554, 0x00000000}, 112 {0x4558, 0x00000000}, 113 {0x455C, 0x00000000}, 114 {0x4560, 0x4060001A}, 115 {0x4564, 0x40000000}, 116 {0x4568, 0x00000000}, 117 {0x456C, 0x00000000}, 118 {0x4570, 0x04000007}, 119 {0x4574, 0x0000DC87}, 120 {0x4578, 0x00000BAB}, 121 {0x457C, 0x03E00000}, 122 {0x4580, 0x00000048}, 123 {0x4584, 0x00000000}, 124 {0x4588, 0x000003E8}, 125 {0x458C, 0x30000000}, 126 {0x4590, 0x00000000}, 127 {0x4594, 0x10000000}, 128 {0x4598, 0x00000001}, 129 {0x459C, 0x00030000}, 130 {0x45A0, 0x01000000}, 131 {0x45A4, 0x03000200}, 132 {0x45A8, 0xC00001C0}, 133 {0x45AC, 0x78018000}, 134 {0x45B0, 0x80000000}, 135 {0x45B4, 0x01C80600}, 136 {0x45B8, 0x00000002}, 137 {0x4594, 0x10000000} 138 }; 139 140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 141 {0x4624, GENMASK(20, 14), 0x40}, 142 {0x46f8, GENMASK(20, 14), 0x40}, 143 {0x4674, GENMASK(20, 19), 0x2}, 144 {0x4748, GENMASK(20, 19), 0x2}, 145 {0x4650, GENMASK(14, 10), 0x18}, 146 {0x4724, GENMASK(14, 10), 0x18}, 147 {0x4688, GENMASK(1, 0), 0x3}, 148 {0x475c, GENMASK(1, 0), 0x3}, 149 }; 150 151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 152 153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 154 {0x4624, GENMASK(20, 14), 0x1a}, 155 {0x46f8, GENMASK(20, 14), 0x1a}, 156 {0x4674, GENMASK(20, 19), 0x1}, 157 {0x4748, GENMASK(20, 19), 0x1}, 158 {0x4650, GENMASK(14, 10), 0x12}, 159 {0x4724, GENMASK(14, 10), 0x12}, 160 {0x4688, GENMASK(1, 0), 0x0}, 161 {0x475c, GENMASK(1, 0), 0x0}, 162 }; 163 164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 165 166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 167 {0x00C6, 168 PWR_CV_MSK_B, 169 PWR_INTF_MSK_PCIE, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(6), BIT(6)}, 172 {0x1086, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_SDIO, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(0), 0}, 177 {0x1086, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_SDIO, 180 PWR_BASE_MAC, 181 PWR_CMD_POLL, BIT(1), BIT(1)}, 182 {0x0005, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 187 {0x0005, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(7), 0}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(2), 0}, 197 {0x0006, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(1), BIT(1)}, 202 {0x0006, 203 PWR_CV_MSK_ALL, 204 PWR_INTF_MSK_ALL, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(0), BIT(0)}, 207 {0x0005, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0005, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_POLL, BIT(0), 0}, 217 {0x106D, 218 PWR_CV_MSK_B | PWR_CV_MSK_C, 219 PWR_INTF_MSK_USB, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(6), 0}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), BIT(0)}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x0088, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(0), BIT(0)}, 237 {0x0088, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(0), 0}, 242 {0x0088, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(0), BIT(0)}, 247 {0x0083, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(6), 0}, 252 {0x0080, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(5), BIT(5)}, 257 {0x0024, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 262 {0x02A0, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(1), BIT(1)}, 267 {0x02A2, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 272 {0x0071, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_PCIE, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(4), 0}, 277 {0x0010, 278 PWR_CV_MSK_A, 279 PWR_INTF_MSK_PCIE, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(2), BIT(2)}, 282 {0x02A0, 283 PWR_CV_MSK_A, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 287 {0xFFFF, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 0, 291 PWR_CMD_END, 0, 0}, 292 }; 293 294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 295 {0x02F0, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, 0xFF, 0}, 300 {0x02F1, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, 0xFF, 0}, 305 {0x0006, 306 PWR_CV_MSK_ALL, 307 PWR_INTF_MSK_ALL, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(0), BIT(0)}, 310 {0x0002, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 315 {0x0082, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 320 {0x106D, 321 PWR_CV_MSK_B | PWR_CV_MSK_C, 322 PWR_INTF_MSK_USB, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(6), BIT(6)}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_ALL, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(1), BIT(1)}, 330 {0x0005, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_ALL, 333 PWR_BASE_MAC, 334 PWR_CMD_POLL, BIT(1), 0}, 335 {0x0091, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_PCIE, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(0), 0}, 340 {0x0092, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_PCIE, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(4), BIT(4)}, 345 {0x0005, 346 PWR_CV_MSK_ALL, 347 PWR_INTF_MSK_PCIE, 348 PWR_BASE_MAC, 349 PWR_CMD_WRITE, BIT(2), BIT(2)}, 350 {0x0007, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_USB, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(4), 0}, 355 {0x0007, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 360 {0x0005, 361 PWR_CV_MSK_ALL, 362 PWR_INTF_MSK_SDIO, 363 PWR_BASE_MAC, 364 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 365 {0x0005, 366 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 367 PWR_CV_MSK_G, 368 PWR_INTF_MSK_USB, 369 PWR_BASE_MAC, 370 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 371 {0x1086, 372 PWR_CV_MSK_ALL, 373 PWR_INTF_MSK_SDIO, 374 PWR_BASE_MAC, 375 PWR_CMD_WRITE, BIT(0), BIT(0)}, 376 {0x1086, 377 PWR_CV_MSK_ALL, 378 PWR_INTF_MSK_SDIO, 379 PWR_BASE_MAC, 380 PWR_CMD_POLL, BIT(1), 0}, 381 {0xFFFF, 382 PWR_CV_MSK_ALL, 383 PWR_INTF_MSK_ALL, 384 0, 385 PWR_CMD_END, 0, 0}, 386 }; 387 388 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 389 rtw8852a_pwron, NULL 390 }; 391 392 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 393 rtw8852a_pwroff, NULL 394 }; 395 396 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 397 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 398 R_AX_H2CREG_DATA3 399 }; 400 401 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 402 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 403 R_AX_C2HREG_DATA3 404 }; 405 406 static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 407 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 408 }; 409 410 static const struct rtw89_page_regs rtw8852a_page_regs = { 411 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 412 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 413 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 414 .ach_page_info = R_AX_ACH0_PAGE_INFO, 415 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 416 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 417 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 418 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 419 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 420 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 421 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 422 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 423 }; 424 425 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 426 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 427 }; 428 429 static const struct rtw89_imr_info rtw8852a_imr_info = { 430 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 431 .wsec_imr_reg = R_AX_SEC_DEBUG, 432 .wsec_imr_set = B_AX_IMR_ERROR, 433 .mpdu_tx_imr_set = 0, 434 .mpdu_rx_imr_set = 0, 435 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 436 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 437 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 438 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 439 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 440 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 441 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 442 .wde_imr_clr = B_AX_WDE_IMR_CLR, 443 .wde_imr_set = B_AX_WDE_IMR_SET, 444 .ple_imr_clr = B_AX_PLE_IMR_CLR, 445 .ple_imr_set = B_AX_PLE_IMR_SET, 446 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 447 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 448 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 449 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 450 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 451 .other_disp_imr_set = 0, 452 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 453 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 454 .bbrpt_err_imr_set = 0, 455 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 456 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 457 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 458 .cdma_imr_0_reg = R_AX_DLE_CTRL, 459 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 460 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 461 .cdma_imr_1_reg = 0, 462 .cdma_imr_1_clr = 0, 463 .cdma_imr_1_set = 0, 464 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 465 .phy_intf_imr_clr = 0, 466 .phy_intf_imr_set = 0, 467 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 468 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 469 .rmac_imr_set = B_AX_RMAC_IMR_SET, 470 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 471 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 472 .tmac_imr_set = B_AX_TMAC_IMR_SET, 473 }; 474 475 static const struct rtw89_xtal_info rtw8852a_xtal_info = { 476 .xcap_reg = R_AX_XTAL_ON_CTRL0, 477 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK, 478 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK, 479 }; 480 481 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 482 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 483 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 484 }; 485 486 static const struct rtw89_rfkill_regs rtw8852a_rfkill_regs = { 487 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 488 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 489 0xf}, 490 .mode = {R_AX_GPIO_EXT_CTRL + 2, 491 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 492 0x0}, 493 }; 494 495 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 496 .seg0_pd_reg = R_SEG0R_PD, 497 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 498 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 499 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 500 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 501 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 502 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 503 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 504 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 505 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 506 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 507 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 508 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 509 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 510 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 511 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 512 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 513 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 514 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 515 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 516 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 517 }; 518 519 static const struct rtw89_edcca_regs rtw8852a_edcca_regs = { 520 .edcca_level = R_SEG0R_EDCCA_LVL, 521 .edcca_mask = B_EDCCA_LVL_MSK0, 522 .edcca_p_mask = B_EDCCA_LVL_MSK1, 523 .ppdu_level = R_SEG0R_EDCCA_LVL, 524 .ppdu_mask = B_EDCCA_LVL_MSK3, 525 .rpt_a = R_EDCCA_RPT_A, 526 .rpt_b = R_EDCCA_RPT_B, 527 .rpt_sel = R_EDCCA_RPT_SEL, 528 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 529 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 530 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 531 }; 532 533 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 534 struct rtw8852a_efuse *map) 535 { 536 ether_addr_copy(efuse->addr, map->e.mac_addr); 537 efuse->rfe_type = map->rfe_type; 538 efuse->xtal_cap = map->xtal_k; 539 } 540 541 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 542 struct rtw8852a_efuse *map) 543 { 544 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 545 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 546 u8 i, j; 547 548 tssi->thermal[RF_PATH_A] = map->path_a_therm; 549 tssi->thermal[RF_PATH_B] = map->path_b_therm; 550 551 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 552 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 553 sizeof(ofst[i]->cck_tssi)); 554 555 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 556 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 557 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 558 i, j, tssi->tssi_cck[i][j]); 559 560 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 561 sizeof(ofst[i]->bw40_tssi)); 562 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 563 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 564 565 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 566 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 567 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 568 i, j, tssi->tssi_mcs[i][j]); 569 } 570 } 571 572 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 573 enum rtw89_efuse_block block) 574 { 575 struct rtw89_efuse *efuse = &rtwdev->efuse; 576 struct rtw8852a_efuse *map; 577 578 map = (struct rtw8852a_efuse *)log_map; 579 580 efuse->country_code[0] = map->country_code[0]; 581 efuse->country_code[1] = map->country_code[1]; 582 rtw8852a_efuse_parsing_tssi(rtwdev, map); 583 584 switch (rtwdev->hci.type) { 585 case RTW89_HCI_TYPE_PCIE: 586 rtw8852ae_efuse_parsing(efuse, map); 587 break; 588 default: 589 return -ENOTSUPP; 590 } 591 592 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 593 594 return 0; 595 } 596 597 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 598 { 599 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 600 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 601 u32 addr = rtwdev->chip->phycap_addr; 602 bool pg = false; 603 u32 ofst; 604 u8 i, j; 605 606 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 607 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 608 /* addrs are in decreasing order */ 609 ofst = tssi_trim_addr[i] - addr - j; 610 tssi->tssi_trim[i][j] = phycap_map[ofst]; 611 612 if (phycap_map[ofst] != 0xff) 613 pg = true; 614 } 615 } 616 617 if (!pg) { 618 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 619 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 620 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 621 } 622 623 for (i = 0; i < RF_PATH_NUM_8852A; i++) 624 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 625 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 626 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 627 i, j, tssi->tssi_trim[i][j], 628 tssi_trim_addr[i] - j); 629 } 630 631 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 632 u8 *phycap_map) 633 { 634 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 635 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 636 u32 addr = rtwdev->chip->phycap_addr; 637 u8 i; 638 639 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 640 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 641 642 rtw89_debug(rtwdev, RTW89_DBG_RFK, 643 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 644 i, info->thermal_trim[i]); 645 646 if (info->thermal_trim[i] != 0xff) 647 info->pg_thermal_trim = true; 648 } 649 } 650 651 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 652 { 653 #define __thm_setting(raw) \ 654 ({ \ 655 u8 __v = (raw); \ 656 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 657 }) 658 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 659 u8 i, val; 660 661 if (!info->pg_thermal_trim) { 662 rtw89_debug(rtwdev, RTW89_DBG_RFK, 663 "[THERMAL][TRIM] no PG, do nothing\n"); 664 665 return; 666 } 667 668 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 669 val = __thm_setting(info->thermal_trim[i]); 670 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 671 672 rtw89_debug(rtwdev, RTW89_DBG_RFK, 673 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 674 i, val); 675 } 676 #undef __thm_setting 677 } 678 679 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 680 u8 *phycap_map) 681 { 682 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 683 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 684 u32 addr = rtwdev->chip->phycap_addr; 685 u8 i; 686 687 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 688 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 689 690 rtw89_debug(rtwdev, RTW89_DBG_RFK, 691 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 692 i, info->pa_bias_trim[i]); 693 694 if (info->pa_bias_trim[i] != 0xff) 695 info->pg_pa_bias_trim = true; 696 } 697 } 698 699 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 700 { 701 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 702 u8 pabias_2g, pabias_5g; 703 u8 i; 704 705 if (!info->pg_pa_bias_trim) { 706 rtw89_debug(rtwdev, RTW89_DBG_RFK, 707 "[PA_BIAS][TRIM] no PG, do nothing\n"); 708 709 return; 710 } 711 712 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 713 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 714 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 715 716 rtw89_debug(rtwdev, RTW89_DBG_RFK, 717 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 718 i, pabias_2g, pabias_5g); 719 720 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 721 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 722 } 723 } 724 725 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 726 { 727 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 728 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 729 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 730 731 return 0; 732 } 733 734 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 735 { 736 rtw8852a_thermal_trim(rtwdev); 737 rtw8852a_pa_bias_trim(rtwdev); 738 } 739 740 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 741 const struct rtw89_chan *chan, 742 u8 mac_idx) 743 { 744 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 745 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 746 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 747 u8 txsc20 = 0, txsc40 = 0; 748 749 switch (chan->band_width) { 750 case RTW89_CHANNEL_WIDTH_80: 751 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 752 RTW89_CHANNEL_WIDTH_40); 753 fallthrough; 754 case RTW89_CHANNEL_WIDTH_40: 755 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 756 RTW89_CHANNEL_WIDTH_20); 757 break; 758 default: 759 break; 760 } 761 762 switch (chan->band_width) { 763 case RTW89_CHANNEL_WIDTH_80: 764 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 765 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 766 break; 767 case RTW89_CHANNEL_WIDTH_40: 768 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 769 rtw89_write32(rtwdev, sub_carr, txsc20); 770 break; 771 case RTW89_CHANNEL_WIDTH_20: 772 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 773 rtw89_write32(rtwdev, sub_carr, 0); 774 break; 775 default: 776 break; 777 } 778 779 if (chan->channel > 14) 780 rtw89_write8_set(rtwdev, chk_rate, 781 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 782 else 783 rtw89_write8_clr(rtwdev, chk_rate, 784 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 785 } 786 787 static const u32 rtw8852a_sco_barker_threshold[14] = { 788 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 789 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 790 }; 791 792 static const u32 rtw8852a_sco_cck_threshold[14] = { 793 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 794 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 795 }; 796 797 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 798 u8 primary_ch, enum rtw89_bandwidth bw) 799 { 800 u8 ch_element; 801 802 if (bw == RTW89_CHANNEL_WIDTH_20) { 803 ch_element = central_ch - 1; 804 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 805 if (primary_ch == 1) 806 ch_element = central_ch - 1 + 2; 807 else 808 ch_element = central_ch - 1 - 2; 809 } else { 810 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 811 return -EINVAL; 812 } 813 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 814 rtw8852a_sco_barker_threshold[ch_element]); 815 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 816 rtw8852a_sco_cck_threshold[ch_element]); 817 818 return 0; 819 } 820 821 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 822 u8 path) 823 { 824 u32 val; 825 826 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 827 if (val == INV_RF_DATA) { 828 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 829 return; 830 } 831 val &= ~0x303ff; 832 val |= central_ch; 833 if (central_ch > 14) 834 val |= (BIT(16) | BIT(8)); 835 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 836 } 837 838 static u8 rtw8852a_sco_mapping(u8 central_ch) 839 { 840 if (central_ch == 1) 841 return 109; 842 else if (central_ch >= 2 && central_ch <= 6) 843 return 108; 844 else if (central_ch >= 7 && central_ch <= 10) 845 return 107; 846 else if (central_ch >= 11 && central_ch <= 14) 847 return 106; 848 else if (central_ch == 36 || central_ch == 38) 849 return 51; 850 else if (central_ch >= 40 && central_ch <= 58) 851 return 50; 852 else if (central_ch >= 60 && central_ch <= 64) 853 return 49; 854 else if (central_ch == 100 || central_ch == 102) 855 return 48; 856 else if (central_ch >= 104 && central_ch <= 126) 857 return 47; 858 else if (central_ch >= 128 && central_ch <= 151) 859 return 46; 860 else if (central_ch >= 153 && central_ch <= 177) 861 return 45; 862 else 863 return 0; 864 } 865 866 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 867 enum rtw89_phy_idx phy_idx) 868 { 869 u8 sco_comp; 870 bool is_2g = central_ch <= 14; 871 872 if (phy_idx == RTW89_PHY_0) { 873 /* Path A */ 874 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 875 if (is_2g) 876 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 877 B_PATH0_TIA_ERR_G1_SEL, 1, 878 phy_idx); 879 else 880 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 881 B_PATH0_TIA_ERR_G1_SEL, 0, 882 phy_idx); 883 884 /* Path B */ 885 if (!rtwdev->dbcc_en) { 886 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 887 if (is_2g) 888 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 889 B_P1_MODE_SEL, 890 1, phy_idx); 891 else 892 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 893 B_P1_MODE_SEL, 894 0, phy_idx); 895 } else { 896 if (is_2g) 897 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 898 B_2P4G_BAND_SEL); 899 else 900 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 901 B_2P4G_BAND_SEL); 902 } 903 /* SCO compensate FC setting */ 904 sco_comp = rtw8852a_sco_mapping(central_ch); 905 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 906 sco_comp, phy_idx); 907 } else { 908 /* Path B */ 909 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 910 if (is_2g) 911 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 912 B_P1_MODE_SEL, 913 1, phy_idx); 914 else 915 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 916 B_P1_MODE_SEL, 917 0, phy_idx); 918 /* SCO compensate FC setting */ 919 sco_comp = rtw8852a_sco_mapping(central_ch); 920 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 921 sco_comp, phy_idx); 922 } 923 924 /* Band edge */ 925 if (is_2g) 926 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 927 phy_idx); 928 else 929 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 930 phy_idx); 931 932 /* CCK parameters */ 933 if (central_ch == 14) { 934 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 935 0x3b13ff); 936 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 937 0x1c42de); 938 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 939 0xfdb0ad); 940 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 941 0xf60f6e); 942 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 943 0xfd8f92); 944 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 945 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 946 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 947 0xfff00a); 948 } else { 949 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 950 0x3d23ff); 951 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 952 0x29b354); 953 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 954 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 955 0xfdb053); 956 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 957 0xf86f9a); 958 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 959 0xfaef92); 960 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 961 0xfe5fcc); 962 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 963 0xffdff5); 964 } 965 } 966 967 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 968 { 969 u32 val = 0; 970 u32 adc_sel[2] = {0x12d0, 0x32d0}; 971 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 972 973 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 974 if (val == INV_RF_DATA) { 975 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 976 return; 977 } 978 val &= ~(BIT(11) | BIT(10)); 979 switch (bw) { 980 case RTW89_CHANNEL_WIDTH_5: 981 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 982 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 983 val |= (BIT(11) | BIT(10)); 984 break; 985 case RTW89_CHANNEL_WIDTH_10: 986 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 987 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 988 val |= (BIT(11) | BIT(10)); 989 break; 990 case RTW89_CHANNEL_WIDTH_20: 991 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 992 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 993 val |= (BIT(11) | BIT(10)); 994 break; 995 case RTW89_CHANNEL_WIDTH_40: 996 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 997 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 998 val |= BIT(11); 999 break; 1000 case RTW89_CHANNEL_WIDTH_80: 1001 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1002 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1003 val |= BIT(10); 1004 break; 1005 default: 1006 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1007 } 1008 1009 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 1010 } 1011 1012 static void 1013 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1014 enum rtw89_phy_idx phy_idx) 1015 { 1016 /* Switch bandwidth */ 1017 switch (bw) { 1018 case RTW89_CHANNEL_WIDTH_5: 1019 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1020 phy_idx); 1021 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 1022 phy_idx); 1023 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1024 0x0, phy_idx); 1025 break; 1026 case RTW89_CHANNEL_WIDTH_10: 1027 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1028 phy_idx); 1029 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 1030 phy_idx); 1031 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1032 0x0, phy_idx); 1033 break; 1034 case RTW89_CHANNEL_WIDTH_20: 1035 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1036 phy_idx); 1037 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1038 phy_idx); 1039 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1040 0x0, phy_idx); 1041 break; 1042 case RTW89_CHANNEL_WIDTH_40: 1043 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1044 phy_idx); 1045 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1046 phy_idx); 1047 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1048 pri_ch, 1049 phy_idx); 1050 if (pri_ch == RTW89_SC_20_UPPER) 1051 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1052 else 1053 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1054 break; 1055 case RTW89_CHANNEL_WIDTH_80: 1056 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1057 phy_idx); 1058 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1059 phy_idx); 1060 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1061 pri_ch, 1062 phy_idx); 1063 break; 1064 default: 1065 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1066 pri_ch); 1067 } 1068 1069 if (phy_idx == RTW89_PHY_0) { 1070 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1071 if (!rtwdev->dbcc_en) 1072 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1073 } else { 1074 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1075 } 1076 } 1077 1078 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1079 { 1080 if (central_ch == 153) { 1081 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1082 0x210); 1083 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1084 0x210); 1085 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1086 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1087 B_P0_NBIIDX_NOTCH_EN, 0x1); 1088 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1089 B_P1_NBIIDX_NOTCH_EN, 0x1); 1090 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1091 0x1); 1092 } else if (central_ch == 151) { 1093 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1094 0x210); 1095 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1096 0x210); 1097 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1098 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1099 B_P0_NBIIDX_NOTCH_EN, 0x1); 1100 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1101 B_P1_NBIIDX_NOTCH_EN, 0x1); 1102 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1103 0x1); 1104 } else if (central_ch == 155) { 1105 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1106 0x2d0); 1107 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1108 0x2d0); 1109 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1110 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1111 B_P0_NBIIDX_NOTCH_EN, 0x1); 1112 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1113 B_P1_NBIIDX_NOTCH_EN, 0x1); 1114 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1115 0x1); 1116 } else { 1117 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1118 B_P0_NBIIDX_NOTCH_EN, 0x0); 1119 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1120 B_P1_NBIIDX_NOTCH_EN, 0x0); 1121 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1122 0x0); 1123 } 1124 } 1125 1126 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1127 enum rtw89_phy_idx phy_idx) 1128 { 1129 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1130 phy_idx); 1131 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1132 phy_idx); 1133 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1134 phy_idx); 1135 } 1136 1137 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1138 enum rtw89_phy_idx phy_idx, bool en) 1139 { 1140 if (en) 1141 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1142 1, 1143 phy_idx); 1144 else 1145 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1146 0, 1147 phy_idx); 1148 } 1149 1150 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1151 enum rtw89_phy_idx phy_idx) 1152 { 1153 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1154 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1155 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1156 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1157 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1158 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1159 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1160 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1161 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1162 } 1163 1164 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1165 enum rtw89_phy_idx phy_idx) 1166 { 1167 u32 addr; 1168 1169 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1170 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1171 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1172 } 1173 1174 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1175 { 1176 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1177 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1178 1179 if (rtwdev->hal.cv <= CHIP_CCV) { 1180 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1181 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1182 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1183 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1184 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1185 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1186 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1187 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1188 } 1189 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1190 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1191 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1192 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1193 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1194 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1195 1196 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1197 } 1198 1199 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1200 enum rtw89_phy_idx phy_idx) 1201 { 1202 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1203 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1204 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1205 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1206 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1207 udelay(1); 1208 } 1209 1210 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1211 const struct rtw89_chan *chan, 1212 enum rtw89_phy_idx phy_idx) 1213 { 1214 bool cck_en = chan->channel <= 14; 1215 u8 pri_ch_idx = chan->pri_ch_idx; 1216 1217 if (cck_en) 1218 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1219 chan->primary_channel, 1220 chan->band_width); 1221 1222 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1223 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1224 if (cck_en) { 1225 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1226 } else { 1227 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1228 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1229 } 1230 rtw8852a_spur_elimination(rtwdev, chan->channel); 1231 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1232 chan->primary_channel); 1233 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1234 } 1235 1236 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1237 const struct rtw89_chan *chan, 1238 enum rtw89_mac_idx mac_idx, 1239 enum rtw89_phy_idx phy_idx) 1240 { 1241 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1242 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1243 } 1244 1245 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1246 { 1247 if (en) 1248 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1249 else 1250 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1251 } 1252 1253 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1254 enum rtw89_rf_path path) 1255 { 1256 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1257 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1258 1259 if (en) { 1260 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1261 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1262 } else { 1263 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1264 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1265 } 1266 } 1267 1268 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1269 u8 phy_idx) 1270 { 1271 if (!rtwdev->dbcc_en) { 1272 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1273 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1274 } else { 1275 if (phy_idx == RTW89_PHY_0) 1276 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1277 else 1278 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1279 } 1280 } 1281 1282 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1283 { 1284 if (en) 1285 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1286 0x0); 1287 else 1288 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1289 0xf); 1290 } 1291 1292 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1293 struct rtw89_channel_help_params *p, 1294 const struct rtw89_chan *chan, 1295 enum rtw89_mac_idx mac_idx, 1296 enum rtw89_phy_idx phy_idx) 1297 { 1298 if (enter) { 1299 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1300 RTW89_SCH_TX_SEL_ALL); 1301 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1302 rtw8852a_dfs_en(rtwdev, false); 1303 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1304 rtw8852a_adc_en(rtwdev, false); 1305 fsleep(40); 1306 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1307 } else { 1308 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1309 rtw8852a_adc_en(rtwdev, true); 1310 rtw8852a_dfs_en(rtwdev, true); 1311 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1312 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1313 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1314 } 1315 } 1316 1317 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1318 { 1319 struct rtw89_efuse *efuse = &rtwdev->efuse; 1320 1321 switch (efuse->rfe_type) { 1322 case 11: 1323 case 12: 1324 case 17: 1325 case 18: 1326 case 51: 1327 case 53: 1328 rtwdev->fem.epa_2g = true; 1329 rtwdev->fem.elna_2g = true; 1330 fallthrough; 1331 case 9: 1332 case 10: 1333 case 15: 1334 case 16: 1335 rtwdev->fem.epa_5g = true; 1336 rtwdev->fem.elna_5g = true; 1337 break; 1338 default: 1339 break; 1340 } 1341 } 1342 1343 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1344 { 1345 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1346 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1347 1348 rtw8852a_rck(rtwdev); 1349 rtw8852a_dack(rtwdev, RTW89_CHANCTX_0); 1350 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true, RTW89_CHANCTX_0); 1351 } 1352 1353 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 1354 { 1355 enum rtw89_chanctx_idx chanctx_idx = rtwvif->chanctx_idx; 1356 enum rtw89_phy_idx phy_idx = rtwvif->phy_idx; 1357 1358 rtw8852a_rx_dck(rtwdev, phy_idx, true, chanctx_idx); 1359 rtw8852a_iqk(rtwdev, phy_idx, chanctx_idx); 1360 rtw8852a_tssi(rtwdev, phy_idx, chanctx_idx); 1361 rtw8852a_dpk(rtwdev, phy_idx, chanctx_idx); 1362 } 1363 1364 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1365 enum rtw89_phy_idx phy_idx, 1366 const struct rtw89_chan *chan) 1367 { 1368 rtw8852a_tssi_scan(rtwdev, phy_idx, chan); 1369 } 1370 1371 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1372 bool start) 1373 { 1374 rtw8852a_wifi_scan_notify(rtwdev, start, rtwvif->phy_idx); 1375 } 1376 1377 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1378 { 1379 rtw8852a_dpk_track(rtwdev); 1380 rtw8852a_tssi_track(rtwdev); 1381 } 1382 1383 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1384 enum rtw89_phy_idx phy_idx, s16 ref) 1385 { 1386 s8 ofst_int = 0; 1387 u8 base_cw_0db = 0x27; 1388 u16 tssi_16dbm_cw = 0x12c; 1389 s16 pwr_s10_3 = 0; 1390 s16 rf_pwr_cw = 0; 1391 u16 bb_pwr_cw = 0; 1392 u32 pwr_cw = 0; 1393 u32 tssi_ofst_cw = 0; 1394 1395 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1396 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1397 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1398 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1399 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1400 1401 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1402 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1403 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1404 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1405 1406 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1407 } 1408 1409 static 1410 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1411 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1412 { 1413 s8 val_1t = 0; 1414 s8 val_2t = 0; 1415 u32 reg; 1416 1417 if (pw_ofst < -16 || pw_ofst > 15) { 1418 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1419 pw_ofst); 1420 return; 1421 } 1422 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1423 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1424 val_1t = pw_ofst; 1425 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1426 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1427 val_2t = max(val_1t - 3, -16); 1428 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1429 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1430 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1431 val_1t, val_2t); 1432 } 1433 1434 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1435 enum rtw89_phy_idx phy_idx) 1436 { 1437 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1438 const u32 mask = 0x7FFFFFF; 1439 const u8 ofst_ofdm = 0x4; 1440 const u8 ofst_cck = 0x8; 1441 s16 ref_ofdm = 0; 1442 s16 ref_cck = 0; 1443 u32 val; 1444 u8 i; 1445 1446 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1447 1448 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1449 GENMASK(27, 10), 0x0); 1450 1451 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1452 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1453 1454 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1455 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1456 phy_idx); 1457 1458 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1459 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1460 1461 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1462 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1463 phy_idx); 1464 } 1465 1466 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1467 const struct rtw89_chan *chan, 1468 enum rtw89_phy_idx phy_idx) 1469 { 1470 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1471 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1472 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1473 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1474 } 1475 1476 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1477 enum rtw89_phy_idx phy_idx) 1478 { 1479 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1480 } 1481 1482 static int 1483 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1484 { 1485 int ret; 1486 1487 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1488 if (ret) 1489 return ret; 1490 1491 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1492 if (ret) 1493 return ret; 1494 1495 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1496 if (ret) 1497 return ret; 1498 1499 return 0; 1500 } 1501 1502 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1503 { 1504 u8 i = 0; 1505 u32 addr, val; 1506 1507 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1508 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1509 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1510 rtw89_phy_write32(rtwdev, addr, val); 1511 } 1512 } 1513 1514 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1515 struct rtw8852a_bb_pmac_info *tx_info, 1516 enum rtw89_phy_idx idx) 1517 { 1518 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1519 if (tx_info->mode == CONT_TX) 1520 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1521 idx); 1522 else if (tx_info->mode == PKTS_TX) 1523 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1524 idx); 1525 } 1526 1527 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1528 struct rtw8852a_bb_pmac_info *tx_info, 1529 enum rtw89_phy_idx idx) 1530 { 1531 enum rtw8852a_pmac_mode mode = tx_info->mode; 1532 u32 pkt_cnt = tx_info->tx_cnt; 1533 u16 period = tx_info->period; 1534 1535 if (mode == CONT_TX && !tx_info->is_cck) { 1536 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1537 idx); 1538 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1539 } else if (mode == PKTS_TX) { 1540 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1541 idx); 1542 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1543 B_PMAC_TX_PRD_MSK, period, idx); 1544 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1545 pkt_cnt, idx); 1546 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1547 } 1548 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1549 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1550 } 1551 1552 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1553 struct rtw8852a_bb_pmac_info *tx_info, 1554 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1555 { 1556 if (!tx_info->en_pmac_tx) { 1557 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1558 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1559 if (chan->band_type == RTW89_BAND_2G) 1560 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1561 return; 1562 } 1563 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1564 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1565 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1566 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1567 idx); 1568 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1569 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1570 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1571 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1572 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1573 } 1574 1575 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1576 u16 tx_cnt, u16 period, u16 tx_time, 1577 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1578 { 1579 struct rtw8852a_bb_pmac_info tx_info = {0}; 1580 1581 tx_info.en_pmac_tx = enable; 1582 tx_info.is_cck = 0; 1583 tx_info.mode = PKTS_TX; 1584 tx_info.tx_cnt = tx_cnt; 1585 tx_info.period = period; 1586 tx_info.tx_time = tx_time; 1587 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan); 1588 } 1589 1590 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1591 enum rtw89_phy_idx idx) 1592 { 1593 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1594 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1595 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1596 } 1597 1598 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1599 { 1600 u32 rst_mask0 = 0; 1601 u32 rst_mask1 = 0; 1602 1603 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1604 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1605 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1606 if (!rtwdev->dbcc_en) { 1607 if (tx_path == RF_PATH_A) { 1608 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1609 B_TXPATH_SEL_MSK, 1); 1610 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1611 B_TXNSS_MAP_MSK, 0); 1612 } else if (tx_path == RF_PATH_B) { 1613 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1614 B_TXPATH_SEL_MSK, 2); 1615 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1616 B_TXNSS_MAP_MSK, 0); 1617 } else if (tx_path == RF_PATH_AB) { 1618 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1619 B_TXPATH_SEL_MSK, 3); 1620 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1621 B_TXNSS_MAP_MSK, 4); 1622 } else { 1623 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1624 } 1625 } else { 1626 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1627 1); 1628 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1629 RTW89_PHY_1); 1630 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1631 0); 1632 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1633 RTW89_PHY_1); 1634 } 1635 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1636 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1637 if (tx_path == RF_PATH_A) { 1638 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1639 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1640 } else { 1641 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1642 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1643 } 1644 } 1645 1646 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1647 enum rtw89_phy_idx idx, u8 mode) 1648 { 1649 if (mode != 0) 1650 return; 1651 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1652 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1653 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1654 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1655 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1656 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1657 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1658 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1659 } 1660 1661 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1662 enum rtw89_phy_idx phy_idx) 1663 { 1664 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl : 1665 &rtw8852a_btc_preagc_dis_defs_tbl); 1666 } 1667 1668 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1669 { 1670 if (rtwdev->is_tssi_mode[rf_path]) { 1671 u32 addr = 0x1c10 + (rf_path << 13); 1672 1673 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1674 } 1675 1676 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1677 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1678 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1679 1680 fsleep(200); 1681 1682 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1683 } 1684 1685 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1686 { 1687 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 1688 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 1689 1690 if (ver->fcxinit == 7) { 1691 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 1692 md->md_v7.kt_ver = rtwdev->hal.cv; 1693 md->md_v7.bt_solo = 0; 1694 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 1695 1696 if (md->md_v7.rfe_type > 0) 1697 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 1698 else 1699 md->md_v7.ant.num = 2; 1700 1701 md->md_v7.ant.diversity = 0; 1702 md->md_v7.ant.isolation = 10; 1703 1704 if (md->md_v7.ant.num == 3) { 1705 md->md_v7.ant.type = BTC_ANT_DEDICATED; 1706 md->md_v7.bt_pos = BTC_BT_ALONE; 1707 } else { 1708 md->md_v7.ant.type = BTC_ANT_SHARED; 1709 md->md_v7.bt_pos = BTC_BT_BTG; 1710 } 1711 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 1712 rtwdev->btc.ant_type = md->md_v7.ant.type; 1713 } else { 1714 md->md.rfe_type = rtwdev->efuse.rfe_type; 1715 md->md.cv = rtwdev->hal.cv; 1716 md->md.bt_solo = 0; 1717 md->md.switch_type = BTC_SWITCH_INTERNAL; 1718 1719 if (md->md.rfe_type > 0) 1720 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 1721 else 1722 md->md.ant.num = 2; 1723 1724 md->md.ant.diversity = 0; 1725 md->md.ant.isolation = 10; 1726 1727 if (md->md.ant.num == 3) { 1728 md->md.ant.type = BTC_ANT_DEDICATED; 1729 md->md.bt_pos = BTC_BT_ALONE; 1730 } else { 1731 md->md.ant.type = BTC_ANT_SHARED; 1732 md->md.bt_pos = BTC_BT_BTG; 1733 } 1734 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 1735 rtwdev->btc.ant_type = md->md.ant.type; 1736 } 1737 } 1738 1739 static 1740 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1741 { 1742 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1743 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1744 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1745 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1746 } 1747 1748 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1749 enum rtw89_phy_idx phy_idx) 1750 { 1751 if (en) { 1752 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1753 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1754 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1755 } else { 1756 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1757 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1758 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1759 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1760 } 1761 } 1762 1763 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1764 { 1765 struct rtw89_btc *btc = &rtwdev->btc; 1766 const struct rtw89_chip_info *chip = rtwdev->chip; 1767 const struct rtw89_mac_ax_coex coex_params = { 1768 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1769 .direction = RTW89_MAC_AX_COEX_INNER, 1770 }; 1771 1772 /* PTA init */ 1773 rtw89_mac_coex_init(rtwdev, &coex_params); 1774 1775 /* set WL Tx response = Hi-Pri */ 1776 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1777 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1778 1779 /* set rf gnt debug off */ 1780 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1781 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1782 1783 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1784 if (btc->ant_type == BTC_ANT_SHARED) { 1785 rtw8852a_set_trx_mask(rtwdev, 1786 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1787 rtw8852a_set_trx_mask(rtwdev, 1788 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1789 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1790 rtw8852a_set_trx_mask(rtwdev, 1791 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1792 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1793 rtw8852a_set_trx_mask(rtwdev, 1794 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1795 rtw8852a_set_trx_mask(rtwdev, 1796 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1797 } 1798 1799 /* set PTA break table */ 1800 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1801 1802 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1803 rtw89_write32_set(rtwdev, 1804 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1805 btc->cx.wl.status.map.init_ok = true; 1806 } 1807 1808 static 1809 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1810 { 1811 u32 bitmap = 0; 1812 u32 reg = 0; 1813 1814 switch (map) { 1815 case BTC_PRI_MASK_TX_RESP: 1816 reg = R_BTC_BT_COEX_MSK_TABLE; 1817 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1818 break; 1819 case BTC_PRI_MASK_BEACON: 1820 reg = R_AX_WL_PRI_MSK; 1821 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1822 break; 1823 default: 1824 return; 1825 } 1826 1827 if (state) 1828 rtw89_write32_set(rtwdev, reg, bitmap); 1829 else 1830 rtw89_write32_clr(rtwdev, reg, bitmap); 1831 } 1832 1833 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1834 { 1835 return FIELD_GET(GENMASK(15, 0), ctrl); 1836 } 1837 1838 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1839 { 1840 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1841 } 1842 1843 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1844 { 1845 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1846 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1847 1848 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1849 } 1850 1851 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1852 { 1853 return FIELD_GET(GENMASK(31, 16), ctrl); 1854 } 1855 1856 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1857 { 1858 return cur & ~B_AX_TXAGC_BT_EN; 1859 } 1860 1861 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1862 { 1863 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1864 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1865 1866 return ov | iv | B_AX_TXAGC_BT_EN; 1867 } 1868 1869 static void 1870 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1871 { 1872 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1873 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1874 1875 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1876 #define __handle(_case) \ 1877 do { \ 1878 const u32 _reg = __btc_cr_ ## _case; \ 1879 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1880 u32 _cur, _wrt; \ 1881 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1882 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1883 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1884 break; \ 1885 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1886 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1887 _wrt = __do_clr(_val) ? \ 1888 __btc_ctrl_rst_ ## _case(_cur) : \ 1889 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1890 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1891 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1892 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1893 } while (0) 1894 1895 __handle(all_time); 1896 __handle(gnt_bt); 1897 1898 #undef __handle 1899 #undef __do_clr 1900 } 1901 1902 static 1903 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1904 { 1905 /* +6 for compensate offset */ 1906 return clamp_t(s8, val + 6, -100, 0) + 100; 1907 } 1908 1909 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1910 {255, 0, 0, 7}, /* 0 -> original */ 1911 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1912 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1913 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1914 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1915 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1916 {6, 1, 0, 7}, 1917 {13, 1, 0, 7}, 1918 {13, 1, 0, 7} 1919 }; 1920 1921 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1922 {255, 0, 0, 7}, /* 0 -> original */ 1923 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1924 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1925 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1926 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1927 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1928 {255, 1, 0, 7}, 1929 {255, 1, 0, 7}, 1930 {255, 1, 0, 7} 1931 }; 1932 1933 static const 1934 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1935 static const 1936 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1937 1938 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1939 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1940 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1941 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1942 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1943 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1944 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1945 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1946 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1947 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1948 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1949 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1950 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1951 }; 1952 1953 static 1954 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1955 { 1956 struct rtw89_btc *btc = &rtwdev->btc; 1957 const struct rtw89_btc_ver *ver = btc->ver; 1958 struct rtw89_btc_cx *cx = &btc->cx; 1959 u32 val; 1960 1961 if (ver->fcxbtcrpt != 1) 1962 return; 1963 1964 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1965 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1966 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1967 1968 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1969 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1970 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1971 1972 /* clock-gate off before reset counter*/ 1973 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1974 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1975 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1976 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1977 } 1978 1979 static 1980 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1981 { 1982 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1983 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1984 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1985 1986 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1987 if (state) 1988 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1989 RFREG_MASK, 0xa2d7c); 1990 else 1991 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1992 RFREG_MASK, 0xa2020); 1993 1994 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1995 } 1996 1997 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1998 { 1999 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2000 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2001 * To improve BT ACI in co-rx 2002 */ 2003 2004 switch (level) { 2005 case 0: /* default */ 2006 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2007 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2008 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2009 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2010 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2011 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2012 break; 2013 case 1: /* Fix LNA2=5 */ 2014 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2015 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2016 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2017 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2018 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2019 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2020 break; 2021 } 2022 } 2023 2024 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2025 { 2026 struct rtw89_btc *btc = &rtwdev->btc; 2027 2028 switch (level) { 2029 case 0: /* original */ 2030 default: 2031 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2032 btc->dm.wl_lna2 = 0; 2033 break; 2034 case 1: /* for FDD free-run */ 2035 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2036 btc->dm.wl_lna2 = 0; 2037 break; 2038 case 2: /* for BTG Co-Rx*/ 2039 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2040 btc->dm.wl_lna2 = 1; 2041 break; 2042 } 2043 2044 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2045 } 2046 2047 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2048 struct rtw89_rx_phy_ppdu *phy_ppdu, 2049 struct ieee80211_rx_status *status) 2050 { 2051 u16 chan = phy_ppdu->chan_idx; 2052 u8 band; 2053 2054 if (chan == 0) 2055 return; 2056 2057 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2058 status->freq = ieee80211_channel_to_frequency(chan, band); 2059 status->band = band; 2060 } 2061 2062 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2063 struct rtw89_rx_phy_ppdu *phy_ppdu, 2064 struct ieee80211_rx_status *status) 2065 { 2066 u8 path; 2067 u8 *rx_power = phy_ppdu->rssi; 2068 2069 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2070 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2071 status->chains |= BIT(path); 2072 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2073 } 2074 if (phy_ppdu->valid) 2075 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2076 } 2077 2078 #ifdef CONFIG_PM 2079 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2080 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2081 .n_patterns = RTW89_MAX_PATTERN_NUM, 2082 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2083 .pattern_min_len = 1, 2084 }; 2085 #endif 2086 2087 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2088 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2089 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2090 .bb_preinit = NULL, 2091 .bb_postinit = NULL, 2092 .bb_reset = rtw8852a_bb_reset, 2093 .bb_sethw = rtw8852a_bb_sethw, 2094 .read_rf = rtw89_phy_read_rf, 2095 .write_rf = rtw89_phy_write_rf, 2096 .set_channel = rtw8852a_set_channel, 2097 .set_channel_help = rtw8852a_set_channel_help, 2098 .read_efuse = rtw8852a_read_efuse, 2099 .read_phycap = rtw8852a_read_phycap, 2100 .fem_setup = rtw8852a_fem_setup, 2101 .rfe_gpio = NULL, 2102 .rfk_hw_init = NULL, 2103 .rfk_init = rtw8852a_rfk_init, 2104 .rfk_init_late = NULL, 2105 .rfk_channel = rtw8852a_rfk_channel, 2106 .rfk_band_changed = rtw8852a_rfk_band_changed, 2107 .rfk_scan = rtw8852a_rfk_scan, 2108 .rfk_track = rtw8852a_rfk_track, 2109 .power_trim = rtw8852a_power_trim, 2110 .set_txpwr = rtw8852a_set_txpwr, 2111 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2112 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2113 .get_thermal = rtw8852a_get_thermal, 2114 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx, 2115 .query_ppdu = rtw8852a_query_ppdu, 2116 .convert_rpl_to_rssi = NULL, 2117 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx, 2118 .cfg_txrx_path = NULL, 2119 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2120 .digital_pwr_comp = NULL, 2121 .pwr_on_func = NULL, 2122 .pwr_off_func = NULL, 2123 .query_rxdesc = rtw89_core_query_rxdesc, 2124 .fill_txdesc = rtw89_core_fill_txdesc, 2125 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2126 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2127 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2128 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2129 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2130 .h2c_dctl_sec_cam = NULL, 2131 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2132 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2133 .h2c_ampdu_cmac_tbl = NULL, 2134 .h2c_default_dmac_tbl = NULL, 2135 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2136 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2137 2138 .btc_set_rfe = rtw8852a_btc_set_rfe, 2139 .btc_init_cfg = rtw8852a_btc_init_cfg, 2140 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2141 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2142 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2143 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2144 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2145 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2146 .btc_set_policy = rtw89_btc_set_policy, 2147 }; 2148 2149 const struct rtw89_chip_info rtw8852a_chip_info = { 2150 .chip_id = RTL8852A, 2151 .chip_gen = RTW89_CHIP_AX, 2152 .ops = &rtw8852a_chip_ops, 2153 .mac_def = &rtw89_mac_gen_ax, 2154 .phy_def = &rtw89_phy_gen_ax, 2155 .fw_basename = RTW8852A_FW_BASENAME, 2156 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2157 .try_ce_fw = false, 2158 .bbmcu_nr = 0, 2159 .needed_fw_elms = 0, 2160 .fifo_size = 458752, 2161 .small_fifo_size = false, 2162 .dle_scc_rsvd_size = 0, 2163 .max_amsdu_limit = 3500, 2164 .dis_2g_40m_ul_ofdma = true, 2165 .rsvd_ple_ofst = 0x6f800, 2166 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2167 .dle_mem = rtw8852a_dle_mem_pcie, 2168 .wde_qempty_acq_grpnum = 16, 2169 .wde_qempty_mgq_grpsel = 16, 2170 .rf_base_addr = {0xc000, 0xd000}, 2171 .pwr_on_seq = pwr_on_seq_8852a, 2172 .pwr_off_seq = pwr_off_seq_8852a, 2173 .bb_table = &rtw89_8852a_phy_bb_table, 2174 .bb_gain_table = NULL, 2175 .rf_table = {&rtw89_8852a_phy_radioa_table, 2176 &rtw89_8852a_phy_radiob_table,}, 2177 .nctl_table = &rtw89_8852a_phy_nctl_table, 2178 .nctl_post_table = NULL, 2179 .dflt_parms = &rtw89_8852a_dflt_parms, 2180 .rfe_parms_conf = NULL, 2181 .txpwr_factor_rf = 2, 2182 .txpwr_factor_mac = 1, 2183 .dig_table = &rtw89_8852a_phy_dig_table, 2184 .dig_regs = &rtw8852a_dig_regs, 2185 .tssi_dbw_table = NULL, 2186 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2187 .support_link_num = 0, 2188 .support_chanctx_num = 1, 2189 .support_rnr = false, 2190 .support_bands = BIT(NL80211_BAND_2GHZ) | 2191 BIT(NL80211_BAND_5GHZ), 2192 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2193 BIT(NL80211_CHAN_WIDTH_40) | 2194 BIT(NL80211_CHAN_WIDTH_80), 2195 .support_unii4 = false, 2196 .ul_tb_waveform_ctrl = false, 2197 .ul_tb_pwr_diff = false, 2198 .hw_sec_hdr = false, 2199 .hw_mgmt_tx_encrypt = false, 2200 .rf_path_num = 2, 2201 .tx_nss = 2, 2202 .rx_nss = 2, 2203 .acam_num = 128, 2204 .bcam_num = 10, 2205 .scam_num = 128, 2206 .bacam_num = 2, 2207 .bacam_dynamic_num = 4, 2208 .bacam_ver = RTW89_BACAM_V0, 2209 .ppdu_max_usr = 4, 2210 .sec_ctrl_efuse_size = 4, 2211 .physical_efuse_size = 1216, 2212 .logical_efuse_size = 1536, 2213 .limit_efuse_size = 1152, 2214 .dav_phy_efuse_size = 0, 2215 .dav_log_efuse_size = 0, 2216 .efuse_blocks = NULL, 2217 .phycap_addr = 0x580, 2218 .phycap_size = 128, 2219 .para_ver = 0x0, 2220 .wlcx_desired = 0x06000000, 2221 .btcx_desired = 0x7, 2222 .scbd = 0x1, 2223 .mailbox = 0x1, 2224 2225 .afh_guard_ch = 6, 2226 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2227 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2228 .rssi_tol = 2, 2229 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2230 .mon_reg = rtw89_btc_8852a_mon_reg, 2231 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2232 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2233 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2234 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2235 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2236 BIT(RTW89_PS_MODE_CLK_GATED) | 2237 BIT(RTW89_PS_MODE_PWR_GATED), 2238 .low_power_hci_modes = 0, 2239 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2240 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2241 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2242 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2243 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2244 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2245 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2246 .h2c_regs = rtw8852a_h2c_regs, 2247 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2248 .c2h_regs = rtw8852a_c2h_regs, 2249 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2250 .page_regs = &rtw8852a_page_regs, 2251 .wow_reason_reg = rtw8852a_wow_wakeup_regs, 2252 .cfo_src_fd = false, 2253 .cfo_hw_comp = false, 2254 .dcfo_comp = &rtw8852a_dcfo_comp, 2255 .dcfo_comp_sft = 10, 2256 .imr_info = &rtw8852a_imr_info, 2257 .imr_dmac_table = NULL, 2258 .imr_cmac_table = NULL, 2259 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2260 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2261 .bss_clr_map_reg = R_BSS_CLR_MAP, 2262 .rfkill_init = &rtw8852a_rfkill_regs, 2263 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 2264 .dma_ch_mask = 0, 2265 .edcca_regs = &rtw8852a_edcca_regs, 2266 #ifdef CONFIG_PM 2267 .wowlan_stub = &rtw_wowlan_stub_8852a, 2268 #endif 2269 .xtal_info = &rtw8852a_xtal_info, 2270 }; 2271 EXPORT_SYMBOL(rtw8852a_chip_info); 2272 2273 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2274 MODULE_AUTHOR("Realtek Corporation"); 2275 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2276 MODULE_LICENSE("Dual BSD/GPL"); 2277