1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 #define RTW8852A_FW_FORMAT_MAX 0 16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17 #define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 55 &rtw89_mac_size.ple_qt5}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 59 &rtw89_mac_size.ple_qt_52a_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 69 {0x44AC, 0x00000000}, 70 {0x44B0, 0x00000000}, 71 {0x44B4, 0x00000000}, 72 {0x44B8, 0x00000000}, 73 {0x44BC, 0x00000000}, 74 {0x44C0, 0x00000000}, 75 {0x44C4, 0x00000000}, 76 {0x44C8, 0x00000000}, 77 {0x44CC, 0x00000000}, 78 {0x44D0, 0x00000000}, 79 {0x44D4, 0x00000000}, 80 {0x44D8, 0x00000000}, 81 {0x44DC, 0x00000000}, 82 {0x44E0, 0x00000000}, 83 {0x44E4, 0x00000000}, 84 {0x44E8, 0x00000000}, 85 {0x44EC, 0x00000000}, 86 {0x44F0, 0x00000000}, 87 {0x44F4, 0x00000000}, 88 {0x44F8, 0x00000000}, 89 {0x44FC, 0x00000000}, 90 {0x4500, 0x00000000}, 91 {0x4504, 0x00000000}, 92 {0x4508, 0x00000000}, 93 {0x450C, 0x00000000}, 94 {0x4510, 0x00000000}, 95 {0x4514, 0x00000000}, 96 {0x4518, 0x00000000}, 97 {0x451C, 0x00000000}, 98 {0x4520, 0x00000000}, 99 {0x4524, 0x00000000}, 100 {0x4528, 0x00000000}, 101 {0x452C, 0x00000000}, 102 {0x4530, 0x4E1F3E81}, 103 {0x4534, 0x00000000}, 104 {0x4538, 0x0000005A}, 105 {0x453C, 0x00000000}, 106 {0x4540, 0x00000000}, 107 {0x4544, 0x00000000}, 108 {0x4548, 0x00000000}, 109 {0x454C, 0x00000000}, 110 {0x4550, 0x00000000}, 111 {0x4554, 0x00000000}, 112 {0x4558, 0x00000000}, 113 {0x455C, 0x00000000}, 114 {0x4560, 0x4060001A}, 115 {0x4564, 0x40000000}, 116 {0x4568, 0x00000000}, 117 {0x456C, 0x00000000}, 118 {0x4570, 0x04000007}, 119 {0x4574, 0x0000DC87}, 120 {0x4578, 0x00000BAB}, 121 {0x457C, 0x03E00000}, 122 {0x4580, 0x00000048}, 123 {0x4584, 0x00000000}, 124 {0x4588, 0x000003E8}, 125 {0x458C, 0x30000000}, 126 {0x4590, 0x00000000}, 127 {0x4594, 0x10000000}, 128 {0x4598, 0x00000001}, 129 {0x459C, 0x00030000}, 130 {0x45A0, 0x01000000}, 131 {0x45A4, 0x03000200}, 132 {0x45A8, 0xC00001C0}, 133 {0x45AC, 0x78018000}, 134 {0x45B0, 0x80000000}, 135 {0x45B4, 0x01C80600}, 136 {0x45B8, 0x00000002}, 137 {0x4594, 0x10000000} 138 }; 139 140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 141 {0x4624, GENMASK(20, 14), 0x40}, 142 {0x46f8, GENMASK(20, 14), 0x40}, 143 {0x4674, GENMASK(20, 19), 0x2}, 144 {0x4748, GENMASK(20, 19), 0x2}, 145 {0x4650, GENMASK(14, 10), 0x18}, 146 {0x4724, GENMASK(14, 10), 0x18}, 147 {0x4688, GENMASK(1, 0), 0x3}, 148 {0x475c, GENMASK(1, 0), 0x3}, 149 }; 150 151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 152 153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 154 {0x4624, GENMASK(20, 14), 0x1a}, 155 {0x46f8, GENMASK(20, 14), 0x1a}, 156 {0x4674, GENMASK(20, 19), 0x1}, 157 {0x4748, GENMASK(20, 19), 0x1}, 158 {0x4650, GENMASK(14, 10), 0x12}, 159 {0x4724, GENMASK(14, 10), 0x12}, 160 {0x4688, GENMASK(1, 0), 0x0}, 161 {0x475c, GENMASK(1, 0), 0x0}, 162 }; 163 164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 165 166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 167 {0x00C6, 168 PWR_CV_MSK_B, 169 PWR_INTF_MSK_PCIE, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(6), BIT(6)}, 172 {0x1086, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_SDIO, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(0), 0}, 177 {0x1086, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_SDIO, 180 PWR_BASE_MAC, 181 PWR_CMD_POLL, BIT(1), BIT(1)}, 182 {0x0005, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 187 {0x0005, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(7), 0}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(2), 0}, 197 {0x0006, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(1), BIT(1)}, 202 {0x0006, 203 PWR_CV_MSK_ALL, 204 PWR_INTF_MSK_ALL, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(0), BIT(0)}, 207 {0x0005, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0005, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_POLL, BIT(0), 0}, 217 {0x106D, 218 PWR_CV_MSK_B | PWR_CV_MSK_C, 219 PWR_INTF_MSK_USB, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(6), 0}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), BIT(0)}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x0088, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(0), BIT(0)}, 237 {0x0088, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(0), 0}, 242 {0x0088, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(0), BIT(0)}, 247 {0x0083, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(6), 0}, 252 {0x0080, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(5), BIT(5)}, 257 {0x0024, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 262 {0x02A0, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(1), BIT(1)}, 267 {0x02A2, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 272 {0x0071, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_PCIE, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(4), 0}, 277 {0x0010, 278 PWR_CV_MSK_A, 279 PWR_INTF_MSK_PCIE, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(2), BIT(2)}, 282 {0x02A0, 283 PWR_CV_MSK_A, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 287 {0xFFFF, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 0, 291 PWR_CMD_END, 0, 0}, 292 }; 293 294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 295 {0x02F0, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, 0xFF, 0}, 300 {0x02F1, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, 0xFF, 0}, 305 {0x0006, 306 PWR_CV_MSK_ALL, 307 PWR_INTF_MSK_ALL, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(0), BIT(0)}, 310 {0x0002, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 315 {0x0082, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 320 {0x106D, 321 PWR_CV_MSK_B | PWR_CV_MSK_C, 322 PWR_INTF_MSK_USB, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(6), BIT(6)}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_ALL, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(1), BIT(1)}, 330 {0x0005, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_ALL, 333 PWR_BASE_MAC, 334 PWR_CMD_POLL, BIT(1), 0}, 335 {0x0091, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_PCIE, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(0), 0}, 340 {0x0092, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_PCIE, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(4), BIT(4)}, 345 {0x0005, 346 PWR_CV_MSK_ALL, 347 PWR_INTF_MSK_PCIE, 348 PWR_BASE_MAC, 349 PWR_CMD_WRITE, BIT(2), BIT(2)}, 350 {0x0007, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_USB, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(4), 0}, 355 {0x0007, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 360 {0x0005, 361 PWR_CV_MSK_ALL, 362 PWR_INTF_MSK_SDIO, 363 PWR_BASE_MAC, 364 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 365 {0x0005, 366 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 367 PWR_CV_MSK_G, 368 PWR_INTF_MSK_USB, 369 PWR_BASE_MAC, 370 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 371 {0x1086, 372 PWR_CV_MSK_ALL, 373 PWR_INTF_MSK_SDIO, 374 PWR_BASE_MAC, 375 PWR_CMD_WRITE, BIT(0), BIT(0)}, 376 {0x1086, 377 PWR_CV_MSK_ALL, 378 PWR_INTF_MSK_SDIO, 379 PWR_BASE_MAC, 380 PWR_CMD_POLL, BIT(1), 0}, 381 {0xFFFF, 382 PWR_CV_MSK_ALL, 383 PWR_INTF_MSK_ALL, 384 0, 385 PWR_CMD_END, 0, 0}, 386 }; 387 388 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 389 rtw8852a_pwron, NULL 390 }; 391 392 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 393 rtw8852a_pwroff, NULL 394 }; 395 396 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 397 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 398 R_AX_H2CREG_DATA3 399 }; 400 401 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 402 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 403 R_AX_C2HREG_DATA3 404 }; 405 406 static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 407 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 408 }; 409 410 static const struct rtw89_page_regs rtw8852a_page_regs = { 411 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 412 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 413 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 414 .ach_page_info = R_AX_ACH0_PAGE_INFO, 415 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 416 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 417 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 418 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 419 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 420 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 421 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 422 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 423 }; 424 425 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 426 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 427 }; 428 429 static const struct rtw89_reg_def rtw8852a_nhm_th[RTW89_NHM_TH_NUM] = { 430 {R_NHM_CFG, B_NHM_TH0_MSK}, 431 {R_NHM_TH1, B_NHM_TH1_MSK}, 432 {R_NHM_TH1, B_NHM_TH2_MSK}, 433 {R_NHM_TH1, B_NHM_TH3_MSK}, 434 {R_NHM_TH1, B_NHM_TH4_MSK}, 435 {R_NHM_TH5, B_NHM_TH5_MSK}, 436 {R_NHM_TH5, B_NHM_TH6_MSK}, 437 {R_NHM_TH5, B_NHM_TH7_MSK}, 438 {R_NHM_TH5, B_NHM_TH8_MSK}, 439 {R_NHM_TH9, B_NHM_TH9_MSK}, 440 {R_NHM_TH9, B_NHM_TH10_MSK}, 441 }; 442 443 static const struct rtw89_reg_def rtw8852a_nhm_rpt[RTW89_NHM_RPT_NUM] = { 444 {R_NHM_CNT0, B_NHM_CNT0_MSK}, 445 {R_NHM_CNT0, B_NHM_CNT1_MSK}, 446 {R_NHM_CNT2, B_NHM_CNT2_MSK}, 447 {R_NHM_CNT2, B_NHM_CNT3_MSK}, 448 {R_NHM_CNT4, B_NHM_CNT4_MSK}, 449 {R_NHM_CNT4, B_NHM_CNT5_MSK}, 450 {R_NHM_CNT6, B_NHM_CNT6_MSK}, 451 {R_NHM_CNT6, B_NHM_CNT7_MSK}, 452 {R_NHM_CNT8, B_NHM_CNT8_MSK}, 453 {R_NHM_CNT8, B_NHM_CNT9_MSK}, 454 {R_NHM_CNT10, B_NHM_CNT10_MSK}, 455 {R_NHM_CNT10, B_NHM_CNT11_MSK}, 456 }; 457 458 static const struct rtw89_imr_info rtw8852a_imr_info = { 459 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 460 .wsec_imr_reg = R_AX_SEC_DEBUG, 461 .wsec_imr_set = B_AX_IMR_ERROR, 462 .mpdu_tx_imr_set = 0, 463 .mpdu_rx_imr_set = 0, 464 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 465 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 466 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 467 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 468 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 469 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 470 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 471 .wde_imr_clr = B_AX_WDE_IMR_CLR, 472 .wde_imr_set = B_AX_WDE_IMR_SET, 473 .ple_imr_clr = B_AX_PLE_IMR_CLR, 474 .ple_imr_set = B_AX_PLE_IMR_SET, 475 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 476 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 477 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 478 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 479 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 480 .other_disp_imr_set = 0, 481 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 482 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 483 .bbrpt_err_imr_set = 0, 484 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 485 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 486 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 487 .cdma_imr_0_reg = R_AX_DLE_CTRL, 488 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 489 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 490 .cdma_imr_1_reg = 0, 491 .cdma_imr_1_clr = 0, 492 .cdma_imr_1_set = 0, 493 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 494 .phy_intf_imr_clr = 0, 495 .phy_intf_imr_set = 0, 496 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 497 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 498 .rmac_imr_set = B_AX_RMAC_IMR_SET, 499 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 500 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 501 .tmac_imr_set = B_AX_TMAC_IMR_SET, 502 }; 503 504 static const struct rtw89_xtal_info rtw8852a_xtal_info = { 505 .xcap_reg = R_AX_XTAL_ON_CTRL0, 506 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK, 507 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK, 508 }; 509 510 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 511 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 512 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 513 }; 514 515 static const struct rtw89_rfkill_regs rtw8852a_rfkill_regs = { 516 .pinmux = {R_AX_GPIO8_15_FUNC_SEL, 517 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK, 518 0xf}, 519 .mode = {R_AX_GPIO_EXT_CTRL + 2, 520 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16, 521 0x0}, 522 }; 523 524 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 525 .seg0_pd_reg = R_SEG0R_PD, 526 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 527 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 528 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 529 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 530 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 531 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 532 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 533 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 534 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 535 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 536 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 537 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 538 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 539 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 540 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 541 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 542 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 543 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 544 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 545 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 546 }; 547 548 static const struct rtw89_edcca_regs rtw8852a_edcca_regs = { 549 .edcca_level = R_SEG0R_EDCCA_LVL, 550 .edcca_mask = B_EDCCA_LVL_MSK0, 551 .edcca_p_mask = B_EDCCA_LVL_MSK1, 552 .ppdu_level = R_SEG0R_EDCCA_LVL, 553 .ppdu_mask = B_EDCCA_LVL_MSK3, 554 .p = {{ 555 .rpt_a = R_EDCCA_RPT_A, 556 .rpt_b = R_EDCCA_RPT_B, 557 .rpt_sel = R_EDCCA_RPT_SEL, 558 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 559 }, { 560 .rpt_a = R_EDCCA_RPT_P1_A, 561 .rpt_b = R_EDCCA_RPT_P1_B, 562 .rpt_sel = R_EDCCA_RPT_SEL, 563 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK, 564 }}, 565 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 566 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 567 }; 568 569 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 570 struct rtw8852a_efuse *map) 571 { 572 ether_addr_copy(efuse->addr, map->e.mac_addr); 573 efuse->rfe_type = map->rfe_type; 574 efuse->xtal_cap = map->xtal_k; 575 } 576 577 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 578 struct rtw8852a_efuse *map) 579 { 580 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 581 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 582 u8 i, j; 583 584 tssi->thermal[RF_PATH_A] = map->path_a_therm; 585 tssi->thermal[RF_PATH_B] = map->path_b_therm; 586 587 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 588 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 589 sizeof(ofst[i]->cck_tssi)); 590 591 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 592 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 593 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 594 i, j, tssi->tssi_cck[i][j]); 595 596 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 597 sizeof(ofst[i]->bw40_tssi)); 598 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 599 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 600 601 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 602 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 603 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 604 i, j, tssi->tssi_mcs[i][j]); 605 } 606 } 607 608 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 609 enum rtw89_efuse_block block) 610 { 611 struct rtw89_efuse *efuse = &rtwdev->efuse; 612 struct rtw8852a_efuse *map; 613 614 map = (struct rtw8852a_efuse *)log_map; 615 616 efuse->country_code[0] = map->country_code[0]; 617 efuse->country_code[1] = map->country_code[1]; 618 rtw8852a_efuse_parsing_tssi(rtwdev, map); 619 620 switch (rtwdev->hci.type) { 621 case RTW89_HCI_TYPE_PCIE: 622 rtw8852ae_efuse_parsing(efuse, map); 623 break; 624 default: 625 return -ENOTSUPP; 626 } 627 628 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 629 630 return 0; 631 } 632 633 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 634 { 635 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 636 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 637 u32 addr = rtwdev->chip->phycap_addr; 638 bool pg = false; 639 u32 ofst; 640 u8 i, j; 641 642 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 643 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 644 /* addrs are in decreasing order */ 645 ofst = tssi_trim_addr[i] - addr - j; 646 tssi->tssi_trim[i][j] = phycap_map[ofst]; 647 648 if (phycap_map[ofst] != 0xff) 649 pg = true; 650 } 651 } 652 653 if (!pg) { 654 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 655 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 656 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 657 } 658 659 for (i = 0; i < RF_PATH_NUM_8852A; i++) 660 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 661 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 662 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 663 i, j, tssi->tssi_trim[i][j], 664 tssi_trim_addr[i] - j); 665 } 666 667 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 668 u8 *phycap_map) 669 { 670 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 671 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 672 u32 addr = rtwdev->chip->phycap_addr; 673 u8 i; 674 675 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 676 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 677 678 rtw89_debug(rtwdev, RTW89_DBG_RFK, 679 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 680 i, info->thermal_trim[i]); 681 682 if (info->thermal_trim[i] != 0xff) 683 info->pg_thermal_trim = true; 684 } 685 } 686 687 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 688 { 689 #define __thm_setting(raw) \ 690 ({ \ 691 u8 __v = (raw); \ 692 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 693 }) 694 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 695 u8 i, val; 696 697 if (!info->pg_thermal_trim) { 698 rtw89_debug(rtwdev, RTW89_DBG_RFK, 699 "[THERMAL][TRIM] no PG, do nothing\n"); 700 701 return; 702 } 703 704 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 705 val = __thm_setting(info->thermal_trim[i]); 706 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 707 708 rtw89_debug(rtwdev, RTW89_DBG_RFK, 709 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 710 i, val); 711 } 712 #undef __thm_setting 713 } 714 715 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 716 u8 *phycap_map) 717 { 718 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 719 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 720 u32 addr = rtwdev->chip->phycap_addr; 721 u8 i; 722 723 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 724 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 725 726 rtw89_debug(rtwdev, RTW89_DBG_RFK, 727 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 728 i, info->pa_bias_trim[i]); 729 730 if (info->pa_bias_trim[i] != 0xff) 731 info->pg_pa_bias_trim = true; 732 } 733 } 734 735 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 736 { 737 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 738 u8 pabias_2g, pabias_5g; 739 u8 i; 740 741 if (!info->pg_pa_bias_trim) { 742 rtw89_debug(rtwdev, RTW89_DBG_RFK, 743 "[PA_BIAS][TRIM] no PG, do nothing\n"); 744 745 return; 746 } 747 748 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 749 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 750 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 751 752 rtw89_debug(rtwdev, RTW89_DBG_RFK, 753 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 754 i, pabias_2g, pabias_5g); 755 756 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 757 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 758 } 759 } 760 761 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 762 { 763 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 764 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 765 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 766 767 return 0; 768 } 769 770 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 771 { 772 rtw8852a_thermal_trim(rtwdev); 773 rtw8852a_pa_bias_trim(rtwdev); 774 } 775 776 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 777 const struct rtw89_chan *chan, 778 u8 mac_idx) 779 { 780 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 781 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 782 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 783 u8 txsc20 = 0, txsc40 = 0; 784 785 switch (chan->band_width) { 786 case RTW89_CHANNEL_WIDTH_80: 787 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 788 RTW89_CHANNEL_WIDTH_40); 789 fallthrough; 790 case RTW89_CHANNEL_WIDTH_40: 791 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 792 RTW89_CHANNEL_WIDTH_20); 793 break; 794 default: 795 break; 796 } 797 798 switch (chan->band_width) { 799 case RTW89_CHANNEL_WIDTH_80: 800 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 801 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 802 break; 803 case RTW89_CHANNEL_WIDTH_40: 804 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 805 rtw89_write32(rtwdev, sub_carr, txsc20); 806 break; 807 case RTW89_CHANNEL_WIDTH_20: 808 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 809 rtw89_write32(rtwdev, sub_carr, 0); 810 break; 811 default: 812 break; 813 } 814 815 if (chan->channel > 14) 816 rtw89_write8_set(rtwdev, chk_rate, 817 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 818 else 819 rtw89_write8_clr(rtwdev, chk_rate, 820 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 821 } 822 823 static const u32 rtw8852a_sco_barker_threshold[14] = { 824 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 825 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 826 }; 827 828 static const u32 rtw8852a_sco_cck_threshold[14] = { 829 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 830 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 831 }; 832 833 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 834 u8 primary_ch, enum rtw89_bandwidth bw) 835 { 836 u8 ch_element; 837 838 if (bw == RTW89_CHANNEL_WIDTH_20) { 839 ch_element = central_ch - 1; 840 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 841 if (primary_ch == 1) 842 ch_element = central_ch - 1 + 2; 843 else 844 ch_element = central_ch - 1 - 2; 845 } else { 846 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 847 return -EINVAL; 848 } 849 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 850 rtw8852a_sco_barker_threshold[ch_element]); 851 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 852 rtw8852a_sco_cck_threshold[ch_element]); 853 854 return 0; 855 } 856 857 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 858 u8 path) 859 { 860 u32 val; 861 862 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 863 if (val == INV_RF_DATA) { 864 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 865 return; 866 } 867 val &= ~0x303ff; 868 val |= central_ch; 869 if (central_ch > 14) 870 val |= (BIT(16) | BIT(8)); 871 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 872 } 873 874 static u8 rtw8852a_sco_mapping(u8 central_ch) 875 { 876 if (central_ch == 1) 877 return 109; 878 else if (central_ch >= 2 && central_ch <= 6) 879 return 108; 880 else if (central_ch >= 7 && central_ch <= 10) 881 return 107; 882 else if (central_ch >= 11 && central_ch <= 14) 883 return 106; 884 else if (central_ch == 36 || central_ch == 38) 885 return 51; 886 else if (central_ch >= 40 && central_ch <= 58) 887 return 50; 888 else if (central_ch >= 60 && central_ch <= 64) 889 return 49; 890 else if (central_ch == 100 || central_ch == 102) 891 return 48; 892 else if (central_ch >= 104 && central_ch <= 126) 893 return 47; 894 else if (central_ch >= 128 && central_ch <= 151) 895 return 46; 896 else if (central_ch >= 153 && central_ch <= 177) 897 return 45; 898 else 899 return 0; 900 } 901 902 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 903 enum rtw89_phy_idx phy_idx) 904 { 905 u8 sco_comp; 906 bool is_2g = central_ch <= 14; 907 908 if (phy_idx == RTW89_PHY_0) { 909 /* Path A */ 910 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 911 if (is_2g) 912 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 913 B_PATH0_TIA_ERR_G1_SEL, 1, 914 phy_idx); 915 else 916 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 917 B_PATH0_TIA_ERR_G1_SEL, 0, 918 phy_idx); 919 920 /* Path B */ 921 if (!rtwdev->dbcc_en) { 922 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 923 if (is_2g) 924 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 925 B_P1_MODE_SEL, 926 1, phy_idx); 927 else 928 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 929 B_P1_MODE_SEL, 930 0, phy_idx); 931 } else { 932 if (is_2g) 933 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 934 B_2P4G_BAND_SEL); 935 else 936 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 937 B_2P4G_BAND_SEL); 938 } 939 /* SCO compensate FC setting */ 940 sco_comp = rtw8852a_sco_mapping(central_ch); 941 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 942 sco_comp, phy_idx); 943 } else { 944 /* Path B */ 945 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 946 if (is_2g) 947 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 948 B_P1_MODE_SEL, 949 1, phy_idx); 950 else 951 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 952 B_P1_MODE_SEL, 953 0, phy_idx); 954 /* SCO compensate FC setting */ 955 sco_comp = rtw8852a_sco_mapping(central_ch); 956 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 957 sco_comp, phy_idx); 958 } 959 960 /* Band edge */ 961 if (is_2g) 962 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 963 phy_idx); 964 else 965 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 966 phy_idx); 967 968 /* CCK parameters */ 969 if (central_ch == 14) { 970 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 971 0x3b13ff); 972 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 973 0x1c42de); 974 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 975 0xfdb0ad); 976 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 977 0xf60f6e); 978 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 979 0xfd8f92); 980 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 981 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 982 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 983 0xfff00a); 984 } else { 985 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 986 0x3d23ff); 987 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 988 0x29b354); 989 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 990 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 991 0xfdb053); 992 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 993 0xf86f9a); 994 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 995 0xfaef92); 996 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 997 0xfe5fcc); 998 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 999 0xffdff5); 1000 } 1001 } 1002 1003 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1004 { 1005 u32 val = 0; 1006 u32 adc_sel[2] = {0x12d0, 0x32d0}; 1007 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 1008 1009 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 1010 if (val == INV_RF_DATA) { 1011 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 1012 return; 1013 } 1014 val &= ~(BIT(11) | BIT(10)); 1015 switch (bw) { 1016 case RTW89_CHANNEL_WIDTH_5: 1017 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1018 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1019 val |= (BIT(11) | BIT(10)); 1020 break; 1021 case RTW89_CHANNEL_WIDTH_10: 1022 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1023 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1024 val |= (BIT(11) | BIT(10)); 1025 break; 1026 case RTW89_CHANNEL_WIDTH_20: 1027 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1028 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1029 val |= (BIT(11) | BIT(10)); 1030 break; 1031 case RTW89_CHANNEL_WIDTH_40: 1032 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1033 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1034 val |= BIT(11); 1035 break; 1036 case RTW89_CHANNEL_WIDTH_80: 1037 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1038 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1039 val |= BIT(10); 1040 break; 1041 default: 1042 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1043 } 1044 1045 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 1046 } 1047 1048 static void 1049 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1050 enum rtw89_phy_idx phy_idx) 1051 { 1052 /* Switch bandwidth */ 1053 switch (bw) { 1054 case RTW89_CHANNEL_WIDTH_5: 1055 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1056 phy_idx); 1057 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 1058 phy_idx); 1059 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1060 0x0, phy_idx); 1061 break; 1062 case RTW89_CHANNEL_WIDTH_10: 1063 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1064 phy_idx); 1065 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 1066 phy_idx); 1067 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1068 0x0, phy_idx); 1069 break; 1070 case RTW89_CHANNEL_WIDTH_20: 1071 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1072 phy_idx); 1073 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1074 phy_idx); 1075 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1076 0x0, phy_idx); 1077 break; 1078 case RTW89_CHANNEL_WIDTH_40: 1079 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1080 phy_idx); 1081 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1082 phy_idx); 1083 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1084 pri_ch, 1085 phy_idx); 1086 if (pri_ch == RTW89_SC_20_UPPER) 1087 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1088 else 1089 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1090 break; 1091 case RTW89_CHANNEL_WIDTH_80: 1092 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1093 phy_idx); 1094 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1095 phy_idx); 1096 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1097 pri_ch, 1098 phy_idx); 1099 break; 1100 default: 1101 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1102 pri_ch); 1103 } 1104 1105 if (phy_idx == RTW89_PHY_0) { 1106 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1107 if (!rtwdev->dbcc_en) 1108 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1109 } else { 1110 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1111 } 1112 } 1113 1114 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1115 { 1116 if (central_ch == 153) { 1117 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1118 0x210); 1119 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1120 0x210); 1121 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1122 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1123 B_P0_NBIIDX_NOTCH_EN, 0x1); 1124 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1125 B_P1_NBIIDX_NOTCH_EN, 0x1); 1126 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1127 0x1); 1128 } else if (central_ch == 151) { 1129 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1130 0x210); 1131 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1132 0x210); 1133 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1134 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1135 B_P0_NBIIDX_NOTCH_EN, 0x1); 1136 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1137 B_P1_NBIIDX_NOTCH_EN, 0x1); 1138 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1139 0x1); 1140 } else if (central_ch == 155) { 1141 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1142 0x2d0); 1143 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1144 0x2d0); 1145 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1146 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1147 B_P0_NBIIDX_NOTCH_EN, 0x1); 1148 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1149 B_P1_NBIIDX_NOTCH_EN, 0x1); 1150 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1151 0x1); 1152 } else { 1153 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1154 B_P0_NBIIDX_NOTCH_EN, 0x0); 1155 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1156 B_P1_NBIIDX_NOTCH_EN, 0x0); 1157 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1158 0x0); 1159 } 1160 } 1161 1162 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1163 enum rtw89_phy_idx phy_idx) 1164 { 1165 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1166 phy_idx); 1167 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1168 phy_idx); 1169 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1170 phy_idx); 1171 } 1172 1173 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1174 enum rtw89_phy_idx phy_idx, bool en) 1175 { 1176 if (en) 1177 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1178 1, 1179 phy_idx); 1180 else 1181 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1182 0, 1183 phy_idx); 1184 } 1185 1186 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1187 enum rtw89_phy_idx phy_idx) 1188 { 1189 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1190 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1191 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1192 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1193 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1194 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1195 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1196 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1197 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1198 } 1199 1200 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1201 enum rtw89_phy_idx phy_idx) 1202 { 1203 u32 addr; 1204 1205 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1206 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1207 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1208 } 1209 1210 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1211 { 1212 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1213 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1214 1215 if (rtwdev->hal.cv <= CHIP_CCV) { 1216 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1217 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1218 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1219 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1220 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1221 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1222 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1223 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1224 } 1225 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1226 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1227 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1228 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1229 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1230 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1231 1232 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1233 } 1234 1235 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1236 enum rtw89_phy_idx phy_idx) 1237 { 1238 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1239 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1240 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1241 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1242 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1243 udelay(1); 1244 } 1245 1246 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1247 const struct rtw89_chan *chan, 1248 enum rtw89_phy_idx phy_idx) 1249 { 1250 bool cck_en = chan->channel <= 14; 1251 u8 pri_ch_idx = chan->pri_ch_idx; 1252 1253 if (cck_en) 1254 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1255 chan->primary_channel, 1256 chan->band_width); 1257 1258 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1259 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1260 if (cck_en) { 1261 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1262 } else { 1263 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1264 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1265 } 1266 rtw8852a_spur_elimination(rtwdev, chan->channel); 1267 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1268 chan->primary_channel); 1269 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1270 } 1271 1272 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1273 const struct rtw89_chan *chan, 1274 enum rtw89_mac_idx mac_idx, 1275 enum rtw89_phy_idx phy_idx) 1276 { 1277 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1278 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1279 } 1280 1281 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1282 { 1283 if (en) 1284 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1285 else 1286 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1287 } 1288 1289 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1290 enum rtw89_rf_path path) 1291 { 1292 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1293 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1294 1295 if (en) { 1296 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1297 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1298 } else { 1299 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1300 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1301 } 1302 } 1303 1304 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1305 u8 phy_idx) 1306 { 1307 if (!rtwdev->dbcc_en) { 1308 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1309 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1310 } else { 1311 if (phy_idx == RTW89_PHY_0) 1312 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1313 else 1314 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1315 } 1316 } 1317 1318 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1319 { 1320 if (en) 1321 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1322 0x0); 1323 else 1324 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1325 0xf); 1326 } 1327 1328 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1329 struct rtw89_channel_help_params *p, 1330 const struct rtw89_chan *chan, 1331 enum rtw89_mac_idx mac_idx, 1332 enum rtw89_phy_idx phy_idx) 1333 { 1334 if (enter) { 1335 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1336 RTW89_SCH_TX_SEL_ALL); 1337 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1338 rtw8852a_dfs_en(rtwdev, false); 1339 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1340 rtw8852a_adc_en(rtwdev, false); 1341 fsleep(40); 1342 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1343 } else { 1344 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1345 rtw8852a_adc_en(rtwdev, true); 1346 rtw8852a_dfs_en(rtwdev, true); 1347 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1348 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1349 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1350 } 1351 } 1352 1353 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1354 { 1355 struct rtw89_efuse *efuse = &rtwdev->efuse; 1356 1357 switch (efuse->rfe_type) { 1358 case 11: 1359 case 12: 1360 case 17: 1361 case 18: 1362 case 51: 1363 case 53: 1364 rtwdev->fem.epa_2g = true; 1365 rtwdev->fem.elna_2g = true; 1366 fallthrough; 1367 case 9: 1368 case 10: 1369 case 15: 1370 case 16: 1371 rtwdev->fem.epa_5g = true; 1372 rtwdev->fem.elna_5g = true; 1373 break; 1374 default: 1375 break; 1376 } 1377 } 1378 1379 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1380 { 1381 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1382 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1383 1384 rtw8852a_rck(rtwdev); 1385 rtw8852a_dack(rtwdev, RTW89_CHANCTX_0); 1386 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true, RTW89_CHANCTX_0); 1387 } 1388 1389 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev, 1390 struct rtw89_vif_link *rtwvif_link) 1391 { 1392 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx; 1393 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 1394 1395 rtw89_btc_ntfy_conn_rfk(rtwdev, true); 1396 1397 rtw8852a_rx_dck(rtwdev, phy_idx, true, chanctx_idx); 1398 rtw8852a_iqk(rtwdev, phy_idx, chanctx_idx); 1399 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1400 rtw8852a_tssi(rtwdev, phy_idx, chanctx_idx); 1401 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30); 1402 rtw8852a_dpk(rtwdev, phy_idx, chanctx_idx); 1403 1404 rtw89_btc_ntfy_conn_rfk(rtwdev, false); 1405 } 1406 1407 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1408 enum rtw89_phy_idx phy_idx, 1409 const struct rtw89_chan *chan) 1410 { 1411 rtw8852a_tssi_scan(rtwdev, phy_idx, chan); 1412 } 1413 1414 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, 1415 struct rtw89_vif_link *rtwvif_link, 1416 bool start) 1417 { 1418 rtw8852a_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx); 1419 } 1420 1421 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1422 { 1423 rtw8852a_dpk_track(rtwdev); 1424 rtw8852a_tssi_track(rtwdev); 1425 } 1426 1427 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1428 enum rtw89_phy_idx phy_idx, s16 ref) 1429 { 1430 s8 ofst_int = 0; 1431 u8 base_cw_0db = 0x27; 1432 u16 tssi_16dbm_cw = 0x12c; 1433 s16 pwr_s10_3 = 0; 1434 s16 rf_pwr_cw = 0; 1435 u16 bb_pwr_cw = 0; 1436 u32 pwr_cw = 0; 1437 u32 tssi_ofst_cw = 0; 1438 1439 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1440 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1441 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1442 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1443 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1444 1445 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1446 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1447 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1448 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1449 1450 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1451 } 1452 1453 static 1454 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1455 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1456 { 1457 s8 val_1t = 0; 1458 s8 val_2t = 0; 1459 u32 reg; 1460 1461 if (pw_ofst < -16 || pw_ofst > 15) { 1462 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1463 pw_ofst); 1464 return; 1465 } 1466 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1467 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1468 val_1t = pw_ofst; 1469 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1470 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1471 val_2t = max(val_1t - 3, -16); 1472 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1473 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1474 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1475 val_1t, val_2t); 1476 } 1477 1478 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1479 enum rtw89_phy_idx phy_idx) 1480 { 1481 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1482 const u32 mask = 0x7FFFFFF; 1483 const u8 ofst_ofdm = 0x4; 1484 const u8 ofst_cck = 0x8; 1485 s16 ref_ofdm = 0; 1486 s16 ref_cck = 0; 1487 u32 val; 1488 u8 i; 1489 1490 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1491 1492 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1493 GENMASK(27, 10), 0x0); 1494 1495 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1496 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1497 1498 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1499 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1500 phy_idx); 1501 1502 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1503 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1504 1505 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1506 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1507 phy_idx); 1508 } 1509 1510 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1511 const struct rtw89_chan *chan, 1512 enum rtw89_phy_idx phy_idx) 1513 { 1514 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1515 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1516 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1517 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1518 } 1519 1520 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1521 enum rtw89_phy_idx phy_idx) 1522 { 1523 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1524 } 1525 1526 static int 1527 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1528 { 1529 int ret; 1530 1531 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1532 if (ret) 1533 return ret; 1534 1535 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1536 if (ret) 1537 return ret; 1538 1539 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1540 if (ret) 1541 return ret; 1542 1543 return 0; 1544 } 1545 1546 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1547 { 1548 u8 i = 0; 1549 u32 addr, val; 1550 1551 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1552 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1553 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1554 rtw89_phy_write32(rtwdev, addr, val); 1555 } 1556 } 1557 1558 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1559 struct rtw8852a_bb_pmac_info *tx_info, 1560 enum rtw89_phy_idx idx) 1561 { 1562 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1563 if (tx_info->mode == CONT_TX) 1564 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1565 idx); 1566 else if (tx_info->mode == PKTS_TX) 1567 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1568 idx); 1569 } 1570 1571 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1572 struct rtw8852a_bb_pmac_info *tx_info, 1573 enum rtw89_phy_idx idx) 1574 { 1575 enum rtw8852a_pmac_mode mode = tx_info->mode; 1576 u32 pkt_cnt = tx_info->tx_cnt; 1577 u16 period = tx_info->period; 1578 1579 if (mode == CONT_TX && !tx_info->is_cck) { 1580 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1581 idx); 1582 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1583 } else if (mode == PKTS_TX) { 1584 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1585 idx); 1586 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1587 B_PMAC_TX_PRD_MSK, period, idx); 1588 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1589 pkt_cnt, idx); 1590 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1591 } 1592 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1593 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1594 } 1595 1596 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1597 struct rtw8852a_bb_pmac_info *tx_info, 1598 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1599 { 1600 if (!tx_info->en_pmac_tx) { 1601 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1602 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1603 if (chan->band_type == RTW89_BAND_2G) 1604 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1605 return; 1606 } 1607 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1608 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1609 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1610 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1611 idx); 1612 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1613 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1614 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1615 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1616 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1617 } 1618 1619 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1620 u16 tx_cnt, u16 period, u16 tx_time, 1621 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1622 { 1623 struct rtw8852a_bb_pmac_info tx_info = {0}; 1624 1625 tx_info.en_pmac_tx = enable; 1626 tx_info.is_cck = 0; 1627 tx_info.mode = PKTS_TX; 1628 tx_info.tx_cnt = tx_cnt; 1629 tx_info.period = period; 1630 tx_info.tx_time = tx_time; 1631 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan); 1632 } 1633 1634 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1635 enum rtw89_phy_idx idx) 1636 { 1637 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1638 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1639 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1640 } 1641 1642 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1643 { 1644 u32 rst_mask0 = 0; 1645 u32 rst_mask1 = 0; 1646 1647 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1648 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1649 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1650 if (!rtwdev->dbcc_en) { 1651 if (tx_path == RF_PATH_A) { 1652 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1653 B_TXPATH_SEL_MSK, 1); 1654 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1655 B_TXNSS_MAP_MSK, 0); 1656 } else if (tx_path == RF_PATH_B) { 1657 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1658 B_TXPATH_SEL_MSK, 2); 1659 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1660 B_TXNSS_MAP_MSK, 0); 1661 } else if (tx_path == RF_PATH_AB) { 1662 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1663 B_TXPATH_SEL_MSK, 3); 1664 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1665 B_TXNSS_MAP_MSK, 4); 1666 } else { 1667 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1668 } 1669 } else { 1670 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1671 1); 1672 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1673 RTW89_PHY_1); 1674 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1675 0); 1676 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1677 RTW89_PHY_1); 1678 } 1679 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1680 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1681 if (tx_path == RF_PATH_A) { 1682 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1683 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1684 } else { 1685 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1686 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1687 } 1688 } 1689 1690 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1691 enum rtw89_phy_idx idx, u8 mode) 1692 { 1693 if (mode != 0) 1694 return; 1695 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1696 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1697 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1698 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1699 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1700 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1701 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1702 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1703 } 1704 1705 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1706 enum rtw89_phy_idx phy_idx) 1707 { 1708 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl : 1709 &rtw8852a_btc_preagc_dis_defs_tbl); 1710 } 1711 1712 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1713 { 1714 if (rtwdev->is_tssi_mode[rf_path]) { 1715 u32 addr = 0x1c10 + (rf_path << 13); 1716 1717 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1718 } 1719 1720 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1721 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1722 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1723 1724 fsleep(200); 1725 1726 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1727 } 1728 1729 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1730 { 1731 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 1732 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 1733 1734 if (ver->fcxinit == 7) { 1735 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 1736 md->md_v7.kt_ver = rtwdev->hal.cv; 1737 md->md_v7.bt_solo = 0; 1738 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 1739 1740 if (md->md_v7.rfe_type > 0) 1741 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 1742 else 1743 md->md_v7.ant.num = 2; 1744 1745 md->md_v7.ant.diversity = 0; 1746 md->md_v7.ant.isolation = 10; 1747 1748 if (md->md_v7.ant.num == 3) { 1749 md->md_v7.ant.type = BTC_ANT_DEDICATED; 1750 md->md_v7.bt_pos = BTC_BT_ALONE; 1751 } else { 1752 md->md_v7.ant.type = BTC_ANT_SHARED; 1753 md->md_v7.bt_pos = BTC_BT_BTG; 1754 } 1755 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 1756 rtwdev->btc.ant_type = md->md_v7.ant.type; 1757 } else { 1758 md->md.rfe_type = rtwdev->efuse.rfe_type; 1759 md->md.cv = rtwdev->hal.cv; 1760 md->md.bt_solo = 0; 1761 md->md.switch_type = BTC_SWITCH_INTERNAL; 1762 1763 if (md->md.rfe_type > 0) 1764 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 1765 else 1766 md->md.ant.num = 2; 1767 1768 md->md.ant.diversity = 0; 1769 md->md.ant.isolation = 10; 1770 1771 if (md->md.ant.num == 3) { 1772 md->md.ant.type = BTC_ANT_DEDICATED; 1773 md->md.bt_pos = BTC_BT_ALONE; 1774 } else { 1775 md->md.ant.type = BTC_ANT_SHARED; 1776 md->md.bt_pos = BTC_BT_BTG; 1777 } 1778 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 1779 rtwdev->btc.ant_type = md->md.ant.type; 1780 } 1781 } 1782 1783 static 1784 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1785 { 1786 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1787 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1788 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1789 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1790 } 1791 1792 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1793 enum rtw89_phy_idx phy_idx) 1794 { 1795 if (en) { 1796 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1797 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1798 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1799 } else { 1800 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1801 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1802 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1803 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1804 } 1805 } 1806 1807 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1808 { 1809 struct rtw89_btc *btc = &rtwdev->btc; 1810 const struct rtw89_chip_info *chip = rtwdev->chip; 1811 const struct rtw89_mac_ax_coex coex_params = { 1812 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1813 .direction = RTW89_MAC_AX_COEX_INNER, 1814 }; 1815 1816 /* PTA init */ 1817 rtw89_mac_coex_init(rtwdev, &coex_params); 1818 1819 /* set WL Tx response = Hi-Pri */ 1820 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1821 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1822 1823 /* set rf gnt debug off */ 1824 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1825 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1826 1827 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1828 if (btc->ant_type == BTC_ANT_SHARED) { 1829 rtw8852a_set_trx_mask(rtwdev, 1830 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1831 rtw8852a_set_trx_mask(rtwdev, 1832 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1833 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1834 rtw8852a_set_trx_mask(rtwdev, 1835 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1836 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1837 rtw8852a_set_trx_mask(rtwdev, 1838 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1839 rtw8852a_set_trx_mask(rtwdev, 1840 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1841 } 1842 1843 /* set PTA break table */ 1844 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1845 1846 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1847 rtw89_write32_set(rtwdev, 1848 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1849 btc->cx.wl.status.map.init_ok = true; 1850 } 1851 1852 static 1853 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1854 { 1855 u32 bitmap = 0; 1856 u32 reg = 0; 1857 1858 switch (map) { 1859 case BTC_PRI_MASK_TX_RESP: 1860 reg = R_BTC_BT_COEX_MSK_TABLE; 1861 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1862 break; 1863 case BTC_PRI_MASK_BEACON: 1864 reg = R_AX_WL_PRI_MSK; 1865 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1866 break; 1867 default: 1868 return; 1869 } 1870 1871 if (state) 1872 rtw89_write32_set(rtwdev, reg, bitmap); 1873 else 1874 rtw89_write32_clr(rtwdev, reg, bitmap); 1875 } 1876 1877 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1878 { 1879 return FIELD_GET(GENMASK(15, 0), ctrl); 1880 } 1881 1882 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1883 { 1884 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1885 } 1886 1887 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1888 { 1889 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1890 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1891 1892 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1893 } 1894 1895 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1896 { 1897 return FIELD_GET(GENMASK(31, 16), ctrl); 1898 } 1899 1900 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1901 { 1902 return cur & ~B_AX_TXAGC_BT_EN; 1903 } 1904 1905 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1906 { 1907 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1908 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1909 1910 return ov | iv | B_AX_TXAGC_BT_EN; 1911 } 1912 1913 static void 1914 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1915 { 1916 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1917 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1918 1919 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1920 #define __handle(_case) \ 1921 do { \ 1922 const u32 _reg = __btc_cr_ ## _case; \ 1923 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1924 u32 _cur, _wrt; \ 1925 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1926 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1927 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1928 break; \ 1929 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1930 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1931 _wrt = __do_clr(_val) ? \ 1932 __btc_ctrl_rst_ ## _case(_cur) : \ 1933 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1934 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1935 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1936 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1937 } while (0) 1938 1939 __handle(all_time); 1940 __handle(gnt_bt); 1941 1942 #undef __handle 1943 #undef __do_clr 1944 } 1945 1946 static 1947 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1948 { 1949 /* +6 for compensate offset */ 1950 return clamp_t(s8, val + 6, -100, 0) + 100; 1951 } 1952 1953 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1954 {255, 0, 0, 7}, /* 0 -> original */ 1955 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1956 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1957 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1958 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1959 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1960 {6, 1, 0, 7}, 1961 {13, 1, 0, 7}, 1962 {13, 1, 0, 7} 1963 }; 1964 1965 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1966 {255, 0, 0, 7}, /* 0 -> original */ 1967 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1968 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1969 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1970 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1971 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1972 {255, 1, 0, 7}, 1973 {255, 1, 0, 7}, 1974 {255, 1, 0, 7} 1975 }; 1976 1977 static const 1978 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1979 static const 1980 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1981 1982 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1983 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1984 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1985 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1986 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1987 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1988 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1989 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1990 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1991 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1992 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1993 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1994 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1995 }; 1996 1997 static 1998 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1999 { 2000 struct rtw89_btc *btc = &rtwdev->btc; 2001 const struct rtw89_btc_ver *ver = btc->ver; 2002 struct rtw89_btc_cx *cx = &btc->cx; 2003 u32 val; 2004 2005 if (ver->fcxbtcrpt != 1) 2006 return; 2007 2008 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 2009 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 2010 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 2011 2012 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 2013 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 2014 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 2015 2016 /* clock-gate off before reset counter*/ 2017 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2018 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2019 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2020 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2021 } 2022 2023 static 2024 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2025 { 2026 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2027 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2028 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 2029 2030 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2031 if (state) 2032 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2033 RFREG_MASK, 0xa2d7c); 2034 else 2035 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2036 RFREG_MASK, 0xa2020); 2037 2038 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2039 } 2040 2041 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2042 { 2043 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2044 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2045 * To improve BT ACI in co-rx 2046 */ 2047 2048 switch (level) { 2049 case 0: /* default */ 2050 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2051 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2052 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2053 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2054 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2055 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2056 break; 2057 case 1: /* Fix LNA2=5 */ 2058 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2059 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2060 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2061 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2062 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2063 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2064 break; 2065 } 2066 } 2067 2068 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2069 { 2070 struct rtw89_btc *btc = &rtwdev->btc; 2071 2072 switch (level) { 2073 case 0: /* original */ 2074 default: 2075 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2076 btc->dm.wl_lna2 = 0; 2077 break; 2078 case 1: /* for FDD free-run */ 2079 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2080 btc->dm.wl_lna2 = 0; 2081 break; 2082 case 2: /* for BTG Co-Rx*/ 2083 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2084 btc->dm.wl_lna2 = 1; 2085 break; 2086 } 2087 2088 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2089 } 2090 2091 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2092 struct rtw89_rx_phy_ppdu *phy_ppdu, 2093 struct ieee80211_rx_status *status) 2094 { 2095 u16 chan = phy_ppdu->chan_idx; 2096 u8 band; 2097 2098 if (chan == 0) 2099 return; 2100 2101 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2102 status->freq = ieee80211_channel_to_frequency(chan, band); 2103 status->band = band; 2104 } 2105 2106 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2107 struct rtw89_rx_phy_ppdu *phy_ppdu, 2108 struct ieee80211_rx_status *status) 2109 { 2110 u8 path; 2111 u8 *rx_power = phy_ppdu->rssi; 2112 u8 raw; 2113 2114 if (!status->signal) { 2115 if (phy_ppdu->to_self) 2116 raw = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 2117 else 2118 raw = max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 2119 2120 status->signal = RTW89_RSSI_RAW_TO_DBM(raw); 2121 } 2122 2123 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2124 status->chains |= BIT(path); 2125 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2126 } 2127 if (phy_ppdu->valid) 2128 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2129 } 2130 2131 #ifdef CONFIG_PM 2132 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2133 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2134 .n_patterns = RTW89_MAX_PATTERN_NUM, 2135 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2136 .pattern_min_len = 1, 2137 }; 2138 #endif 2139 2140 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2141 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2142 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2143 .bb_preinit = NULL, 2144 .bb_postinit = NULL, 2145 .bb_reset = rtw8852a_bb_reset, 2146 .bb_sethw = rtw8852a_bb_sethw, 2147 .read_rf = rtw89_phy_read_rf, 2148 .write_rf = rtw89_phy_write_rf, 2149 .set_channel = rtw8852a_set_channel, 2150 .set_channel_help = rtw8852a_set_channel_help, 2151 .read_efuse = rtw8852a_read_efuse, 2152 .read_phycap = rtw8852a_read_phycap, 2153 .fem_setup = rtw8852a_fem_setup, 2154 .rfe_gpio = NULL, 2155 .rfk_hw_init = NULL, 2156 .rfk_init = rtw8852a_rfk_init, 2157 .rfk_init_late = NULL, 2158 .rfk_channel = rtw8852a_rfk_channel, 2159 .rfk_band_changed = rtw8852a_rfk_band_changed, 2160 .rfk_scan = rtw8852a_rfk_scan, 2161 .rfk_track = rtw8852a_rfk_track, 2162 .power_trim = rtw8852a_power_trim, 2163 .set_txpwr = rtw8852a_set_txpwr, 2164 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2165 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2166 .get_thermal = rtw8852a_get_thermal, 2167 .chan_to_rf18_val = NULL, 2168 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx, 2169 .query_ppdu = rtw8852a_query_ppdu, 2170 .convert_rpl_to_rssi = NULL, 2171 .phy_rpt_to_rssi = NULL, 2172 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx, 2173 .cfg_txrx_path = NULL, 2174 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2175 .digital_pwr_comp = NULL, 2176 .pwr_on_func = NULL, 2177 .pwr_off_func = NULL, 2178 .query_rxdesc = rtw89_core_query_rxdesc, 2179 .fill_txdesc = rtw89_core_fill_txdesc, 2180 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2181 .get_ch_dma = rtw89_core_get_ch_dma, 2182 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2183 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2184 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2185 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2186 .h2c_dctl_sec_cam = NULL, 2187 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2188 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2189 .h2c_ampdu_cmac_tbl = NULL, 2190 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl, 2191 .h2c_punctured_cmac_tbl = NULL, 2192 .h2c_default_dmac_tbl = NULL, 2193 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2194 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2195 2196 .btc_set_rfe = rtw8852a_btc_set_rfe, 2197 .btc_init_cfg = rtw8852a_btc_init_cfg, 2198 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2199 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2200 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2201 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2202 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2203 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2204 .btc_set_policy = rtw89_btc_set_policy, 2205 }; 2206 2207 const struct rtw89_chip_info rtw8852a_chip_info = { 2208 .chip_id = RTL8852A, 2209 .chip_gen = RTW89_CHIP_AX, 2210 .ops = &rtw8852a_chip_ops, 2211 .mac_def = &rtw89_mac_gen_ax, 2212 .phy_def = &rtw89_phy_gen_ax, 2213 .fw_basename = RTW8852A_FW_BASENAME, 2214 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2215 .try_ce_fw = false, 2216 .bbmcu_nr = 0, 2217 .needed_fw_elms = 0, 2218 .fw_blacklist = NULL, 2219 .fifo_size = 458752, 2220 .small_fifo_size = false, 2221 .dle_scc_rsvd_size = 0, 2222 .max_amsdu_limit = 3500, 2223 .dis_2g_40m_ul_ofdma = true, 2224 .rsvd_ple_ofst = 0x6f800, 2225 .hfc_param_ini = {rtw8852a_hfc_param_ini_pcie, NULL, NULL}, 2226 .dle_mem = {rtw8852a_dle_mem_pcie, NULL, NULL, NULL}, 2227 .wde_qempty_acq_grpnum = 16, 2228 .wde_qempty_mgq_grpsel = 16, 2229 .rf_base_addr = {0xc000, 0xd000}, 2230 .thermal_th = {0x32, 0x35}, 2231 .pwr_on_seq = pwr_on_seq_8852a, 2232 .pwr_off_seq = pwr_off_seq_8852a, 2233 .bb_table = &rtw89_8852a_phy_bb_table, 2234 .bb_gain_table = NULL, 2235 .rf_table = {&rtw89_8852a_phy_radioa_table, 2236 &rtw89_8852a_phy_radiob_table,}, 2237 .nctl_table = &rtw89_8852a_phy_nctl_table, 2238 .nctl_post_table = NULL, 2239 .dflt_parms = &rtw89_8852a_dflt_parms, 2240 .rfe_parms_conf = NULL, 2241 .txpwr_factor_bb = 3, 2242 .txpwr_factor_rf = 2, 2243 .txpwr_factor_mac = 1, 2244 .dig_table = &rtw89_8852a_phy_dig_table, 2245 .dig_regs = &rtw8852a_dig_regs, 2246 .tssi_dbw_table = NULL, 2247 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2248 .support_link_num = 0, 2249 .support_chanctx_num = 1, 2250 .support_rnr = false, 2251 .support_bands = BIT(NL80211_BAND_2GHZ) | 2252 BIT(NL80211_BAND_5GHZ), 2253 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2254 BIT(NL80211_CHAN_WIDTH_40) | 2255 BIT(NL80211_CHAN_WIDTH_80), 2256 .support_unii4 = false, 2257 .support_ant_gain = false, 2258 .support_tas = false, 2259 .support_sar_by_ant = false, 2260 .support_noise = true, 2261 .ul_tb_waveform_ctrl = false, 2262 .ul_tb_pwr_diff = false, 2263 .rx_freq_frome_ie = true, 2264 .hw_sec_hdr = false, 2265 .hw_mgmt_tx_encrypt = false, 2266 .hw_tkip_crypto = false, 2267 .hw_mlo_bmc_crypto = false, 2268 .rf_path_num = 2, 2269 .tx_nss = 2, 2270 .rx_nss = 2, 2271 .acam_num = 128, 2272 .bcam_num = 10, 2273 .scam_num = 128, 2274 .bacam_num = 2, 2275 .bacam_dynamic_num = 4, 2276 .bacam_ver = RTW89_BACAM_V0, 2277 .ppdu_max_usr = 4, 2278 .sec_ctrl_efuse_size = 4, 2279 .physical_efuse_size = 1216, 2280 .logical_efuse_size = 1536, 2281 .limit_efuse_size = 1152, 2282 .dav_phy_efuse_size = 0, 2283 .dav_log_efuse_size = 0, 2284 .efuse_blocks = NULL, 2285 .phycap_addr = 0x580, 2286 .phycap_size = 128, 2287 .para_ver = 0x0, 2288 .wlcx_desired = 0x06000000, 2289 .scbd = 0x1, 2290 .mailbox = 0x1, 2291 2292 .afh_guard_ch = 6, 2293 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2294 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2295 .rssi_tol = 2, 2296 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2297 .mon_reg = rtw89_btc_8852a_mon_reg, 2298 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2299 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2300 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2301 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2302 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2303 BIT(RTW89_PS_MODE_CLK_GATED) | 2304 BIT(RTW89_PS_MODE_PWR_GATED), 2305 .low_power_hci_modes = 0, 2306 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2307 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2308 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2309 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2310 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2311 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2312 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2313 .h2c_regs = rtw8852a_h2c_regs, 2314 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2315 .c2h_regs = rtw8852a_c2h_regs, 2316 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2317 .page_regs = &rtw8852a_page_regs, 2318 .wow_reason_reg = rtw8852a_wow_wakeup_regs, 2319 .cfo_src_fd = false, 2320 .cfo_hw_comp = false, 2321 .dcfo_comp = &rtw8852a_dcfo_comp, 2322 .dcfo_comp_sft = 10, 2323 .nhm_report = &rtw8852a_nhm_rpt, 2324 .nhm_th = &rtw8852a_nhm_th, 2325 .imr_info = &rtw8852a_imr_info, 2326 .imr_dmac_table = NULL, 2327 .imr_cmac_table = NULL, 2328 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2329 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2330 .bss_clr_map_reg = R_BSS_CLR_MAP, 2331 .rfkill_init = &rtw8852a_rfkill_regs, 2332 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9}, 2333 .dma_ch_mask = 0, 2334 .edcca_regs = &rtw8852a_edcca_regs, 2335 #ifdef CONFIG_PM 2336 .wowlan_stub = &rtw_wowlan_stub_8852a, 2337 #endif 2338 .xtal_info = &rtw8852a_xtal_info, 2339 }; 2340 EXPORT_SYMBOL(rtw8852a_chip_info); 2341 2342 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2343 MODULE_AUTHOR("Realtek Corporation"); 2344 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2345 MODULE_LICENSE("Dual BSD/GPL"); 2346