1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "mac.h" 7 #include "phy.h" 8 #include "reg.h" 9 #include "rtw8852a.h" 10 #include "rtw8852a_rfk.h" 11 #include "rtw8852a_table.h" 12 #include "txrx.h" 13 14 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 15 {128, 1896, grp_0}, /* ACH 0 */ 16 {128, 1896, grp_0}, /* ACH 1 */ 17 {128, 1896, grp_0}, /* ACH 2 */ 18 {128, 1896, grp_0}, /* ACH 3 */ 19 {128, 1896, grp_1}, /* ACH 4 */ 20 {128, 1896, grp_1}, /* ACH 5 */ 21 {128, 1896, grp_1}, /* ACH 6 */ 22 {128, 1896, grp_1}, /* ACH 7 */ 23 {32, 1896, grp_0}, /* B0MGQ */ 24 {128, 1896, grp_0}, /* B0HIQ */ 25 {32, 1896, grp_1}, /* B1MGQ */ 26 {128, 1896, grp_1}, /* B1HIQ */ 27 {40, 0, 0} /* FWCMDQ */ 28 }; 29 30 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 31 1896, /* Group 0 */ 32 1896, /* Group 1 */ 33 3792, /* Public Max */ 34 0 /* WP threshold */ 35 }; 36 37 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 38 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 39 &rtw89_hfc_preccfg_pcie, RTW89_HCIFC_POH}, 40 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_hfc_preccfg_pcie, 41 RTW89_HCIFC_POH}, 42 [RTW89_QTA_INVALID] = {NULL}, 43 }; 44 45 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 46 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_wde_size0, &rtw89_ple_size0, 47 &rtw89_wde_qt0, &rtw89_wde_qt0, &rtw89_ple_qt4, 48 &rtw89_ple_qt5}, 49 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_wde_size4, &rtw89_ple_size4, 50 &rtw89_wde_qt4, &rtw89_wde_qt4, &rtw89_ple_qt13, 51 &rtw89_ple_qt13}, 52 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 53 NULL}, 54 }; 55 56 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 57 {0x44AC, 0x00000000}, 58 {0x44B0, 0x00000000}, 59 {0x44B4, 0x00000000}, 60 {0x44B8, 0x00000000}, 61 {0x44BC, 0x00000000}, 62 {0x44C0, 0x00000000}, 63 {0x44C4, 0x00000000}, 64 {0x44C8, 0x00000000}, 65 {0x44CC, 0x00000000}, 66 {0x44D0, 0x00000000}, 67 {0x44D4, 0x00000000}, 68 {0x44D8, 0x00000000}, 69 {0x44DC, 0x00000000}, 70 {0x44E0, 0x00000000}, 71 {0x44E4, 0x00000000}, 72 {0x44E8, 0x00000000}, 73 {0x44EC, 0x00000000}, 74 {0x44F0, 0x00000000}, 75 {0x44F4, 0x00000000}, 76 {0x44F8, 0x00000000}, 77 {0x44FC, 0x00000000}, 78 {0x4500, 0x00000000}, 79 {0x4504, 0x00000000}, 80 {0x4508, 0x00000000}, 81 {0x450C, 0x00000000}, 82 {0x4510, 0x00000000}, 83 {0x4514, 0x00000000}, 84 {0x4518, 0x00000000}, 85 {0x451C, 0x00000000}, 86 {0x4520, 0x00000000}, 87 {0x4524, 0x00000000}, 88 {0x4528, 0x00000000}, 89 {0x452C, 0x00000000}, 90 {0x4530, 0x4E1F3E81}, 91 {0x4534, 0x00000000}, 92 {0x4538, 0x0000005A}, 93 {0x453C, 0x00000000}, 94 {0x4540, 0x00000000}, 95 {0x4544, 0x00000000}, 96 {0x4548, 0x00000000}, 97 {0x454C, 0x00000000}, 98 {0x4550, 0x00000000}, 99 {0x4554, 0x00000000}, 100 {0x4558, 0x00000000}, 101 {0x455C, 0x00000000}, 102 {0x4560, 0x4060001A}, 103 {0x4564, 0x40000000}, 104 {0x4568, 0x00000000}, 105 {0x456C, 0x00000000}, 106 {0x4570, 0x04000007}, 107 {0x4574, 0x0000DC87}, 108 {0x4578, 0x00000BAB}, 109 {0x457C, 0x03E00000}, 110 {0x4580, 0x00000048}, 111 {0x4584, 0x00000000}, 112 {0x4588, 0x000003E8}, 113 {0x458C, 0x30000000}, 114 {0x4590, 0x00000000}, 115 {0x4594, 0x10000000}, 116 {0x4598, 0x00000001}, 117 {0x459C, 0x00030000}, 118 {0x45A0, 0x01000000}, 119 {0x45A4, 0x03000200}, 120 {0x45A8, 0xC00001C0}, 121 {0x45AC, 0x78018000}, 122 {0x45B0, 0x80000000}, 123 {0x45B4, 0x01C80600}, 124 {0x45B8, 0x00000002}, 125 {0x4594, 0x10000000} 126 }; 127 128 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 129 {0x4624, GENMASK(20, 14), 0x40}, 130 {0x46f8, GENMASK(20, 14), 0x40}, 131 {0x4674, GENMASK(20, 19), 0x2}, 132 {0x4748, GENMASK(20, 19), 0x2}, 133 {0x4650, GENMASK(14, 10), 0x18}, 134 {0x4724, GENMASK(14, 10), 0x18}, 135 {0x4688, GENMASK(1, 0), 0x3}, 136 {0x475c, GENMASK(1, 0), 0x3}, 137 }; 138 139 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 140 141 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 142 {0x4624, GENMASK(20, 14), 0x1a}, 143 {0x46f8, GENMASK(20, 14), 0x1a}, 144 {0x4674, GENMASK(20, 19), 0x1}, 145 {0x4748, GENMASK(20, 19), 0x1}, 146 {0x4650, GENMASK(14, 10), 0x12}, 147 {0x4724, GENMASK(14, 10), 0x12}, 148 {0x4688, GENMASK(1, 0), 0x0}, 149 {0x475c, GENMASK(1, 0), 0x0}, 150 }; 151 152 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 153 154 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 155 {0x00C6, 156 PWR_CV_MSK_B, 157 PWR_INTF_MSK_PCIE, 158 PWR_BASE_MAC, 159 PWR_CMD_WRITE, BIT(6), BIT(6)}, 160 {0x1086, 161 PWR_CV_MSK_ALL, 162 PWR_INTF_MSK_SDIO, 163 PWR_BASE_MAC, 164 PWR_CMD_WRITE, BIT(0), 0}, 165 {0x1086, 166 PWR_CV_MSK_ALL, 167 PWR_INTF_MSK_SDIO, 168 PWR_BASE_MAC, 169 PWR_CMD_POLL, BIT(1), BIT(1)}, 170 {0x0005, 171 PWR_CV_MSK_ALL, 172 PWR_INTF_MSK_ALL, 173 PWR_BASE_MAC, 174 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 175 {0x0005, 176 PWR_CV_MSK_ALL, 177 PWR_INTF_MSK_ALL, 178 PWR_BASE_MAC, 179 PWR_CMD_WRITE, BIT(7), 0}, 180 {0x0005, 181 PWR_CV_MSK_ALL, 182 PWR_INTF_MSK_ALL, 183 PWR_BASE_MAC, 184 PWR_CMD_WRITE, BIT(2), 0}, 185 {0x0006, 186 PWR_CV_MSK_ALL, 187 PWR_INTF_MSK_ALL, 188 PWR_BASE_MAC, 189 PWR_CMD_POLL, BIT(1), BIT(1)}, 190 {0x0006, 191 PWR_CV_MSK_ALL, 192 PWR_INTF_MSK_ALL, 193 PWR_BASE_MAC, 194 PWR_CMD_WRITE, BIT(0), BIT(0)}, 195 {0x0005, 196 PWR_CV_MSK_ALL, 197 PWR_INTF_MSK_ALL, 198 PWR_BASE_MAC, 199 PWR_CMD_WRITE, BIT(0), BIT(0)}, 200 {0x0005, 201 PWR_CV_MSK_ALL, 202 PWR_INTF_MSK_ALL, 203 PWR_BASE_MAC, 204 PWR_CMD_POLL, BIT(0), 0}, 205 {0x106D, 206 PWR_CV_MSK_B | PWR_CV_MSK_C, 207 PWR_INTF_MSK_USB, 208 PWR_BASE_MAC, 209 PWR_CMD_WRITE, BIT(6), 0}, 210 {0x0088, 211 PWR_CV_MSK_ALL, 212 PWR_INTF_MSK_ALL, 213 PWR_BASE_MAC, 214 PWR_CMD_WRITE, BIT(0), BIT(0)}, 215 {0x0088, 216 PWR_CV_MSK_ALL, 217 PWR_INTF_MSK_ALL, 218 PWR_BASE_MAC, 219 PWR_CMD_WRITE, BIT(0), 0}, 220 {0x0088, 221 PWR_CV_MSK_ALL, 222 PWR_INTF_MSK_ALL, 223 PWR_BASE_MAC, 224 PWR_CMD_WRITE, BIT(0), BIT(0)}, 225 {0x0088, 226 PWR_CV_MSK_ALL, 227 PWR_INTF_MSK_ALL, 228 PWR_BASE_MAC, 229 PWR_CMD_WRITE, BIT(0), 0}, 230 {0x0088, 231 PWR_CV_MSK_ALL, 232 PWR_INTF_MSK_ALL, 233 PWR_BASE_MAC, 234 PWR_CMD_WRITE, BIT(0), BIT(0)}, 235 {0x0083, 236 PWR_CV_MSK_ALL, 237 PWR_INTF_MSK_ALL, 238 PWR_BASE_MAC, 239 PWR_CMD_WRITE, BIT(6), 0}, 240 {0x0080, 241 PWR_CV_MSK_ALL, 242 PWR_INTF_MSK_ALL, 243 PWR_BASE_MAC, 244 PWR_CMD_WRITE, BIT(5), BIT(5)}, 245 {0x0024, 246 PWR_CV_MSK_ALL, 247 PWR_INTF_MSK_ALL, 248 PWR_BASE_MAC, 249 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 250 {0x02A0, 251 PWR_CV_MSK_ALL, 252 PWR_INTF_MSK_ALL, 253 PWR_BASE_MAC, 254 PWR_CMD_WRITE, BIT(1), BIT(1)}, 255 {0x02A2, 256 PWR_CV_MSK_ALL, 257 PWR_INTF_MSK_ALL, 258 PWR_BASE_MAC, 259 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 260 {0x0071, 261 PWR_CV_MSK_ALL, 262 PWR_INTF_MSK_PCIE, 263 PWR_BASE_MAC, 264 PWR_CMD_WRITE, BIT(4), 0}, 265 {0x0010, 266 PWR_CV_MSK_A, 267 PWR_INTF_MSK_PCIE, 268 PWR_BASE_MAC, 269 PWR_CMD_WRITE, BIT(2), BIT(2)}, 270 {0x02A0, 271 PWR_CV_MSK_A, 272 PWR_INTF_MSK_ALL, 273 PWR_BASE_MAC, 274 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 275 {0xFFFF, 276 PWR_CV_MSK_ALL, 277 PWR_INTF_MSK_ALL, 278 0, 279 PWR_CMD_END, 0, 0}, 280 }; 281 282 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 283 {0x02F0, 284 PWR_CV_MSK_ALL, 285 PWR_INTF_MSK_ALL, 286 PWR_BASE_MAC, 287 PWR_CMD_WRITE, 0xFF, 0}, 288 {0x02F1, 289 PWR_CV_MSK_ALL, 290 PWR_INTF_MSK_ALL, 291 PWR_BASE_MAC, 292 PWR_CMD_WRITE, 0xFF, 0}, 293 {0x0006, 294 PWR_CV_MSK_ALL, 295 PWR_INTF_MSK_ALL, 296 PWR_BASE_MAC, 297 PWR_CMD_WRITE, BIT(0), BIT(0)}, 298 {0x0002, 299 PWR_CV_MSK_ALL, 300 PWR_INTF_MSK_ALL, 301 PWR_BASE_MAC, 302 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 303 {0x0082, 304 PWR_CV_MSK_ALL, 305 PWR_INTF_MSK_ALL, 306 PWR_BASE_MAC, 307 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 308 {0x106D, 309 PWR_CV_MSK_B | PWR_CV_MSK_C, 310 PWR_INTF_MSK_USB, 311 PWR_BASE_MAC, 312 PWR_CMD_WRITE, BIT(6), BIT(6)}, 313 {0x0005, 314 PWR_CV_MSK_ALL, 315 PWR_INTF_MSK_ALL, 316 PWR_BASE_MAC, 317 PWR_CMD_WRITE, BIT(1), BIT(1)}, 318 {0x0005, 319 PWR_CV_MSK_ALL, 320 PWR_INTF_MSK_ALL, 321 PWR_BASE_MAC, 322 PWR_CMD_POLL, BIT(1), 0}, 323 {0x0091, 324 PWR_CV_MSK_ALL, 325 PWR_INTF_MSK_PCIE, 326 PWR_BASE_MAC, 327 PWR_CMD_WRITE, BIT(0), 0}, 328 {0x0005, 329 PWR_CV_MSK_ALL, 330 PWR_INTF_MSK_PCIE, 331 PWR_BASE_MAC, 332 PWR_CMD_WRITE, BIT(2), BIT(2)}, 333 {0x0007, 334 PWR_CV_MSK_ALL, 335 PWR_INTF_MSK_USB, 336 PWR_BASE_MAC, 337 PWR_CMD_WRITE, BIT(4), 0}, 338 {0x0007, 339 PWR_CV_MSK_ALL, 340 PWR_INTF_MSK_SDIO, 341 PWR_BASE_MAC, 342 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 343 {0x0005, 344 PWR_CV_MSK_ALL, 345 PWR_INTF_MSK_SDIO, 346 PWR_BASE_MAC, 347 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 348 {0x0005, 349 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 350 PWR_CV_MSK_G, 351 PWR_INTF_MSK_USB, 352 PWR_BASE_MAC, 353 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 354 {0x1086, 355 PWR_CV_MSK_ALL, 356 PWR_INTF_MSK_SDIO, 357 PWR_BASE_MAC, 358 PWR_CMD_WRITE, BIT(0), BIT(0)}, 359 {0x1086, 360 PWR_CV_MSK_ALL, 361 PWR_INTF_MSK_SDIO, 362 PWR_BASE_MAC, 363 PWR_CMD_POLL, BIT(1), 0}, 364 {0xFFFF, 365 PWR_CV_MSK_ALL, 366 PWR_INTF_MSK_ALL, 367 0, 368 PWR_CMD_END, 0, 0}, 369 }; 370 371 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 372 rtw8852a_pwron, NULL 373 }; 374 375 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 376 rtw8852a_pwroff, NULL 377 }; 378 379 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 380 struct rtw8852a_efuse *map) 381 { 382 ether_addr_copy(efuse->addr, map->e.mac_addr); 383 efuse->rfe_type = map->rfe_type; 384 efuse->xtal_cap = map->xtal_k; 385 } 386 387 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 388 struct rtw8852a_efuse *map) 389 { 390 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 391 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 392 u8 i, j; 393 394 tssi->thermal[RF_PATH_A] = map->path_a_therm; 395 tssi->thermal[RF_PATH_B] = map->path_b_therm; 396 397 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 398 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 399 sizeof(ofst[i]->cck_tssi)); 400 401 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 402 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 403 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 404 i, j, tssi->tssi_cck[i][j]); 405 406 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 407 sizeof(ofst[i]->bw40_tssi)); 408 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 409 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 410 411 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 412 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 413 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 414 i, j, tssi->tssi_mcs[i][j]); 415 } 416 } 417 418 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 419 { 420 struct rtw89_efuse *efuse = &rtwdev->efuse; 421 struct rtw8852a_efuse *map; 422 423 map = (struct rtw8852a_efuse *)log_map; 424 425 efuse->country_code[0] = map->country_code[0]; 426 efuse->country_code[1] = map->country_code[1]; 427 rtw8852a_efuse_parsing_tssi(rtwdev, map); 428 429 switch (rtwdev->hci.type) { 430 case RTW89_HCI_TYPE_PCIE: 431 rtw8852ae_efuse_parsing(efuse, map); 432 break; 433 default: 434 return -ENOTSUPP; 435 } 436 437 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 438 439 return 0; 440 } 441 442 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 443 { 444 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 445 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 446 u32 addr = rtwdev->chip->phycap_addr; 447 bool pg = false; 448 u32 ofst; 449 u8 i, j; 450 451 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 452 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 453 /* addrs are in decreasing order */ 454 ofst = tssi_trim_addr[i] - addr - j; 455 tssi->tssi_trim[i][j] = phycap_map[ofst]; 456 457 if (phycap_map[ofst] != 0xff) 458 pg = true; 459 } 460 } 461 462 if (!pg) { 463 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 464 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 465 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 466 } 467 468 for (i = 0; i < RF_PATH_NUM_8852A; i++) 469 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 470 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 471 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 472 i, j, tssi->tssi_trim[i][j], 473 tssi_trim_addr[i] - j); 474 } 475 476 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 477 u8 *phycap_map) 478 { 479 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 480 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 481 u32 addr = rtwdev->chip->phycap_addr; 482 u8 i; 483 484 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 485 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 486 487 rtw89_debug(rtwdev, RTW89_DBG_RFK, 488 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 489 i, info->thermal_trim[i]); 490 491 if (info->thermal_trim[i] != 0xff) 492 info->pg_thermal_trim = true; 493 } 494 } 495 496 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 497 { 498 #define __thm_setting(raw) \ 499 ({ \ 500 u8 __v = (raw); \ 501 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 502 }) 503 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 504 u8 i, val; 505 506 if (!info->pg_thermal_trim) { 507 rtw89_debug(rtwdev, RTW89_DBG_RFK, 508 "[THERMAL][TRIM] no PG, do nothing\n"); 509 510 return; 511 } 512 513 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 514 val = __thm_setting(info->thermal_trim[i]); 515 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 516 517 rtw89_debug(rtwdev, RTW89_DBG_RFK, 518 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 519 i, val); 520 } 521 #undef __thm_setting 522 } 523 524 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 525 u8 *phycap_map) 526 { 527 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 528 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 529 u32 addr = rtwdev->chip->phycap_addr; 530 u8 i; 531 532 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 533 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 534 535 rtw89_debug(rtwdev, RTW89_DBG_RFK, 536 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 537 i, info->pa_bias_trim[i]); 538 539 if (info->pa_bias_trim[i] != 0xff) 540 info->pg_pa_bias_trim = true; 541 } 542 } 543 544 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 545 { 546 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 547 u8 pabias_2g, pabias_5g; 548 u8 i; 549 550 if (!info->pg_pa_bias_trim) { 551 rtw89_debug(rtwdev, RTW89_DBG_RFK, 552 "[PA_BIAS][TRIM] no PG, do nothing\n"); 553 554 return; 555 } 556 557 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 558 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 559 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 560 561 rtw89_debug(rtwdev, RTW89_DBG_RFK, 562 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 563 i, pabias_2g, pabias_5g); 564 565 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 566 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 567 } 568 } 569 570 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 571 { 572 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 573 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 574 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 575 576 return 0; 577 } 578 579 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 580 { 581 rtw8852a_thermal_trim(rtwdev); 582 rtw8852a_pa_bias_trim(rtwdev); 583 } 584 585 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 586 struct rtw89_channel_params *param, 587 u8 mac_idx) 588 { 589 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 590 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 591 mac_idx); 592 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 593 u8 txsc20 = 0, txsc40 = 0; 594 595 switch (param->bandwidth) { 596 case RTW89_CHANNEL_WIDTH_80: 597 txsc40 = rtw89_phy_get_txsc(rtwdev, param, 598 RTW89_CHANNEL_WIDTH_40); 599 fallthrough; 600 case RTW89_CHANNEL_WIDTH_40: 601 txsc20 = rtw89_phy_get_txsc(rtwdev, param, 602 RTW89_CHANNEL_WIDTH_20); 603 break; 604 default: 605 break; 606 } 607 608 switch (param->bandwidth) { 609 case RTW89_CHANNEL_WIDTH_80: 610 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 611 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 612 break; 613 case RTW89_CHANNEL_WIDTH_40: 614 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 615 rtw89_write32(rtwdev, sub_carr, txsc20); 616 break; 617 case RTW89_CHANNEL_WIDTH_20: 618 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 619 rtw89_write32(rtwdev, sub_carr, 0); 620 break; 621 default: 622 break; 623 } 624 625 if (param->center_chan > 14) 626 rtw89_write8_set(rtwdev, chk_rate, 627 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 628 else 629 rtw89_write8_clr(rtwdev, chk_rate, 630 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 631 } 632 633 static const u32 rtw8852a_sco_barker_threshold[14] = { 634 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 635 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 636 }; 637 638 static const u32 rtw8852a_sco_cck_threshold[14] = { 639 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 640 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 641 }; 642 643 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 644 u8 primary_ch, enum rtw89_bandwidth bw) 645 { 646 u8 ch_element; 647 648 if (bw == RTW89_CHANNEL_WIDTH_20) { 649 ch_element = central_ch - 1; 650 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 651 if (primary_ch == 1) 652 ch_element = central_ch - 1 + 2; 653 else 654 ch_element = central_ch - 1 - 2; 655 } else { 656 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 657 return -EINVAL; 658 } 659 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 660 rtw8852a_sco_barker_threshold[ch_element]); 661 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 662 rtw8852a_sco_cck_threshold[ch_element]); 663 664 return 0; 665 } 666 667 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 668 u8 path) 669 { 670 u32 val; 671 672 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 673 if (val == INV_RF_DATA) { 674 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 675 return; 676 } 677 val &= ~0x303ff; 678 val |= central_ch; 679 if (central_ch > 14) 680 val |= (BIT(16) | BIT(8)); 681 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 682 } 683 684 static u8 rtw8852a_sco_mapping(u8 central_ch) 685 { 686 if (central_ch == 1) 687 return 109; 688 else if (central_ch >= 2 && central_ch <= 6) 689 return 108; 690 else if (central_ch >= 7 && central_ch <= 10) 691 return 107; 692 else if (central_ch >= 11 && central_ch <= 14) 693 return 106; 694 else if (central_ch == 36 || central_ch == 38) 695 return 51; 696 else if (central_ch >= 40 && central_ch <= 58) 697 return 50; 698 else if (central_ch >= 60 && central_ch <= 64) 699 return 49; 700 else if (central_ch == 100 || central_ch == 102) 701 return 48; 702 else if (central_ch >= 104 && central_ch <= 126) 703 return 47; 704 else if (central_ch >= 128 && central_ch <= 151) 705 return 46; 706 else if (central_ch >= 153 && central_ch <= 177) 707 return 45; 708 else 709 return 0; 710 } 711 712 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 713 enum rtw89_phy_idx phy_idx) 714 { 715 u8 sco_comp; 716 bool is_2g = central_ch <= 14; 717 718 if (phy_idx == RTW89_PHY_0) { 719 /* Path A */ 720 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 721 if (is_2g) 722 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 723 B_PATH0_TIA_ERR_G1_SEL, 1, 724 phy_idx); 725 else 726 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 727 B_PATH0_TIA_ERR_G1_SEL, 0, 728 phy_idx); 729 730 /* Path B */ 731 if (!rtwdev->dbcc_en) { 732 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 733 if (is_2g) 734 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 735 B_P1_MODE_SEL, 736 1, phy_idx); 737 else 738 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 739 B_P1_MODE_SEL, 740 0, phy_idx); 741 } else { 742 if (is_2g) 743 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 744 B_2P4G_BAND_SEL); 745 else 746 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 747 B_2P4G_BAND_SEL); 748 } 749 /* SCO compensate FC setting */ 750 sco_comp = rtw8852a_sco_mapping(central_ch); 751 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 752 sco_comp, phy_idx); 753 } else { 754 /* Path B */ 755 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 756 if (is_2g) 757 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 758 B_P1_MODE_SEL, 759 1, phy_idx); 760 else 761 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 762 B_P1_MODE_SEL, 763 0, phy_idx); 764 /* SCO compensate FC setting */ 765 sco_comp = rtw8852a_sco_mapping(central_ch); 766 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 767 sco_comp, phy_idx); 768 } 769 770 /* Band edge */ 771 if (is_2g) 772 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 773 phy_idx); 774 else 775 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 776 phy_idx); 777 778 /* CCK parameters */ 779 if (central_ch == 14) { 780 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 781 0x3b13ff); 782 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 783 0x1c42de); 784 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 785 0xfdb0ad); 786 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 787 0xf60f6e); 788 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 789 0xfd8f92); 790 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 791 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 792 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 793 0xfff00a); 794 } else { 795 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 796 0x3d23ff); 797 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 798 0x29b354); 799 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 800 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 801 0xfdb053); 802 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 803 0xf86f9a); 804 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 805 0xfaef92); 806 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 807 0xfe5fcc); 808 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 809 0xffdff5); 810 } 811 } 812 813 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 814 { 815 u32 val = 0; 816 u32 adc_sel[2] = {0x12d0, 0x32d0}; 817 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 818 819 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 820 if (val == INV_RF_DATA) { 821 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 822 return; 823 } 824 val &= ~(BIT(11) | BIT(10)); 825 switch (bw) { 826 case RTW89_CHANNEL_WIDTH_5: 827 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 828 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 829 val |= (BIT(11) | BIT(10)); 830 break; 831 case RTW89_CHANNEL_WIDTH_10: 832 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 833 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 834 val |= (BIT(11) | BIT(10)); 835 break; 836 case RTW89_CHANNEL_WIDTH_20: 837 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 838 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 839 val |= (BIT(11) | BIT(10)); 840 break; 841 case RTW89_CHANNEL_WIDTH_40: 842 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 843 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 844 val |= BIT(11); 845 break; 846 case RTW89_CHANNEL_WIDTH_80: 847 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 848 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 849 val |= BIT(10); 850 break; 851 default: 852 rtw89_warn(rtwdev, "Fail to set ADC\n"); 853 } 854 855 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 856 } 857 858 static void 859 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 860 enum rtw89_phy_idx phy_idx) 861 { 862 /* Switch bandwidth */ 863 switch (bw) { 864 case RTW89_CHANNEL_WIDTH_5: 865 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 866 phy_idx); 867 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 868 phy_idx); 869 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 870 0x0, phy_idx); 871 break; 872 case RTW89_CHANNEL_WIDTH_10: 873 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 874 phy_idx); 875 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 876 phy_idx); 877 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 878 0x0, phy_idx); 879 break; 880 case RTW89_CHANNEL_WIDTH_20: 881 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 882 phy_idx); 883 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 884 phy_idx); 885 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 886 0x0, phy_idx); 887 break; 888 case RTW89_CHANNEL_WIDTH_40: 889 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 890 phy_idx); 891 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 892 phy_idx); 893 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 894 pri_ch, 895 phy_idx); 896 if (pri_ch == RTW89_SC_20_UPPER) 897 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 898 else 899 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 900 break; 901 case RTW89_CHANNEL_WIDTH_80: 902 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 903 phy_idx); 904 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 905 phy_idx); 906 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 907 pri_ch, 908 phy_idx); 909 break; 910 default: 911 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 912 pri_ch); 913 } 914 915 if (phy_idx == RTW89_PHY_0) { 916 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 917 if (!rtwdev->dbcc_en) 918 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 919 } else { 920 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 921 } 922 } 923 924 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 925 { 926 if (central_ch == 153) { 927 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 928 0x210); 929 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 930 0x210); 931 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); 932 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 933 B_P0_NBIIDX_NOTCH_EN, 0x1); 934 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 935 B_P1_NBIIDX_NOTCH_EN, 0x1); 936 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 937 0x1); 938 } else if (central_ch == 151) { 939 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 940 0x210); 941 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 942 0x210); 943 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); 944 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 945 B_P0_NBIIDX_NOTCH_EN, 0x1); 946 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 947 B_P1_NBIIDX_NOTCH_EN, 0x1); 948 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 949 0x1); 950 } else if (central_ch == 155) { 951 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 952 0x2d0); 953 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 954 0x2d0); 955 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); 956 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 957 B_P0_NBIIDX_NOTCH_EN, 0x1); 958 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 959 B_P1_NBIIDX_NOTCH_EN, 0x1); 960 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 961 0x1); 962 } else { 963 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 964 B_P0_NBIIDX_NOTCH_EN, 0x0); 965 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 966 B_P1_NBIIDX_NOTCH_EN, 0x0); 967 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 968 0x0); 969 } 970 } 971 972 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 973 enum rtw89_phy_idx phy_idx) 974 { 975 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 976 phy_idx); 977 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 978 phy_idx); 979 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 980 phy_idx); 981 } 982 983 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 984 enum rtw89_phy_idx phy_idx, bool en) 985 { 986 if (en) 987 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 988 1, 989 phy_idx); 990 else 991 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 992 0, 993 phy_idx); 994 } 995 996 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 997 enum rtw89_phy_idx phy_idx) 998 { 999 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1000 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1001 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1002 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1003 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1004 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1005 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1006 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1007 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1008 } 1009 1010 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1011 enum rtw89_phy_idx phy_idx) 1012 { 1013 u32 addr; 1014 1015 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1016 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1017 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1018 } 1019 1020 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1021 { 1022 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1023 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1024 1025 if (rtwdev->hal.cv <= CHIP_CCV) { 1026 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1027 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1028 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F); 1029 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1030 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1031 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1032 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1033 } 1034 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1035 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1036 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1037 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1038 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1039 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1040 1041 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1042 } 1043 1044 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1045 enum rtw89_phy_idx phy_idx) 1046 { 1047 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1048 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1049 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1050 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1051 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1052 udelay(1); 1053 } 1054 1055 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1056 struct rtw89_channel_params *param, 1057 enum rtw89_phy_idx phy_idx) 1058 { 1059 bool cck_en = param->center_chan <= 14; 1060 u8 pri_ch_idx = param->pri_ch_idx; 1061 1062 if (cck_en) 1063 rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan, 1064 param->primary_chan, param->bandwidth); 1065 1066 rtw8852a_ctrl_ch(rtwdev, param->center_chan, phy_idx); 1067 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx); 1068 if (cck_en) { 1069 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1070 } else { 1071 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1072 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1073 } 1074 rtw8852a_spur_elimination(rtwdev, param->center_chan); 1075 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1076 param->primary_chan); 1077 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1078 } 1079 1080 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1081 struct rtw89_channel_params *params) 1082 { 1083 rtw8852a_set_channel_mac(rtwdev, params, RTW89_MAC_0); 1084 rtw8852a_set_channel_bb(rtwdev, params, RTW89_PHY_0); 1085 } 1086 1087 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1088 { 1089 if (en) 1090 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1091 else 1092 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1093 } 1094 1095 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1096 enum rtw89_rf_path path) 1097 { 1098 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1099 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1100 1101 if (en) { 1102 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1103 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1104 } else { 1105 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1106 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1107 } 1108 } 1109 1110 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1111 u8 phy_idx) 1112 { 1113 if (!rtwdev->dbcc_en) { 1114 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1115 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1116 } else { 1117 if (phy_idx == RTW89_PHY_0) 1118 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1119 else 1120 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1121 } 1122 } 1123 1124 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1125 { 1126 if (en) 1127 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1128 0x0); 1129 else 1130 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1131 0xf); 1132 } 1133 1134 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1135 struct rtw89_channel_help_params *p) 1136 { 1137 u8 phy_idx = RTW89_PHY_0; 1138 1139 if (enter) { 1140 rtw89_mac_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1141 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1142 rtw8852a_dfs_en(rtwdev, false); 1143 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1144 rtw8852a_adc_en(rtwdev, false); 1145 fsleep(40); 1146 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1147 } else { 1148 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1149 rtw8852a_adc_en(rtwdev, true); 1150 rtw8852a_dfs_en(rtwdev, true); 1151 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1152 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1153 rtw89_mac_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1154 } 1155 } 1156 1157 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1158 { 1159 struct rtw89_efuse *efuse = &rtwdev->efuse; 1160 1161 switch (efuse->rfe_type) { 1162 case 11: 1163 case 12: 1164 case 17: 1165 case 18: 1166 case 51: 1167 case 53: 1168 rtwdev->fem.epa_2g = true; 1169 rtwdev->fem.elna_2g = true; 1170 fallthrough; 1171 case 9: 1172 case 10: 1173 case 15: 1174 case 16: 1175 rtwdev->fem.epa_5g = true; 1176 rtwdev->fem.elna_5g = true; 1177 break; 1178 default: 1179 break; 1180 } 1181 } 1182 1183 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1184 { 1185 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1186 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1187 1188 rtw8852a_rck(rtwdev); 1189 rtw8852a_dack(rtwdev); 1190 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1191 } 1192 1193 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1194 { 1195 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1196 1197 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1198 rtw8852a_iqk(rtwdev, phy_idx); 1199 rtw8852a_tssi(rtwdev, phy_idx); 1200 rtw8852a_dpk(rtwdev, phy_idx); 1201 } 1202 1203 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev) 1204 { 1205 rtw8852a_tssi_scan(rtwdev, RTW89_PHY_0); 1206 } 1207 1208 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1209 { 1210 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1211 } 1212 1213 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1214 { 1215 rtw8852a_dpk_track(rtwdev); 1216 rtw8852a_iqk_track(rtwdev); 1217 rtw8852a_tssi_track(rtwdev); 1218 } 1219 1220 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1221 enum rtw89_phy_idx phy_idx, s16 ref) 1222 { 1223 s8 ofst_int = 0; 1224 u8 base_cw_0db = 0x27; 1225 u16 tssi_16dbm_cw = 0x12c; 1226 s16 pwr_s10_3 = 0; 1227 s16 rf_pwr_cw = 0; 1228 u16 bb_pwr_cw = 0; 1229 u32 pwr_cw = 0; 1230 u32 tssi_ofst_cw = 0; 1231 1232 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1233 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1234 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1235 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1236 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1237 1238 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1239 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1240 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1241 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1242 1243 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1244 } 1245 1246 static 1247 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1248 s16 pw_ofst, enum rtw89_mac_idx mac_idx) 1249 { 1250 s32 val_1t = 0; 1251 s32 val_2t = 0; 1252 u32 reg; 1253 1254 if (pw_ofst < -16 || pw_ofst > 15) { 1255 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1256 pw_ofst); 1257 return; 1258 } 1259 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); 1260 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1261 val_1t = (s32)pw_ofst; 1262 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1263 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1264 val_2t = max(val_1t - 3, -16); 1265 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1266 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1267 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1268 val_1t, val_2t); 1269 } 1270 1271 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1272 enum rtw89_phy_idx phy_idx) 1273 { 1274 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1275 const u32 mask = 0x7FFFFFF; 1276 const u8 ofst_ofdm = 0x4; 1277 const u8 ofst_cck = 0x8; 1278 s16 ref_ofdm = 0; 1279 s16 ref_cck = 0; 1280 u32 val; 1281 u8 i; 1282 1283 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1284 1285 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1286 GENMASK(27, 10), 0x0); 1287 1288 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1289 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1290 1291 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1292 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1293 phy_idx); 1294 1295 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1296 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1297 1298 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1299 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1300 phy_idx); 1301 } 1302 1303 static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, 1304 enum rtw89_phy_idx phy_idx) 1305 { 1306 u8 ch = rtwdev->hal.current_channel; 1307 static const u8 rs[] = { 1308 RTW89_RS_CCK, 1309 RTW89_RS_OFDM, 1310 RTW89_RS_MCS, 1311 RTW89_RS_HEDCM, 1312 }; 1313 s8 tmp; 1314 u8 i, j; 1315 u32 val, shf, addr = R_AX_PWR_BY_RATE; 1316 struct rtw89_rate_desc cur; 1317 1318 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1319 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 1320 1321 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 1322 for (i = 0; i < ARRAY_SIZE(rs); i++) { 1323 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 1324 continue; 1325 1326 val = 0; 1327 cur.rs = rs[i]; 1328 1329 for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { 1330 cur.idx = j; 1331 shf = (j % 4) * 8; 1332 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur); 1333 val |= (tmp << shf); 1334 1335 if ((j + 1) % 4) 1336 continue; 1337 1338 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1339 val = 0; 1340 addr += 4; 1341 } 1342 } 1343 } 1344 } 1345 1346 static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, 1347 enum rtw89_phy_idx phy_idx) 1348 { 1349 struct rtw89_rate_desc desc = { 1350 .nss = RTW89_NSS_1, 1351 .rs = RTW89_RS_OFFSET, 1352 }; 1353 u32 val = 0; 1354 s8 v; 1355 1356 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 1357 1358 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { 1359 v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc); 1360 val |= ((v & 0xf) << (4 * desc.idx)); 1361 } 1362 1363 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 1364 GENMASK(19, 0), val); 1365 } 1366 1367 static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, 1368 enum rtw89_phy_idx phy_idx) 1369 { 1370 #define __MAC_TXPWR_LMT_PAGE_SIZE 40 1371 u8 ch = rtwdev->hal.current_channel; 1372 u8 bw = rtwdev->hal.current_band_width; 1373 struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; 1374 u32 addr, val; 1375 const s8 *ptr; 1376 u8 i, j, k; 1377 1378 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1379 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 1380 1381 for (i = 0; i < NTX_NUM_8852A; i++) { 1382 rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i); 1383 1384 for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { 1385 addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; 1386 ptr = (s8 *)&lmt[i] + j; 1387 val = 0; 1388 1389 for (k = 0; k < 4; k++) 1390 val |= (ptr[k] << (8 * k)); 1391 1392 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1393 } 1394 } 1395 #undef __MAC_TXPWR_LMT_PAGE_SIZE 1396 } 1397 1398 static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1399 enum rtw89_phy_idx phy_idx) 1400 { 1401 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 1402 u8 ch = rtwdev->hal.current_channel; 1403 u8 bw = rtwdev->hal.current_band_width; 1404 struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; 1405 u32 addr, val; 1406 const s8 *ptr; 1407 u8 i, j, k; 1408 1409 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1410 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 1411 1412 for (i = 0; i < NTX_NUM_8852A; i++) { 1413 rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i); 1414 1415 for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { 1416 addr = R_AX_PWR_RU_LMT + j + 1417 __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; 1418 ptr = (s8 *)&lmt_ru[i] + j; 1419 val = 0; 1420 1421 for (k = 0; k < 4; k++) 1422 val |= (ptr[k] << (8 * k)); 1423 1424 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1425 } 1426 } 1427 1428 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE 1429 } 1430 1431 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev) 1432 { 1433 rtw8852a_set_txpwr_byrate(rtwdev, RTW89_PHY_0); 1434 rtw8852a_set_txpwr_limit(rtwdev, RTW89_PHY_0); 1435 rtw8852a_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0); 1436 } 1437 1438 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 1439 { 1440 rtw8852a_set_txpwr_ref(rtwdev, RTW89_PHY_0); 1441 rtw8852a_set_txpwr_offset(rtwdev, RTW89_PHY_0); 1442 } 1443 1444 static int 1445 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1446 { 1447 int ret; 1448 1449 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1450 if (ret) 1451 return ret; 1452 1453 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1454 if (ret) 1455 return ret; 1456 1457 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1458 if (ret) 1459 return ret; 1460 1461 return 0; 1462 } 1463 1464 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1465 { 1466 u8 i = 0; 1467 u32 addr, val; 1468 1469 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1470 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1471 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1472 rtw89_phy_write32(rtwdev, addr, val); 1473 } 1474 } 1475 1476 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1477 struct rtw8852a_bb_pmac_info *tx_info, 1478 enum rtw89_phy_idx idx) 1479 { 1480 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1481 if (tx_info->mode == CONT_TX) 1482 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1483 idx); 1484 else if (tx_info->mode == PKTS_TX) 1485 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1486 idx); 1487 } 1488 1489 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1490 struct rtw8852a_bb_pmac_info *tx_info, 1491 enum rtw89_phy_idx idx) 1492 { 1493 enum rtw8852a_pmac_mode mode = tx_info->mode; 1494 u32 pkt_cnt = tx_info->tx_cnt; 1495 u16 period = tx_info->period; 1496 1497 if (mode == CONT_TX && !tx_info->is_cck) { 1498 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1499 idx); 1500 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1501 } else if (mode == PKTS_TX) { 1502 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1503 idx); 1504 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1505 B_PMAC_TX_PRD_MSK, period, idx); 1506 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1507 pkt_cnt, idx); 1508 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1509 } 1510 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1511 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1512 } 1513 1514 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1515 struct rtw8852a_bb_pmac_info *tx_info, 1516 enum rtw89_phy_idx idx) 1517 { 1518 if (!tx_info->en_pmac_tx) { 1519 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1520 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1521 if (rtwdev->hal.current_band_type == RTW89_BAND_2G) 1522 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1523 return; 1524 } 1525 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1526 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1527 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1528 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1529 idx); 1530 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1531 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1532 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1533 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1534 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1535 } 1536 1537 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1538 u16 tx_cnt, u16 period, u16 tx_time, 1539 enum rtw89_phy_idx idx) 1540 { 1541 struct rtw8852a_bb_pmac_info tx_info = {0}; 1542 1543 tx_info.en_pmac_tx = enable; 1544 tx_info.is_cck = 0; 1545 tx_info.mode = PKTS_TX; 1546 tx_info.tx_cnt = tx_cnt; 1547 tx_info.period = period; 1548 tx_info.tx_time = tx_time; 1549 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1550 } 1551 1552 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1553 enum rtw89_phy_idx idx) 1554 { 1555 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1556 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1557 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1558 } 1559 1560 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1561 { 1562 u32 rst_mask0 = 0; 1563 u32 rst_mask1 = 0; 1564 1565 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1566 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1567 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1568 if (!rtwdev->dbcc_en) { 1569 if (tx_path == RF_PATH_A) { 1570 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1571 B_TXPATH_SEL_MSK, 1); 1572 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1573 B_TXNSS_MAP_MSK, 0); 1574 } else if (tx_path == RF_PATH_B) { 1575 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1576 B_TXPATH_SEL_MSK, 2); 1577 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1578 B_TXNSS_MAP_MSK, 0); 1579 } else if (tx_path == RF_PATH_AB) { 1580 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1581 B_TXPATH_SEL_MSK, 3); 1582 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1583 B_TXNSS_MAP_MSK, 4); 1584 } else { 1585 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1586 } 1587 } else { 1588 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1589 1); 1590 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1591 RTW89_PHY_1); 1592 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1593 0); 1594 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1595 RTW89_PHY_1); 1596 } 1597 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1598 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1599 if (tx_path == RF_PATH_A) { 1600 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1601 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1602 } else { 1603 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1604 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1605 } 1606 } 1607 1608 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1609 enum rtw89_phy_idx idx, u8 mode) 1610 { 1611 if (mode != 0) 1612 return; 1613 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1614 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1615 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1616 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1617 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1618 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1619 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1620 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1621 } 1622 1623 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1624 { 1625 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : 1626 &rtw8852a_btc_preagc_dis_defs_tbl); 1627 } 1628 1629 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1630 { 1631 if (rtwdev->is_tssi_mode[rf_path]) { 1632 u32 addr = 0x1c10 + (rf_path << 13); 1633 1634 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1635 } 1636 1637 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1638 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1639 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1640 1641 fsleep(200); 1642 1643 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1644 } 1645 1646 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1647 { 1648 struct rtw89_btc *btc = &rtwdev->btc; 1649 struct rtw89_btc_module *module = &btc->mdinfo; 1650 1651 module->rfe_type = rtwdev->efuse.rfe_type; 1652 module->cv = rtwdev->hal.cv; 1653 module->bt_solo = 0; 1654 module->switch_type = BTC_SWITCH_INTERNAL; 1655 1656 if (module->rfe_type > 0) 1657 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1658 else 1659 module->ant.num = 2; 1660 1661 module->ant.diversity = 0; 1662 module->ant.isolation = 10; 1663 1664 if (module->ant.num == 3) { 1665 module->ant.type = BTC_ANT_DEDICATED; 1666 module->bt_pos = BTC_BT_ALONE; 1667 } else { 1668 module->ant.type = BTC_ANT_SHARED; 1669 module->bt_pos = BTC_BT_BTG; 1670 } 1671 } 1672 1673 static 1674 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1675 { 1676 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1677 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1678 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1679 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1680 } 1681 1682 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1683 { 1684 if (btg) { 1685 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1686 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1687 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1688 } else { 1689 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1690 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1691 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1692 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1693 } 1694 } 1695 1696 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1697 { 1698 struct rtw89_btc *btc = &rtwdev->btc; 1699 struct rtw89_btc_module *module = &btc->mdinfo; 1700 const struct rtw89_chip_info *chip = rtwdev->chip; 1701 const struct rtw89_mac_ax_coex coex_params = { 1702 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1703 .direction = RTW89_MAC_AX_COEX_INNER, 1704 }; 1705 1706 /* PTA init */ 1707 rtw89_mac_coex_init(rtwdev, &coex_params); 1708 1709 /* set WL Tx response = Hi-Pri */ 1710 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1711 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1712 1713 /* set rf gnt debug off */ 1714 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1715 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1716 1717 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1718 if (module->ant.type == BTC_ANT_SHARED) { 1719 rtw8852a_set_trx_mask(rtwdev, 1720 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1721 rtw8852a_set_trx_mask(rtwdev, 1722 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1723 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1724 rtw8852a_set_trx_mask(rtwdev, 1725 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1726 rtw8852a_set_trx_mask(rtwdev, 1727 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1728 } 1729 1730 /* set PTA break table */ 1731 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1732 1733 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1734 rtw89_write32_set(rtwdev, 1735 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1736 btc->cx.wl.status.map.init_ok = true; 1737 } 1738 1739 static 1740 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1741 { 1742 u32 bitmap = 0; 1743 u32 reg = 0; 1744 1745 switch (map) { 1746 case BTC_PRI_MASK_TX_RESP: 1747 reg = R_BTC_BT_COEX_MSK_TABLE; 1748 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1749 break; 1750 case BTC_PRI_MASK_BEACON: 1751 reg = R_AX_WL_PRI_MSK; 1752 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1753 break; 1754 default: 1755 return; 1756 } 1757 1758 if (state) 1759 rtw89_write32_set(rtwdev, reg, bitmap); 1760 else 1761 rtw89_write32_clr(rtwdev, reg, bitmap); 1762 } 1763 1764 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1765 { 1766 return FIELD_GET(GENMASK(15, 0), ctrl); 1767 } 1768 1769 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1770 { 1771 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1772 } 1773 1774 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1775 { 1776 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1777 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1778 1779 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1780 } 1781 1782 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1783 { 1784 return FIELD_GET(GENMASK(31, 16), ctrl); 1785 } 1786 1787 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1788 { 1789 return cur & ~B_AX_TXAGC_BT_EN; 1790 } 1791 1792 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1793 { 1794 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1795 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1796 1797 return ov | iv | B_AX_TXAGC_BT_EN; 1798 } 1799 1800 static void 1801 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1802 { 1803 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1804 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1805 1806 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1807 #define __handle(_case) \ 1808 do { \ 1809 const u32 _reg = __btc_cr_ ## _case; \ 1810 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1811 u32 _cur, _wrt; \ 1812 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1813 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1814 rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ 1815 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1816 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1817 _wrt = __do_clr(_val) ? \ 1818 __btc_ctrl_rst_ ## _case(_cur) : \ 1819 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1820 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1821 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1822 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1823 } while (0) 1824 1825 __handle(all_time); 1826 __handle(gnt_bt); 1827 1828 #undef __handle 1829 #undef __do_clr 1830 } 1831 1832 static 1833 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1834 { 1835 return clamp_t(s8, val, -100, 0) + 100; 1836 } 1837 1838 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1839 {255, 0, 0, 7}, /* 0 -> original */ 1840 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1841 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1842 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1843 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1844 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1845 {6, 1, 0, 7}, 1846 {13, 1, 0, 7}, 1847 {13, 1, 0, 7} 1848 }; 1849 1850 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1851 {255, 0, 0, 7}, /* 0 -> original */ 1852 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1853 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1854 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1855 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1856 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1857 {255, 1, 0, 7}, 1858 {255, 1, 0, 7}, 1859 {255, 1, 0, 7} 1860 }; 1861 1862 static const 1863 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1864 static const 1865 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1866 1867 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1868 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1869 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1870 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1871 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1872 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1873 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1874 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1875 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1876 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1877 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1878 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1879 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1880 }; 1881 1882 static 1883 void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) 1884 { 1885 struct rtw89_btc *btc = &rtwdev->btc; 1886 struct rtw89_btc_dm *dm = &btc->dm; 1887 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 1888 struct rtw89_btc_bt_link_info *b = &bt->link_info; 1889 1890 /* fix LNA2 = level-5 for BT ACI issue at BTG */ 1891 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) 1892 dm->trx_para_level = 1; 1893 } 1894 1895 static 1896 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1897 { 1898 struct rtw89_btc *btc = &rtwdev->btc; 1899 struct rtw89_btc_cx *cx = &btc->cx; 1900 u32 val; 1901 1902 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1903 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1904 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1905 1906 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1907 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1908 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1909 1910 /* clock-gate off before reset counter*/ 1911 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1912 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1913 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1914 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1915 } 1916 1917 static 1918 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1919 { 1920 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1922 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1923 1924 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1925 if (state) 1926 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1927 RFREG_MASK, 0xa2d7c); 1928 else 1929 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1930 RFREG_MASK, 0xa2020); 1931 1932 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1933 } 1934 1935 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 1936 struct rtw89_rx_phy_ppdu *phy_ppdu, 1937 struct ieee80211_rx_status *status) 1938 { 1939 u16 chan = phy_ppdu->chan_idx; 1940 u8 band; 1941 1942 if (chan == 0) 1943 return; 1944 1945 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1946 status->freq = ieee80211_channel_to_frequency(chan, band); 1947 status->band = band; 1948 } 1949 1950 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 1951 struct rtw89_rx_phy_ppdu *phy_ppdu, 1952 struct ieee80211_rx_status *status) 1953 { 1954 u8 path; 1955 s8 *rx_power = phy_ppdu->rssi; 1956 1957 status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 1958 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 1959 status->chains |= BIT(path); 1960 status->chain_signal[path] = rx_power[path]; 1961 } 1962 if (phy_ppdu->valid) 1963 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 1964 } 1965 1966 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 1967 .bb_reset = rtw8852a_bb_reset, 1968 .bb_sethw = rtw8852a_bb_sethw, 1969 .read_rf = rtw89_phy_read_rf, 1970 .write_rf = rtw89_phy_write_rf, 1971 .set_channel = rtw8852a_set_channel, 1972 .set_channel_help = rtw8852a_set_channel_help, 1973 .read_efuse = rtw8852a_read_efuse, 1974 .read_phycap = rtw8852a_read_phycap, 1975 .fem_setup = rtw8852a_fem_setup, 1976 .rfk_init = rtw8852a_rfk_init, 1977 .rfk_channel = rtw8852a_rfk_channel, 1978 .rfk_band_changed = rtw8852a_rfk_band_changed, 1979 .rfk_scan = rtw8852a_rfk_scan, 1980 .rfk_track = rtw8852a_rfk_track, 1981 .power_trim = rtw8852a_power_trim, 1982 .set_txpwr = rtw8852a_set_txpwr, 1983 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 1984 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 1985 .get_thermal = rtw8852a_get_thermal, 1986 .ctrl_btg = rtw8852a_ctrl_btg, 1987 .query_ppdu = rtw8852a_query_ppdu, 1988 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, 1989 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 1990 1991 .btc_set_rfe = rtw8852a_btc_set_rfe, 1992 .btc_init_cfg = rtw8852a_btc_init_cfg, 1993 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 1994 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 1995 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 1996 .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, 1997 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 1998 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 1999 }; 2000 2001 const struct rtw89_chip_info rtw8852a_chip_info = { 2002 .chip_id = RTL8852A, 2003 .ops = &rtw8852a_chip_ops, 2004 .fw_name = "rtw89/rtw8852a_fw.bin", 2005 .fifo_size = 458752, 2006 .max_amsdu_limit = 3500, 2007 .dis_2g_40m_ul_ofdma = true, 2008 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2009 .dle_mem = rtw8852a_dle_mem_pcie, 2010 .rf_base_addr = {0xc000, 0xd000}, 2011 .pwr_on_seq = pwr_on_seq_8852a, 2012 .pwr_off_seq = pwr_off_seq_8852a, 2013 .bb_table = &rtw89_8852a_phy_bb_table, 2014 .rf_table = {&rtw89_8852a_phy_radioa_table, 2015 &rtw89_8852a_phy_radiob_table,}, 2016 .nctl_table = &rtw89_8852a_phy_nctl_table, 2017 .byr_table = &rtw89_8852a_byr_table, 2018 .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, 2019 .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, 2020 .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, 2021 .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, 2022 .txpwr_factor_rf = 2, 2023 .txpwr_factor_mac = 1, 2024 .dig_table = &rtw89_8852a_phy_dig_table, 2025 .support_bands = BIT(NL80211_BAND_2GHZ) | 2026 BIT(NL80211_BAND_5GHZ), 2027 .rf_path_num = 2, 2028 .tx_nss = 2, 2029 .rx_nss = 2, 2030 .acam_num = 128, 2031 .bcam_num = 10, 2032 .scam_num = 128, 2033 .sec_ctrl_efuse_size = 4, 2034 .physical_efuse_size = 1216, 2035 .logical_efuse_size = 1536, 2036 .limit_efuse_size = 1152, 2037 .phycap_addr = 0x580, 2038 .phycap_size = 128, 2039 .para_ver = 0x05050864, 2040 .wlcx_desired = 0x05050000, 2041 .btcx_desired = 0x5, 2042 .scbd = 0x1, 2043 .mailbox = 0x1, 2044 .afh_guard_ch = 6, 2045 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2046 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2047 .rssi_tol = 2, 2048 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2049 .mon_reg = rtw89_btc_8852a_mon_reg, 2050 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2051 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2052 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2053 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2054 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2055 BIT(RTW89_PS_MODE_CLK_GATED) | 2056 BIT(RTW89_PS_MODE_PWR_GATED), 2057 }; 2058 EXPORT_SYMBOL(rtw8852a_chip_info); 2059 2060 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); 2061 MODULE_AUTHOR("Realtek Corporation"); 2062 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2063 MODULE_LICENSE("Dual BSD/GPL"); 2064