1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 16 {128, 1896, grp_0}, /* ACH 0 */ 17 {128, 1896, grp_0}, /* ACH 1 */ 18 {128, 1896, grp_0}, /* ACH 2 */ 19 {128, 1896, grp_0}, /* ACH 3 */ 20 {128, 1896, grp_1}, /* ACH 4 */ 21 {128, 1896, grp_1}, /* ACH 5 */ 22 {128, 1896, grp_1}, /* ACH 6 */ 23 {128, 1896, grp_1}, /* ACH 7 */ 24 {32, 1896, grp_0}, /* B0MGQ */ 25 {128, 1896, grp_0}, /* B0HIQ */ 26 {32, 1896, grp_1}, /* B1MGQ */ 27 {128, 1896, grp_1}, /* B1HIQ */ 28 {40, 0, 0} /* FWCMDQ */ 29 }; 30 31 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 32 1896, /* Group 0 */ 33 1896, /* Group 1 */ 34 3792, /* Public Max */ 35 0 /* WP threshold */ 36 }; 37 38 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 39 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 40 &rtw89_hfc_preccfg_pcie, RTW89_HCIFC_POH}, 41 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_hfc_preccfg_pcie, 42 RTW89_HCIFC_POH}, 43 [RTW89_QTA_INVALID] = {NULL}, 44 }; 45 46 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 47 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_wde_size0, &rtw89_ple_size0, 48 &rtw89_wde_qt0, &rtw89_wde_qt0, &rtw89_ple_qt4, 49 &rtw89_ple_qt5}, 50 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_wde_size4, &rtw89_ple_size4, 51 &rtw89_wde_qt4, &rtw89_wde_qt4, &rtw89_ple_qt13, 52 &rtw89_ple_qt13}, 53 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 54 NULL}, 55 }; 56 57 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 58 {0x44AC, 0x00000000}, 59 {0x44B0, 0x00000000}, 60 {0x44B4, 0x00000000}, 61 {0x44B8, 0x00000000}, 62 {0x44BC, 0x00000000}, 63 {0x44C0, 0x00000000}, 64 {0x44C4, 0x00000000}, 65 {0x44C8, 0x00000000}, 66 {0x44CC, 0x00000000}, 67 {0x44D0, 0x00000000}, 68 {0x44D4, 0x00000000}, 69 {0x44D8, 0x00000000}, 70 {0x44DC, 0x00000000}, 71 {0x44E0, 0x00000000}, 72 {0x44E4, 0x00000000}, 73 {0x44E8, 0x00000000}, 74 {0x44EC, 0x00000000}, 75 {0x44F0, 0x00000000}, 76 {0x44F4, 0x00000000}, 77 {0x44F8, 0x00000000}, 78 {0x44FC, 0x00000000}, 79 {0x4500, 0x00000000}, 80 {0x4504, 0x00000000}, 81 {0x4508, 0x00000000}, 82 {0x450C, 0x00000000}, 83 {0x4510, 0x00000000}, 84 {0x4514, 0x00000000}, 85 {0x4518, 0x00000000}, 86 {0x451C, 0x00000000}, 87 {0x4520, 0x00000000}, 88 {0x4524, 0x00000000}, 89 {0x4528, 0x00000000}, 90 {0x452C, 0x00000000}, 91 {0x4530, 0x4E1F3E81}, 92 {0x4534, 0x00000000}, 93 {0x4538, 0x0000005A}, 94 {0x453C, 0x00000000}, 95 {0x4540, 0x00000000}, 96 {0x4544, 0x00000000}, 97 {0x4548, 0x00000000}, 98 {0x454C, 0x00000000}, 99 {0x4550, 0x00000000}, 100 {0x4554, 0x00000000}, 101 {0x4558, 0x00000000}, 102 {0x455C, 0x00000000}, 103 {0x4560, 0x4060001A}, 104 {0x4564, 0x40000000}, 105 {0x4568, 0x00000000}, 106 {0x456C, 0x00000000}, 107 {0x4570, 0x04000007}, 108 {0x4574, 0x0000DC87}, 109 {0x4578, 0x00000BAB}, 110 {0x457C, 0x03E00000}, 111 {0x4580, 0x00000048}, 112 {0x4584, 0x00000000}, 113 {0x4588, 0x000003E8}, 114 {0x458C, 0x30000000}, 115 {0x4590, 0x00000000}, 116 {0x4594, 0x10000000}, 117 {0x4598, 0x00000001}, 118 {0x459C, 0x00030000}, 119 {0x45A0, 0x01000000}, 120 {0x45A4, 0x03000200}, 121 {0x45A8, 0xC00001C0}, 122 {0x45AC, 0x78018000}, 123 {0x45B0, 0x80000000}, 124 {0x45B4, 0x01C80600}, 125 {0x45B8, 0x00000002}, 126 {0x4594, 0x10000000} 127 }; 128 129 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 130 {0x4624, GENMASK(20, 14), 0x40}, 131 {0x46f8, GENMASK(20, 14), 0x40}, 132 {0x4674, GENMASK(20, 19), 0x2}, 133 {0x4748, GENMASK(20, 19), 0x2}, 134 {0x4650, GENMASK(14, 10), 0x18}, 135 {0x4724, GENMASK(14, 10), 0x18}, 136 {0x4688, GENMASK(1, 0), 0x3}, 137 {0x475c, GENMASK(1, 0), 0x3}, 138 }; 139 140 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 141 142 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 143 {0x4624, GENMASK(20, 14), 0x1a}, 144 {0x46f8, GENMASK(20, 14), 0x1a}, 145 {0x4674, GENMASK(20, 19), 0x1}, 146 {0x4748, GENMASK(20, 19), 0x1}, 147 {0x4650, GENMASK(14, 10), 0x12}, 148 {0x4724, GENMASK(14, 10), 0x12}, 149 {0x4688, GENMASK(1, 0), 0x0}, 150 {0x475c, GENMASK(1, 0), 0x0}, 151 }; 152 153 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 154 155 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 156 {0x00C6, 157 PWR_CV_MSK_B, 158 PWR_INTF_MSK_PCIE, 159 PWR_BASE_MAC, 160 PWR_CMD_WRITE, BIT(6), BIT(6)}, 161 {0x1086, 162 PWR_CV_MSK_ALL, 163 PWR_INTF_MSK_SDIO, 164 PWR_BASE_MAC, 165 PWR_CMD_WRITE, BIT(0), 0}, 166 {0x1086, 167 PWR_CV_MSK_ALL, 168 PWR_INTF_MSK_SDIO, 169 PWR_BASE_MAC, 170 PWR_CMD_POLL, BIT(1), BIT(1)}, 171 {0x0005, 172 PWR_CV_MSK_ALL, 173 PWR_INTF_MSK_ALL, 174 PWR_BASE_MAC, 175 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 176 {0x0005, 177 PWR_CV_MSK_ALL, 178 PWR_INTF_MSK_ALL, 179 PWR_BASE_MAC, 180 PWR_CMD_WRITE, BIT(7), 0}, 181 {0x0005, 182 PWR_CV_MSK_ALL, 183 PWR_INTF_MSK_ALL, 184 PWR_BASE_MAC, 185 PWR_CMD_WRITE, BIT(2), 0}, 186 {0x0006, 187 PWR_CV_MSK_ALL, 188 PWR_INTF_MSK_ALL, 189 PWR_BASE_MAC, 190 PWR_CMD_POLL, BIT(1), BIT(1)}, 191 {0x0006, 192 PWR_CV_MSK_ALL, 193 PWR_INTF_MSK_ALL, 194 PWR_BASE_MAC, 195 PWR_CMD_WRITE, BIT(0), BIT(0)}, 196 {0x0005, 197 PWR_CV_MSK_ALL, 198 PWR_INTF_MSK_ALL, 199 PWR_BASE_MAC, 200 PWR_CMD_WRITE, BIT(0), BIT(0)}, 201 {0x0005, 202 PWR_CV_MSK_ALL, 203 PWR_INTF_MSK_ALL, 204 PWR_BASE_MAC, 205 PWR_CMD_POLL, BIT(0), 0}, 206 {0x106D, 207 PWR_CV_MSK_B | PWR_CV_MSK_C, 208 PWR_INTF_MSK_USB, 209 PWR_BASE_MAC, 210 PWR_CMD_WRITE, BIT(6), 0}, 211 {0x0088, 212 PWR_CV_MSK_ALL, 213 PWR_INTF_MSK_ALL, 214 PWR_BASE_MAC, 215 PWR_CMD_WRITE, BIT(0), BIT(0)}, 216 {0x0088, 217 PWR_CV_MSK_ALL, 218 PWR_INTF_MSK_ALL, 219 PWR_BASE_MAC, 220 PWR_CMD_WRITE, BIT(0), 0}, 221 {0x0088, 222 PWR_CV_MSK_ALL, 223 PWR_INTF_MSK_ALL, 224 PWR_BASE_MAC, 225 PWR_CMD_WRITE, BIT(0), BIT(0)}, 226 {0x0088, 227 PWR_CV_MSK_ALL, 228 PWR_INTF_MSK_ALL, 229 PWR_BASE_MAC, 230 PWR_CMD_WRITE, BIT(0), 0}, 231 {0x0088, 232 PWR_CV_MSK_ALL, 233 PWR_INTF_MSK_ALL, 234 PWR_BASE_MAC, 235 PWR_CMD_WRITE, BIT(0), BIT(0)}, 236 {0x0083, 237 PWR_CV_MSK_ALL, 238 PWR_INTF_MSK_ALL, 239 PWR_BASE_MAC, 240 PWR_CMD_WRITE, BIT(6), 0}, 241 {0x0080, 242 PWR_CV_MSK_ALL, 243 PWR_INTF_MSK_ALL, 244 PWR_BASE_MAC, 245 PWR_CMD_WRITE, BIT(5), BIT(5)}, 246 {0x0024, 247 PWR_CV_MSK_ALL, 248 PWR_INTF_MSK_ALL, 249 PWR_BASE_MAC, 250 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 251 {0x02A0, 252 PWR_CV_MSK_ALL, 253 PWR_INTF_MSK_ALL, 254 PWR_BASE_MAC, 255 PWR_CMD_WRITE, BIT(1), BIT(1)}, 256 {0x02A2, 257 PWR_CV_MSK_ALL, 258 PWR_INTF_MSK_ALL, 259 PWR_BASE_MAC, 260 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 261 {0x0071, 262 PWR_CV_MSK_ALL, 263 PWR_INTF_MSK_PCIE, 264 PWR_BASE_MAC, 265 PWR_CMD_WRITE, BIT(4), 0}, 266 {0x0010, 267 PWR_CV_MSK_A, 268 PWR_INTF_MSK_PCIE, 269 PWR_BASE_MAC, 270 PWR_CMD_WRITE, BIT(2), BIT(2)}, 271 {0x02A0, 272 PWR_CV_MSK_A, 273 PWR_INTF_MSK_ALL, 274 PWR_BASE_MAC, 275 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 276 {0xFFFF, 277 PWR_CV_MSK_ALL, 278 PWR_INTF_MSK_ALL, 279 0, 280 PWR_CMD_END, 0, 0}, 281 }; 282 283 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 284 {0x02F0, 285 PWR_CV_MSK_ALL, 286 PWR_INTF_MSK_ALL, 287 PWR_BASE_MAC, 288 PWR_CMD_WRITE, 0xFF, 0}, 289 {0x02F1, 290 PWR_CV_MSK_ALL, 291 PWR_INTF_MSK_ALL, 292 PWR_BASE_MAC, 293 PWR_CMD_WRITE, 0xFF, 0}, 294 {0x0006, 295 PWR_CV_MSK_ALL, 296 PWR_INTF_MSK_ALL, 297 PWR_BASE_MAC, 298 PWR_CMD_WRITE, BIT(0), BIT(0)}, 299 {0x0002, 300 PWR_CV_MSK_ALL, 301 PWR_INTF_MSK_ALL, 302 PWR_BASE_MAC, 303 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 304 {0x0082, 305 PWR_CV_MSK_ALL, 306 PWR_INTF_MSK_ALL, 307 PWR_BASE_MAC, 308 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 309 {0x106D, 310 PWR_CV_MSK_B | PWR_CV_MSK_C, 311 PWR_INTF_MSK_USB, 312 PWR_BASE_MAC, 313 PWR_CMD_WRITE, BIT(6), BIT(6)}, 314 {0x0005, 315 PWR_CV_MSK_ALL, 316 PWR_INTF_MSK_ALL, 317 PWR_BASE_MAC, 318 PWR_CMD_WRITE, BIT(1), BIT(1)}, 319 {0x0005, 320 PWR_CV_MSK_ALL, 321 PWR_INTF_MSK_ALL, 322 PWR_BASE_MAC, 323 PWR_CMD_POLL, BIT(1), 0}, 324 {0x0091, 325 PWR_CV_MSK_ALL, 326 PWR_INTF_MSK_PCIE, 327 PWR_BASE_MAC, 328 PWR_CMD_WRITE, BIT(0), 0}, 329 {0x0005, 330 PWR_CV_MSK_ALL, 331 PWR_INTF_MSK_PCIE, 332 PWR_BASE_MAC, 333 PWR_CMD_WRITE, BIT(2), BIT(2)}, 334 {0x0007, 335 PWR_CV_MSK_ALL, 336 PWR_INTF_MSK_USB, 337 PWR_BASE_MAC, 338 PWR_CMD_WRITE, BIT(4), 0}, 339 {0x0007, 340 PWR_CV_MSK_ALL, 341 PWR_INTF_MSK_SDIO, 342 PWR_BASE_MAC, 343 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 344 {0x0005, 345 PWR_CV_MSK_ALL, 346 PWR_INTF_MSK_SDIO, 347 PWR_BASE_MAC, 348 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 349 {0x0005, 350 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 351 PWR_CV_MSK_G, 352 PWR_INTF_MSK_USB, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 355 {0x1086, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(0), BIT(0)}, 360 {0x1086, 361 PWR_CV_MSK_ALL, 362 PWR_INTF_MSK_SDIO, 363 PWR_BASE_MAC, 364 PWR_CMD_POLL, BIT(1), 0}, 365 {0xFFFF, 366 PWR_CV_MSK_ALL, 367 PWR_INTF_MSK_ALL, 368 0, 369 PWR_CMD_END, 0, 0}, 370 }; 371 372 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 373 rtw8852a_pwron, NULL 374 }; 375 376 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 377 rtw8852a_pwroff, NULL 378 }; 379 380 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 381 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 382 R_AX_H2CREG_DATA3 383 }; 384 385 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 386 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 387 R_AX_C2HREG_DATA3 388 }; 389 390 static const struct rtw89_page_regs rtw8852a_page_regs = { 391 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 392 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 393 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 394 .ach_page_info = R_AX_ACH0_PAGE_INFO, 395 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 396 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 397 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 398 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 399 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 400 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 401 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 402 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 403 }; 404 405 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 406 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 407 }; 408 409 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 410 struct rtw8852a_efuse *map) 411 { 412 ether_addr_copy(efuse->addr, map->e.mac_addr); 413 efuse->rfe_type = map->rfe_type; 414 efuse->xtal_cap = map->xtal_k; 415 } 416 417 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 418 struct rtw8852a_efuse *map) 419 { 420 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 421 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 422 u8 i, j; 423 424 tssi->thermal[RF_PATH_A] = map->path_a_therm; 425 tssi->thermal[RF_PATH_B] = map->path_b_therm; 426 427 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 428 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 429 sizeof(ofst[i]->cck_tssi)); 430 431 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 432 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 433 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 434 i, j, tssi->tssi_cck[i][j]); 435 436 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 437 sizeof(ofst[i]->bw40_tssi)); 438 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 439 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 440 441 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 442 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 443 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 444 i, j, tssi->tssi_mcs[i][j]); 445 } 446 } 447 448 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 449 { 450 struct rtw89_efuse *efuse = &rtwdev->efuse; 451 struct rtw8852a_efuse *map; 452 453 map = (struct rtw8852a_efuse *)log_map; 454 455 efuse->country_code[0] = map->country_code[0]; 456 efuse->country_code[1] = map->country_code[1]; 457 rtw8852a_efuse_parsing_tssi(rtwdev, map); 458 459 switch (rtwdev->hci.type) { 460 case RTW89_HCI_TYPE_PCIE: 461 rtw8852ae_efuse_parsing(efuse, map); 462 break; 463 default: 464 return -ENOTSUPP; 465 } 466 467 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 468 469 return 0; 470 } 471 472 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 473 { 474 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 475 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 476 u32 addr = rtwdev->chip->phycap_addr; 477 bool pg = false; 478 u32 ofst; 479 u8 i, j; 480 481 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 482 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 483 /* addrs are in decreasing order */ 484 ofst = tssi_trim_addr[i] - addr - j; 485 tssi->tssi_trim[i][j] = phycap_map[ofst]; 486 487 if (phycap_map[ofst] != 0xff) 488 pg = true; 489 } 490 } 491 492 if (!pg) { 493 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 494 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 495 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 496 } 497 498 for (i = 0; i < RF_PATH_NUM_8852A; i++) 499 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 500 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 501 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 502 i, j, tssi->tssi_trim[i][j], 503 tssi_trim_addr[i] - j); 504 } 505 506 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 507 u8 *phycap_map) 508 { 509 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 510 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 511 u32 addr = rtwdev->chip->phycap_addr; 512 u8 i; 513 514 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 515 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 516 517 rtw89_debug(rtwdev, RTW89_DBG_RFK, 518 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 519 i, info->thermal_trim[i]); 520 521 if (info->thermal_trim[i] != 0xff) 522 info->pg_thermal_trim = true; 523 } 524 } 525 526 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 527 { 528 #define __thm_setting(raw) \ 529 ({ \ 530 u8 __v = (raw); \ 531 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 532 }) 533 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 534 u8 i, val; 535 536 if (!info->pg_thermal_trim) { 537 rtw89_debug(rtwdev, RTW89_DBG_RFK, 538 "[THERMAL][TRIM] no PG, do nothing\n"); 539 540 return; 541 } 542 543 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 544 val = __thm_setting(info->thermal_trim[i]); 545 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 546 547 rtw89_debug(rtwdev, RTW89_DBG_RFK, 548 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 549 i, val); 550 } 551 #undef __thm_setting 552 } 553 554 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 555 u8 *phycap_map) 556 { 557 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 558 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 559 u32 addr = rtwdev->chip->phycap_addr; 560 u8 i; 561 562 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 563 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 564 565 rtw89_debug(rtwdev, RTW89_DBG_RFK, 566 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 567 i, info->pa_bias_trim[i]); 568 569 if (info->pa_bias_trim[i] != 0xff) 570 info->pg_pa_bias_trim = true; 571 } 572 } 573 574 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 575 { 576 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 577 u8 pabias_2g, pabias_5g; 578 u8 i; 579 580 if (!info->pg_pa_bias_trim) { 581 rtw89_debug(rtwdev, RTW89_DBG_RFK, 582 "[PA_BIAS][TRIM] no PG, do nothing\n"); 583 584 return; 585 } 586 587 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 588 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 589 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 590 591 rtw89_debug(rtwdev, RTW89_DBG_RFK, 592 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 593 i, pabias_2g, pabias_5g); 594 595 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 596 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 597 } 598 } 599 600 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 601 { 602 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 603 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 604 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 605 606 return 0; 607 } 608 609 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 610 { 611 rtw8852a_thermal_trim(rtwdev); 612 rtw8852a_pa_bias_trim(rtwdev); 613 } 614 615 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 616 struct rtw89_channel_params *param, 617 u8 mac_idx) 618 { 619 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 620 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 621 mac_idx); 622 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 623 u8 txsc20 = 0, txsc40 = 0; 624 625 switch (param->bandwidth) { 626 case RTW89_CHANNEL_WIDTH_80: 627 txsc40 = rtw89_phy_get_txsc(rtwdev, param, 628 RTW89_CHANNEL_WIDTH_40); 629 fallthrough; 630 case RTW89_CHANNEL_WIDTH_40: 631 txsc20 = rtw89_phy_get_txsc(rtwdev, param, 632 RTW89_CHANNEL_WIDTH_20); 633 break; 634 default: 635 break; 636 } 637 638 switch (param->bandwidth) { 639 case RTW89_CHANNEL_WIDTH_80: 640 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 641 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 642 break; 643 case RTW89_CHANNEL_WIDTH_40: 644 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 645 rtw89_write32(rtwdev, sub_carr, txsc20); 646 break; 647 case RTW89_CHANNEL_WIDTH_20: 648 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 649 rtw89_write32(rtwdev, sub_carr, 0); 650 break; 651 default: 652 break; 653 } 654 655 if (param->center_chan > 14) 656 rtw89_write8_set(rtwdev, chk_rate, 657 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 658 else 659 rtw89_write8_clr(rtwdev, chk_rate, 660 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 661 } 662 663 static const u32 rtw8852a_sco_barker_threshold[14] = { 664 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 665 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 666 }; 667 668 static const u32 rtw8852a_sco_cck_threshold[14] = { 669 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 670 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 671 }; 672 673 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 674 u8 primary_ch, enum rtw89_bandwidth bw) 675 { 676 u8 ch_element; 677 678 if (bw == RTW89_CHANNEL_WIDTH_20) { 679 ch_element = central_ch - 1; 680 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 681 if (primary_ch == 1) 682 ch_element = central_ch - 1 + 2; 683 else 684 ch_element = central_ch - 1 - 2; 685 } else { 686 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 687 return -EINVAL; 688 } 689 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 690 rtw8852a_sco_barker_threshold[ch_element]); 691 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 692 rtw8852a_sco_cck_threshold[ch_element]); 693 694 return 0; 695 } 696 697 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 698 u8 path) 699 { 700 u32 val; 701 702 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 703 if (val == INV_RF_DATA) { 704 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 705 return; 706 } 707 val &= ~0x303ff; 708 val |= central_ch; 709 if (central_ch > 14) 710 val |= (BIT(16) | BIT(8)); 711 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 712 } 713 714 static u8 rtw8852a_sco_mapping(u8 central_ch) 715 { 716 if (central_ch == 1) 717 return 109; 718 else if (central_ch >= 2 && central_ch <= 6) 719 return 108; 720 else if (central_ch >= 7 && central_ch <= 10) 721 return 107; 722 else if (central_ch >= 11 && central_ch <= 14) 723 return 106; 724 else if (central_ch == 36 || central_ch == 38) 725 return 51; 726 else if (central_ch >= 40 && central_ch <= 58) 727 return 50; 728 else if (central_ch >= 60 && central_ch <= 64) 729 return 49; 730 else if (central_ch == 100 || central_ch == 102) 731 return 48; 732 else if (central_ch >= 104 && central_ch <= 126) 733 return 47; 734 else if (central_ch >= 128 && central_ch <= 151) 735 return 46; 736 else if (central_ch >= 153 && central_ch <= 177) 737 return 45; 738 else 739 return 0; 740 } 741 742 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 743 enum rtw89_phy_idx phy_idx) 744 { 745 u8 sco_comp; 746 bool is_2g = central_ch <= 14; 747 748 if (phy_idx == RTW89_PHY_0) { 749 /* Path A */ 750 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 751 if (is_2g) 752 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 753 B_PATH0_TIA_ERR_G1_SEL, 1, 754 phy_idx); 755 else 756 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 757 B_PATH0_TIA_ERR_G1_SEL, 0, 758 phy_idx); 759 760 /* Path B */ 761 if (!rtwdev->dbcc_en) { 762 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 763 if (is_2g) 764 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 765 B_P1_MODE_SEL, 766 1, phy_idx); 767 else 768 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 769 B_P1_MODE_SEL, 770 0, phy_idx); 771 } else { 772 if (is_2g) 773 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 774 B_2P4G_BAND_SEL); 775 else 776 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 777 B_2P4G_BAND_SEL); 778 } 779 /* SCO compensate FC setting */ 780 sco_comp = rtw8852a_sco_mapping(central_ch); 781 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 782 sco_comp, phy_idx); 783 } else { 784 /* Path B */ 785 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 786 if (is_2g) 787 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 788 B_P1_MODE_SEL, 789 1, phy_idx); 790 else 791 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 792 B_P1_MODE_SEL, 793 0, phy_idx); 794 /* SCO compensate FC setting */ 795 sco_comp = rtw8852a_sco_mapping(central_ch); 796 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 797 sco_comp, phy_idx); 798 } 799 800 /* Band edge */ 801 if (is_2g) 802 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 803 phy_idx); 804 else 805 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 806 phy_idx); 807 808 /* CCK parameters */ 809 if (central_ch == 14) { 810 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 811 0x3b13ff); 812 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 813 0x1c42de); 814 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 815 0xfdb0ad); 816 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 817 0xf60f6e); 818 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 819 0xfd8f92); 820 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 821 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 822 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 823 0xfff00a); 824 } else { 825 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 826 0x3d23ff); 827 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 828 0x29b354); 829 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 830 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 831 0xfdb053); 832 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 833 0xf86f9a); 834 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 835 0xfaef92); 836 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 837 0xfe5fcc); 838 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 839 0xffdff5); 840 } 841 } 842 843 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 844 { 845 u32 val = 0; 846 u32 adc_sel[2] = {0x12d0, 0x32d0}; 847 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 848 849 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 850 if (val == INV_RF_DATA) { 851 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 852 return; 853 } 854 val &= ~(BIT(11) | BIT(10)); 855 switch (bw) { 856 case RTW89_CHANNEL_WIDTH_5: 857 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 858 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 859 val |= (BIT(11) | BIT(10)); 860 break; 861 case RTW89_CHANNEL_WIDTH_10: 862 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 863 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 864 val |= (BIT(11) | BIT(10)); 865 break; 866 case RTW89_CHANNEL_WIDTH_20: 867 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 868 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 869 val |= (BIT(11) | BIT(10)); 870 break; 871 case RTW89_CHANNEL_WIDTH_40: 872 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 873 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 874 val |= BIT(11); 875 break; 876 case RTW89_CHANNEL_WIDTH_80: 877 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 878 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 879 val |= BIT(10); 880 break; 881 default: 882 rtw89_warn(rtwdev, "Fail to set ADC\n"); 883 } 884 885 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 886 } 887 888 static void 889 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 890 enum rtw89_phy_idx phy_idx) 891 { 892 /* Switch bandwidth */ 893 switch (bw) { 894 case RTW89_CHANNEL_WIDTH_5: 895 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 896 phy_idx); 897 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 898 phy_idx); 899 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 900 0x0, phy_idx); 901 break; 902 case RTW89_CHANNEL_WIDTH_10: 903 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 904 phy_idx); 905 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 906 phy_idx); 907 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 908 0x0, phy_idx); 909 break; 910 case RTW89_CHANNEL_WIDTH_20: 911 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 912 phy_idx); 913 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 914 phy_idx); 915 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 916 0x0, phy_idx); 917 break; 918 case RTW89_CHANNEL_WIDTH_40: 919 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 920 phy_idx); 921 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 922 phy_idx); 923 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 924 pri_ch, 925 phy_idx); 926 if (pri_ch == RTW89_SC_20_UPPER) 927 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 928 else 929 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 930 break; 931 case RTW89_CHANNEL_WIDTH_80: 932 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 933 phy_idx); 934 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 935 phy_idx); 936 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 937 pri_ch, 938 phy_idx); 939 break; 940 default: 941 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 942 pri_ch); 943 } 944 945 if (phy_idx == RTW89_PHY_0) { 946 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 947 if (!rtwdev->dbcc_en) 948 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 949 } else { 950 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 951 } 952 } 953 954 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 955 { 956 if (central_ch == 153) { 957 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 958 0x210); 959 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 960 0x210); 961 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); 962 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 963 B_P0_NBIIDX_NOTCH_EN, 0x1); 964 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 965 B_P1_NBIIDX_NOTCH_EN, 0x1); 966 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 967 0x1); 968 } else if (central_ch == 151) { 969 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 970 0x210); 971 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 972 0x210); 973 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); 974 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 975 B_P0_NBIIDX_NOTCH_EN, 0x1); 976 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 977 B_P1_NBIIDX_NOTCH_EN, 0x1); 978 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 979 0x1); 980 } else if (central_ch == 155) { 981 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 982 0x2d0); 983 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 984 0x2d0); 985 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); 986 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 987 B_P0_NBIIDX_NOTCH_EN, 0x1); 988 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 989 B_P1_NBIIDX_NOTCH_EN, 0x1); 990 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 991 0x1); 992 } else { 993 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 994 B_P0_NBIIDX_NOTCH_EN, 0x0); 995 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 996 B_P1_NBIIDX_NOTCH_EN, 0x0); 997 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 998 0x0); 999 } 1000 } 1001 1002 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1003 enum rtw89_phy_idx phy_idx) 1004 { 1005 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1006 phy_idx); 1007 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1008 phy_idx); 1009 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1010 phy_idx); 1011 } 1012 1013 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1014 enum rtw89_phy_idx phy_idx, bool en) 1015 { 1016 if (en) 1017 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1018 1, 1019 phy_idx); 1020 else 1021 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1022 0, 1023 phy_idx); 1024 } 1025 1026 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1027 enum rtw89_phy_idx phy_idx) 1028 { 1029 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1030 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1031 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1032 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1033 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1034 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1035 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1036 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1037 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1038 } 1039 1040 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1041 enum rtw89_phy_idx phy_idx) 1042 { 1043 u32 addr; 1044 1045 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1046 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1047 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1048 } 1049 1050 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1051 { 1052 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1053 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1054 1055 if (rtwdev->hal.cv <= CHIP_CCV) { 1056 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1057 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1058 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F); 1059 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1060 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1061 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1062 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1063 } 1064 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1065 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1066 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1067 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1068 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1069 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1070 1071 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1072 } 1073 1074 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1075 enum rtw89_phy_idx phy_idx) 1076 { 1077 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1078 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1079 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1080 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1081 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1082 udelay(1); 1083 } 1084 1085 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1086 struct rtw89_channel_params *param, 1087 enum rtw89_phy_idx phy_idx) 1088 { 1089 bool cck_en = param->center_chan <= 14; 1090 u8 pri_ch_idx = param->pri_ch_idx; 1091 1092 if (cck_en) 1093 rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan, 1094 param->primary_chan, param->bandwidth); 1095 1096 rtw8852a_ctrl_ch(rtwdev, param->center_chan, phy_idx); 1097 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx); 1098 if (cck_en) { 1099 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1100 } else { 1101 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1102 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1103 } 1104 rtw8852a_spur_elimination(rtwdev, param->center_chan); 1105 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1106 param->primary_chan); 1107 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1108 } 1109 1110 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1111 struct rtw89_channel_params *params) 1112 { 1113 rtw8852a_set_channel_mac(rtwdev, params, RTW89_MAC_0); 1114 rtw8852a_set_channel_bb(rtwdev, params, RTW89_PHY_0); 1115 } 1116 1117 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1118 { 1119 if (en) 1120 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1121 else 1122 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1123 } 1124 1125 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1126 enum rtw89_rf_path path) 1127 { 1128 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1129 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1130 1131 if (en) { 1132 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1133 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1134 } else { 1135 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1136 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1137 } 1138 } 1139 1140 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1141 u8 phy_idx) 1142 { 1143 if (!rtwdev->dbcc_en) { 1144 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1145 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1146 } else { 1147 if (phy_idx == RTW89_PHY_0) 1148 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1149 else 1150 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1151 } 1152 } 1153 1154 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1155 { 1156 if (en) 1157 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1158 0x0); 1159 else 1160 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1161 0xf); 1162 } 1163 1164 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1165 struct rtw89_channel_help_params *p) 1166 { 1167 u8 phy_idx = RTW89_PHY_0; 1168 1169 if (enter) { 1170 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1171 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1172 rtw8852a_dfs_en(rtwdev, false); 1173 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1174 rtw8852a_adc_en(rtwdev, false); 1175 fsleep(40); 1176 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1177 } else { 1178 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1179 rtw8852a_adc_en(rtwdev, true); 1180 rtw8852a_dfs_en(rtwdev, true); 1181 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1182 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1183 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1184 } 1185 } 1186 1187 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1188 { 1189 struct rtw89_efuse *efuse = &rtwdev->efuse; 1190 1191 switch (efuse->rfe_type) { 1192 case 11: 1193 case 12: 1194 case 17: 1195 case 18: 1196 case 51: 1197 case 53: 1198 rtwdev->fem.epa_2g = true; 1199 rtwdev->fem.elna_2g = true; 1200 fallthrough; 1201 case 9: 1202 case 10: 1203 case 15: 1204 case 16: 1205 rtwdev->fem.epa_5g = true; 1206 rtwdev->fem.elna_5g = true; 1207 break; 1208 default: 1209 break; 1210 } 1211 } 1212 1213 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1214 { 1215 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1216 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1217 1218 rtw8852a_rck(rtwdev); 1219 rtw8852a_dack(rtwdev); 1220 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1221 } 1222 1223 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1224 { 1225 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1226 1227 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1228 rtw8852a_iqk(rtwdev, phy_idx); 1229 rtw8852a_tssi(rtwdev, phy_idx); 1230 rtw8852a_dpk(rtwdev, phy_idx); 1231 } 1232 1233 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev) 1234 { 1235 rtw8852a_tssi_scan(rtwdev, RTW89_PHY_0); 1236 } 1237 1238 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1239 { 1240 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1241 } 1242 1243 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1244 { 1245 rtw8852a_dpk_track(rtwdev); 1246 rtw8852a_iqk_track(rtwdev); 1247 rtw8852a_tssi_track(rtwdev); 1248 } 1249 1250 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1251 enum rtw89_phy_idx phy_idx, s16 ref) 1252 { 1253 s8 ofst_int = 0; 1254 u8 base_cw_0db = 0x27; 1255 u16 tssi_16dbm_cw = 0x12c; 1256 s16 pwr_s10_3 = 0; 1257 s16 rf_pwr_cw = 0; 1258 u16 bb_pwr_cw = 0; 1259 u32 pwr_cw = 0; 1260 u32 tssi_ofst_cw = 0; 1261 1262 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1263 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1264 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1265 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1266 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1267 1268 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1269 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1270 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1271 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1272 1273 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1274 } 1275 1276 static 1277 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1278 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1279 { 1280 s8 val_1t = 0; 1281 s8 val_2t = 0; 1282 u32 reg; 1283 1284 if (pw_ofst < -16 || pw_ofst > 15) { 1285 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1286 pw_ofst); 1287 return; 1288 } 1289 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); 1290 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1291 val_1t = pw_ofst; 1292 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1293 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1294 val_2t = max(val_1t - 3, -16); 1295 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1296 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1297 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1298 val_1t, val_2t); 1299 } 1300 1301 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1302 enum rtw89_phy_idx phy_idx) 1303 { 1304 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1305 const u32 mask = 0x7FFFFFF; 1306 const u8 ofst_ofdm = 0x4; 1307 const u8 ofst_cck = 0x8; 1308 s16 ref_ofdm = 0; 1309 s16 ref_cck = 0; 1310 u32 val; 1311 u8 i; 1312 1313 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1314 1315 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1316 GENMASK(27, 10), 0x0); 1317 1318 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1319 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1320 1321 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1322 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1323 phy_idx); 1324 1325 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1326 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1327 1328 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1329 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1330 phy_idx); 1331 } 1332 1333 static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, 1334 enum rtw89_phy_idx phy_idx) 1335 { 1336 u8 ch = rtwdev->hal.current_channel; 1337 static const u8 rs[] = { 1338 RTW89_RS_CCK, 1339 RTW89_RS_OFDM, 1340 RTW89_RS_MCS, 1341 RTW89_RS_HEDCM, 1342 }; 1343 s8 tmp; 1344 u8 i, j; 1345 u32 val, shf, addr = R_AX_PWR_BY_RATE; 1346 struct rtw89_rate_desc cur; 1347 1348 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1349 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 1350 1351 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 1352 for (i = 0; i < ARRAY_SIZE(rs); i++) { 1353 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 1354 continue; 1355 1356 val = 0; 1357 cur.rs = rs[i]; 1358 1359 for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { 1360 cur.idx = j; 1361 shf = (j % 4) * 8; 1362 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur); 1363 val |= (tmp << shf); 1364 1365 if ((j + 1) % 4) 1366 continue; 1367 1368 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1369 val = 0; 1370 addr += 4; 1371 } 1372 } 1373 } 1374 } 1375 1376 static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, 1377 enum rtw89_phy_idx phy_idx) 1378 { 1379 struct rtw89_rate_desc desc = { 1380 .nss = RTW89_NSS_1, 1381 .rs = RTW89_RS_OFFSET, 1382 }; 1383 u32 val = 0; 1384 s8 v; 1385 1386 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 1387 1388 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { 1389 v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc); 1390 val |= ((v & 0xf) << (4 * desc.idx)); 1391 } 1392 1393 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 1394 GENMASK(19, 0), val); 1395 } 1396 1397 static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, 1398 enum rtw89_phy_idx phy_idx) 1399 { 1400 #define __MAC_TXPWR_LMT_PAGE_SIZE 40 1401 u8 ch = rtwdev->hal.current_channel; 1402 u8 bw = rtwdev->hal.current_band_width; 1403 struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; 1404 u32 addr, val; 1405 const s8 *ptr; 1406 u8 i, j, k; 1407 1408 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1409 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 1410 1411 for (i = 0; i < NTX_NUM_8852A; i++) { 1412 rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i); 1413 1414 for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { 1415 addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; 1416 ptr = (s8 *)&lmt[i] + j; 1417 val = 0; 1418 1419 for (k = 0; k < 4; k++) 1420 val |= (ptr[k] << (8 * k)); 1421 1422 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1423 } 1424 } 1425 #undef __MAC_TXPWR_LMT_PAGE_SIZE 1426 } 1427 1428 static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1429 enum rtw89_phy_idx phy_idx) 1430 { 1431 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 1432 u8 ch = rtwdev->hal.current_channel; 1433 u8 bw = rtwdev->hal.current_band_width; 1434 struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; 1435 u32 addr, val; 1436 const s8 *ptr; 1437 u8 i, j, k; 1438 1439 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1440 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 1441 1442 for (i = 0; i < NTX_NUM_8852A; i++) { 1443 rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i); 1444 1445 for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { 1446 addr = R_AX_PWR_RU_LMT + j + 1447 __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; 1448 ptr = (s8 *)&lmt_ru[i] + j; 1449 val = 0; 1450 1451 for (k = 0; k < 4; k++) 1452 val |= (ptr[k] << (8 * k)); 1453 1454 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1455 } 1456 } 1457 1458 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE 1459 } 1460 1461 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev) 1462 { 1463 rtw8852a_set_txpwr_byrate(rtwdev, RTW89_PHY_0); 1464 rtw8852a_set_txpwr_limit(rtwdev, RTW89_PHY_0); 1465 rtw8852a_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0); 1466 } 1467 1468 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 1469 { 1470 rtw8852a_set_txpwr_ref(rtwdev, RTW89_PHY_0); 1471 rtw8852a_set_txpwr_offset(rtwdev, RTW89_PHY_0); 1472 } 1473 1474 static int 1475 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1476 { 1477 int ret; 1478 1479 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1480 if (ret) 1481 return ret; 1482 1483 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1484 if (ret) 1485 return ret; 1486 1487 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1488 if (ret) 1489 return ret; 1490 1491 return 0; 1492 } 1493 1494 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1495 { 1496 u8 i = 0; 1497 u32 addr, val; 1498 1499 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1500 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1501 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1502 rtw89_phy_write32(rtwdev, addr, val); 1503 } 1504 } 1505 1506 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1507 struct rtw8852a_bb_pmac_info *tx_info, 1508 enum rtw89_phy_idx idx) 1509 { 1510 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1511 if (tx_info->mode == CONT_TX) 1512 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1513 idx); 1514 else if (tx_info->mode == PKTS_TX) 1515 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1516 idx); 1517 } 1518 1519 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1520 struct rtw8852a_bb_pmac_info *tx_info, 1521 enum rtw89_phy_idx idx) 1522 { 1523 enum rtw8852a_pmac_mode mode = tx_info->mode; 1524 u32 pkt_cnt = tx_info->tx_cnt; 1525 u16 period = tx_info->period; 1526 1527 if (mode == CONT_TX && !tx_info->is_cck) { 1528 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1529 idx); 1530 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1531 } else if (mode == PKTS_TX) { 1532 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1533 idx); 1534 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1535 B_PMAC_TX_PRD_MSK, period, idx); 1536 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1537 pkt_cnt, idx); 1538 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1539 } 1540 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1541 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1542 } 1543 1544 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1545 struct rtw8852a_bb_pmac_info *tx_info, 1546 enum rtw89_phy_idx idx) 1547 { 1548 if (!tx_info->en_pmac_tx) { 1549 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1550 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1551 if (rtwdev->hal.current_band_type == RTW89_BAND_2G) 1552 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1553 return; 1554 } 1555 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1556 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1557 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1558 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1559 idx); 1560 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1561 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1562 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1563 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1564 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1565 } 1566 1567 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1568 u16 tx_cnt, u16 period, u16 tx_time, 1569 enum rtw89_phy_idx idx) 1570 { 1571 struct rtw8852a_bb_pmac_info tx_info = {0}; 1572 1573 tx_info.en_pmac_tx = enable; 1574 tx_info.is_cck = 0; 1575 tx_info.mode = PKTS_TX; 1576 tx_info.tx_cnt = tx_cnt; 1577 tx_info.period = period; 1578 tx_info.tx_time = tx_time; 1579 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1580 } 1581 1582 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1583 enum rtw89_phy_idx idx) 1584 { 1585 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1586 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1587 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1588 } 1589 1590 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1591 { 1592 u32 rst_mask0 = 0; 1593 u32 rst_mask1 = 0; 1594 1595 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1596 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1597 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1598 if (!rtwdev->dbcc_en) { 1599 if (tx_path == RF_PATH_A) { 1600 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1601 B_TXPATH_SEL_MSK, 1); 1602 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1603 B_TXNSS_MAP_MSK, 0); 1604 } else if (tx_path == RF_PATH_B) { 1605 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1606 B_TXPATH_SEL_MSK, 2); 1607 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1608 B_TXNSS_MAP_MSK, 0); 1609 } else if (tx_path == RF_PATH_AB) { 1610 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1611 B_TXPATH_SEL_MSK, 3); 1612 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1613 B_TXNSS_MAP_MSK, 4); 1614 } else { 1615 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1616 } 1617 } else { 1618 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1619 1); 1620 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1621 RTW89_PHY_1); 1622 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1623 0); 1624 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1625 RTW89_PHY_1); 1626 } 1627 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1628 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1629 if (tx_path == RF_PATH_A) { 1630 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1631 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1632 } else { 1633 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1634 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1635 } 1636 } 1637 1638 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1639 enum rtw89_phy_idx idx, u8 mode) 1640 { 1641 if (mode != 0) 1642 return; 1643 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1644 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1645 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1646 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1647 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1648 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1649 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1650 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1651 } 1652 1653 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1654 { 1655 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : 1656 &rtw8852a_btc_preagc_dis_defs_tbl); 1657 } 1658 1659 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1660 { 1661 if (rtwdev->is_tssi_mode[rf_path]) { 1662 u32 addr = 0x1c10 + (rf_path << 13); 1663 1664 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1665 } 1666 1667 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1668 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1669 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1670 1671 fsleep(200); 1672 1673 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1674 } 1675 1676 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1677 { 1678 struct rtw89_btc *btc = &rtwdev->btc; 1679 struct rtw89_btc_module *module = &btc->mdinfo; 1680 1681 module->rfe_type = rtwdev->efuse.rfe_type; 1682 module->cv = rtwdev->hal.cv; 1683 module->bt_solo = 0; 1684 module->switch_type = BTC_SWITCH_INTERNAL; 1685 1686 if (module->rfe_type > 0) 1687 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1688 else 1689 module->ant.num = 2; 1690 1691 module->ant.diversity = 0; 1692 module->ant.isolation = 10; 1693 1694 if (module->ant.num == 3) { 1695 module->ant.type = BTC_ANT_DEDICATED; 1696 module->bt_pos = BTC_BT_ALONE; 1697 } else { 1698 module->ant.type = BTC_ANT_SHARED; 1699 module->bt_pos = BTC_BT_BTG; 1700 } 1701 } 1702 1703 static 1704 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1705 { 1706 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1707 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1708 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1709 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1710 } 1711 1712 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1713 { 1714 if (btg) { 1715 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1716 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1717 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1718 } else { 1719 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1720 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1721 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1722 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1723 } 1724 } 1725 1726 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1727 { 1728 struct rtw89_btc *btc = &rtwdev->btc; 1729 struct rtw89_btc_module *module = &btc->mdinfo; 1730 const struct rtw89_chip_info *chip = rtwdev->chip; 1731 const struct rtw89_mac_ax_coex coex_params = { 1732 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1733 .direction = RTW89_MAC_AX_COEX_INNER, 1734 }; 1735 1736 /* PTA init */ 1737 rtw89_mac_coex_init(rtwdev, &coex_params); 1738 1739 /* set WL Tx response = Hi-Pri */ 1740 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1741 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1742 1743 /* set rf gnt debug off */ 1744 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1745 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1746 1747 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1748 if (module->ant.type == BTC_ANT_SHARED) { 1749 rtw8852a_set_trx_mask(rtwdev, 1750 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1751 rtw8852a_set_trx_mask(rtwdev, 1752 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1753 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1754 rtw8852a_set_trx_mask(rtwdev, 1755 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1756 rtw8852a_set_trx_mask(rtwdev, 1757 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1758 } 1759 1760 /* set PTA break table */ 1761 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1762 1763 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1764 rtw89_write32_set(rtwdev, 1765 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1766 btc->cx.wl.status.map.init_ok = true; 1767 } 1768 1769 static 1770 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1771 { 1772 u32 bitmap = 0; 1773 u32 reg = 0; 1774 1775 switch (map) { 1776 case BTC_PRI_MASK_TX_RESP: 1777 reg = R_BTC_BT_COEX_MSK_TABLE; 1778 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1779 break; 1780 case BTC_PRI_MASK_BEACON: 1781 reg = R_AX_WL_PRI_MSK; 1782 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1783 break; 1784 default: 1785 return; 1786 } 1787 1788 if (state) 1789 rtw89_write32_set(rtwdev, reg, bitmap); 1790 else 1791 rtw89_write32_clr(rtwdev, reg, bitmap); 1792 } 1793 1794 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1795 { 1796 return FIELD_GET(GENMASK(15, 0), ctrl); 1797 } 1798 1799 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1800 { 1801 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1802 } 1803 1804 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1805 { 1806 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1807 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1808 1809 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1810 } 1811 1812 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1813 { 1814 return FIELD_GET(GENMASK(31, 16), ctrl); 1815 } 1816 1817 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1818 { 1819 return cur & ~B_AX_TXAGC_BT_EN; 1820 } 1821 1822 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1823 { 1824 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1825 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1826 1827 return ov | iv | B_AX_TXAGC_BT_EN; 1828 } 1829 1830 static void 1831 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1832 { 1833 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1834 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1835 1836 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1837 #define __handle(_case) \ 1838 do { \ 1839 const u32 _reg = __btc_cr_ ## _case; \ 1840 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1841 u32 _cur, _wrt; \ 1842 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1843 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1844 rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ 1845 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1846 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1847 _wrt = __do_clr(_val) ? \ 1848 __btc_ctrl_rst_ ## _case(_cur) : \ 1849 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1850 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1851 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1852 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1853 } while (0) 1854 1855 __handle(all_time); 1856 __handle(gnt_bt); 1857 1858 #undef __handle 1859 #undef __do_clr 1860 } 1861 1862 static 1863 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1864 { 1865 return clamp_t(s8, val, -100, 0) + 100; 1866 } 1867 1868 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1869 {255, 0, 0, 7}, /* 0 -> original */ 1870 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1871 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1872 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1873 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1874 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1875 {6, 1, 0, 7}, 1876 {13, 1, 0, 7}, 1877 {13, 1, 0, 7} 1878 }; 1879 1880 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1881 {255, 0, 0, 7}, /* 0 -> original */ 1882 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1883 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1884 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1885 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1886 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1887 {255, 1, 0, 7}, 1888 {255, 1, 0, 7}, 1889 {255, 1, 0, 7} 1890 }; 1891 1892 static const 1893 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1894 static const 1895 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1896 1897 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1898 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1899 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1900 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1901 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1902 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1903 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1904 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1905 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1906 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1907 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1908 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1909 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1910 }; 1911 1912 static 1913 void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) 1914 { 1915 struct rtw89_btc *btc = &rtwdev->btc; 1916 struct rtw89_btc_dm *dm = &btc->dm; 1917 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 1918 struct rtw89_btc_bt_link_info *b = &bt->link_info; 1919 1920 /* fix LNA2 = level-5 for BT ACI issue at BTG */ 1921 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) 1922 dm->trx_para_level = 1; 1923 } 1924 1925 static 1926 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1927 { 1928 struct rtw89_btc *btc = &rtwdev->btc; 1929 struct rtw89_btc_cx *cx = &btc->cx; 1930 u32 val; 1931 1932 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1933 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1934 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1935 1936 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1937 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1938 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1939 1940 /* clock-gate off before reset counter*/ 1941 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1942 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1943 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1944 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1945 } 1946 1947 static 1948 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1949 { 1950 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1951 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1952 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1953 1954 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1955 if (state) 1956 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1957 RFREG_MASK, 0xa2d7c); 1958 else 1959 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1960 RFREG_MASK, 0xa2020); 1961 1962 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1963 } 1964 1965 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 1966 struct rtw89_rx_phy_ppdu *phy_ppdu, 1967 struct ieee80211_rx_status *status) 1968 { 1969 u16 chan = phy_ppdu->chan_idx; 1970 u8 band; 1971 1972 if (chan == 0) 1973 return; 1974 1975 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1976 status->freq = ieee80211_channel_to_frequency(chan, band); 1977 status->band = band; 1978 } 1979 1980 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 1981 struct rtw89_rx_phy_ppdu *phy_ppdu, 1982 struct ieee80211_rx_status *status) 1983 { 1984 u8 path; 1985 s8 *rx_power = phy_ppdu->rssi; 1986 1987 status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 1988 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 1989 status->chains |= BIT(path); 1990 status->chain_signal[path] = rx_power[path]; 1991 } 1992 if (phy_ppdu->valid) 1993 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 1994 } 1995 1996 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 1997 .bb_reset = rtw8852a_bb_reset, 1998 .bb_sethw = rtw8852a_bb_sethw, 1999 .read_rf = rtw89_phy_read_rf, 2000 .write_rf = rtw89_phy_write_rf, 2001 .set_channel = rtw8852a_set_channel, 2002 .set_channel_help = rtw8852a_set_channel_help, 2003 .read_efuse = rtw8852a_read_efuse, 2004 .read_phycap = rtw8852a_read_phycap, 2005 .fem_setup = rtw8852a_fem_setup, 2006 .rfk_init = rtw8852a_rfk_init, 2007 .rfk_channel = rtw8852a_rfk_channel, 2008 .rfk_band_changed = rtw8852a_rfk_band_changed, 2009 .rfk_scan = rtw8852a_rfk_scan, 2010 .rfk_track = rtw8852a_rfk_track, 2011 .power_trim = rtw8852a_power_trim, 2012 .set_txpwr = rtw8852a_set_txpwr, 2013 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2014 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2015 .get_thermal = rtw8852a_get_thermal, 2016 .ctrl_btg = rtw8852a_ctrl_btg, 2017 .query_ppdu = rtw8852a_query_ppdu, 2018 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, 2019 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2020 .pwr_on_func = NULL, 2021 .pwr_off_func = NULL, 2022 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2023 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2024 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2025 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2026 2027 .btc_set_rfe = rtw8852a_btc_set_rfe, 2028 .btc_init_cfg = rtw8852a_btc_init_cfg, 2029 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2030 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2031 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2032 .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, 2033 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2034 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2035 }; 2036 2037 const struct rtw89_chip_info rtw8852a_chip_info = { 2038 .chip_id = RTL8852A, 2039 .ops = &rtw8852a_chip_ops, 2040 .fw_name = "rtw89/rtw8852a_fw.bin", 2041 .fifo_size = 458752, 2042 .max_amsdu_limit = 3500, 2043 .dis_2g_40m_ul_ofdma = true, 2044 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2045 .dle_mem = rtw8852a_dle_mem_pcie, 2046 .rf_base_addr = {0xc000, 0xd000}, 2047 .pwr_on_seq = pwr_on_seq_8852a, 2048 .pwr_off_seq = pwr_off_seq_8852a, 2049 .bb_table = &rtw89_8852a_phy_bb_table, 2050 .rf_table = {&rtw89_8852a_phy_radioa_table, 2051 &rtw89_8852a_phy_radiob_table,}, 2052 .nctl_table = &rtw89_8852a_phy_nctl_table, 2053 .byr_table = &rtw89_8852a_byr_table, 2054 .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, 2055 .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, 2056 .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, 2057 .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, 2058 .txpwr_factor_rf = 2, 2059 .txpwr_factor_mac = 1, 2060 .dig_table = &rtw89_8852a_phy_dig_table, 2061 .support_bands = BIT(NL80211_BAND_2GHZ) | 2062 BIT(NL80211_BAND_5GHZ), 2063 .support_bw160 = false, 2064 .rf_path_num = 2, 2065 .tx_nss = 2, 2066 .rx_nss = 2, 2067 .acam_num = 128, 2068 .bcam_num = 10, 2069 .scam_num = 128, 2070 .sec_ctrl_efuse_size = 4, 2071 .physical_efuse_size = 1216, 2072 .logical_efuse_size = 1536, 2073 .limit_efuse_size = 1152, 2074 .dav_phy_efuse_size = 0, 2075 .dav_log_efuse_size = 0, 2076 .phycap_addr = 0x580, 2077 .phycap_size = 128, 2078 .para_ver = 0x05050864, 2079 .wlcx_desired = 0x05050000, 2080 .btcx_desired = 0x5, 2081 .scbd = 0x1, 2082 .mailbox = 0x1, 2083 .afh_guard_ch = 6, 2084 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2085 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2086 .rssi_tol = 2, 2087 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2088 .mon_reg = rtw89_btc_8852a_mon_reg, 2089 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2090 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2091 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2092 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2093 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2094 BIT(RTW89_PS_MODE_CLK_GATED) | 2095 BIT(RTW89_PS_MODE_PWR_GATED), 2096 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2097 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2098 .h2c_regs = rtw8852a_h2c_regs, 2099 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2100 .c2h_regs = rtw8852a_c2h_regs, 2101 .page_regs = &rtw8852a_page_regs, 2102 .dcfo_comp = &rtw8852a_dcfo_comp, 2103 .dcfo_comp_sft = 3, 2104 }; 2105 EXPORT_SYMBOL(rtw8852a_chip_info); 2106 2107 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); 2108 MODULE_AUTHOR("Realtek Corporation"); 2109 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2110 MODULE_LICENSE("Dual BSD/GPL"); 2111