1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2022-2023 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "efuse.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rtw8851b.h" 12 #include "rtw8851b_rfk.h" 13 #include "rtw8851b_rfk_table.h" 14 #include "rtw8851b_table.h" 15 #include "txrx.h" 16 #include "util.h" 17 18 #define RTW8851B_FW_FORMAT_MAX 0 19 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw" 20 #define RTW8851B_MODULE_FIRMWARE \ 21 RTW8851B_FW_BASENAME ".bin" 22 23 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = { 24 {5, 343, grp_0}, /* ACH 0 */ 25 {5, 343, grp_0}, /* ACH 1 */ 26 {5, 343, grp_0}, /* ACH 2 */ 27 {5, 343, grp_0}, /* ACH 3 */ 28 {0, 0, grp_0}, /* ACH 4 */ 29 {0, 0, grp_0}, /* ACH 5 */ 30 {0, 0, grp_0}, /* ACH 6 */ 31 {0, 0, grp_0}, /* ACH 7 */ 32 {4, 344, grp_0}, /* B0MGQ */ 33 {4, 344, grp_0}, /* B0HIQ */ 34 {0, 0, grp_0}, /* B1MGQ */ 35 {0, 0, grp_0}, /* B1HIQ */ 36 {40, 0, 0} /* FWCMDQ */ 37 }; 38 39 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = { 40 448, /* Group 0 */ 41 0, /* Group 1 */ 42 448, /* Public Max */ 43 0 /* WP threshold */ 44 }; 45 46 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = { 47 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie, 48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 50 RTW89_HCIFC_POH}, 51 [RTW89_QTA_INVALID] = {NULL}, 52 }; 53 54 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = { 55 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6, 56 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 57 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 58 &rtw89_mac_size.ple_qt58}, 59 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6, 60 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 61 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 62 &rtw89_mac_size.ple_qt_51b_wow}, 63 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 64 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 65 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 66 &rtw89_mac_size.ple_qt13}, 67 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 68 NULL}, 69 }; 70 71 static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = { 72 {0x46D0, GENMASK(1, 0), 0x3}, 73 {0x4AD4, GENMASK(31, 0), 0xf}, 74 {0x4688, GENMASK(23, 16), 0x80}, 75 {0x4688, GENMASK(31, 24), 0x80}, 76 {0x4694, GENMASK(7, 0), 0x80}, 77 {0x4694, GENMASK(15, 8), 0x80}, 78 {0x4AE4, GENMASK(11, 6), 0x34}, 79 {0x4AE4, GENMASK(17, 12), 0x0}, 80 {0x469C, GENMASK(31, 26), 0x34}, 81 }; 82 83 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs); 84 85 static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = { 86 {0x46D0, GENMASK(1, 0), 0x0}, 87 {0x4AD4, GENMASK(31, 0), 0x60}, 88 {0x4688, GENMASK(23, 16), 0x10}, 89 {0x4690, GENMASK(31, 24), 0x2a}, 90 {0x4694, GENMASK(15, 8), 0x2a}, 91 {0x4AE4, GENMASK(11, 6), 0x26}, 92 {0x4AE4, GENMASK(17, 12), 0x1e}, 93 {0x469C, GENMASK(31, 26), 0x26}, 94 }; 95 96 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs); 97 98 static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = { 99 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 100 R_AX_H2CREG_DATA3 101 }; 102 103 static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = { 104 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 105 R_AX_C2HREG_DATA3 106 }; 107 108 static const u32 rtw8851b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 109 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 110 }; 111 112 static const struct rtw89_page_regs rtw8851b_page_regs = { 113 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 114 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 115 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 116 .ach_page_info = R_AX_ACH0_PAGE_INFO, 117 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 118 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 119 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 120 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 121 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 122 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 123 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 124 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 125 }; 126 127 static const struct rtw89_reg_def rtw8851b_dcfo_comp = { 128 R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2 129 }; 130 131 static const struct rtw89_imr_info rtw8851b_imr_info = { 132 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 133 .wsec_imr_reg = R_AX_SEC_DEBUG, 134 .wsec_imr_set = B_AX_IMR_ERROR, 135 .mpdu_tx_imr_set = 0, 136 .mpdu_rx_imr_set = 0, 137 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 138 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 139 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 140 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 141 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 142 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 143 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 144 .wde_imr_clr = B_AX_WDE_IMR_CLR, 145 .wde_imr_set = B_AX_WDE_IMR_SET, 146 .ple_imr_clr = B_AX_PLE_IMR_CLR, 147 .ple_imr_set = B_AX_PLE_IMR_SET, 148 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 149 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 150 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 151 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 152 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 153 .other_disp_imr_set = 0, 154 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 155 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 156 .bbrpt_err_imr_set = 0, 157 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 158 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 159 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 160 .cdma_imr_0_reg = R_AX_DLE_CTRL, 161 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 162 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 163 .cdma_imr_1_reg = 0, 164 .cdma_imr_1_clr = 0, 165 .cdma_imr_1_set = 0, 166 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 167 .phy_intf_imr_clr = 0, 168 .phy_intf_imr_set = 0, 169 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 170 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 171 .rmac_imr_set = B_AX_RMAC_IMR_SET, 172 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 173 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 174 .tmac_imr_set = B_AX_TMAC_IMR_SET, 175 }; 176 177 static const struct rtw89_xtal_info rtw8851b_xtal_info = { 178 .xcap_reg = R_AX_XTAL_ON_CTRL3, 179 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK, 180 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK, 181 }; 182 183 static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = { 184 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 185 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 186 }; 187 188 static const struct rtw89_dig_regs rtw8851b_dig_regs = { 189 .seg0_pd_reg = R_SEG0R_PD_V1, 190 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 191 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 192 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 193 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 194 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 195 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 196 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 197 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 198 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 199 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 200 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 201 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 202 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 203 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 204 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 205 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 206 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 207 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 208 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 209 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 210 }; 211 212 static const struct rtw89_edcca_regs rtw8851b_edcca_regs = { 213 .edcca_level = R_SEG0R_EDCCA_LVL_V1, 214 .edcca_mask = B_EDCCA_LVL_MSK0, 215 .edcca_p_mask = B_EDCCA_LVL_MSK1, 216 .ppdu_level = R_SEG0R_EDCCA_LVL_V1, 217 .ppdu_mask = B_EDCCA_LVL_MSK3, 218 .rpt_a = R_EDCCA_RPT_A, 219 .rpt_b = R_EDCCA_RPT_B, 220 .rpt_sel = R_EDCCA_RPT_SEL, 221 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 222 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 223 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 224 }; 225 226 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = { 227 {255, 0, 0, 7}, /* 0 -> original */ 228 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 229 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 230 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 231 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 232 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 233 {6, 1, 0, 7}, 234 {13, 1, 0, 7}, 235 {13, 1, 0, 7} 236 }; 237 238 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = { 239 {255, 0, 0, 7}, /* 0 -> original */ 240 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 241 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 242 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 243 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 244 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 245 {255, 1, 0, 7}, 246 {255, 1, 0, 7}, 247 {255, 1, 0, 7} 248 }; 249 250 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = { 251 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 252 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 253 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 254 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 255 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 256 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 257 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 258 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 259 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 260 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 261 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 262 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 263 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 264 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), 265 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), 266 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), 267 }; 268 269 static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 270 static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 271 272 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev) 273 { 274 u32 val32; 275 u8 val8; 276 u32 ret; 277 278 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 279 B_AX_AFSM_PCIE_SUS_EN); 280 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 281 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 282 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 283 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 284 285 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 286 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 287 if (ret) 288 return ret; 289 290 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 291 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 292 293 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 294 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 295 if (ret) 296 return ret; 297 298 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 299 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 300 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 301 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 302 303 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 304 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 305 306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 307 XTAL_SI_OFF_WEI); 308 if (ret) 309 return ret; 310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 311 XTAL_SI_OFF_EI); 312 if (ret) 313 return ret; 314 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 315 if (ret) 316 return ret; 317 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 318 XTAL_SI_PON_WEI); 319 if (ret) 320 return ret; 321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 322 XTAL_SI_PON_EI); 323 if (ret) 324 return ret; 325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 326 if (ret) 327 return ret; 328 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 329 if (ret) 330 return ret; 331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 332 if (ret) 333 return ret; 334 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 335 if (ret) 336 return ret; 337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH); 338 if (ret) 339 return ret; 340 341 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 342 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 343 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 344 345 fsleep(1000); 346 347 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 348 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 349 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN, 350 B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1); 351 352 if (rtwdev->hal.cv == CHIP_CAV) { 353 ret = rtw89_read_efuse_ver(rtwdev, &val8); 354 if (!ret) 355 rtwdev->hal.cv = val8; 356 } 357 358 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG, 359 B_AX_XTAL_SI_ADDR_NOT_CHK); 360 if (rtwdev->hal.cv != CHIP_CAV) { 361 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY); 362 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY); 363 } 364 365 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 366 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 367 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 368 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 369 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 370 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 371 B_AX_DMACREG_GCKEN); 372 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 373 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 374 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 375 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 376 B_AX_RMAC_EN); 377 378 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, 379 PINMUX_EESK_FUNC_SEL_BT_LOG); 380 381 return 0; 382 } 383 384 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev) 385 { 386 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR); 387 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM); 388 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM); 389 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM); 390 } 391 392 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev) 393 { 394 u32 val32; 395 u32 ret; 396 397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 398 XTAL_SI_RFC2RF); 399 if (ret) 400 return ret; 401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 402 if (ret) 403 return ret; 404 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 405 if (ret) 406 return ret; 407 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 408 if (ret) 409 return ret; 410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 411 XTAL_SI_SRAM2RFC); 412 if (ret) 413 return ret; 414 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 415 if (ret) 416 return ret; 417 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 418 if (ret) 419 return ret; 420 421 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG, 422 B_AX_XTAL_SI_ADDR_NOT_CHK); 423 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 424 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 425 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 426 427 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 428 429 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 430 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 431 if (ret) 432 return ret; 433 434 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 435 436 if (rtwdev->hal.cv == CHIP_CAV) { 437 rtw8851b_patch_swr_pfm2pwm(rtwdev); 438 } else { 439 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY); 440 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY); 441 } 442 443 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 444 445 return 0; 446 } 447 448 static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse, 449 struct rtw8851b_efuse *map) 450 { 451 ether_addr_copy(efuse->addr, map->e.mac_addr); 452 efuse->rfe_type = map->rfe_type; 453 efuse->xtal_cap = map->xtal_k; 454 } 455 456 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 457 struct rtw8851b_efuse *map) 458 { 459 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 460 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi}; 461 u8 i, j; 462 463 tssi->thermal[RF_PATH_A] = map->path_a_therm; 464 465 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 466 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 467 sizeof(ofst[i]->cck_tssi)); 468 469 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 470 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 471 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 472 i, j, tssi->tssi_cck[i][j]); 473 474 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 475 sizeof(ofst[i]->bw40_tssi)); 476 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 477 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 478 479 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 480 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 481 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 482 i, j, tssi->tssi_mcs[i][j]); 483 } 484 } 485 486 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 487 { 488 if (high) 489 *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3); 490 if (low) 491 *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3); 492 493 return data != 0xff; 494 } 495 496 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 497 struct rtw8851b_efuse *map) 498 { 499 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 500 bool valid = false; 501 502 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 503 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 504 NULL); 505 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 506 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 507 NULL); 508 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 509 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 510 NULL); 511 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 512 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 513 NULL); 514 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 515 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 516 NULL); 517 518 gain->offset_valid = valid; 519 } 520 521 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 522 enum rtw89_efuse_block block) 523 { 524 struct rtw89_efuse *efuse = &rtwdev->efuse; 525 struct rtw8851b_efuse *map; 526 527 map = (struct rtw8851b_efuse *)log_map; 528 529 efuse->country_code[0] = map->country_code[0]; 530 efuse->country_code[1] = map->country_code[1]; 531 rtw8851b_efuse_parsing_tssi(rtwdev, map); 532 rtw8851b_efuse_parsing_gain_offset(rtwdev, map); 533 534 switch (rtwdev->hci.type) { 535 case RTW89_HCI_TYPE_PCIE: 536 rtw8851b_efuse_parsing(efuse, map); 537 break; 538 default: 539 return -EOPNOTSUPP; 540 } 541 542 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 543 544 return 0; 545 } 546 547 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 548 { 549 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 550 static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6}; 551 u32 addr = rtwdev->chip->phycap_addr; 552 bool pg = false; 553 u32 ofst; 554 u8 i, j; 555 556 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 557 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 558 /* addrs are in decreasing order */ 559 ofst = tssi_trim_addr[i] - addr - j; 560 tssi->tssi_trim[i][j] = phycap_map[ofst]; 561 562 if (phycap_map[ofst] != 0xff) 563 pg = true; 564 } 565 } 566 567 if (!pg) { 568 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 569 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 570 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 571 } 572 573 for (i = 0; i < RF_PATH_NUM_8851B; i++) 574 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 575 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 576 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 577 i, j, tssi->tssi_trim[i][j], 578 tssi_trim_addr[i] - j); 579 } 580 581 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 582 u8 *phycap_map) 583 { 584 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 585 static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF}; 586 u32 addr = rtwdev->chip->phycap_addr; 587 u8 i; 588 589 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 590 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 591 592 rtw89_debug(rtwdev, RTW89_DBG_RFK, 593 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 594 i, info->thermal_trim[i]); 595 596 if (info->thermal_trim[i] != 0xff) 597 info->pg_thermal_trim = true; 598 } 599 } 600 601 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev) 602 { 603 #define __thm_setting(raw) \ 604 ({ \ 605 u8 __v = (raw); \ 606 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 607 }) 608 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 609 u8 i, val; 610 611 if (!info->pg_thermal_trim) { 612 rtw89_debug(rtwdev, RTW89_DBG_RFK, 613 "[THERMAL][TRIM] no PG, do nothing\n"); 614 615 return; 616 } 617 618 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 619 val = __thm_setting(info->thermal_trim[i]); 620 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 621 622 rtw89_debug(rtwdev, RTW89_DBG_RFK, 623 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 624 i, val); 625 } 626 #undef __thm_setting 627 } 628 629 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 630 u8 *phycap_map) 631 { 632 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 633 static const u32 pabias_trim_addr[] = {0x5DE}; 634 u32 addr = rtwdev->chip->phycap_addr; 635 u8 i; 636 637 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 638 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 639 640 rtw89_debug(rtwdev, RTW89_DBG_RFK, 641 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 642 i, info->pa_bias_trim[i]); 643 644 if (info->pa_bias_trim[i] != 0xff) 645 info->pg_pa_bias_trim = true; 646 } 647 } 648 649 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev) 650 { 651 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 652 u8 pabias_2g, pabias_5g; 653 u8 i; 654 655 if (!info->pg_pa_bias_trim) { 656 rtw89_debug(rtwdev, RTW89_DBG_RFK, 657 "[PA_BIAS][TRIM] no PG, do nothing\n"); 658 659 return; 660 } 661 662 for (i = 0; i < RF_PATH_NUM_8851B; i++) { 663 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0)); 664 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4)); 665 666 rtw89_debug(rtwdev, RTW89_DBG_RFK, 667 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 668 i, pabias_2g, pabias_5g); 669 670 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 671 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 672 } 673 } 674 675 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) 676 { 677 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { 678 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, 679 }; 680 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 681 u32 phycap_addr = rtwdev->chip->phycap_addr; 682 bool valid = false; 683 int path, i; 684 u8 data; 685 686 for (path = 0; path < BB_PATH_NUM_8851B; path++) 687 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { 688 if (comp_addrs[path][i] == 0) 689 continue; 690 691 data = phycap_map[comp_addrs[path][i] - phycap_addr]; 692 valid |= _decode_efuse_gain(data, NULL, 693 &gain->comp[path][i]); 694 } 695 696 gain->comp_valid = valid; 697 } 698 699 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 700 { 701 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map); 702 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map); 703 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 704 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map); 705 706 return 0; 707 } 708 709 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv, 710 u8 src_sel) 711 { 712 u32 addr, mask; 713 714 if (gpio_idx >= 32) 715 return; 716 717 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */ 718 addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32); 719 mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2; 720 721 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A); 722 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv); 723 724 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */ 725 addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32); 726 mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4; 727 728 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel); 729 } 730 731 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func) 732 { 733 static const struct rtw89_reg3_def func16 = { 734 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3) 735 }; 736 static const struct rtw89_reg3_def func17 = { 737 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4, 738 }; 739 const struct rtw89_reg3_def *def; 740 741 switch (func) { 742 case 16: 743 def = &func16; 744 break; 745 case 17: 746 def = &func17; 747 break; 748 default: 749 rtw89_warn(rtwdev, "undefined gpio func %d\n", func); 750 return; 751 } 752 753 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data); 754 } 755 756 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev) 757 { 758 u8 rfe_type = rtwdev->efuse.rfe_type; 759 760 if (rfe_type > 50) 761 return; 762 763 if (rfe_type % 3 == 2) { 764 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0); 765 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0); 766 767 rtw8851b_set_mac_gpio(rtwdev, 16); 768 rtw8851b_set_mac_gpio(rtwdev, 17); 769 } 770 } 771 772 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev) 773 { 774 rtw8851b_thermal_trim(rtwdev); 775 rtw8851b_pa_bias_trim(rtwdev); 776 } 777 778 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev, 779 const struct rtw89_chan *chan, 780 u8 mac_idx) 781 { 782 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 783 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 784 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 785 u8 txsc20 = 0, txsc40 = 0; 786 787 switch (chan->band_width) { 788 case RTW89_CHANNEL_WIDTH_80: 789 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); 790 fallthrough; 791 case RTW89_CHANNEL_WIDTH_40: 792 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); 793 break; 794 default: 795 break; 796 } 797 798 switch (chan->band_width) { 799 case RTW89_CHANNEL_WIDTH_80: 800 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 801 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 802 break; 803 case RTW89_CHANNEL_WIDTH_40: 804 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 805 rtw89_write32(rtwdev, sub_carr, txsc20); 806 break; 807 case RTW89_CHANNEL_WIDTH_20: 808 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 809 rtw89_write32(rtwdev, sub_carr, 0); 810 break; 811 default: 812 break; 813 } 814 815 if (chan->channel > 14) { 816 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); 817 rtw89_write8_set(rtwdev, chk_rate, 818 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 819 } else { 820 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); 821 rtw89_write8_clr(rtwdev, chk_rate, 822 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 823 } 824 } 825 826 static const u32 rtw8851b_sco_barker_threshold[14] = { 827 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 828 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 829 }; 830 831 static const u32 rtw8851b_sco_cck_threshold[14] = { 832 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 833 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 834 }; 835 836 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) 837 { 838 u8 ch_element = primary_ch - 1; 839 840 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 841 rtw8851b_sco_barker_threshold[ch_element]); 842 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 843 rtw8851b_sco_cck_threshold[ch_element]); 844 } 845 846 static u8 rtw8851b_sco_mapping(u8 central_ch) 847 { 848 if (central_ch == 1) 849 return 109; 850 else if (central_ch >= 2 && central_ch <= 6) 851 return 108; 852 else if (central_ch >= 7 && central_ch <= 10) 853 return 107; 854 else if (central_ch >= 11 && central_ch <= 14) 855 return 106; 856 else if (central_ch == 36 || central_ch == 38) 857 return 51; 858 else if (central_ch >= 40 && central_ch <= 58) 859 return 50; 860 else if (central_ch >= 60 && central_ch <= 64) 861 return 49; 862 else if (central_ch == 100 || central_ch == 102) 863 return 48; 864 else if (central_ch >= 104 && central_ch <= 126) 865 return 47; 866 else if (central_ch >= 128 && central_ch <= 151) 867 return 46; 868 else if (central_ch >= 153 && central_ch <= 177) 869 return 45; 870 else 871 return 0; 872 } 873 874 struct rtw8851b_bb_gain { 875 u32 gain_g[BB_PATH_NUM_8851B]; 876 u32 gain_a[BB_PATH_NUM_8851B]; 877 u32 gain_mask; 878 }; 879 880 static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 881 { .gain_g = {0x4678}, .gain_a = {0x45DC}, 882 .gain_mask = 0x00ff0000 }, 883 { .gain_g = {0x4678}, .gain_a = {0x45DC}, 884 .gain_mask = 0xff000000 }, 885 { .gain_g = {0x467C}, .gain_a = {0x4660}, 886 .gain_mask = 0x000000ff }, 887 { .gain_g = {0x467C}, .gain_a = {0x4660}, 888 .gain_mask = 0x0000ff00 }, 889 { .gain_g = {0x467C}, .gain_a = {0x4660}, 890 .gain_mask = 0x00ff0000 }, 891 { .gain_g = {0x467C}, .gain_a = {0x4660}, 892 .gain_mask = 0xff000000 }, 893 { .gain_g = {0x4680}, .gain_a = {0x4664}, 894 .gain_mask = 0x000000ff }, 895 }; 896 897 static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 898 { .gain_g = {0x4680}, .gain_a = {0x4664}, 899 .gain_mask = 0x00ff0000 }, 900 { .gain_g = {0x4680}, .gain_a = {0x4664}, 901 .gain_mask = 0xff000000 }, 902 }; 903 904 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev, 905 enum rtw89_subband subband, 906 enum rtw89_rf_path path) 907 { 908 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 909 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 910 s32 val; 911 u32 reg; 912 u32 mask; 913 int i; 914 915 for (i = 0; i < LNA_GAIN_NUM; i++) { 916 if (subband == RTW89_CH_2G) 917 reg = bb_gain_lna[i].gain_g[path]; 918 else 919 reg = bb_gain_lna[i].gain_a[path]; 920 921 mask = bb_gain_lna[i].gain_mask; 922 val = gain->lna_gain[gain_band][path][i]; 923 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 924 } 925 926 for (i = 0; i < TIA_GAIN_NUM; i++) { 927 if (subband == RTW89_CH_2G) 928 reg = bb_gain_tia[i].gain_g[path]; 929 else 930 reg = bb_gain_tia[i].gain_a[path]; 931 932 mask = bb_gain_tia[i].gain_mask; 933 val = gain->tia_gain[gain_band][path][i]; 934 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 935 } 936 } 937 938 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev, 939 enum rtw89_subband subband, 940 enum rtw89_phy_idx phy_idx) 941 { 942 static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1}; 943 static const u32 gain_err_addr[] = {R_P0_AGC_RSVD}; 944 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 945 enum rtw89_gain_offset gain_ofdm_band; 946 s32 offset_ofdm, offset_cck; 947 s32 offset_a; 948 s32 tmp; 949 u8 path; 950 951 if (!efuse_gain->comp_valid) 952 goto next; 953 954 for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) { 955 tmp = efuse_gain->comp[path][subband]; 956 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); 957 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); 958 } 959 960 next: 961 if (!efuse_gain->offset_valid) 962 return; 963 964 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); 965 966 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 967 968 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 969 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 970 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); 971 972 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 973 offset_cck = -efuse_gain->offset[RF_PATH_A][0]; 974 975 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; 976 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 977 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 978 979 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; 980 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 981 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 982 983 if (subband == RTW89_CH_2G) { 984 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); 985 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); 986 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, 987 B_RX_RPL_OFST_CCK_MASK, tmp); 988 } 989 } 990 991 static 992 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) 993 { 994 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 995 u8 band = rtw89_subband_to_bb_gain_band(subband); 996 u32 val; 997 998 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) | 999 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) | 1000 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK); 1001 val >>= B_P0_RPL1_SHIFT; 1002 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); 1003 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); 1004 1005 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) | 1006 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) | 1007 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) | 1008 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK); 1009 rtw89_phy_write32(rtwdev, R_P0_RPL2, val); 1010 rtw89_phy_write32(rtwdev, R_P1_RPL2, val); 1011 1012 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) | 1013 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) | 1014 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) | 1015 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK); 1016 rtw89_phy_write32(rtwdev, R_P0_RPL3, val); 1017 rtw89_phy_write32(rtwdev, R_P1_RPL3, val); 1018 } 1019 1020 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev, 1021 const struct rtw89_chan *chan, 1022 enum rtw89_phy_idx phy_idx) 1023 { 1024 u8 subband = chan->subband_type; 1025 u8 central_ch = chan->channel; 1026 bool is_2g = central_ch <= 14; 1027 u8 sco_comp; 1028 1029 if (is_2g) 1030 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1031 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); 1032 else 1033 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1034 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); 1035 /* SCO compensate FC setting */ 1036 sco_comp = rtw8851b_sco_mapping(central_ch); 1037 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); 1038 1039 if (chan->band_type == RTW89_BAND_6G) 1040 return; 1041 1042 /* CCK parameters */ 1043 if (central_ch == 14) { 1044 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); 1045 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); 1046 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); 1047 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); 1048 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); 1049 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 1050 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 1051 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); 1052 } else { 1053 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); 1054 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); 1055 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 1056 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); 1057 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); 1058 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); 1059 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); 1060 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); 1061 } 1062 1063 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A); 1064 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx); 1065 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband); 1066 } 1067 1068 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw) 1069 { 1070 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8); 1071 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2); 1072 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2); 1073 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4); 1074 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf); 1075 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa); 1076 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); 1077 1078 switch (bw) { 1079 case RTW89_CHANNEL_WIDTH_5: 1080 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1); 1081 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0); 1082 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1); 1083 break; 1084 case RTW89_CHANNEL_WIDTH_10: 1085 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1); 1086 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1); 1087 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1088 break; 1089 case RTW89_CHANNEL_WIDTH_20: 1090 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2); 1091 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2); 1092 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1093 break; 1094 case RTW89_CHANNEL_WIDTH_40: 1095 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2); 1096 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2); 1097 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1098 break; 1099 case RTW89_CHANNEL_WIDTH_80: 1100 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0); 1101 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2); 1102 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0); 1103 break; 1104 default: 1105 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1106 } 1107 } 1108 1109 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1110 enum rtw89_phy_idx phy_idx) 1111 { 1112 switch (bw) { 1113 case RTW89_CHANNEL_WIDTH_5: 1114 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1115 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); 1116 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1117 break; 1118 case RTW89_CHANNEL_WIDTH_10: 1119 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1120 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); 1121 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1122 break; 1123 case RTW89_CHANNEL_WIDTH_20: 1124 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1125 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1126 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1127 break; 1128 case RTW89_CHANNEL_WIDTH_40: 1129 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); 1130 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1131 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1132 pri_ch, phy_idx); 1133 /* CCK primary channel */ 1134 if (pri_ch == RTW89_SC_20_UPPER) 1135 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1136 else 1137 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1138 1139 break; 1140 case RTW89_CHANNEL_WIDTH_80: 1141 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); 1142 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1143 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1144 pri_ch, phy_idx); 1145 break; 1146 default: 1147 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1148 pri_ch); 1149 } 1150 1151 rtw8851b_bw_setting(rtwdev, bw); 1152 } 1153 1154 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) 1155 { 1156 if (cck_en) { 1157 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1158 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF, 1159 B_PD_ARBITER_OFF, 0); 1160 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1161 } else { 1162 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1163 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF, 1164 B_PD_ARBITER_OFF, 1); 1165 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1166 } 1167 } 1168 1169 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev, 1170 const struct rtw89_chan *chan) 1171 { 1172 u8 center_chan = chan->channel; 1173 1174 switch (chan->band_type) { 1175 case RTW89_BAND_5G: 1176 if (center_chan == 151 || center_chan == 153 || 1177 center_chan == 155 || center_chan == 163) 1178 return 5760; 1179 else if (center_chan == 54 || center_chan == 58) 1180 return 5280; 1181 break; 1182 default: 1183 break; 1184 } 1185 1186 return 0; 1187 } 1188 1189 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1190 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1191 #define MAX_TONE_NUM 2048 1192 1193 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1194 const struct rtw89_chan *chan, 1195 enum rtw89_phy_idx phy_idx) 1196 { 1197 u32 spur_freq; 1198 s32 freq_diff, csi_idx, csi_tone_idx; 1199 1200 spur_freq = rtw8851b_spur_freq(rtwdev, chan); 1201 if (spur_freq == 0) { 1202 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1203 0, phy_idx); 1204 return; 1205 } 1206 1207 freq_diff = (spur_freq - chan->freq) * 1000000; 1208 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1209 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1210 1211 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX, 1212 csi_tone_idx, phy_idx); 1213 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx); 1214 } 1215 1216 static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = { 1217 .notch1_idx = {0x46E4, 0xFF}, 1218 .notch1_frac_idx = {0x46E4, 0xC00}, 1219 .notch1_en = {0x46E4, 0x1000}, 1220 .notch2_idx = {0x47A4, 0xFF}, 1221 .notch2_frac_idx = {0x47A4, 0xC00}, 1222 .notch2_en = {0x47A4, 0x1000}, 1223 }; 1224 1225 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1226 const struct rtw89_chan *chan) 1227 { 1228 const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def; 1229 s32 nbi_frac_idx, nbi_frac_tone_idx; 1230 s32 nbi_idx, nbi_tone_idx; 1231 bool notch2_chk = false; 1232 u32 spur_freq, fc; 1233 s32 freq_diff; 1234 1235 spur_freq = rtw8851b_spur_freq(rtwdev, chan); 1236 if (spur_freq == 0) { 1237 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1238 nbi->notch1_en.mask, 0); 1239 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1240 nbi->notch2_en.mask, 0); 1241 return; 1242 } 1243 1244 fc = chan->freq; 1245 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1246 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1247 if ((fc > spur_freq && 1248 chan->channel < chan->primary_channel) || 1249 (fc < spur_freq && 1250 chan->channel > chan->primary_channel)) 1251 notch2_chk = true; 1252 } 1253 1254 freq_diff = (spur_freq - fc) * 1000000; 1255 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, 1256 &nbi_frac_idx); 1257 1258 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1259 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1260 } else { 1261 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1262 128 : 256; 1263 1264 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1265 } 1266 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, 1267 CARRIER_SPACING_78_125); 1268 1269 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1270 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1271 nbi->notch2_idx.mask, nbi_tone_idx); 1272 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1273 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1274 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1275 nbi->notch2_en.mask, 0); 1276 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1277 nbi->notch2_en.mask, 1); 1278 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1279 nbi->notch1_en.mask, 0); 1280 } else { 1281 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1282 nbi->notch1_idx.mask, nbi_tone_idx); 1283 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1284 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1285 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1286 nbi->notch1_en.mask, 0); 1287 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, 1288 nbi->notch1_en.mask, 1); 1289 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, 1290 nbi->notch2_en.mask, 0); 1291 } 1292 } 1293 1294 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan) 1295 { 1296 if (chan->band_type == RTW89_BAND_2G && 1297 chan->band_width == RTW89_CHANNEL_WIDTH_20 && 1298 (chan->channel == 1 || chan->channel == 13)) { 1299 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1300 B_PATH0_TX_CFR_LGC0, 0xf8); 1301 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1302 B_PATH0_TX_CFR_LGC1, 0x120); 1303 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1304 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0); 1305 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1306 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3); 1307 } else { 1308 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1309 B_PATH0_TX_CFR_LGC0, 0x120); 1310 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR, 1311 B_PATH0_TX_CFR_LGC1, 0x3ff); 1312 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1313 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3); 1314 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING, 1315 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7); 1316 } 1317 } 1318 1319 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1320 enum rtw89_phy_idx phy_idx) 1321 { 1322 u8 pri_ch = chan->pri_ch_idx; 1323 bool mask_5m_low; 1324 bool mask_5m_en; 1325 1326 switch (chan->band_width) { 1327 case RTW89_CHANNEL_WIDTH_40: 1328 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ 1329 mask_5m_en = true; 1330 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1331 break; 1332 case RTW89_CHANNEL_WIDTH_80: 1333 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ 1334 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1335 pri_ch == RTW89_SC_20_LOWEST; 1336 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1337 break; 1338 default: 1339 mask_5m_en = false; 1340 break; 1341 } 1342 1343 if (!mask_5m_en) { 1344 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); 1345 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1346 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); 1347 return; 1348 } 1349 1350 if (mask_5m_low) { 1351 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5); 1352 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1353 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); 1354 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); 1355 } else { 1356 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5); 1357 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1358 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); 1359 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); 1360 } 1361 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1362 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); 1363 } 1364 1365 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1366 { 1367 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1368 fsleep(1); 1369 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1370 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1371 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1372 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1373 } 1374 1375 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1376 enum rtw89_phy_idx phy_idx, bool en) 1377 { 1378 if (en) { 1379 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1380 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1381 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1382 if (band == RTW89_BAND_2G) 1383 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 1384 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1385 } else { 1386 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 1387 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1388 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1389 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1390 fsleep(1); 1391 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1392 } 1393 } 1394 1395 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev, 1396 enum rtw89_phy_idx phy_idx) 1397 { 1398 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1399 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1); 1400 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1401 rtw8851b_bb_reset_all(rtwdev, phy_idx); 1402 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 1403 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3); 1404 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1405 } 1406 1407 static 1408 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1409 u8 tx_path_en, u8 trsw_tx, 1410 u8 trsw_rx, u8 trsw_a, u8 trsw_b) 1411 { 1412 u32 mask_ofst = 16; 1413 u32 val; 1414 1415 if (path != RF_PATH_A) 1416 return; 1417 1418 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1419 val = u32_encode_bits(trsw_a, B_P0_TRSW_A) | 1420 u32_encode_bits(trsw_b, B_P0_TRSW_B); 1421 1422 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW, 1423 (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1424 } 1425 1426 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev) 1427 { 1428 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A); 1429 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X); 1430 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2); 1431 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777); 1432 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777); 1433 1434 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1435 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1436 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1437 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1438 1439 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1440 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1441 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1442 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1443 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1444 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1445 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1446 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1447 } 1448 1449 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1450 enum rtw89_phy_idx phy_idx) 1451 { 1452 u32 addr; 1453 1454 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1455 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1456 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1457 } 1458 1459 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev) 1460 { 1461 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1462 1463 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1464 1465 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1466 rtw8851b_bb_gpio_init(rtwdev); 1467 1468 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE); 1469 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN); 1470 1471 /* read these registers after loading BB parameters */ 1472 gain->offset_base[RTW89_PHY_0] = 1473 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); 1474 gain->rssi_base[RTW89_PHY_0] = 1475 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); 1476 } 1477 1478 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1479 enum rtw89_phy_idx phy_idx) 1480 { 1481 u8 band = chan->band_type, chan_idx; 1482 bool cck_en = chan->channel <= 14; 1483 u8 pri_ch_idx = chan->pri_ch_idx; 1484 1485 if (cck_en) 1486 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel); 1487 1488 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx); 1489 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1490 rtw8851b_ctrl_cck_en(rtwdev, cck_en); 1491 rtw8851b_set_nbi_tone_idx(rtwdev, chan); 1492 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx); 1493 1494 if (chan->band_type == RTW89_BAND_5G) { 1495 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1496 B_PATH0_BT_SHARE_V1, 0x0); 1497 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1498 B_PATH0_BTG_PATH_V1, 0x0); 1499 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1500 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1501 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1502 B_BT_DYN_DC_EST_EN_MSK, 0x0); 1503 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1504 } 1505 1506 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1507 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); 1508 rtw8851b_5m_mask(rtwdev, chan, phy_idx); 1509 rtw8851b_set_cfr(rtwdev, chan); 1510 rtw8851b_bb_reset_all(rtwdev, phy_idx); 1511 } 1512 1513 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev, 1514 const struct rtw89_chan *chan, 1515 enum rtw89_mac_idx mac_idx, 1516 enum rtw89_phy_idx phy_idx) 1517 { 1518 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx); 1519 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx); 1520 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx); 1521 } 1522 1523 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1524 enum rtw89_rf_path path) 1525 { 1526 if (en) { 1527 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0); 1528 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0); 1529 } else { 1530 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1); 1531 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1); 1532 } 1533 } 1534 1535 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1536 u8 phy_idx) 1537 { 1538 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A); 1539 } 1540 1541 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en) 1542 { 1543 if (en) 1544 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 1545 else 1546 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 1547 } 1548 1549 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1550 struct rtw89_channel_help_params *p, 1551 const struct rtw89_chan *chan, 1552 enum rtw89_mac_idx mac_idx, 1553 enum rtw89_phy_idx phy_idx) 1554 { 1555 if (enter) { 1556 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1557 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1558 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1559 rtw8851b_adc_en(rtwdev, false); 1560 fsleep(40); 1561 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1562 } else { 1563 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1564 rtw8851b_adc_en(rtwdev, true); 1565 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1566 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1567 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1568 } 1569 } 1570 1571 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev) 1572 { 1573 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1574 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1575 rtw8851b_lck_init(rtwdev); 1576 1577 rtw8851b_dpk_init(rtwdev); 1578 rtw8851b_aack(rtwdev); 1579 rtw8851b_rck(rtwdev); 1580 rtw8851b_dack(rtwdev); 1581 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0); 1582 } 1583 1584 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev) 1585 { 1586 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1587 1588 rtw8851b_rx_dck(rtwdev, phy_idx); 1589 rtw8851b_iqk(rtwdev, phy_idx); 1590 rtw8851b_tssi(rtwdev, phy_idx, true); 1591 rtw8851b_dpk(rtwdev, phy_idx); 1592 } 1593 1594 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev, 1595 enum rtw89_phy_idx phy_idx) 1596 { 1597 rtw8851b_tssi_scan(rtwdev, phy_idx); 1598 } 1599 1600 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1601 { 1602 rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1603 } 1604 1605 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev) 1606 { 1607 rtw8851b_dpk_track(rtwdev); 1608 rtw8851b_lck_track(rtwdev); 1609 } 1610 1611 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1612 enum rtw89_phy_idx phy_idx, s16 ref) 1613 { 1614 const u16 tssi_16dbm_cw = 0x12c; 1615 const u8 base_cw_0db = 0x27; 1616 const s8 ofst_int = 0; 1617 s16 pwr_s10_3; 1618 s16 rf_pwr_cw; 1619 u16 bb_pwr_cw; 1620 u32 pwr_cw; 1621 u32 tssi_ofst_cw; 1622 1623 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1624 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0)); 1625 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3)); 1626 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1627 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1628 1629 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1630 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1631 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1632 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1633 1634 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) | 1635 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) | 1636 u32_encode_bits(ref, B_DPD_REF); 1637 } 1638 1639 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev, 1640 enum rtw89_phy_idx phy_idx) 1641 { 1642 static const u32 addr[RF_PATH_NUM_8851B] = {0x5800}; 1643 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; 1644 const u8 ofst_ofdm = 0x4; 1645 const u8 ofst_cck = 0x8; 1646 const s16 ref_ofdm = 0; 1647 const s16 ref_cck = 0; 1648 u32 val; 1649 u8 i; 1650 1651 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1652 1653 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1654 B_AX_PWR_REF, 0x0); 1655 1656 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1657 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1658 1659 for (i = 0; i < RF_PATH_NUM_8851B; i++) 1660 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1661 phy_idx); 1662 1663 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1664 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1665 1666 for (i = 0; i < RF_PATH_NUM_8851B; i++) 1667 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1668 phy_idx); 1669 } 1670 1671 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1672 const struct rtw89_chan *chan, 1673 u8 tx_shape_idx, 1674 enum rtw89_phy_idx phy_idx) 1675 { 1676 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) 1677 #define __DFIR_CFG_MASK 0xffffffff 1678 #define __DFIR_CFG_NR 8 1679 #define __DECL_DFIR_PARAM(_name, _val...) \ 1680 static const u32 param_ ## _name[] = {_val}; \ 1681 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) 1682 1683 __DECL_DFIR_PARAM(flat, 1684 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1685 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1686 __DECL_DFIR_PARAM(sharp, 1687 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1688 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); 1689 __DECL_DFIR_PARAM(sharp_14, 1690 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1691 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); 1692 u8 ch = chan->channel; 1693 const u32 *param; 1694 u32 addr; 1695 int i; 1696 1697 if (ch > 14) { 1698 rtw89_warn(rtwdev, 1699 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1700 return; 1701 } 1702 1703 if (ch == 14) 1704 param = param_sharp_14; 1705 else 1706 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1707 1708 for (i = 0; i < __DFIR_CFG_NR; i++) { 1709 addr = __DFIR_CFG_ADDR(i); 1710 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1711 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); 1712 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], 1713 phy_idx); 1714 } 1715 1716 #undef __DECL_DFIR_PARAM 1717 #undef __DFIR_CFG_NR 1718 #undef __DFIR_CFG_MASK 1719 #undef __DECL_CFG_ADDR 1720 } 1721 1722 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev, 1723 const struct rtw89_chan *chan, 1724 enum rtw89_phy_idx phy_idx) 1725 { 1726 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1727 u8 band = chan->band_type; 1728 u8 regd = rtw89_regd_get(rtwdev, band); 1729 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 1730 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 1731 1732 if (band == RTW89_BAND_2G) 1733 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1734 1735 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, 1736 tx_shape_ofdm); 1737 } 1738 1739 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev, 1740 const struct rtw89_chan *chan, 1741 enum rtw89_phy_idx phy_idx) 1742 { 1743 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1744 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1745 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx); 1746 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1747 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1748 } 1749 1750 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1751 enum rtw89_phy_idx phy_idx) 1752 { 1753 rtw8851b_set_txpwr_ref(rtwdev, phy_idx); 1754 } 1755 1756 static 1757 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1758 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1759 { 1760 u32 reg; 1761 1762 if (pw_ofst < -16 || pw_ofst > 15) { 1763 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1764 return; 1765 } 1766 1767 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1768 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1769 1770 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1771 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); 1772 1773 pw_ofst = max_t(s8, pw_ofst - 3, -16); 1774 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1775 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); 1776 } 1777 1778 static int 1779 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1780 { 1781 int ret; 1782 1783 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1784 if (ret) 1785 return ret; 1786 1787 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 1788 if (ret) 1789 return ret; 1790 1791 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1792 if (ret) 1793 return ret; 1794 1795 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 1796 RTW89_MAC_1 : RTW89_MAC_0); 1797 1798 return 0; 1799 } 1800 1801 static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1802 enum rtw89_phy_idx phy_idx) 1803 { 1804 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1805 1806 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl : 1807 &rtw8851b_btc_preagc_dis_defs_tbl); 1808 1809 if (!en) { 1810 if (chan->band_type == RTW89_BAND_2G) { 1811 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1812 B_PATH0_G_LNA6_OP1DB_V1, 0x20); 1813 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1814 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30); 1815 } else { 1816 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1817 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 1818 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1819 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1820 } 1821 } 1822 } 1823 1824 static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1825 enum rtw89_phy_idx phy_idx) 1826 { 1827 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1828 1829 if (en) { 1830 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1831 B_PATH0_BT_SHARE_V1, 0x1); 1832 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1833 B_PATH0_BTG_PATH_V1, 0x1); 1834 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1835 B_PATH0_G_LNA6_OP1DB_V1, 0x20); 1836 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1837 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30); 1838 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1839 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); 1840 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1); 1841 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1842 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1843 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); 1844 } else { 1845 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1846 B_PATH0_BT_SHARE_V1, 0x0); 1847 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1848 B_PATH0_BTG_PATH_V1, 0x0); 1849 if (chan->band_type == RTW89_BAND_2G) { 1850 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1851 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 1852 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1853 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 1854 } else { 1855 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 1856 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 1857 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 1858 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1859 } 1860 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); 1861 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1862 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1863 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1864 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1865 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1866 } 1867 } 1868 1869 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 1870 enum rtw89_rf_path_bit rx_path) 1871 { 1872 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1873 u32 rst_mask0; 1874 1875 if (rx_path == RF_A) { 1876 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); 1877 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); 1878 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); 1879 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1880 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1881 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1882 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1883 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1884 } 1885 1886 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); 1887 1888 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1889 if (rx_path == RF_A) { 1890 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1891 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1892 } 1893 } 1894 1895 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 1896 { 1897 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A); 1898 1899 if (rtwdev->hal.rx_nss == 1) { 1900 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1901 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1902 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1903 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1904 } 1905 1906 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1907 } 1908 1909 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1910 { 1911 if (rtwdev->is_tssi_mode[rf_path]) { 1912 u32 addr = R_TSSI_THER + (rf_path << 13); 1913 1914 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER); 1915 } 1916 1917 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1918 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1919 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1920 1921 fsleep(200); 1922 1923 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1924 } 1925 1926 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev) 1927 { 1928 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 1929 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 1930 1931 if (ver->fcxinit == 7) { 1932 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 1933 md->md_v7.kt_ver = rtwdev->hal.cv; 1934 md->md_v7.bt_solo = 0; 1935 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 1936 md->md_v7.ant.isolation = 10; 1937 md->md_v7.kt_ver_adie = rtwdev->hal.acv; 1938 1939 if (md->md_v7.rfe_type == 0) 1940 return; 1941 1942 /* rfe_type 3*n+1: 1-Ant(shared), 1943 * 3*n+2: 2-Ant+Div(non-shared), 1944 * 3*n+3: 2-Ant+no-Div(non-shared) 1945 */ 1946 md->md_v7.ant.num = (md->md_v7.rfe_type % 3 == 1) ? 1 : 2; 1947 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ 1948 md->md_v7.ant.single_pos = RF_PATH_A; 1949 md->md_v7.ant.btg_pos = RF_PATH_A; 1950 md->md_v7.ant.stream_cnt = 1; 1951 1952 if (md->md_v7.ant.num == 1) { 1953 md->md_v7.ant.type = BTC_ANT_SHARED; 1954 md->md_v7.bt_pos = BTC_BT_BTG; 1955 md->md_v7.wa_type = 1; 1956 md->md_v7.ant.diversity = 0; 1957 } else { /* ant.num == 2 */ 1958 md->md_v7.ant.type = BTC_ANT_DEDICATED; 1959 md->md_v7.bt_pos = BTC_BT_ALONE; 1960 md->md_v7.switch_type = BTC_SWITCH_EXTERNAL; 1961 md->md_v7.wa_type = 0; 1962 if (md->md_v7.rfe_type % 3 == 2) 1963 md->md_v7.ant.diversity = 1; 1964 } 1965 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 1966 rtwdev->btc.ant_type = md->md_v7.ant.type; 1967 } else { 1968 md->md.rfe_type = rtwdev->efuse.rfe_type; 1969 md->md.cv = rtwdev->hal.cv; 1970 md->md.bt_solo = 0; 1971 md->md.switch_type = BTC_SWITCH_INTERNAL; 1972 md->md.ant.isolation = 10; 1973 md->md.kt_ver_adie = rtwdev->hal.acv; 1974 1975 if (md->md.rfe_type == 0) 1976 return; 1977 1978 /* rfe_type 3*n+1: 1-Ant(shared), 1979 * 3*n+2: 2-Ant+Div(non-shared), 1980 * 3*n+3: 2-Ant+no-Div(non-shared) 1981 */ 1982 md->md.ant.num = (md->md.rfe_type % 3 == 1) ? 1 : 2; 1983 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ 1984 md->md.ant.single_pos = RF_PATH_A; 1985 md->md.ant.btg_pos = RF_PATH_A; 1986 md->md.ant.stream_cnt = 1; 1987 1988 if (md->md.ant.num == 1) { 1989 md->md.ant.type = BTC_ANT_SHARED; 1990 md->md.bt_pos = BTC_BT_BTG; 1991 md->md.wa_type = 1; 1992 md->md.ant.diversity = 0; 1993 } else { /* ant.num == 2 */ 1994 md->md.ant.type = BTC_ANT_DEDICATED; 1995 md->md.bt_pos = BTC_BT_ALONE; 1996 md->md.switch_type = BTC_SWITCH_EXTERNAL; 1997 md->md.wa_type = 0; 1998 if (md->md.rfe_type % 3 == 2) 1999 md->md.ant.diversity = 1; 2000 } 2001 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2002 rtwdev->btc.ant_type = md->md.ant.type; 2003 } 2004 } 2005 2006 static 2007 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2008 { 2009 if (group > BTC_BT_SS_GROUP) 2010 group--; /* Tx-group=1, Rx-group=2 */ 2011 2012 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */ 2013 group += 3; 2014 2015 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2016 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2017 } 2018 2019 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev) 2020 { 2021 static const struct rtw89_mac_ax_coex coex_params = { 2022 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2023 .direction = RTW89_MAC_AX_COEX_INNER, 2024 }; 2025 const struct rtw89_chip_info *chip = rtwdev->chip; 2026 struct rtw89_btc *btc = &rtwdev->btc; 2027 union rtw89_btc_module_info *md = &btc->mdinfo; 2028 const struct rtw89_btc_ver *ver = btc->ver; 2029 u8 path, path_min, path_max, str_cnt, ant_sing_pos; 2030 2031 /* PTA init */ 2032 rtw89_mac_coex_init(rtwdev, &coex_params); 2033 2034 /* set WL Tx response = Hi-Pri */ 2035 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2036 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2037 2038 if (ver->fcxinit == 7) { 2039 str_cnt = md->md_v7.ant.stream_cnt; 2040 ant_sing_pos = md->md_v7.ant.single_pos; 2041 } else { 2042 str_cnt = md->md.ant.stream_cnt; 2043 ant_sing_pos = md->md.ant.single_pos; 2044 } 2045 2046 /* for 1-Ant && 1-ss case: only 1-path */ 2047 if (str_cnt == 1) { 2048 path_min = ant_sing_pos; 2049 path_max = path_min; 2050 } else { 2051 path_min = RF_PATH_A; 2052 path_max = RF_PATH_B; 2053 } 2054 2055 for (path = path_min; path <= path_max; path++) { 2056 /* set rf gnt-debug off */ 2057 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0); 2058 2059 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */ 2060 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17)); 2061 2062 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ 2063 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); 2064 2065 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ 2066 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); 2067 2068 /* if GNT_WL = 0 && BT = Tx_group --> 2069 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) 2070 */ 2071 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path) 2072 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); 2073 else 2074 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); 2075 2076 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */ 2077 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); 2078 } 2079 2080 /* set PTA break table */ 2081 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 2082 2083 /* enable BT counter 0xda40[16,2] = 2b'11 */ 2084 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 2085 2086 btc->cx.wl.status.map.init_ok = true; 2087 } 2088 2089 static 2090 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2091 { 2092 u32 bitmap; 2093 u32 reg; 2094 2095 switch (map) { 2096 case BTC_PRI_MASK_TX_RESP: 2097 reg = R_BTC_BT_COEX_MSK_TABLE; 2098 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 2099 break; 2100 case BTC_PRI_MASK_BEACON: 2101 reg = R_AX_WL_PRI_MSK; 2102 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 2103 break; 2104 case BTC_PRI_MASK_RX_CCK: 2105 reg = R_BTC_BT_COEX_MSK_TABLE; 2106 bitmap = B_BTC_PRI_MASK_RXCCK_V1; 2107 break; 2108 default: 2109 return; 2110 } 2111 2112 if (state) 2113 rtw89_write32_set(rtwdev, reg, bitmap); 2114 else 2115 rtw89_write32_clr(rtwdev, reg, bitmap); 2116 } 2117 2118 union rtw8851b_btc_wl_txpwr_ctrl { 2119 u32 txpwr_val; 2120 struct { 2121 union { 2122 u16 ctrl_all_time; 2123 struct { 2124 s16 data:9; 2125 u16 rsvd:6; 2126 u16 flag:1; 2127 } all_time; 2128 }; 2129 union { 2130 u16 ctrl_gnt_bt; 2131 struct { 2132 s16 data:9; 2133 u16 rsvd:7; 2134 } gnt_bt; 2135 }; 2136 }; 2137 } __packed; 2138 2139 static void 2140 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2141 { 2142 union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2143 s32 val; 2144 2145 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2146 do { \ 2147 u32 _wrt = FIELD_PREP(_msk, _val); \ 2148 BUILD_BUG_ON(!!(_msk & _en)); \ 2149 if (_cond) \ 2150 _wrt |= _en; \ 2151 else \ 2152 _wrt &= ~_en; \ 2153 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2154 _msk | _en, _wrt); \ 2155 } while (0) 2156 2157 switch (arg.ctrl_all_time) { 2158 case 0xffff: 2159 val = 0; 2160 break; 2161 default: 2162 val = arg.all_time.data; 2163 break; 2164 } 2165 2166 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2167 val, B_AX_FORCE_PWR_BY_RATE_EN, 2168 arg.ctrl_all_time != 0xffff); 2169 2170 switch (arg.ctrl_gnt_bt) { 2171 case 0xffff: 2172 val = 0; 2173 break; 2174 default: 2175 val = arg.gnt_bt.data; 2176 break; 2177 } 2178 2179 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2180 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2181 2182 #undef __write_ctrl 2183 } 2184 2185 static 2186 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2187 { 2188 val = clamp_t(s8, val, -100, 0) + 100; 2189 val = min(val + 6, 100); /* compensate offset */ 2190 2191 return val; 2192 } 2193 2194 static 2195 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2196 { 2197 /* Feature move to firmware */ 2198 } 2199 2200 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2201 { 2202 struct rtw89_btc *btc = &rtwdev->btc; 2203 2204 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000); 2205 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1); 2206 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110); 2207 2208 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2209 if (state) 2210 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c); 2211 else 2212 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208); 2213 2214 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0); 2215 } 2216 2217 #define LNA2_51B_MA 0x700 2218 2219 static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}}; 2220 static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}}; 2221 2222 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2223 { 2224 /* To improve BT ACI in co-rx 2225 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2226 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2227 */ 2228 struct rtw89_btc *btc = &rtwdev->btc; 2229 const struct rtw89_reg2_def *rf; 2230 u32 n, i, val; 2231 2232 switch (level) { 2233 case 0: /* original */ 2234 default: 2235 btc->dm.wl_lna2 = 0; 2236 break; 2237 case 1: /* for FDD free-run */ 2238 btc->dm.wl_lna2 = 0; 2239 break; 2240 case 2: /* for BTG Co-Rx*/ 2241 btc->dm.wl_lna2 = 1; 2242 break; 2243 } 2244 2245 if (btc->dm.wl_lna2 == 0) { 2246 rf = btc_8851b_rf_0; 2247 n = ARRAY_SIZE(btc_8851b_rf_0); 2248 } else { 2249 rf = btc_8851b_rf_1; 2250 n = ARRAY_SIZE(btc_8851b_rf_1); 2251 } 2252 2253 for (i = 0; i < n; i++, rf++) { 2254 val = rf->data; 2255 /* bit[10] = 1 if non-shared-ant for 8851b */ 2256 if (btc->ant_type == BTC_ANT_DEDICATED) 2257 val |= 0x4; 2258 2259 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val); 2260 } 2261 } 2262 2263 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2264 struct rtw89_rx_phy_ppdu *phy_ppdu, 2265 struct ieee80211_rx_status *status) 2266 { 2267 u16 chan = phy_ppdu->chan_idx; 2268 enum nl80211_band band; 2269 u8 ch; 2270 2271 if (chan == 0) 2272 return; 2273 2274 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); 2275 status->freq = ieee80211_channel_to_frequency(ch, band); 2276 status->band = band; 2277 } 2278 2279 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev, 2280 struct rtw89_rx_phy_ppdu *phy_ppdu, 2281 struct ieee80211_rx_status *status) 2282 { 2283 u8 path; 2284 u8 *rx_power = phy_ppdu->rssi; 2285 2286 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]); 2287 2288 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2289 status->chains |= BIT(path); 2290 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2291 } 2292 if (phy_ppdu->valid) 2293 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2294 } 2295 2296 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2297 { 2298 int ret; 2299 2300 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2301 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2302 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2303 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2304 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2305 2306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, 2307 FULL_BIT_MASK); 2308 if (ret) 2309 return ret; 2310 2311 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, 2312 FULL_BIT_MASK); 2313 if (ret) 2314 return ret; 2315 2316 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); 2317 2318 return 0; 2319 } 2320 2321 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2322 { 2323 u8 wl_rfc_s0; 2324 u8 wl_rfc_s1; 2325 int ret; 2326 2327 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2328 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2329 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2330 2331 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); 2332 if (ret) 2333 return ret; 2334 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; 2335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, 2336 FULL_BIT_MASK); 2337 if (ret) 2338 return ret; 2339 2340 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); 2341 if (ret) 2342 return ret; 2343 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; 2344 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, 2345 FULL_BIT_MASK); 2346 return ret; 2347 } 2348 2349 static const struct rtw89_chip_ops rtw8851b_chip_ops = { 2350 .enable_bb_rf = rtw8851b_mac_enable_bb_rf, 2351 .disable_bb_rf = rtw8851b_mac_disable_bb_rf, 2352 .bb_preinit = NULL, 2353 .bb_postinit = NULL, 2354 .bb_reset = rtw8851b_bb_reset, 2355 .bb_sethw = rtw8851b_bb_sethw, 2356 .read_rf = rtw89_phy_read_rf_v1, 2357 .write_rf = rtw89_phy_write_rf_v1, 2358 .set_channel = rtw8851b_set_channel, 2359 .set_channel_help = rtw8851b_set_channel_help, 2360 .read_efuse = rtw8851b_read_efuse, 2361 .read_phycap = rtw8851b_read_phycap, 2362 .fem_setup = NULL, 2363 .rfe_gpio = rtw8851b_rfe_gpio, 2364 .rfk_hw_init = NULL, 2365 .rfk_init = rtw8851b_rfk_init, 2366 .rfk_init_late = NULL, 2367 .rfk_channel = rtw8851b_rfk_channel, 2368 .rfk_band_changed = rtw8851b_rfk_band_changed, 2369 .rfk_scan = rtw8851b_rfk_scan, 2370 .rfk_track = rtw8851b_rfk_track, 2371 .power_trim = rtw8851b_power_trim, 2372 .set_txpwr = rtw8851b_set_txpwr, 2373 .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl, 2374 .init_txpwr_unit = rtw8851b_init_txpwr_unit, 2375 .get_thermal = rtw8851b_get_thermal, 2376 .ctrl_btg_bt_rx = rtw8851b_ctrl_btg_bt_rx, 2377 .query_ppdu = rtw8851b_query_ppdu, 2378 .ctrl_nbtg_bt_tx = rtw8851b_ctrl_nbtg_bt_tx, 2379 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path, 2380 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset, 2381 .pwr_on_func = rtw8851b_pwr_on_func, 2382 .pwr_off_func = rtw8851b_pwr_off_func, 2383 .query_rxdesc = rtw89_core_query_rxdesc, 2384 .fill_txdesc = rtw89_core_fill_txdesc, 2385 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2386 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2387 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2388 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2389 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2390 .h2c_dctl_sec_cam = NULL, 2391 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2392 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2393 .h2c_ampdu_cmac_tbl = NULL, 2394 .h2c_default_dmac_tbl = NULL, 2395 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2396 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2397 2398 .btc_set_rfe = rtw8851b_btc_set_rfe, 2399 .btc_init_cfg = rtw8851b_btc_init_cfg, 2400 .btc_set_wl_pri = rtw8851b_btc_set_wl_pri, 2401 .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl, 2402 .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi, 2403 .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt, 2404 .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby, 2405 .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain, 2406 .btc_set_policy = rtw89_btc_set_policy_v1, 2407 }; 2408 2409 #ifdef CONFIG_PM 2410 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = { 2411 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2412 .n_patterns = RTW89_MAX_PATTERN_NUM, 2413 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2414 .pattern_min_len = 1, 2415 }; 2416 #endif 2417 2418 const struct rtw89_chip_info rtw8851b_chip_info = { 2419 .chip_id = RTL8851B, 2420 .chip_gen = RTW89_CHIP_AX, 2421 .ops = &rtw8851b_chip_ops, 2422 .mac_def = &rtw89_mac_gen_ax, 2423 .phy_def = &rtw89_phy_gen_ax, 2424 .fw_basename = RTW8851B_FW_BASENAME, 2425 .fw_format_max = RTW8851B_FW_FORMAT_MAX, 2426 .try_ce_fw = true, 2427 .bbmcu_nr = 0, 2428 .needed_fw_elms = 0, 2429 .fifo_size = 196608, 2430 .small_fifo_size = true, 2431 .dle_scc_rsvd_size = 98304, 2432 .max_amsdu_limit = 3500, 2433 .dis_2g_40m_ul_ofdma = true, 2434 .rsvd_ple_ofst = 0x2f800, 2435 .hfc_param_ini = rtw8851b_hfc_param_ini_pcie, 2436 .dle_mem = rtw8851b_dle_mem_pcie, 2437 .wde_qempty_acq_grpnum = 4, 2438 .wde_qempty_mgq_grpsel = 4, 2439 .rf_base_addr = {0xe000}, 2440 .pwr_on_seq = NULL, 2441 .pwr_off_seq = NULL, 2442 .bb_table = &rtw89_8851b_phy_bb_table, 2443 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table, 2444 .rf_table = {&rtw89_8851b_phy_radioa_table,}, 2445 .nctl_table = &rtw89_8851b_phy_nctl_table, 2446 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl, 2447 .dflt_parms = &rtw89_8851b_dflt_parms, 2448 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf, 2449 .txpwr_factor_rf = 2, 2450 .txpwr_factor_mac = 1, 2451 .dig_table = NULL, 2452 .dig_regs = &rtw8851b_dig_regs, 2453 .tssi_dbw_table = NULL, 2454 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2455 .support_chanctx_num = 0, 2456 .support_rnr = false, 2457 .support_bands = BIT(NL80211_BAND_2GHZ) | 2458 BIT(NL80211_BAND_5GHZ), 2459 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2460 BIT(NL80211_CHAN_WIDTH_40) | 2461 BIT(NL80211_CHAN_WIDTH_80), 2462 .support_unii4 = true, 2463 .ul_tb_waveform_ctrl = true, 2464 .ul_tb_pwr_diff = false, 2465 .hw_sec_hdr = false, 2466 .rf_path_num = 1, 2467 .tx_nss = 1, 2468 .rx_nss = 1, 2469 .acam_num = 32, 2470 .bcam_num = 20, 2471 .scam_num = 128, 2472 .bacam_num = 2, 2473 .bacam_dynamic_num = 4, 2474 .bacam_ver = RTW89_BACAM_V0, 2475 .ppdu_max_usr = 4, 2476 .sec_ctrl_efuse_size = 4, 2477 .physical_efuse_size = 1216, 2478 .logical_efuse_size = 2048, 2479 .limit_efuse_size = 1280, 2480 .dav_phy_efuse_size = 0, 2481 .dav_log_efuse_size = 0, 2482 .efuse_blocks = NULL, 2483 .phycap_addr = 0x580, 2484 .phycap_size = 128, 2485 .para_ver = 0, 2486 .wlcx_desired = 0x06000000, 2487 .btcx_desired = 0x7, 2488 .scbd = 0x1, 2489 .mailbox = 0x1, 2490 2491 .afh_guard_ch = 6, 2492 .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres, 2493 .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres, 2494 .rssi_tol = 2, 2495 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg), 2496 .mon_reg = rtw89_btc_8851b_mon_reg, 2497 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul), 2498 .rf_para_ulink = rtw89_btc_8851b_rf_ul, 2499 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl), 2500 .rf_para_dlink = rtw89_btc_8851b_rf_dl, 2501 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2502 BIT(RTW89_PS_MODE_CLK_GATED), 2503 .low_power_hci_modes = 0, 2504 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2505 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2506 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2507 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2508 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2509 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2510 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2511 .h2c_regs = rtw8851b_h2c_regs, 2512 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2513 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2514 .c2h_regs = rtw8851b_c2h_regs, 2515 .page_regs = &rtw8851b_page_regs, 2516 .wow_reason_reg = rtw8851b_wow_wakeup_regs, 2517 .cfo_src_fd = true, 2518 .cfo_hw_comp = true, 2519 .dcfo_comp = &rtw8851b_dcfo_comp, 2520 .dcfo_comp_sft = 12, 2521 .imr_info = &rtw8851b_imr_info, 2522 .imr_dmac_table = NULL, 2523 .imr_cmac_table = NULL, 2524 .rrsr_cfgs = &rtw8851b_rrsr_cfgs, 2525 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0}, 2526 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 2527 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 2528 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 2529 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 2530 .edcca_regs = &rtw8851b_edcca_regs, 2531 #ifdef CONFIG_PM 2532 .wowlan_stub = &rtw_wowlan_stub_8851b, 2533 #endif 2534 .xtal_info = &rtw8851b_xtal_info, 2535 }; 2536 EXPORT_SYMBOL(rtw8851b_chip_info); 2537 2538 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE); 2539 MODULE_AUTHOR("Realtek Corporation"); 2540 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver"); 2541 MODULE_LICENSE("Dual BSD/GPL"); 2542