1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 11 12 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 13 #define PHY_HEADLINE_VALID 0xf 14 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 15 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 16 FIELD_PREP(GENMASK(7, 0), cv)) 17 18 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 19 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 20 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 21 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 22 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 23 #define PHY_COND_BRANCH_IF 0x8 24 #define PHY_COND_BRANCH_ELIF 0x9 25 #define PHY_COND_BRANCH_ELSE 0xa 26 #define PHY_COND_BRANCH_END 0xb 27 #define PHY_COND_CHECK 0x4 28 #define PHY_COND_DONT_CARE 0xff 29 30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 32 #define RA_MASK_SUBCCK_RATES 0x5ULL 33 #define RA_MASK_SUBOFDM_RATES 0x10ULL 34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 39 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 40 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 41 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 42 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 46 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 47 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 48 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 49 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12) 50 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28) 51 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44) 52 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60) 53 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12) 54 55 #define CFO_TRK_ENABLE_TH (2 << 2) 56 #define CFO_TRK_STOP_TH_4 (30 << 2) 57 #define CFO_TRK_STOP_TH_3 (20 << 2) 58 #define CFO_TRK_STOP_TH_2 (10 << 2) 59 #define CFO_TRK_STOP_TH_1 (00 << 2) 60 #define CFO_TRK_STOP_TH (2 << 2) 61 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 62 #define CFO_PERIOD_CNT 15 63 #define CFO_BOUND 64 64 #define CFO_TP_UPPER 100 65 #define CFO_TP_LOWER 50 66 #define CFO_COMP_PERIOD 250 67 #define CFO_COMP_WEIGHT 8 68 #define MAX_CFO_TOLERANCE 30 69 #define CFO_TF_CNT_TH 300 70 71 #define UL_TB_TF_CNT_L2H_TH 100 72 #define UL_TB_TF_CNT_H2L_TH 70 73 74 #define ANTDIV_TRAINNING_CNT 2 75 #define ANTDIV_TRAINNING_INTVL 30 76 #define ANTDIV_DELAY 110 77 #define ANTDIV_TP_DIFF_TH_HIGH 100 78 #define ANTDIV_TP_DIFF_TH_LOW 5 79 #define ANTDIV_EVM_DIFF_TH 8 80 #define ANTDIV_RSSI_DIFF_TH 3 81 82 #define CCX_MAX_PERIOD 2097 83 #define CCX_MAX_PERIOD_UNIT 32 84 #define MS_TO_4US_RATIO 250 85 #define ENV_MNTR_FAIL_DWORD 0xffffffff 86 #define ENV_MNTR_IFSCLM_HIS_MAX 127 87 #define PERMIL 1000 88 #define PERCENT 100 89 #define IFS_CLM_TH0_UPPER 64 90 #define IFS_CLM_TH_MUL 4 91 #define IFS_CLM_TH_START_IDX 0 92 93 #define TIA0_GAIN_A 12 94 #define TIA0_GAIN_G 16 95 #define LNA0_GAIN (-24) 96 #define U4_MAX_BIT 3 97 #define U8_MAX_BIT 7 98 #define DIG_GAIN_SHIFT 2 99 #define DIG_GAIN 8 100 101 #define LNA_IDX_MAX 6 102 #define LNA_IDX_MIN 0 103 #define TIA_IDX_MAX 1 104 #define TIA_IDX_MIN 0 105 #define RXB_IDX_MAX 31 106 #define RXB_IDX_MIN 0 107 108 #define IGI_RSSI_MAX 110 109 #define PD_TH_MAX_RSSI 70 110 #define PD_TH_MIN_RSSI 8 111 #define CCKPD_TH_MIN_RSSI (-18) 112 #define PD_TH_BW160_CMP_VAL 9 113 #define PD_TH_BW80_CMP_VAL 6 114 #define PD_TH_BW40_CMP_VAL 3 115 #define PD_TH_BW20_CMP_VAL 0 116 #define PD_TH_CMP_VAL 3 117 #define PD_TH_SB_FLTR_CMP_VAL 7 118 119 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 120 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 121 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 122 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 123 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 124 125 #define EDCCA_MAX 249 126 #define EDCCA_TH_L2H_LB 66 127 #define EDCCA_TH_REF 3 128 #define EDCCA_HL_DIFF_NORMAL 8 129 #define RSSI_UNIT_CONVER 110 130 #define EDCCA_UNIT_CONVER 128 131 132 enum rtw89_phy_c2h_ra_func { 133 RTW89_PHY_C2H_FUNC_STS_RPT, 134 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 135 RTW89_PHY_C2H_FUNC_TXSTS, 136 RTW89_PHY_C2H_FUNC_RA_MAX, 137 }; 138 139 enum rtw89_phy_c2h_rfk_log_func { 140 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0, 141 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1, 142 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2, 143 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3, 144 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, 145 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, 146 147 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, 148 }; 149 150 enum rtw89_phy_c2h_rfk_report_func { 151 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0, 152 }; 153 154 enum rtw89_phy_c2h_dm_func { 155 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 156 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 157 RTW89_PHY_C2H_DM_FUNC_SIGB, 158 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 159 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 160 RTW89_PHY_C2H_DM_FUNC_NUM, 161 }; 162 163 enum rtw89_phy_c2h_class { 164 RTW89_PHY_C2H_CLASS_RUA, 165 RTW89_PHY_C2H_CLASS_RA, 166 RTW89_PHY_C2H_CLASS_DM, 167 RTW89_PHY_C2H_RFK_LOG = 0x8, 168 RTW89_PHY_C2H_RFK_REPORT = 0x9, 169 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 170 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 171 RTW89_PHY_C2H_CLASS_MAX, 172 }; 173 174 enum rtw89_env_monitor_result_level { 175 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 176 RTW89_PHY_ENV_MON_NHM = BIT(0), 177 RTW89_PHY_ENV_MON_CLM = BIT(1), 178 RTW89_PHY_ENV_MON_FAHM = BIT(2), 179 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 180 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 181 }; 182 183 #define CCX_US_BASE_RATIO 4 184 enum rtw89_ccx_unit { 185 RTW89_CCX_4_US = 0, 186 RTW89_CCX_8_US = 1, 187 RTW89_CCX_16_US = 2, 188 RTW89_CCX_32_US = 3 189 }; 190 191 enum rtw89_phy_status_ie_type { 192 RTW89_PHYSTS_IE00_CMN_CCK = 0, 193 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 194 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 195 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 196 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 197 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 198 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 199 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 200 RTW89_PHYSTS_IE08_FTR_CH = 8, 201 RTW89_PHYSTS_IE09_FTR_0 = 9, 202 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 203 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 204 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 205 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 206 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 207 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 208 RTW89_PHYSTS_IE16_RSVD16 = 16, 209 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 210 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 211 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 212 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 213 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 214 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 215 RTW89_PHYSTS_IE23_RSVD23 = 23, 216 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 217 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 218 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 219 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 220 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 221 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 222 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 223 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 224 225 /* keep last */ 226 RTW89_PHYSTS_IE_NUM, 227 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 228 }; 229 230 enum rtw89_phy_status_bitmap { 231 RTW89_TD_SEARCH_FAIL = 0, 232 RTW89_BRK_BY_TX_PKT = 1, 233 RTW89_CCA_SPOOF = 2, 234 RTW89_OFDM_BRK = 3, 235 RTW89_CCK_BRK = 4, 236 RTW89_DL_MU_SPOOFING = 5, 237 RTW89_HE_MU = 6, 238 RTW89_VHT_MU = 7, 239 RTW89_UL_TB_SPOOFING = 8, 240 RTW89_RSVD_9 = 9, 241 RTW89_TRIG_BASE_PPDU = 10, 242 RTW89_CCK_PKT = 11, 243 RTW89_LEGACY_OFDM_PKT = 12, 244 RTW89_HT_PKT = 13, 245 RTW89_VHT_PKT = 14, 246 RTW89_HE_PKT = 15, 247 248 RTW89_PHYSTS_BITMAP_NUM 249 }; 250 251 enum rtw89_dig_gain_type { 252 RTW89_DIG_GAIN_LNA_G = 0, 253 RTW89_DIG_GAIN_TIA_G = 1, 254 RTW89_DIG_GAIN_LNA_A = 2, 255 RTW89_DIG_GAIN_TIA_A = 3, 256 RTW89_DIG_GAIN_MAX = 4 257 }; 258 259 enum rtw89_dig_gain_lna_idx { 260 RTW89_DIG_GAIN_LNA_IDX1 = 1, 261 RTW89_DIG_GAIN_LNA_IDX2 = 2, 262 RTW89_DIG_GAIN_LNA_IDX3 = 3, 263 RTW89_DIG_GAIN_LNA_IDX4 = 4, 264 RTW89_DIG_GAIN_LNA_IDX5 = 5, 265 RTW89_DIG_GAIN_LNA_IDX6 = 6 266 }; 267 268 enum rtw89_dig_gain_tia_idx { 269 RTW89_DIG_GAIN_TIA_IDX0 = 0, 270 RTW89_DIG_GAIN_TIA_IDX1 = 1 271 }; 272 273 enum rtw89_tssi_bandedge_cfg { 274 RTW89_TSSI_BANDEDGE_FLAT, 275 RTW89_TSSI_BANDEDGE_LOW, 276 RTW89_TSSI_BANDEDGE_MID, 277 RTW89_TSSI_BANDEDGE_HIGH, 278 279 RTW89_TSSI_CFG_NUM, 280 }; 281 282 enum rtw89_tssi_sbw_idx { 283 RTW89_TSSI_SBW20, 284 RTW89_TSSI_SBW40_0, 285 RTW89_TSSI_SBW40_1, 286 RTW89_TSSI_SBW80_0, 287 RTW89_TSSI_SBW80_1, 288 RTW89_TSSI_SBW80_2, 289 RTW89_TSSI_SBW80_3, 290 RTW89_TSSI_SBW160_0, 291 RTW89_TSSI_SBW160_1, 292 RTW89_TSSI_SBW160_2, 293 RTW89_TSSI_SBW160_3, 294 RTW89_TSSI_SBW160_4, 295 RTW89_TSSI_SBW160_5, 296 RTW89_TSSI_SBW160_6, 297 RTW89_TSSI_SBW160_7, 298 299 RTW89_TSSI_SBW_NUM, 300 }; 301 302 struct rtw89_txpwr_byrate_cfg { 303 enum rtw89_band band; 304 enum rtw89_nss nss; 305 enum rtw89_rate_section rs; 306 u8 shf; 307 u8 len; 308 u32 data; 309 }; 310 311 struct rtw89_txpwr_track_cfg { 312 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 313 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 314 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 315 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 316 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 317 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 318 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 319 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 320 const s8 *delta_swingidx_2gb_n; 321 const s8 *delta_swingidx_2gb_p; 322 const s8 *delta_swingidx_2ga_n; 323 const s8 *delta_swingidx_2ga_p; 324 const s8 *delta_swingidx_2g_cck_b_n; 325 const s8 *delta_swingidx_2g_cck_b_p; 326 const s8 *delta_swingidx_2g_cck_a_n; 327 const s8 *delta_swingidx_2g_cck_a_p; 328 }; 329 330 struct rtw89_phy_dig_gain_cfg { 331 const struct rtw89_reg_def *table; 332 u8 size; 333 }; 334 335 struct rtw89_phy_dig_gain_table { 336 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 337 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 338 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 339 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 340 }; 341 342 struct rtw89_phy_tssi_dbw_table { 343 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 344 }; 345 346 struct rtw89_phy_reg3_tbl { 347 const struct rtw89_reg3_def *reg3; 348 int size; 349 }; 350 351 #define DECLARE_PHY_REG3_TBL(_name) \ 352 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 353 .reg3 = _name, \ 354 .size = ARRAY_SIZE(_name), \ 355 } 356 357 struct rtw89_nbi_reg_def { 358 struct rtw89_reg_def notch1_idx; 359 struct rtw89_reg_def notch1_frac_idx; 360 struct rtw89_reg_def notch1_en; 361 struct rtw89_reg_def notch2_idx; 362 struct rtw89_reg_def notch2_frac_idx; 363 struct rtw89_reg_def notch2_en; 364 }; 365 366 struct rtw89_ccx_regs { 367 u32 setting_addr; 368 u32 edcca_opt_mask; 369 u32 measurement_trig_mask; 370 u32 trig_opt_mask; 371 u32 en_mask; 372 u32 ifs_cnt_addr; 373 u32 ifs_clm_period_mask; 374 u32 ifs_clm_cnt_unit_mask; 375 u32 ifs_clm_cnt_clear_mask; 376 u32 ifs_collect_en_mask; 377 u32 ifs_t1_addr; 378 u32 ifs_t1_th_h_mask; 379 u32 ifs_t1_en_mask; 380 u32 ifs_t1_th_l_mask; 381 u32 ifs_t2_addr; 382 u32 ifs_t2_th_h_mask; 383 u32 ifs_t2_en_mask; 384 u32 ifs_t2_th_l_mask; 385 u32 ifs_t3_addr; 386 u32 ifs_t3_th_h_mask; 387 u32 ifs_t3_en_mask; 388 u32 ifs_t3_th_l_mask; 389 u32 ifs_t4_addr; 390 u32 ifs_t4_th_h_mask; 391 u32 ifs_t4_en_mask; 392 u32 ifs_t4_th_l_mask; 393 u32 ifs_clm_tx_cnt_addr; 394 u32 ifs_clm_edcca_excl_cca_fa_mask; 395 u32 ifs_clm_tx_cnt_msk; 396 u32 ifs_clm_cca_addr; 397 u32 ifs_clm_ofdmcca_excl_fa_mask; 398 u32 ifs_clm_cckcca_excl_fa_mask; 399 u32 ifs_clm_fa_addr; 400 u32 ifs_clm_ofdm_fa_mask; 401 u32 ifs_clm_cck_fa_mask; 402 u32 ifs_his_addr; 403 u32 ifs_t4_his_mask; 404 u32 ifs_t3_his_mask; 405 u32 ifs_t2_his_mask; 406 u32 ifs_t1_his_mask; 407 u32 ifs_avg_l_addr; 408 u32 ifs_t2_avg_mask; 409 u32 ifs_t1_avg_mask; 410 u32 ifs_avg_h_addr; 411 u32 ifs_t4_avg_mask; 412 u32 ifs_t3_avg_mask; 413 u32 ifs_cca_l_addr; 414 u32 ifs_t2_cca_mask; 415 u32 ifs_t1_cca_mask; 416 u32 ifs_cca_h_addr; 417 u32 ifs_t4_cca_mask; 418 u32 ifs_t3_cca_mask; 419 u32 ifs_total_addr; 420 u32 ifs_cnt_done_mask; 421 u32 ifs_total_mask; 422 }; 423 424 struct rtw89_physts_regs { 425 u32 setting_addr; 426 u32 dis_trigger_fail_mask; 427 u32 dis_trigger_brk_mask; 428 }; 429 430 struct rtw89_cfo_regs { 431 u32 comp; 432 u32 weighting_mask; 433 u32 comp_seg0; 434 u32 valid_0_mask; 435 }; 436 437 enum rtw89_bandwidth_section_num_ax { 438 RTW89_BW20_SEC_NUM_AX = 8, 439 RTW89_BW40_SEC_NUM_AX = 4, 440 RTW89_BW80_SEC_NUM_AX = 2, 441 }; 442 443 enum rtw89_bandwidth_section_num_be { 444 RTW89_BW20_SEC_NUM_BE = 16, 445 RTW89_BW40_SEC_NUM_BE = 8, 446 RTW89_BW80_SEC_NUM_BE = 4, 447 RTW89_BW160_SEC_NUM_BE = 2, 448 }; 449 450 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 451 452 struct rtw89_txpwr_limit_ax { 453 s8 cck_20m[RTW89_BF_NUM]; 454 s8 cck_40m[RTW89_BF_NUM]; 455 s8 ofdm[RTW89_BF_NUM]; 456 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; 457 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; 458 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; 459 s8 mcs_160m[RTW89_BF_NUM]; 460 s8 mcs_40m_0p5[RTW89_BF_NUM]; 461 s8 mcs_40m_2p5[RTW89_BF_NUM]; 462 }; 463 464 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 465 466 struct rtw89_txpwr_limit_be { 467 s8 cck_20m[RTW89_BF_NUM]; 468 s8 cck_40m[RTW89_BF_NUM]; 469 s8 ofdm[RTW89_BF_NUM]; 470 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; 471 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; 472 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; 473 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; 474 s8 mcs_320m[RTW89_BF_NUM]; 475 s8 mcs_40m_0p5[RTW89_BF_NUM]; 476 s8 mcs_40m_2p5[RTW89_BF_NUM]; 477 s8 mcs_40m_4p5[RTW89_BF_NUM]; 478 s8 mcs_40m_6p5[RTW89_BF_NUM]; 479 }; 480 481 #define RTW89_RU_SEC_NUM_AX 8 482 483 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 484 485 struct rtw89_txpwr_limit_ru_ax { 486 s8 ru26[RTW89_RU_SEC_NUM_AX]; 487 s8 ru52[RTW89_RU_SEC_NUM_AX]; 488 s8 ru106[RTW89_RU_SEC_NUM_AX]; 489 }; 490 491 #define RTW89_RU_SEC_NUM_BE 16 492 493 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 494 495 struct rtw89_txpwr_limit_ru_be { 496 s8 ru26[RTW89_RU_SEC_NUM_BE]; 497 s8 ru52[RTW89_RU_SEC_NUM_BE]; 498 s8 ru106[RTW89_RU_SEC_NUM_BE]; 499 s8 ru52_26[RTW89_RU_SEC_NUM_BE]; 500 s8 ru106_26[RTW89_RU_SEC_NUM_BE]; 501 }; 502 503 struct rtw89_phy_rfk_log_fmt { 504 const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM]; 505 }; 506 507 struct rtw89_phy_gen_def { 508 u32 cr_base; 509 const struct rtw89_ccx_regs *ccx; 510 const struct rtw89_physts_regs *physts; 511 const struct rtw89_cfo_regs *cfo; 512 513 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, 514 const struct rtw89_chan *chan, 515 enum rtw89_phy_idx phy_idx); 516 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, 517 const struct rtw89_chan *chan, 518 enum rtw89_phy_idx phy_idx); 519 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, 520 const struct rtw89_chan *chan, 521 enum rtw89_phy_idx phy_idx); 522 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, 523 const struct rtw89_chan *chan, 524 enum rtw89_phy_idx phy_idx); 525 }; 526 527 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 528 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 529 530 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 531 u32 addr, u8 data) 532 { 533 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 534 535 rtw89_write8(rtwdev, addr + phy->cr_base, data); 536 } 537 538 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 539 u32 addr, u16 data) 540 { 541 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 542 543 rtw89_write16(rtwdev, addr + phy->cr_base, data); 544 } 545 546 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 547 u32 addr, u32 data) 548 { 549 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 550 551 rtw89_write32(rtwdev, addr + phy->cr_base, data); 552 } 553 554 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 555 u32 addr, u32 bits) 556 { 557 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 558 559 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 560 } 561 562 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 563 u32 addr, u32 bits) 564 { 565 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 566 567 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 568 } 569 570 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 571 u32 addr, u32 mask, u32 data) 572 { 573 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 574 575 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 576 } 577 578 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 579 { 580 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 581 582 return rtw89_read8(rtwdev, addr + phy->cr_base); 583 } 584 585 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 586 { 587 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 588 589 return rtw89_read16(rtwdev, addr + phy->cr_base); 590 } 591 592 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 593 { 594 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 595 596 return rtw89_read32(rtwdev, addr + phy->cr_base); 597 } 598 599 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 600 u32 addr, u32 mask) 601 { 602 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 603 604 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 605 } 606 607 static inline 608 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 609 { 610 switch (subband) { 611 default: 612 case RTW89_CH_2G: 613 return RTW89_GAIN_OFFSET_2G_OFDM; 614 case RTW89_CH_5G_BAND_1: 615 return RTW89_GAIN_OFFSET_5G_LOW; 616 case RTW89_CH_5G_BAND_3: 617 return RTW89_GAIN_OFFSET_5G_MID; 618 case RTW89_CH_5G_BAND_4: 619 return RTW89_GAIN_OFFSET_5G_HIGH; 620 case RTW89_CH_6G_BAND_IDX0: 621 return RTW89_GAIN_OFFSET_6G_L0; 622 case RTW89_CH_6G_BAND_IDX1: 623 return RTW89_GAIN_OFFSET_6G_L1; 624 case RTW89_CH_6G_BAND_IDX2: 625 return RTW89_GAIN_OFFSET_6G_M0; 626 case RTW89_CH_6G_BAND_IDX3: 627 return RTW89_GAIN_OFFSET_6G_M1; 628 case RTW89_CH_6G_BAND_IDX4: 629 return RTW89_GAIN_OFFSET_6G_H0; 630 case RTW89_CH_6G_BAND_IDX5: 631 return RTW89_GAIN_OFFSET_6G_H1; 632 case RTW89_CH_6G_BAND_IDX6: 633 return RTW89_GAIN_OFFSET_6G_UH0; 634 case RTW89_CH_6G_BAND_IDX7: 635 return RTW89_GAIN_OFFSET_6G_UH1; 636 } 637 } 638 639 static inline 640 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 641 { 642 switch (subband) { 643 default: 644 case RTW89_CH_2G: 645 return RTW89_BB_GAIN_BAND_2G; 646 case RTW89_CH_5G_BAND_1: 647 return RTW89_BB_GAIN_BAND_5G_L; 648 case RTW89_CH_5G_BAND_3: 649 return RTW89_BB_GAIN_BAND_5G_M; 650 case RTW89_CH_5G_BAND_4: 651 return RTW89_BB_GAIN_BAND_5G_H; 652 case RTW89_CH_6G_BAND_IDX0: 653 case RTW89_CH_6G_BAND_IDX1: 654 return RTW89_BB_GAIN_BAND_6G_L; 655 case RTW89_CH_6G_BAND_IDX2: 656 case RTW89_CH_6G_BAND_IDX3: 657 return RTW89_BB_GAIN_BAND_6G_M; 658 case RTW89_CH_6G_BAND_IDX4: 659 case RTW89_CH_6G_BAND_IDX5: 660 return RTW89_BB_GAIN_BAND_6G_H; 661 case RTW89_CH_6G_BAND_IDX6: 662 case RTW89_CH_6G_BAND_IDX7: 663 return RTW89_BB_GAIN_BAND_6G_UH; 664 } 665 } 666 667 enum rtw89_rfk_flag { 668 RTW89_RFK_F_WRF = 0, 669 RTW89_RFK_F_WM = 1, 670 RTW89_RFK_F_WS = 2, 671 RTW89_RFK_F_WC = 3, 672 RTW89_RFK_F_DELAY = 4, 673 RTW89_RFK_F_NUM, 674 }; 675 676 struct rtw89_rfk_tbl { 677 const struct rtw89_reg5_def *defs; 678 u32 size; 679 }; 680 681 #define RTW89_DECLARE_RFK_TBL(_name) \ 682 const struct rtw89_rfk_tbl _name ## _tbl = { \ 683 .defs = _name, \ 684 .size = ARRAY_SIZE(_name), \ 685 } 686 687 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 688 {.flag = RTW89_RFK_F_WRF, \ 689 .path = _path, \ 690 .addr = _addr, \ 691 .mask = _mask, \ 692 .data = _data,} 693 694 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 695 {.flag = RTW89_RFK_F_WM, \ 696 .addr = _addr, \ 697 .mask = _mask, \ 698 .data = _data,} 699 700 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 701 {.flag = RTW89_RFK_F_WS, \ 702 .addr = _addr, \ 703 .mask = _mask,} 704 705 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 706 {.flag = RTW89_RFK_F_WC, \ 707 .addr = _addr, \ 708 .mask = _mask,} 709 710 #define RTW89_DECL_RFK_DELAY(_data) \ 711 {.flag = RTW89_RFK_F_DELAY, \ 712 .data = _data,} 713 714 void 715 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 716 717 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 718 do { \ 719 typeof(dev) __dev = (dev); \ 720 if (cond) \ 721 rtw89_rfk_parser(__dev, (tbl_t)); \ 722 else \ 723 rtw89_rfk_parser(__dev, (tbl_f)); \ 724 } while (0) 725 726 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 727 const struct rtw89_phy_reg3_tbl *tbl); 728 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 729 const struct rtw89_chan *chan, 730 enum rtw89_bandwidth dbw); 731 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 732 u32 addr, u32 mask); 733 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 734 u32 addr, u32 mask); 735 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 736 u32 addr, u32 mask, u32 data); 737 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 738 u32 addr, u32 mask, u32 data); 739 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 740 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 741 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 742 const struct rtw89_reg2_def *reg, 743 enum rtw89_rf_path rf_path, 744 void *extra_data); 745 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 746 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 747 u32 data, enum rtw89_phy_idx phy_idx); 748 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 749 enum rtw89_phy_idx phy_idx); 750 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 751 struct rtw89_txpwr_byrate *head, 752 const struct rtw89_rate_desc *desc); 753 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 754 const struct rtw89_rate_desc *rate_desc); 755 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 756 const struct rtw89_txpwr_table *tbl); 757 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 758 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 759 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 760 u8 ru, u8 ntx, u8 ch); 761 762 static inline 763 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 764 const struct rtw89_chan *chan, 765 enum rtw89_phy_idx phy_idx) 766 { 767 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 768 769 phy->set_txpwr_byrate(rtwdev, chan, phy_idx); 770 } 771 772 static inline 773 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 774 const struct rtw89_chan *chan, 775 enum rtw89_phy_idx phy_idx) 776 { 777 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 778 779 phy->set_txpwr_offset(rtwdev, chan, phy_idx); 780 } 781 782 static inline 783 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 784 const struct rtw89_chan *chan, 785 enum rtw89_phy_idx phy_idx) 786 { 787 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 788 789 phy->set_txpwr_limit(rtwdev, chan, phy_idx); 790 } 791 792 static inline 793 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 794 const struct rtw89_chan *chan, 795 enum rtw89_phy_idx phy_idx) 796 { 797 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 798 799 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); 800 } 801 802 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 803 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 804 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 805 u32 changed); 806 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 807 struct ieee80211_vif *vif, 808 const struct cfg80211_bitrate_mask *mask); 809 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); 810 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 811 u32 len, u8 class, u8 func); 812 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 813 void rtw89_phy_cfo_track_work(struct work_struct *work); 814 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 815 struct rtw89_rx_phy_ppdu *phy_ppdu); 816 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 817 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 818 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 819 u32 val); 820 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 821 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 822 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 823 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 824 struct rtw89_rx_phy_ppdu *phy_ppdu); 825 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 826 void rtw89_phy_antdiv_work(struct work_struct *work); 827 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 828 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 829 enum rtw89_mac_idx mac_idx, 830 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 831 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 832 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 833 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 834 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 835 u8 *ch, enum nl80211_band *band); 836 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); 837 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev); 838 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev); 839 840 #endif 841