1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_BBMCU_ADDR_OFFSET 0x30000 11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 12 13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 14 #define PHY_HEADLINE_VALID 0xf 15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 17 FIELD_PREP(GENMASK(7, 0), cv)) 18 19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 24 #define PHY_COND_BRANCH_IF 0x8 25 #define PHY_COND_BRANCH_ELIF 0x9 26 #define PHY_COND_BRANCH_ELSE 0xa 27 #define PHY_COND_BRANCH_END 0xb 28 #define PHY_COND_CHECK 0x4 29 #define PHY_COND_DONT_CARE 0xff 30 31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 33 #define RA_MASK_SUBCCK_RATES 0x5ULL 34 #define RA_MASK_SUBOFDM_RATES 0x10ULL 35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 50 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12) 51 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28) 52 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44) 53 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60) 54 #define RA_MASK_EHT_1SS_MCS0_11 GENMASK_ULL(23, 12) 55 #define RA_MASK_EHT_2SS_MCS0_11 GENMASK_ULL(39, 28) 56 #define RA_MASK_EHT_3SS_MCS0_11 GENMASK_ULL(55, 44) 57 #define RA_MASK_EHT_4SS_MCS0_11 GENMASK_ULL(62, 60) 58 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12) 59 60 #define CFO_TRK_ENABLE_TH (2 << 2) 61 #define CFO_TRK_STOP_TH_4 (30 << 2) 62 #define CFO_TRK_STOP_TH_3 (20 << 2) 63 #define CFO_TRK_STOP_TH_2 (10 << 2) 64 #define CFO_TRK_STOP_TH_1 (03 << 2) 65 #define CFO_TRK_STOP_TH (2 << 2) 66 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 67 #define CFO_PERIOD_CNT 15 68 #define CFO_BOUND 64 69 #define CFO_TP_UPPER 100 70 #define CFO_TP_LOWER 50 71 #define CFO_COMP_PERIOD 250 72 #define CFO_COMP_WEIGHT 8 73 #define MAX_CFO_TOLERANCE 30 74 #define CFO_TF_CNT_TH 300 75 76 #define UL_TB_TF_CNT_L2H_TH 100 77 #define UL_TB_TF_CNT_H2L_TH 70 78 79 #define ANTDIV_TRAINNING_CNT 2 80 #define ANTDIV_TRAINNING_INTVL 30 81 #define ANTDIV_DELAY 110 82 #define ANTDIV_TP_DIFF_TH_HIGH 100 83 #define ANTDIV_TP_DIFF_TH_LOW 5 84 #define ANTDIV_EVM_DIFF_TH 8 85 #define ANTDIV_RSSI_DIFF_TH 3 86 87 #define CCX_MAX_PERIOD 2097 88 #define CCX_MAX_PERIOD_UNIT 32 89 #define MS_TO_4US_RATIO 250 90 #define ENV_MNTR_FAIL_DWORD 0xffffffff 91 #define ENV_MNTR_IFSCLM_HIS_MAX 127 92 #define PERMIL 1000 93 #define PERCENT 100 94 #define IFS_CLM_TH0_UPPER 64 95 #define IFS_CLM_TH_MUL 4 96 #define IFS_CLM_TH_START_IDX 0 97 98 #define TIA0_GAIN_A 12 99 #define TIA0_GAIN_G 16 100 #define LNA0_GAIN (-24) 101 #define U4_MAX_BIT 3 102 #define U8_MAX_BIT 7 103 #define DIG_GAIN_SHIFT 2 104 #define DIG_GAIN 8 105 106 #define LNA_IDX_MAX 6 107 #define LNA_IDX_MIN 0 108 #define TIA_IDX_MAX 1 109 #define TIA_IDX_MIN 0 110 #define RXB_IDX_MAX 31 111 #define RXB_IDX_MIN 0 112 113 #define IGI_RSSI_MAX 110 114 #define PD_TH_MAX_RSSI 70 115 #define PD_TH_MIN_RSSI 8 116 #define CCKPD_TH_MIN_RSSI (-18) 117 #define PD_TH_BW160_CMP_VAL 9 118 #define PD_TH_BW80_CMP_VAL 6 119 #define PD_TH_BW40_CMP_VAL 3 120 #define PD_TH_BW20_CMP_VAL 0 121 #define PD_TH_CMP_VAL 3 122 #define PD_TH_SB_FLTR_CMP_VAL 7 123 124 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 125 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 126 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 127 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 128 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 129 130 #define EDCCA_MAX 249 131 #define EDCCA_TH_L2H_LB 66 132 #define EDCCA_TH_REF 3 133 #define EDCCA_HL_DIFF_NORMAL 8 134 #define RSSI_UNIT_CONVER 110 135 #define EDCCA_UNIT_CONVER 128 136 #define EDCCA_PWROFST_DEFAULT 18 137 138 enum rtw89_phy_c2h_ra_func { 139 RTW89_PHY_C2H_FUNC_STS_RPT, 140 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 141 RTW89_PHY_C2H_FUNC_TXSTS, 142 RTW89_PHY_C2H_FUNC_ACCELERATE_EN = 0x7, 143 144 RTW89_PHY_C2H_FUNC_RA_NUM, 145 }; 146 147 enum rtw89_phy_c2h_rfk_log_func { 148 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0, 149 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1, 150 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2, 151 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3, 152 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, 153 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, 154 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9, 155 RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK = 0xc, 156 RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K = 0xe, 157 158 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, 159 }; 160 161 enum rtw89_phy_c2h_rfk_report_func { 162 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0, 163 RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR = 6, 164 }; 165 166 enum rtw89_phy_c2h_dm_func { 167 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 168 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 169 RTW89_PHY_C2H_DM_FUNC_SIGB, 170 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 171 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 172 RTW89_PHY_C2H_DM_FUNC_LPS = 0x9, 173 RTW89_PHY_C2H_DM_FUNC_ENV_MNTR = 0xa, 174 RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc, 175 RTW89_PHY_C2H_DM_FUNC_NUM, 176 }; 177 178 enum rtw89_phy_c2h_class { 179 RTW89_PHY_C2H_CLASS_RUA, 180 RTW89_PHY_C2H_CLASS_RA, 181 RTW89_PHY_C2H_CLASS_DM, 182 RTW89_PHY_C2H_RFK_LOG = 0x8, 183 RTW89_PHY_C2H_RFK_REPORT = 0x9, 184 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 185 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 186 RTW89_PHY_C2H_CLASS_MAX, 187 }; 188 189 enum rtw89_env_monitor_result_level { 190 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 191 RTW89_PHY_ENV_MON_NHM = BIT(0), 192 RTW89_PHY_ENV_MON_CLM = BIT(1), 193 RTW89_PHY_ENV_MON_FAHM = BIT(2), 194 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 195 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 196 }; 197 198 #define RTW89_NHM_WEIGHT_OFFSET 2 199 #define RTW89_NHM_WA_TH (109 << 1) 200 #define RTW89_NOISE_DEFAULT -96 201 #define RTW89_NHM_MNTR_TIME 40 202 #define RTW89_NHM_TH_FACTOR 1 203 204 #define CCX_US_BASE_RATIO 4 205 enum rtw89_ccx_unit { 206 RTW89_CCX_4_US = 0, 207 RTW89_CCX_8_US = 1, 208 RTW89_CCX_16_US = 2, 209 RTW89_CCX_32_US = 3 210 }; 211 212 enum rtw89_phy_status_ie_type { 213 RTW89_PHYSTS_IE00_CMN_CCK = 0, 214 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 215 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 216 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 217 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 218 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 219 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 220 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 221 RTW89_PHYSTS_IE08_FTR_CH = 8, 222 RTW89_PHYSTS_IE09_FTR_0 = 9, 223 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 224 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 225 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 226 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 227 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 228 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 229 RTW89_PHYSTS_IE16_RSVD16 = 16, 230 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 231 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 232 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 233 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 234 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 235 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 236 RTW89_PHYSTS_IE23_RSVD23 = 23, 237 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 238 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 239 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 240 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 241 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 242 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 243 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 244 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 245 246 /* keep last */ 247 RTW89_PHYSTS_IE_NUM, 248 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 249 }; 250 251 enum rtw89_phy_status_bitmap { 252 RTW89_TD_SEARCH_FAIL = 0, 253 RTW89_BRK_BY_TX_PKT = 1, 254 RTW89_CCA_SPOOF = 2, 255 RTW89_OFDM_BRK = 3, 256 RTW89_CCK_BRK = 4, 257 RTW89_DL_MU_SPOOFING = 5, 258 RTW89_HE_MU = 6, 259 RTW89_VHT_MU = 7, 260 RTW89_UL_TB_SPOOFING = 8, 261 RTW89_RSVD_9 = 9, 262 RTW89_TRIG_BASE_PPDU = 10, 263 RTW89_CCK_PKT = 11, 264 RTW89_LEGACY_OFDM_PKT = 12, 265 RTW89_HT_PKT = 13, 266 RTW89_VHT_PKT = 14, 267 RTW89_HE_PKT = 15, 268 RTW89_EHT_PKT = 16, 269 270 RTW89_PHYSTS_BITMAP_NUM 271 }; 272 273 enum rtw89_dig_gain_type { 274 RTW89_DIG_GAIN_LNA_G = 0, 275 RTW89_DIG_GAIN_TIA_G = 1, 276 RTW89_DIG_GAIN_LNA_A = 2, 277 RTW89_DIG_GAIN_TIA_A = 3, 278 RTW89_DIG_GAIN_MAX = 4 279 }; 280 281 enum rtw89_dig_gain_lna_idx { 282 RTW89_DIG_GAIN_LNA_IDX1 = 1, 283 RTW89_DIG_GAIN_LNA_IDX2 = 2, 284 RTW89_DIG_GAIN_LNA_IDX3 = 3, 285 RTW89_DIG_GAIN_LNA_IDX4 = 4, 286 RTW89_DIG_GAIN_LNA_IDX5 = 5, 287 RTW89_DIG_GAIN_LNA_IDX6 = 6 288 }; 289 290 enum rtw89_dig_gain_tia_idx { 291 RTW89_DIG_GAIN_TIA_IDX0 = 0, 292 RTW89_DIG_GAIN_TIA_IDX1 = 1 293 }; 294 295 enum rtw89_tssi_bandedge_cfg { 296 RTW89_TSSI_BANDEDGE_FLAT, 297 RTW89_TSSI_BANDEDGE_LOW, 298 RTW89_TSSI_BANDEDGE_MID, 299 RTW89_TSSI_BANDEDGE_HIGH, 300 301 RTW89_TSSI_CFG_NUM, 302 }; 303 304 enum rtw89_tssi_sbw_idx { 305 RTW89_TSSI_SBW20, 306 RTW89_TSSI_SBW40_0, 307 RTW89_TSSI_SBW40_1, 308 RTW89_TSSI_SBW80_0, 309 RTW89_TSSI_SBW80_1, 310 RTW89_TSSI_SBW80_2, 311 RTW89_TSSI_SBW80_3, 312 RTW89_TSSI_SBW160_0, 313 RTW89_TSSI_SBW160_1, 314 RTW89_TSSI_SBW160_2, 315 RTW89_TSSI_SBW160_3, 316 RTW89_TSSI_SBW160_4, 317 RTW89_TSSI_SBW160_5, 318 RTW89_TSSI_SBW160_6, 319 RTW89_TSSI_SBW160_7, 320 321 RTW89_TSSI_SBW_NUM, 322 }; 323 324 struct rtw89_txpwr_byrate_cfg { 325 enum rtw89_band band; 326 enum rtw89_nss nss; 327 enum rtw89_rate_section rs; 328 u8 shf; 329 u8 len; 330 u32 data; 331 }; 332 333 struct rtw89_txpwr_track_cfg { 334 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 335 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 336 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 337 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 338 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 339 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 340 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 341 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 342 const s8 *delta_swingidx_2gb_n; 343 const s8 *delta_swingidx_2gb_p; 344 const s8 *delta_swingidx_2ga_n; 345 const s8 *delta_swingidx_2ga_p; 346 const s8 *delta_swingidx_2g_cck_b_n; 347 const s8 *delta_swingidx_2g_cck_b_p; 348 const s8 *delta_swingidx_2g_cck_a_n; 349 const s8 *delta_swingidx_2g_cck_a_p; 350 }; 351 352 struct rtw89_phy_dig_gain_cfg { 353 const struct rtw89_reg_def *table; 354 u8 size; 355 }; 356 357 struct rtw89_phy_dig_gain_table { 358 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 359 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 360 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 361 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 362 }; 363 364 struct rtw89_phy_tssi_dbw_table { 365 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 366 }; 367 368 struct rtw89_phy_reg3_tbl { 369 const struct rtw89_reg3_def *reg3; 370 int size; 371 }; 372 373 #define DECLARE_PHY_REG3_TBL(_name) \ 374 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 375 .reg3 = _name, \ 376 .size = ARRAY_SIZE(_name), \ 377 } 378 379 struct rtw89_nbi_reg_def { 380 struct rtw89_reg_def notch1_idx; 381 struct rtw89_reg_def notch1_frac_idx; 382 struct rtw89_reg_def notch1_en; 383 struct rtw89_reg_def notch2_idx; 384 struct rtw89_reg_def notch2_frac_idx; 385 struct rtw89_reg_def notch2_en; 386 }; 387 388 struct rtw89_ccx_regs { 389 u32 setting_addr; 390 u32 edcca_opt_mask; 391 u32 measurement_trig_mask; 392 u32 trig_opt_mask; 393 u32 en_mask; 394 u32 ifs_cnt_addr; 395 u32 ifs_clm_period_mask; 396 u32 ifs_clm_cnt_unit_mask; 397 u32 ifs_clm_cnt_clear_mask; 398 u32 ifs_collect_en_mask; 399 u32 ifs_t1_addr; 400 u32 ifs_t1_th_h_mask; 401 u32 ifs_t1_en_mask; 402 u32 ifs_t1_th_l_mask; 403 u32 ifs_t2_addr; 404 u32 ifs_t2_th_h_mask; 405 u32 ifs_t2_en_mask; 406 u32 ifs_t2_th_l_mask; 407 u32 ifs_t3_addr; 408 u32 ifs_t3_th_h_mask; 409 u32 ifs_t3_en_mask; 410 u32 ifs_t3_th_l_mask; 411 u32 ifs_t4_addr; 412 u32 ifs_t4_th_h_mask; 413 u32 ifs_t4_en_mask; 414 u32 ifs_t4_th_l_mask; 415 u32 ifs_clm_tx_cnt_addr; 416 u32 ifs_clm_edcca_excl_cca_fa_mask; 417 u32 ifs_clm_tx_cnt_msk; 418 u32 ifs_clm_cca_addr; 419 u32 ifs_clm_ofdmcca_excl_fa_mask; 420 u32 ifs_clm_cckcca_excl_fa_mask; 421 u32 ifs_clm_fa_addr; 422 u32 ifs_clm_ofdm_fa_mask; 423 u32 ifs_clm_cck_fa_mask; 424 u32 ifs_his_addr; 425 u32 ifs_his_addr2; 426 u32 ifs_t4_his_mask; 427 u32 ifs_t3_his_mask; 428 u32 ifs_t2_his_mask; 429 u32 ifs_t1_his_mask; 430 u32 ifs_avg_l_addr; 431 u32 ifs_t2_avg_mask; 432 u32 ifs_t1_avg_mask; 433 u32 ifs_avg_h_addr; 434 u32 ifs_t4_avg_mask; 435 u32 ifs_t3_avg_mask; 436 u32 ifs_cca_l_addr; 437 u32 ifs_t2_cca_mask; 438 u32 ifs_t1_cca_mask; 439 u32 ifs_cca_h_addr; 440 u32 ifs_t4_cca_mask; 441 u32 ifs_t3_cca_mask; 442 u32 ifs_total_addr; 443 u32 ifs_cnt_done_mask; 444 u32 ifs_total_mask; 445 u32 nhm; 446 u32 nhm_ready; 447 u32 nhm_config; 448 u32 nhm_period_mask; 449 u32 nhm_unit_mask; 450 u32 nhm_include_cca_mask; 451 u32 nhm_en_mask; 452 u32 nhm_method; 453 u32 nhm_pwr_method_msk; 454 }; 455 456 struct rtw89_physts_regs { 457 u32 setting_addr; 458 u32 dis_trigger_fail_mask; 459 u32 dis_trigger_brk_mask; 460 }; 461 462 struct rtw89_cfo_regs { 463 u32 comp; 464 u32 weighting_mask; 465 u32 comp_seg0; 466 u32 valid_0_mask; 467 }; 468 469 struct rtw89_bb_wrap_regs { 470 u32 pwr_macid_lmt; 471 u32 pwr_macid_path; 472 }; 473 474 enum rtw89_bandwidth_section_num_ax { 475 RTW89_BW20_SEC_NUM_AX = 8, 476 RTW89_BW40_SEC_NUM_AX = 4, 477 RTW89_BW80_SEC_NUM_AX = 2, 478 }; 479 480 enum rtw89_bandwidth_section_num_be { 481 RTW89_BW20_SEC_NUM_BE = 16, 482 RTW89_BW40_SEC_NUM_BE = 8, 483 RTW89_BW80_SEC_NUM_BE = 4, 484 RTW89_BW160_SEC_NUM_BE = 2, 485 }; 486 487 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 488 489 struct rtw89_txpwr_limit_ax { 490 s8 cck_20m[RTW89_BF_NUM]; 491 s8 cck_40m[RTW89_BF_NUM]; 492 s8 ofdm[RTW89_BF_NUM]; 493 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; 494 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; 495 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; 496 s8 mcs_160m[RTW89_BF_NUM]; 497 s8 mcs_40m_0p5[RTW89_BF_NUM]; 498 s8 mcs_40m_2p5[RTW89_BF_NUM]; 499 }; 500 501 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 502 503 struct rtw89_txpwr_limit_be { 504 s8 cck_20m[RTW89_BF_NUM]; 505 s8 cck_40m[RTW89_BF_NUM]; 506 s8 ofdm[RTW89_BF_NUM]; 507 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; 508 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; 509 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; 510 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; 511 s8 mcs_320m[RTW89_BF_NUM]; 512 s8 mcs_40m_0p5[RTW89_BF_NUM]; 513 s8 mcs_40m_2p5[RTW89_BF_NUM]; 514 s8 mcs_40m_4p5[RTW89_BF_NUM]; 515 s8 mcs_40m_6p5[RTW89_BF_NUM]; 516 }; 517 518 #define RTW89_RU_SEC_NUM_AX 8 519 520 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 521 522 struct rtw89_txpwr_limit_ru_ax { 523 s8 ru26[RTW89_RU_SEC_NUM_AX]; 524 s8 ru52[RTW89_RU_SEC_NUM_AX]; 525 s8 ru106[RTW89_RU_SEC_NUM_AX]; 526 }; 527 528 #define RTW89_RU_SEC_NUM_BE 16 529 530 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 531 532 struct rtw89_txpwr_limit_ru_be { 533 s8 ru26[RTW89_RU_SEC_NUM_BE]; 534 s8 ru52[RTW89_RU_SEC_NUM_BE]; 535 s8 ru106[RTW89_RU_SEC_NUM_BE]; 536 s8 ru52_26[RTW89_RU_SEC_NUM_BE]; 537 s8 ru106_26[RTW89_RU_SEC_NUM_BE]; 538 }; 539 540 struct rtw89_phy_rfk_log_fmt { 541 const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM]; 542 }; 543 544 struct rtw89_phy_gen_def { 545 u32 cr_base; 546 u32 physt_bmp_start; 547 u32 physt_bmp_eht; 548 const struct rtw89_ccx_regs *ccx; 549 const struct rtw89_physts_regs *physts; 550 const struct rtw89_cfo_regs *cfo; 551 const struct rtw89_bb_wrap_regs *bb_wrap; 552 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr); 553 void (*config_bb_gain)(struct rtw89_dev *rtwdev, 554 const struct rtw89_reg2_def *reg, 555 enum rtw89_rf_path rf_path, 556 void *extra_data); 557 void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev); 558 void (*bb_wrap_init)(struct rtw89_dev *rtwdev); 559 void (*ch_info_init)(struct rtw89_dev *rtwdev); 560 561 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, 562 const struct rtw89_chan *chan, 563 enum rtw89_phy_idx phy_idx); 564 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, 565 const struct rtw89_chan *chan, 566 enum rtw89_phy_idx phy_idx); 567 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, 568 const struct rtw89_chan *chan, 569 enum rtw89_phy_idx phy_idx); 570 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, 571 const struct rtw89_chan *chan, 572 enum rtw89_phy_idx phy_idx); 573 }; 574 575 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 576 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 577 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1; 578 579 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 580 u32 addr, u8 data) 581 { 582 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 583 584 rtw89_write8(rtwdev, addr + phy->cr_base, data); 585 } 586 587 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 588 u32 addr, u16 data) 589 { 590 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 591 592 rtw89_write16(rtwdev, addr + phy->cr_base, data); 593 } 594 595 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 596 u32 addr, u32 data) 597 { 598 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 599 600 rtw89_write32(rtwdev, addr + phy->cr_base, data); 601 } 602 603 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 604 u32 addr, u32 bits) 605 { 606 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 607 608 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 609 } 610 611 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 612 u32 addr, u32 bits) 613 { 614 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 615 616 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 617 } 618 619 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 620 u32 addr, u32 mask, u32 data) 621 { 622 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 623 624 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 625 } 626 627 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 628 { 629 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 630 631 return rtw89_read8(rtwdev, addr + phy->cr_base); 632 } 633 634 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 635 { 636 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 637 638 return rtw89_read16(rtwdev, addr + phy->cr_base); 639 } 640 641 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 642 { 643 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 644 645 return rtw89_read32(rtwdev, addr + phy->cr_base); 646 } 647 648 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 649 u32 addr, u32 mask) 650 { 651 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 652 653 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 654 } 655 656 static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev, 657 u32 addr, u32 data, enum rtw89_phy_idx phy_idx) 658 { 659 if (phy_idx && addr < 0x10000) 660 addr += 0x20000; 661 662 rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data); 663 } 664 665 static inline 666 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 667 { 668 switch (subband) { 669 default: 670 case RTW89_CH_2G: 671 return RTW89_GAIN_OFFSET_2G_OFDM; 672 case RTW89_CH_5G_BAND_1: 673 return RTW89_GAIN_OFFSET_5G_LOW; 674 case RTW89_CH_5G_BAND_3: 675 return RTW89_GAIN_OFFSET_5G_MID; 676 case RTW89_CH_5G_BAND_4: 677 return RTW89_GAIN_OFFSET_5G_HIGH; 678 case RTW89_CH_6G_BAND_IDX0: 679 return RTW89_GAIN_OFFSET_6G_L0; 680 case RTW89_CH_6G_BAND_IDX1: 681 return RTW89_GAIN_OFFSET_6G_L1; 682 case RTW89_CH_6G_BAND_IDX2: 683 return RTW89_GAIN_OFFSET_6G_M0; 684 case RTW89_CH_6G_BAND_IDX3: 685 return RTW89_GAIN_OFFSET_6G_M1; 686 case RTW89_CH_6G_BAND_IDX4: 687 return RTW89_GAIN_OFFSET_6G_H0; 688 case RTW89_CH_6G_BAND_IDX5: 689 return RTW89_GAIN_OFFSET_6G_H1; 690 case RTW89_CH_6G_BAND_IDX6: 691 return RTW89_GAIN_OFFSET_6G_UH0; 692 case RTW89_CH_6G_BAND_IDX7: 693 return RTW89_GAIN_OFFSET_6G_UH1; 694 } 695 } 696 697 static inline 698 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 699 { 700 switch (subband) { 701 default: 702 case RTW89_CH_2G: 703 return RTW89_BB_GAIN_BAND_2G; 704 case RTW89_CH_5G_BAND_1: 705 return RTW89_BB_GAIN_BAND_5G_L; 706 case RTW89_CH_5G_BAND_3: 707 return RTW89_BB_GAIN_BAND_5G_M; 708 case RTW89_CH_5G_BAND_4: 709 return RTW89_BB_GAIN_BAND_5G_H; 710 case RTW89_CH_6G_BAND_IDX0: 711 case RTW89_CH_6G_BAND_IDX1: 712 return RTW89_BB_GAIN_BAND_6G_L; 713 case RTW89_CH_6G_BAND_IDX2: 714 case RTW89_CH_6G_BAND_IDX3: 715 return RTW89_BB_GAIN_BAND_6G_M; 716 case RTW89_CH_6G_BAND_IDX4: 717 case RTW89_CH_6G_BAND_IDX5: 718 return RTW89_BB_GAIN_BAND_6G_H; 719 case RTW89_CH_6G_BAND_IDX6: 720 case RTW89_CH_6G_BAND_IDX7: 721 return RTW89_BB_GAIN_BAND_6G_UH; 722 } 723 } 724 725 static inline 726 enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband) 727 { 728 switch (subband) { 729 default: 730 case RTW89_CH_2G: 731 return RTW89_BB_GAIN_BAND_2G_BE; 732 case RTW89_CH_5G_BAND_1: 733 return RTW89_BB_GAIN_BAND_5G_L_BE; 734 case RTW89_CH_5G_BAND_3: 735 return RTW89_BB_GAIN_BAND_5G_M_BE; 736 case RTW89_CH_5G_BAND_4: 737 return RTW89_BB_GAIN_BAND_5G_H_BE; 738 case RTW89_CH_6G_BAND_IDX0: 739 return RTW89_BB_GAIN_BAND_6G_L0_BE; 740 case RTW89_CH_6G_BAND_IDX1: 741 return RTW89_BB_GAIN_BAND_6G_L1_BE; 742 case RTW89_CH_6G_BAND_IDX2: 743 return RTW89_BB_GAIN_BAND_6G_M0_BE; 744 case RTW89_CH_6G_BAND_IDX3: 745 return RTW89_BB_GAIN_BAND_6G_M1_BE; 746 case RTW89_CH_6G_BAND_IDX4: 747 return RTW89_BB_GAIN_BAND_6G_H0_BE; 748 case RTW89_CH_6G_BAND_IDX5: 749 return RTW89_BB_GAIN_BAND_6G_H1_BE; 750 case RTW89_CH_6G_BAND_IDX6: 751 return RTW89_BB_GAIN_BAND_6G_UH0_BE; 752 case RTW89_CH_6G_BAND_IDX7: 753 return RTW89_BB_GAIN_BAND_6G_UH1_BE; 754 } 755 } 756 757 struct rtw89_rfk_chan_desc { 758 /* desc is valid iff ch is non-zero */ 759 u8 ch; 760 761 /* To avoid us from extending old chip code every time, each new 762 * field must be defined along with a bool flag in positivte way. 763 */ 764 bool has_band; 765 u8 band; 766 bool has_bw; 767 u8 bw; 768 }; 769 770 enum rtw89_rfk_flag { 771 RTW89_RFK_F_WRF = 0, 772 RTW89_RFK_F_WM = 1, 773 RTW89_RFK_F_WS = 2, 774 RTW89_RFK_F_WC = 3, 775 RTW89_RFK_F_DELAY = 4, 776 RTW89_RFK_F_NUM, 777 }; 778 779 struct rtw89_rfk_tbl { 780 const struct rtw89_reg5_def *defs; 781 u32 size; 782 }; 783 784 #define RTW89_DECLARE_RFK_TBL(_name) \ 785 const struct rtw89_rfk_tbl _name ## _tbl = { \ 786 .defs = _name, \ 787 .size = ARRAY_SIZE(_name), \ 788 } 789 790 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 791 {.flag = RTW89_RFK_F_WRF, \ 792 .path = _path, \ 793 .addr = _addr, \ 794 .mask = _mask, \ 795 .data = _data,} 796 797 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 798 {.flag = RTW89_RFK_F_WM, \ 799 .addr = _addr, \ 800 .mask = _mask, \ 801 .data = _data,} 802 803 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 804 {.flag = RTW89_RFK_F_WS, \ 805 .addr = _addr, \ 806 .mask = _mask,} 807 808 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 809 {.flag = RTW89_RFK_F_WC, \ 810 .addr = _addr, \ 811 .mask = _mask,} 812 813 #define RTW89_DECL_RFK_DELAY(_data) \ 814 {.flag = RTW89_RFK_F_DELAY, \ 815 .data = _data,} 816 817 void 818 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 819 820 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 821 do { \ 822 typeof(dev) __dev = (dev); \ 823 if (cond) \ 824 rtw89_rfk_parser(__dev, (tbl_t)); \ 825 else \ 826 rtw89_rfk_parser(__dev, (tbl_f)); \ 827 } while (0) 828 829 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 830 const struct rtw89_phy_reg3_tbl *tbl); 831 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 832 const struct rtw89_chan *chan, 833 enum rtw89_bandwidth dbw); 834 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 835 enum rtw89_bandwidth dbw); 836 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 837 u32 addr, u32 mask); 838 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 839 u32 addr, u32 mask); 840 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 841 u32 addr, u32 mask); 842 u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 843 u32 addr, u32 mask); 844 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 845 u32 addr, u32 mask, u32 data); 846 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 847 u32 addr, u32 mask, u32 data); 848 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 849 u32 addr, u32 mask, u32 data); 850 bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 851 u32 addr, u32 mask, u32 data); 852 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 853 void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev); 854 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 855 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 856 const struct rtw89_reg2_def *reg, 857 enum rtw89_rf_path rf_path, 858 void *extra_data); 859 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 860 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev); 861 void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev); 862 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 863 u32 data, enum rtw89_phy_idx phy_idx); 864 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 865 enum rtw89_phy_idx phy_idx); 866 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 867 enum rtw89_phy_idx phy_idx); 868 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 869 enum rtw89_phy_idx phy_idx); 870 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 871 struct rtw89_txpwr_byrate *head, 872 const struct rtw89_rate_desc *desc); 873 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 874 const struct rtw89_rate_desc *rate_desc); 875 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev); 876 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev, 877 const struct rtw89_chan *chan); 878 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 879 const struct rtw89_chan *chan); 880 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 881 const struct rtw89_txpwr_table *tbl); 882 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 883 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 884 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 885 u8 ru, u8 ntx, u8 ch); 886 887 static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev) 888 { 889 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 890 891 phy->preinit_rf_nctl(rtwdev); 892 } 893 894 static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev) 895 { 896 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 897 898 if (phy->bb_wrap_init) 899 phy->bb_wrap_init(rtwdev); 900 } 901 902 void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev, 903 enum rtw89_phy_idx phy_idx); 904 void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev, 905 const struct rtw89_chan *chan, 906 enum rtw89_phy_idx phy_idx); 907 908 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) 909 { 910 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 911 912 if (phy->ch_info_init) 913 phy->ch_info_init(rtwdev); 914 } 915 916 static inline 917 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 918 const struct rtw89_chan *chan, 919 enum rtw89_phy_idx phy_idx) 920 { 921 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 922 923 phy->set_txpwr_byrate(rtwdev, chan, phy_idx); 924 } 925 926 static inline 927 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 928 const struct rtw89_chan *chan, 929 enum rtw89_phy_idx phy_idx) 930 { 931 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 932 933 phy->set_txpwr_offset(rtwdev, chan, phy_idx); 934 } 935 936 static inline 937 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 938 const struct rtw89_chan *chan, 939 enum rtw89_phy_idx phy_idx) 940 { 941 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 942 943 phy->set_txpwr_limit(rtwdev, chan, phy_idx); 944 } 945 946 static inline 947 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 948 const struct rtw89_chan *chan, 949 enum rtw89_phy_idx phy_idx) 950 { 951 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 952 953 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); 954 } 955 956 static inline s8 rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_rf) 957 { 958 const struct rtw89_chip_info *chip = rtwdev->chip; 959 960 return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf); 961 } 962 963 static inline s8 rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_bb) 964 { 965 const struct rtw89_chip_info *chip = rtwdev->chip; 966 967 return txpwr_bb >> (chip->txpwr_factor_bb - chip->txpwr_factor_rf); 968 } 969 970 static inline s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 971 { 972 const struct rtw89_chip_info *chip = rtwdev->chip; 973 974 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 975 } 976 977 static inline s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm) 978 { 979 const struct rtw89_chip_info *chip = rtwdev->chip; 980 981 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63); 982 } 983 984 static inline s16 rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_mac) 985 { 986 const struct rtw89_chip_info *chip = rtwdev->chip; 987 988 return txpwr_mac << (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 989 } 990 991 static inline s16 rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_mac) 992 { 993 const struct rtw89_chip_info *chip = rtwdev->chip; 994 995 return txpwr_mac << (chip->txpwr_factor_bb - chip->txpwr_factor_mac); 996 } 997 998 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link); 999 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 1000 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 1001 u32 changed); 1002 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev, 1003 struct rtw89_sta_link *rtwsta_link, 1004 u32 changed); 1005 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 1006 struct ieee80211_vif *vif, 1007 const struct cfg80211_bitrate_mask *mask); 1008 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); 1009 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1010 u32 len, u8 class, u8 func); 1011 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 1012 enum rtw89_phy_idx phy_idx, 1013 unsigned int ms); 1014 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 1015 enum rtw89_phy_idx phy_idx, 1016 const struct rtw89_chan *chan, 1017 enum rtw89_tssi_mode tssi_mode, 1018 unsigned int ms); 1019 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 1020 enum rtw89_phy_idx phy_idx, 1021 const struct rtw89_chan *chan, 1022 unsigned int ms); 1023 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 1024 enum rtw89_phy_idx phy_idx, 1025 const struct rtw89_chan *chan, 1026 unsigned int ms); 1027 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 1028 enum rtw89_phy_idx phy_idx, 1029 const struct rtw89_chan *chan, 1030 unsigned int ms); 1031 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 1032 enum rtw89_phy_idx phy_idx, 1033 const struct rtw89_chan *chan, 1034 unsigned int ms); 1035 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 1036 enum rtw89_phy_idx phy_idx, 1037 const struct rtw89_chan *chan, 1038 bool is_chl_k, unsigned int ms); 1039 int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, 1040 enum rtw89_phy_idx phy_idx, 1041 const struct rtw89_chan *chan, 1042 unsigned int ms); 1043 int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev, 1044 enum rtw89_phy_idx phy_idx, 1045 const struct rtw89_chan *chan, 1046 unsigned int ms); 1047 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 1048 enum rtw89_phy_idx phy, 1049 const struct rtw89_chan *chan, 1050 struct rtw89_h2c_rf_tssi *h2c); 1051 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 1052 enum rtw89_phy_idx phy, 1053 const struct rtw89_chan *chan, 1054 struct rtw89_h2c_rf_tssi *h2c); 1055 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 1056 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work); 1057 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 1058 struct rtw89_rx_phy_ppdu *phy_ppdu); 1059 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 1060 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 1061 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1062 u32 val); 1063 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb); 1064 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 1065 void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev); 1066 void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore); 1067 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 1068 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 1069 struct rtw89_rx_phy_ppdu *phy_ppdu); 1070 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 1071 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work); 1072 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, 1073 struct rtw89_vif_link *rtwvif_link); 1074 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 1075 enum rtw89_mac_idx mac_idx, 1076 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 1077 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1078 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 1079 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 1080 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 1081 u8 *ch, enum nl80211_band *band); 1082 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, 1083 struct rtw89_bb_ctx *bb, bool scan); 1084 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev); 1085 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb); 1086 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 1087 enum rtw89_phy_idx phy_idx); 1088 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 1089 enum rtw89_phy_idx phy_idx); 1090 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 1091 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 1092 const struct rtw89_chan *target_chan); 1093 void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev); 1094 void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band, 1095 u16 ch_hw_value); 1096 void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev); 1097 1098 #endif 1099