1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_BBMCU_ADDR_OFFSET 0x30000 11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 12 13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 14 #define PHY_HEADLINE_VALID 0xf 15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 17 FIELD_PREP(GENMASK(7, 0), cv)) 18 19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 24 #define PHY_COND_BRANCH_IF 0x8 25 #define PHY_COND_BRANCH_ELIF 0x9 26 #define PHY_COND_BRANCH_ELSE 0xa 27 #define PHY_COND_BRANCH_END 0xb 28 #define PHY_COND_CHECK 0x4 29 #define PHY_COND_DONT_CARE 0xff 30 31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 33 #define RA_MASK_SUBCCK_RATES 0x5ULL 34 #define RA_MASK_SUBOFDM_RATES 0x10ULL 35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 50 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12) 51 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28) 52 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44) 53 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60) 54 #define RA_MASK_EHT_1SS_MCS0_11 GENMASK_ULL(23, 12) 55 #define RA_MASK_EHT_2SS_MCS0_11 GENMASK_ULL(39, 28) 56 #define RA_MASK_EHT_3SS_MCS0_11 GENMASK_ULL(55, 44) 57 #define RA_MASK_EHT_4SS_MCS0_11 GENMASK_ULL(62, 60) 58 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12) 59 60 #define CFO_TRK_ENABLE_TH (2 << 2) 61 #define CFO_TRK_STOP_TH_4 (30 << 2) 62 #define CFO_TRK_STOP_TH_3 (20 << 2) 63 #define CFO_TRK_STOP_TH_2 (10 << 2) 64 #define CFO_TRK_STOP_TH_1 (03 << 2) 65 #define CFO_TRK_STOP_TH (2 << 2) 66 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 67 #define CFO_PERIOD_CNT 15 68 #define CFO_BOUND 64 69 #define CFO_TP_UPPER 100 70 #define CFO_TP_LOWER 50 71 #define CFO_COMP_PERIOD 250 72 #define CFO_COMP_WEIGHT 8 73 #define MAX_CFO_TOLERANCE 30 74 #define CFO_TF_CNT_TH 300 75 76 #define UL_TB_TF_CNT_L2H_TH 100 77 #define UL_TB_TF_CNT_H2L_TH 70 78 79 #define ANTDIV_TRAINNING_CNT 2 80 #define ANTDIV_TRAINNING_INTVL 30 81 #define ANTDIV_DELAY 110 82 #define ANTDIV_TP_DIFF_TH_HIGH 100 83 #define ANTDIV_TP_DIFF_TH_LOW 5 84 #define ANTDIV_EVM_DIFF_TH 8 85 #define ANTDIV_RSSI_DIFF_TH 3 86 87 #define CCX_MAX_PERIOD 2097 88 #define CCX_MAX_PERIOD_UNIT 32 89 #define MS_TO_4US_RATIO 250 90 #define ENV_MNTR_FAIL_DWORD 0xffffffff 91 #define ENV_MNTR_IFSCLM_HIS_MAX 127 92 #define PERMIL 1000 93 #define PERCENT 100 94 #define IFS_CLM_TH0_UPPER 64 95 #define IFS_CLM_TH_MUL 4 96 #define IFS_CLM_TH_START_IDX 0 97 98 #define TIA0_GAIN_A 12 99 #define TIA0_GAIN_G 16 100 #define LNA0_GAIN (-24) 101 #define U4_MAX_BIT 3 102 #define U8_MAX_BIT 7 103 #define DIG_GAIN_SHIFT 2 104 #define DIG_GAIN 8 105 106 #define LNA_IDX_MAX 6 107 #define LNA_IDX_MIN 0 108 #define TIA_IDX_MAX 1 109 #define TIA_IDX_MIN 0 110 #define RXB_IDX_MAX 31 111 #define RXB_IDX_MIN 0 112 113 #define IGI_RSSI_MAX 110 114 #define PD_TH_MAX_RSSI 70 115 #define PD_TH_MIN_RSSI 8 116 #define CCKPD_TH_MIN_RSSI (-18) 117 #define PD_TH_BW160_CMP_VAL 9 118 #define PD_TH_BW80_CMP_VAL 6 119 #define PD_TH_BW40_CMP_VAL 3 120 #define PD_TH_BW20_CMP_VAL 0 121 #define PD_TH_CMP_VAL 3 122 #define PD_TH_SB_FLTR_CMP_VAL 7 123 124 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 125 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 126 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 127 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 128 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 129 130 #define EDCCA_MAX 249 131 #define EDCCA_TH_L2H_LB 66 132 #define EDCCA_TH_REF 3 133 #define EDCCA_HL_DIFF_NORMAL 8 134 #define RSSI_UNIT_CONVER 110 135 #define EDCCA_UNIT_CONVER 128 136 #define EDCCA_PWROFST_DEFAULT 18 137 138 enum rtw89_phy_c2h_ra_func { 139 RTW89_PHY_C2H_FUNC_STS_RPT, 140 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 141 RTW89_PHY_C2H_FUNC_TXSTS, 142 RTW89_PHY_C2H_FUNC_RA_MAX, 143 }; 144 145 enum rtw89_phy_c2h_rfk_log_func { 146 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0, 147 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1, 148 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2, 149 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3, 150 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, 151 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, 152 153 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, 154 }; 155 156 enum rtw89_phy_c2h_rfk_report_func { 157 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0, 158 RTW89_PHY_C2H_RFK_LOG_TAS_PWR = 6, 159 }; 160 161 enum rtw89_phy_c2h_dm_func { 162 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 163 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 164 RTW89_PHY_C2H_DM_FUNC_SIGB, 165 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 166 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 167 RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc, 168 RTW89_PHY_C2H_DM_FUNC_NUM, 169 }; 170 171 enum rtw89_phy_c2h_class { 172 RTW89_PHY_C2H_CLASS_RUA, 173 RTW89_PHY_C2H_CLASS_RA, 174 RTW89_PHY_C2H_CLASS_DM, 175 RTW89_PHY_C2H_RFK_LOG = 0x8, 176 RTW89_PHY_C2H_RFK_REPORT = 0x9, 177 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 178 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 179 RTW89_PHY_C2H_CLASS_MAX, 180 }; 181 182 enum rtw89_env_monitor_result_level { 183 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 184 RTW89_PHY_ENV_MON_NHM = BIT(0), 185 RTW89_PHY_ENV_MON_CLM = BIT(1), 186 RTW89_PHY_ENV_MON_FAHM = BIT(2), 187 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 188 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 189 }; 190 191 #define CCX_US_BASE_RATIO 4 192 enum rtw89_ccx_unit { 193 RTW89_CCX_4_US = 0, 194 RTW89_CCX_8_US = 1, 195 RTW89_CCX_16_US = 2, 196 RTW89_CCX_32_US = 3 197 }; 198 199 enum rtw89_phy_status_ie_type { 200 RTW89_PHYSTS_IE00_CMN_CCK = 0, 201 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 202 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 203 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 204 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 205 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 206 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 207 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 208 RTW89_PHYSTS_IE08_FTR_CH = 8, 209 RTW89_PHYSTS_IE09_FTR_0 = 9, 210 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 211 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 212 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 213 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 214 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 215 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 216 RTW89_PHYSTS_IE16_RSVD16 = 16, 217 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 218 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 219 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 220 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 221 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 222 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 223 RTW89_PHYSTS_IE23_RSVD23 = 23, 224 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 225 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 226 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 227 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 228 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 229 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 230 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 231 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 232 233 /* keep last */ 234 RTW89_PHYSTS_IE_NUM, 235 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 236 }; 237 238 enum rtw89_phy_status_bitmap { 239 RTW89_TD_SEARCH_FAIL = 0, 240 RTW89_BRK_BY_TX_PKT = 1, 241 RTW89_CCA_SPOOF = 2, 242 RTW89_OFDM_BRK = 3, 243 RTW89_CCK_BRK = 4, 244 RTW89_DL_MU_SPOOFING = 5, 245 RTW89_HE_MU = 6, 246 RTW89_VHT_MU = 7, 247 RTW89_UL_TB_SPOOFING = 8, 248 RTW89_RSVD_9 = 9, 249 RTW89_TRIG_BASE_PPDU = 10, 250 RTW89_CCK_PKT = 11, 251 RTW89_LEGACY_OFDM_PKT = 12, 252 RTW89_HT_PKT = 13, 253 RTW89_VHT_PKT = 14, 254 RTW89_HE_PKT = 15, 255 256 RTW89_PHYSTS_BITMAP_NUM 257 }; 258 259 enum rtw89_dig_gain_type { 260 RTW89_DIG_GAIN_LNA_G = 0, 261 RTW89_DIG_GAIN_TIA_G = 1, 262 RTW89_DIG_GAIN_LNA_A = 2, 263 RTW89_DIG_GAIN_TIA_A = 3, 264 RTW89_DIG_GAIN_MAX = 4 265 }; 266 267 enum rtw89_dig_gain_lna_idx { 268 RTW89_DIG_GAIN_LNA_IDX1 = 1, 269 RTW89_DIG_GAIN_LNA_IDX2 = 2, 270 RTW89_DIG_GAIN_LNA_IDX3 = 3, 271 RTW89_DIG_GAIN_LNA_IDX4 = 4, 272 RTW89_DIG_GAIN_LNA_IDX5 = 5, 273 RTW89_DIG_GAIN_LNA_IDX6 = 6 274 }; 275 276 enum rtw89_dig_gain_tia_idx { 277 RTW89_DIG_GAIN_TIA_IDX0 = 0, 278 RTW89_DIG_GAIN_TIA_IDX1 = 1 279 }; 280 281 enum rtw89_tssi_bandedge_cfg { 282 RTW89_TSSI_BANDEDGE_FLAT, 283 RTW89_TSSI_BANDEDGE_LOW, 284 RTW89_TSSI_BANDEDGE_MID, 285 RTW89_TSSI_BANDEDGE_HIGH, 286 287 RTW89_TSSI_CFG_NUM, 288 }; 289 290 enum rtw89_tssi_sbw_idx { 291 RTW89_TSSI_SBW20, 292 RTW89_TSSI_SBW40_0, 293 RTW89_TSSI_SBW40_1, 294 RTW89_TSSI_SBW80_0, 295 RTW89_TSSI_SBW80_1, 296 RTW89_TSSI_SBW80_2, 297 RTW89_TSSI_SBW80_3, 298 RTW89_TSSI_SBW160_0, 299 RTW89_TSSI_SBW160_1, 300 RTW89_TSSI_SBW160_2, 301 RTW89_TSSI_SBW160_3, 302 RTW89_TSSI_SBW160_4, 303 RTW89_TSSI_SBW160_5, 304 RTW89_TSSI_SBW160_6, 305 RTW89_TSSI_SBW160_7, 306 307 RTW89_TSSI_SBW_NUM, 308 }; 309 310 struct rtw89_txpwr_byrate_cfg { 311 enum rtw89_band band; 312 enum rtw89_nss nss; 313 enum rtw89_rate_section rs; 314 u8 shf; 315 u8 len; 316 u32 data; 317 }; 318 319 struct rtw89_txpwr_track_cfg { 320 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 321 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 322 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 323 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 324 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 325 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 326 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 327 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 328 const s8 *delta_swingidx_2gb_n; 329 const s8 *delta_swingidx_2gb_p; 330 const s8 *delta_swingidx_2ga_n; 331 const s8 *delta_swingidx_2ga_p; 332 const s8 *delta_swingidx_2g_cck_b_n; 333 const s8 *delta_swingidx_2g_cck_b_p; 334 const s8 *delta_swingidx_2g_cck_a_n; 335 const s8 *delta_swingidx_2g_cck_a_p; 336 }; 337 338 struct rtw89_phy_dig_gain_cfg { 339 const struct rtw89_reg_def *table; 340 u8 size; 341 }; 342 343 struct rtw89_phy_dig_gain_table { 344 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 345 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 346 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 347 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 348 }; 349 350 struct rtw89_phy_tssi_dbw_table { 351 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 352 }; 353 354 struct rtw89_phy_reg3_tbl { 355 const struct rtw89_reg3_def *reg3; 356 int size; 357 }; 358 359 #define DECLARE_PHY_REG3_TBL(_name) \ 360 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 361 .reg3 = _name, \ 362 .size = ARRAY_SIZE(_name), \ 363 } 364 365 struct rtw89_nbi_reg_def { 366 struct rtw89_reg_def notch1_idx; 367 struct rtw89_reg_def notch1_frac_idx; 368 struct rtw89_reg_def notch1_en; 369 struct rtw89_reg_def notch2_idx; 370 struct rtw89_reg_def notch2_frac_idx; 371 struct rtw89_reg_def notch2_en; 372 }; 373 374 struct rtw89_ccx_regs { 375 u32 setting_addr; 376 u32 edcca_opt_mask; 377 u32 measurement_trig_mask; 378 u32 trig_opt_mask; 379 u32 en_mask; 380 u32 ifs_cnt_addr; 381 u32 ifs_clm_period_mask; 382 u32 ifs_clm_cnt_unit_mask; 383 u32 ifs_clm_cnt_clear_mask; 384 u32 ifs_collect_en_mask; 385 u32 ifs_t1_addr; 386 u32 ifs_t1_th_h_mask; 387 u32 ifs_t1_en_mask; 388 u32 ifs_t1_th_l_mask; 389 u32 ifs_t2_addr; 390 u32 ifs_t2_th_h_mask; 391 u32 ifs_t2_en_mask; 392 u32 ifs_t2_th_l_mask; 393 u32 ifs_t3_addr; 394 u32 ifs_t3_th_h_mask; 395 u32 ifs_t3_en_mask; 396 u32 ifs_t3_th_l_mask; 397 u32 ifs_t4_addr; 398 u32 ifs_t4_th_h_mask; 399 u32 ifs_t4_en_mask; 400 u32 ifs_t4_th_l_mask; 401 u32 ifs_clm_tx_cnt_addr; 402 u32 ifs_clm_edcca_excl_cca_fa_mask; 403 u32 ifs_clm_tx_cnt_msk; 404 u32 ifs_clm_cca_addr; 405 u32 ifs_clm_ofdmcca_excl_fa_mask; 406 u32 ifs_clm_cckcca_excl_fa_mask; 407 u32 ifs_clm_fa_addr; 408 u32 ifs_clm_ofdm_fa_mask; 409 u32 ifs_clm_cck_fa_mask; 410 u32 ifs_his_addr; 411 u32 ifs_t4_his_mask; 412 u32 ifs_t3_his_mask; 413 u32 ifs_t2_his_mask; 414 u32 ifs_t1_his_mask; 415 u32 ifs_avg_l_addr; 416 u32 ifs_t2_avg_mask; 417 u32 ifs_t1_avg_mask; 418 u32 ifs_avg_h_addr; 419 u32 ifs_t4_avg_mask; 420 u32 ifs_t3_avg_mask; 421 u32 ifs_cca_l_addr; 422 u32 ifs_t2_cca_mask; 423 u32 ifs_t1_cca_mask; 424 u32 ifs_cca_h_addr; 425 u32 ifs_t4_cca_mask; 426 u32 ifs_t3_cca_mask; 427 u32 ifs_total_addr; 428 u32 ifs_cnt_done_mask; 429 u32 ifs_total_mask; 430 }; 431 432 struct rtw89_physts_regs { 433 u32 setting_addr; 434 u32 dis_trigger_fail_mask; 435 u32 dis_trigger_brk_mask; 436 }; 437 438 struct rtw89_cfo_regs { 439 u32 comp; 440 u32 weighting_mask; 441 u32 comp_seg0; 442 u32 valid_0_mask; 443 }; 444 445 enum rtw89_bandwidth_section_num_ax { 446 RTW89_BW20_SEC_NUM_AX = 8, 447 RTW89_BW40_SEC_NUM_AX = 4, 448 RTW89_BW80_SEC_NUM_AX = 2, 449 }; 450 451 enum rtw89_bandwidth_section_num_be { 452 RTW89_BW20_SEC_NUM_BE = 16, 453 RTW89_BW40_SEC_NUM_BE = 8, 454 RTW89_BW80_SEC_NUM_BE = 4, 455 RTW89_BW160_SEC_NUM_BE = 2, 456 }; 457 458 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 459 460 struct rtw89_txpwr_limit_ax { 461 s8 cck_20m[RTW89_BF_NUM]; 462 s8 cck_40m[RTW89_BF_NUM]; 463 s8 ofdm[RTW89_BF_NUM]; 464 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; 465 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; 466 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; 467 s8 mcs_160m[RTW89_BF_NUM]; 468 s8 mcs_40m_0p5[RTW89_BF_NUM]; 469 s8 mcs_40m_2p5[RTW89_BF_NUM]; 470 }; 471 472 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 473 474 struct rtw89_txpwr_limit_be { 475 s8 cck_20m[RTW89_BF_NUM]; 476 s8 cck_40m[RTW89_BF_NUM]; 477 s8 ofdm[RTW89_BF_NUM]; 478 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; 479 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; 480 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; 481 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; 482 s8 mcs_320m[RTW89_BF_NUM]; 483 s8 mcs_40m_0p5[RTW89_BF_NUM]; 484 s8 mcs_40m_2p5[RTW89_BF_NUM]; 485 s8 mcs_40m_4p5[RTW89_BF_NUM]; 486 s8 mcs_40m_6p5[RTW89_BF_NUM]; 487 }; 488 489 #define RTW89_RU_SEC_NUM_AX 8 490 491 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 492 493 struct rtw89_txpwr_limit_ru_ax { 494 s8 ru26[RTW89_RU_SEC_NUM_AX]; 495 s8 ru52[RTW89_RU_SEC_NUM_AX]; 496 s8 ru106[RTW89_RU_SEC_NUM_AX]; 497 }; 498 499 #define RTW89_RU_SEC_NUM_BE 16 500 501 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 502 503 struct rtw89_txpwr_limit_ru_be { 504 s8 ru26[RTW89_RU_SEC_NUM_BE]; 505 s8 ru52[RTW89_RU_SEC_NUM_BE]; 506 s8 ru106[RTW89_RU_SEC_NUM_BE]; 507 s8 ru52_26[RTW89_RU_SEC_NUM_BE]; 508 s8 ru106_26[RTW89_RU_SEC_NUM_BE]; 509 }; 510 511 struct rtw89_phy_rfk_log_fmt { 512 const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM]; 513 }; 514 515 struct rtw89_phy_gen_def { 516 u32 cr_base; 517 const struct rtw89_ccx_regs *ccx; 518 const struct rtw89_physts_regs *physts; 519 const struct rtw89_cfo_regs *cfo; 520 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr); 521 void (*config_bb_gain)(struct rtw89_dev *rtwdev, 522 const struct rtw89_reg2_def *reg, 523 enum rtw89_rf_path rf_path, 524 void *extra_data); 525 void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev); 526 void (*bb_wrap_init)(struct rtw89_dev *rtwdev); 527 void (*ch_info_init)(struct rtw89_dev *rtwdev); 528 529 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, 530 const struct rtw89_chan *chan, 531 enum rtw89_phy_idx phy_idx); 532 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, 533 const struct rtw89_chan *chan, 534 enum rtw89_phy_idx phy_idx); 535 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, 536 const struct rtw89_chan *chan, 537 enum rtw89_phy_idx phy_idx); 538 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, 539 const struct rtw89_chan *chan, 540 enum rtw89_phy_idx phy_idx); 541 }; 542 543 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 544 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 545 546 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 547 u32 addr, u8 data) 548 { 549 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 550 551 rtw89_write8(rtwdev, addr + phy->cr_base, data); 552 } 553 554 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 555 u32 addr, u16 data) 556 { 557 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 558 559 rtw89_write16(rtwdev, addr + phy->cr_base, data); 560 } 561 562 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 563 u32 addr, u32 data) 564 { 565 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 566 567 rtw89_write32(rtwdev, addr + phy->cr_base, data); 568 } 569 570 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 571 u32 addr, u32 bits) 572 { 573 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 574 575 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 576 } 577 578 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 579 u32 addr, u32 bits) 580 { 581 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 582 583 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 584 } 585 586 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 587 u32 addr, u32 mask, u32 data) 588 { 589 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 590 591 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 592 } 593 594 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 595 { 596 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 597 598 return rtw89_read8(rtwdev, addr + phy->cr_base); 599 } 600 601 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 602 { 603 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 604 605 return rtw89_read16(rtwdev, addr + phy->cr_base); 606 } 607 608 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 609 { 610 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 611 612 return rtw89_read32(rtwdev, addr + phy->cr_base); 613 } 614 615 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 616 u32 addr, u32 mask) 617 { 618 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 619 620 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 621 } 622 623 static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev, 624 u32 addr, u32 data, enum rtw89_phy_idx phy_idx) 625 { 626 if (phy_idx && addr < 0x10000) 627 addr += 0x20000; 628 629 rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data); 630 } 631 632 static inline 633 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 634 { 635 switch (subband) { 636 default: 637 case RTW89_CH_2G: 638 return RTW89_GAIN_OFFSET_2G_OFDM; 639 case RTW89_CH_5G_BAND_1: 640 return RTW89_GAIN_OFFSET_5G_LOW; 641 case RTW89_CH_5G_BAND_3: 642 return RTW89_GAIN_OFFSET_5G_MID; 643 case RTW89_CH_5G_BAND_4: 644 return RTW89_GAIN_OFFSET_5G_HIGH; 645 case RTW89_CH_6G_BAND_IDX0: 646 return RTW89_GAIN_OFFSET_6G_L0; 647 case RTW89_CH_6G_BAND_IDX1: 648 return RTW89_GAIN_OFFSET_6G_L1; 649 case RTW89_CH_6G_BAND_IDX2: 650 return RTW89_GAIN_OFFSET_6G_M0; 651 case RTW89_CH_6G_BAND_IDX3: 652 return RTW89_GAIN_OFFSET_6G_M1; 653 case RTW89_CH_6G_BAND_IDX4: 654 return RTW89_GAIN_OFFSET_6G_H0; 655 case RTW89_CH_6G_BAND_IDX5: 656 return RTW89_GAIN_OFFSET_6G_H1; 657 case RTW89_CH_6G_BAND_IDX6: 658 return RTW89_GAIN_OFFSET_6G_UH0; 659 case RTW89_CH_6G_BAND_IDX7: 660 return RTW89_GAIN_OFFSET_6G_UH1; 661 } 662 } 663 664 static inline 665 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 666 { 667 switch (subband) { 668 default: 669 case RTW89_CH_2G: 670 return RTW89_BB_GAIN_BAND_2G; 671 case RTW89_CH_5G_BAND_1: 672 return RTW89_BB_GAIN_BAND_5G_L; 673 case RTW89_CH_5G_BAND_3: 674 return RTW89_BB_GAIN_BAND_5G_M; 675 case RTW89_CH_5G_BAND_4: 676 return RTW89_BB_GAIN_BAND_5G_H; 677 case RTW89_CH_6G_BAND_IDX0: 678 case RTW89_CH_6G_BAND_IDX1: 679 return RTW89_BB_GAIN_BAND_6G_L; 680 case RTW89_CH_6G_BAND_IDX2: 681 case RTW89_CH_6G_BAND_IDX3: 682 return RTW89_BB_GAIN_BAND_6G_M; 683 case RTW89_CH_6G_BAND_IDX4: 684 case RTW89_CH_6G_BAND_IDX5: 685 return RTW89_BB_GAIN_BAND_6G_H; 686 case RTW89_CH_6G_BAND_IDX6: 687 case RTW89_CH_6G_BAND_IDX7: 688 return RTW89_BB_GAIN_BAND_6G_UH; 689 } 690 } 691 692 static inline 693 enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband) 694 { 695 switch (subband) { 696 default: 697 case RTW89_CH_2G: 698 return RTW89_BB_GAIN_BAND_2G_BE; 699 case RTW89_CH_5G_BAND_1: 700 return RTW89_BB_GAIN_BAND_5G_L_BE; 701 case RTW89_CH_5G_BAND_3: 702 return RTW89_BB_GAIN_BAND_5G_M_BE; 703 case RTW89_CH_5G_BAND_4: 704 return RTW89_BB_GAIN_BAND_5G_H_BE; 705 case RTW89_CH_6G_BAND_IDX0: 706 return RTW89_BB_GAIN_BAND_6G_L0_BE; 707 case RTW89_CH_6G_BAND_IDX1: 708 return RTW89_BB_GAIN_BAND_6G_L1_BE; 709 case RTW89_CH_6G_BAND_IDX2: 710 return RTW89_BB_GAIN_BAND_6G_M0_BE; 711 case RTW89_CH_6G_BAND_IDX3: 712 return RTW89_BB_GAIN_BAND_6G_M1_BE; 713 case RTW89_CH_6G_BAND_IDX4: 714 return RTW89_BB_GAIN_BAND_6G_H0_BE; 715 case RTW89_CH_6G_BAND_IDX5: 716 return RTW89_BB_GAIN_BAND_6G_H1_BE; 717 case RTW89_CH_6G_BAND_IDX6: 718 return RTW89_BB_GAIN_BAND_6G_UH0_BE; 719 case RTW89_CH_6G_BAND_IDX7: 720 return RTW89_BB_GAIN_BAND_6G_UH1_BE; 721 } 722 } 723 724 struct rtw89_rfk_chan_desc { 725 /* desc is valid iff ch is non-zero */ 726 u8 ch; 727 728 /* To avoid us from extending old chip code every time, each new 729 * field must be defined along with a bool flag in positivte way. 730 */ 731 bool has_band; 732 u8 band; 733 bool has_bw; 734 u8 bw; 735 }; 736 737 enum rtw89_rfk_flag { 738 RTW89_RFK_F_WRF = 0, 739 RTW89_RFK_F_WM = 1, 740 RTW89_RFK_F_WS = 2, 741 RTW89_RFK_F_WC = 3, 742 RTW89_RFK_F_DELAY = 4, 743 RTW89_RFK_F_NUM, 744 }; 745 746 struct rtw89_rfk_tbl { 747 const struct rtw89_reg5_def *defs; 748 u32 size; 749 }; 750 751 #define RTW89_DECLARE_RFK_TBL(_name) \ 752 const struct rtw89_rfk_tbl _name ## _tbl = { \ 753 .defs = _name, \ 754 .size = ARRAY_SIZE(_name), \ 755 } 756 757 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 758 {.flag = RTW89_RFK_F_WRF, \ 759 .path = _path, \ 760 .addr = _addr, \ 761 .mask = _mask, \ 762 .data = _data,} 763 764 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 765 {.flag = RTW89_RFK_F_WM, \ 766 .addr = _addr, \ 767 .mask = _mask, \ 768 .data = _data,} 769 770 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 771 {.flag = RTW89_RFK_F_WS, \ 772 .addr = _addr, \ 773 .mask = _mask,} 774 775 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 776 {.flag = RTW89_RFK_F_WC, \ 777 .addr = _addr, \ 778 .mask = _mask,} 779 780 #define RTW89_DECL_RFK_DELAY(_data) \ 781 {.flag = RTW89_RFK_F_DELAY, \ 782 .data = _data,} 783 784 void 785 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 786 787 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 788 do { \ 789 typeof(dev) __dev = (dev); \ 790 if (cond) \ 791 rtw89_rfk_parser(__dev, (tbl_t)); \ 792 else \ 793 rtw89_rfk_parser(__dev, (tbl_f)); \ 794 } while (0) 795 796 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 797 const struct rtw89_phy_reg3_tbl *tbl); 798 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 799 const struct rtw89_chan *chan, 800 enum rtw89_bandwidth dbw); 801 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 802 enum rtw89_bandwidth dbw); 803 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 804 u32 addr, u32 mask); 805 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 806 u32 addr, u32 mask); 807 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 808 u32 addr, u32 mask); 809 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 810 u32 addr, u32 mask, u32 data); 811 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 812 u32 addr, u32 mask, u32 data); 813 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 814 u32 addr, u32 mask, u32 data); 815 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 816 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 817 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 818 const struct rtw89_reg2_def *reg, 819 enum rtw89_rf_path rf_path, 820 void *extra_data); 821 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 822 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev); 823 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 824 u32 data, enum rtw89_phy_idx phy_idx); 825 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 826 enum rtw89_phy_idx phy_idx); 827 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 828 enum rtw89_phy_idx phy_idx); 829 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 830 enum rtw89_phy_idx phy_idx); 831 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 832 struct rtw89_txpwr_byrate *head, 833 const struct rtw89_rate_desc *desc); 834 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 835 const struct rtw89_rate_desc *rate_desc); 836 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev); 837 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev, 838 const struct rtw89_chan *chan); 839 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 840 const struct rtw89_chan *chan); 841 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 842 const struct rtw89_txpwr_table *tbl); 843 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 844 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 845 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 846 u8 ru, u8 ntx, u8 ch); 847 848 static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev) 849 { 850 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 851 852 phy->preinit_rf_nctl(rtwdev); 853 } 854 855 static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev) 856 { 857 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 858 859 if (phy->bb_wrap_init) 860 phy->bb_wrap_init(rtwdev); 861 } 862 863 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) 864 { 865 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 866 867 if (phy->ch_info_init) 868 phy->ch_info_init(rtwdev); 869 } 870 871 static inline 872 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 873 const struct rtw89_chan *chan, 874 enum rtw89_phy_idx phy_idx) 875 { 876 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 877 878 phy->set_txpwr_byrate(rtwdev, chan, phy_idx); 879 } 880 881 static inline 882 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 883 const struct rtw89_chan *chan, 884 enum rtw89_phy_idx phy_idx) 885 { 886 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 887 888 phy->set_txpwr_offset(rtwdev, chan, phy_idx); 889 } 890 891 static inline 892 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 893 const struct rtw89_chan *chan, 894 enum rtw89_phy_idx phy_idx) 895 { 896 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 897 898 phy->set_txpwr_limit(rtwdev, chan, phy_idx); 899 } 900 901 static inline 902 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 903 const struct rtw89_chan *chan, 904 enum rtw89_phy_idx phy_idx) 905 { 906 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 907 908 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); 909 } 910 911 static inline s8 rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_rf) 912 { 913 const struct rtw89_chip_info *chip = rtwdev->chip; 914 915 return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf); 916 } 917 918 static inline s8 rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_bb) 919 { 920 const struct rtw89_chip_info *chip = rtwdev->chip; 921 922 return txpwr_bb >> (chip->txpwr_factor_bb - chip->txpwr_factor_rf); 923 } 924 925 static inline s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 926 { 927 const struct rtw89_chip_info *chip = rtwdev->chip; 928 929 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 930 } 931 932 static inline s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm) 933 { 934 const struct rtw89_chip_info *chip = rtwdev->chip; 935 936 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63); 937 } 938 939 static inline s16 rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_mac) 940 { 941 const struct rtw89_chip_info *chip = rtwdev->chip; 942 943 return txpwr_mac << (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 944 } 945 946 static inline s16 rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_mac) 947 { 948 const struct rtw89_chip_info *chip = rtwdev->chip; 949 950 return txpwr_mac << (chip->txpwr_factor_bb - chip->txpwr_factor_mac); 951 } 952 953 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link); 954 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 955 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 956 u32 changed); 957 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev, 958 struct rtw89_sta_link *rtwsta_link, 959 u32 changed); 960 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 961 struct ieee80211_vif *vif, 962 const struct cfg80211_bitrate_mask *mask); 963 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); 964 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 965 u32 len, u8 class, u8 func); 966 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 967 enum rtw89_phy_idx phy_idx, 968 unsigned int ms); 969 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 970 enum rtw89_phy_idx phy_idx, 971 const struct rtw89_chan *chan, 972 enum rtw89_tssi_mode tssi_mode, 973 unsigned int ms); 974 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 975 enum rtw89_phy_idx phy_idx, 976 const struct rtw89_chan *chan, 977 unsigned int ms); 978 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 979 enum rtw89_phy_idx phy_idx, 980 const struct rtw89_chan *chan, 981 unsigned int ms); 982 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 983 enum rtw89_phy_idx phy_idx, 984 const struct rtw89_chan *chan, 985 unsigned int ms); 986 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 987 enum rtw89_phy_idx phy_idx, 988 const struct rtw89_chan *chan, 989 unsigned int ms); 990 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 991 enum rtw89_phy_idx phy_idx, 992 const struct rtw89_chan *chan, 993 bool is_chl_k, unsigned int ms); 994 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 995 enum rtw89_phy_idx phy, 996 const struct rtw89_chan *chan, 997 struct rtw89_h2c_rf_tssi *h2c); 998 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 999 enum rtw89_phy_idx phy, 1000 const struct rtw89_chan *chan, 1001 struct rtw89_h2c_rf_tssi *h2c); 1002 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 1003 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work); 1004 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 1005 struct rtw89_rx_phy_ppdu *phy_ppdu); 1006 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 1007 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 1008 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1009 u32 val); 1010 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb); 1011 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 1012 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 1013 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 1014 struct rtw89_rx_phy_ppdu *phy_ppdu); 1015 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 1016 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work); 1017 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, 1018 struct rtw89_vif_link *rtwvif_link); 1019 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 1020 enum rtw89_mac_idx mac_idx, 1021 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 1022 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1023 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 1024 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 1025 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 1026 u8 *ch, enum nl80211_band *band); 1027 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, 1028 struct rtw89_bb_ctx *bb, bool scan); 1029 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev); 1030 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb); 1031 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 1032 enum rtw89_phy_idx phy_idx); 1033 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 1034 enum rtw89_phy_idx phy_idx); 1035 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 1036 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 1037 const struct rtw89_chan *target_chan); 1038 1039 #endif 1040