1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 11 12 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 13 #define PHY_HEADLINE_VALID 0xf 14 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 15 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 16 FIELD_PREP(GENMASK(7, 0), cv)) 17 18 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 19 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 20 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 21 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 22 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 23 #define PHY_COND_BRANCH_IF 0x8 24 #define PHY_COND_BRANCH_ELIF 0x9 25 #define PHY_COND_BRANCH_ELSE 0xa 26 #define PHY_COND_BRANCH_END 0xb 27 #define PHY_COND_CHECK 0x4 28 #define PHY_COND_DONT_CARE 0xff 29 30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 32 #define RA_MASK_SUBCCK_RATES 0x5ULL 33 #define RA_MASK_SUBOFDM_RATES 0x10ULL 34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 39 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 40 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 41 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 42 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 46 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 47 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 48 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 49 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12) 50 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28) 51 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44) 52 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60) 53 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12) 54 55 #define CFO_TRK_ENABLE_TH (2 << 2) 56 #define CFO_TRK_STOP_TH_4 (30 << 2) 57 #define CFO_TRK_STOP_TH_3 (20 << 2) 58 #define CFO_TRK_STOP_TH_2 (10 << 2) 59 #define CFO_TRK_STOP_TH_1 (00 << 2) 60 #define CFO_TRK_STOP_TH (2 << 2) 61 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 62 #define CFO_PERIOD_CNT 15 63 #define CFO_BOUND 64 64 #define CFO_TP_UPPER 100 65 #define CFO_TP_LOWER 50 66 #define CFO_COMP_PERIOD 250 67 #define CFO_COMP_WEIGHT 8 68 #define MAX_CFO_TOLERANCE 30 69 #define CFO_TF_CNT_TH 300 70 71 #define UL_TB_TF_CNT_L2H_TH 100 72 #define UL_TB_TF_CNT_H2L_TH 70 73 74 #define ANTDIV_TRAINNING_CNT 2 75 #define ANTDIV_TRAINNING_INTVL 30 76 #define ANTDIV_DELAY 110 77 #define ANTDIV_TP_DIFF_TH_HIGH 100 78 #define ANTDIV_TP_DIFF_TH_LOW 5 79 #define ANTDIV_EVM_DIFF_TH 8 80 #define ANTDIV_RSSI_DIFF_TH 3 81 82 #define CCX_MAX_PERIOD 2097 83 #define CCX_MAX_PERIOD_UNIT 32 84 #define MS_TO_4US_RATIO 250 85 #define ENV_MNTR_FAIL_DWORD 0xffffffff 86 #define ENV_MNTR_IFSCLM_HIS_MAX 127 87 #define PERMIL 1000 88 #define PERCENT 100 89 #define IFS_CLM_TH0_UPPER 64 90 #define IFS_CLM_TH_MUL 4 91 #define IFS_CLM_TH_START_IDX 0 92 93 #define TIA0_GAIN_A 12 94 #define TIA0_GAIN_G 16 95 #define LNA0_GAIN (-24) 96 #define U4_MAX_BIT 3 97 #define U8_MAX_BIT 7 98 #define DIG_GAIN_SHIFT 2 99 #define DIG_GAIN 8 100 101 #define LNA_IDX_MAX 6 102 #define LNA_IDX_MIN 0 103 #define TIA_IDX_MAX 1 104 #define TIA_IDX_MIN 0 105 #define RXB_IDX_MAX 31 106 #define RXB_IDX_MIN 0 107 108 #define IGI_RSSI_MAX 110 109 #define PD_TH_MAX_RSSI 70 110 #define PD_TH_MIN_RSSI 8 111 #define CCKPD_TH_MIN_RSSI (-18) 112 #define PD_TH_BW160_CMP_VAL 9 113 #define PD_TH_BW80_CMP_VAL 6 114 #define PD_TH_BW40_CMP_VAL 3 115 #define PD_TH_BW20_CMP_VAL 0 116 #define PD_TH_CMP_VAL 3 117 #define PD_TH_SB_FLTR_CMP_VAL 7 118 119 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 120 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 121 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 122 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 123 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 124 125 enum rtw89_phy_c2h_ra_func { 126 RTW89_PHY_C2H_FUNC_STS_RPT, 127 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 128 RTW89_PHY_C2H_FUNC_TXSTS, 129 RTW89_PHY_C2H_FUNC_RA_MAX, 130 }; 131 132 enum rtw89_phy_c2h_dm_func { 133 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 134 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 135 RTW89_PHY_C2H_DM_FUNC_SIGB, 136 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 137 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 138 RTW89_PHY_C2H_DM_FUNC_NUM, 139 }; 140 141 enum rtw89_phy_c2h_class { 142 RTW89_PHY_C2H_CLASS_RUA, 143 RTW89_PHY_C2H_CLASS_RA, 144 RTW89_PHY_C2H_CLASS_DM, 145 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 146 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 147 RTW89_PHY_C2H_CLASS_MAX, 148 }; 149 150 enum rtw89_env_monitor_result_level { 151 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 152 RTW89_PHY_ENV_MON_NHM = BIT(0), 153 RTW89_PHY_ENV_MON_CLM = BIT(1), 154 RTW89_PHY_ENV_MON_FAHM = BIT(2), 155 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 156 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 157 }; 158 159 #define CCX_US_BASE_RATIO 4 160 enum rtw89_ccx_unit { 161 RTW89_CCX_4_US = 0, 162 RTW89_CCX_8_US = 1, 163 RTW89_CCX_16_US = 2, 164 RTW89_CCX_32_US = 3 165 }; 166 167 enum rtw89_phy_status_ie_type { 168 RTW89_PHYSTS_IE00_CMN_CCK = 0, 169 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 170 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 171 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 172 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 173 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 174 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 175 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 176 RTW89_PHYSTS_IE08_FTR_CH = 8, 177 RTW89_PHYSTS_IE09_FTR_0 = 9, 178 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 179 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 180 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 181 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 182 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 183 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 184 RTW89_PHYSTS_IE16_RSVD16 = 16, 185 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 186 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 187 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 188 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 189 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 190 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 191 RTW89_PHYSTS_IE23_RSVD23 = 23, 192 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 193 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 194 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 195 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 196 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 197 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 198 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 199 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 200 201 /* keep last */ 202 RTW89_PHYSTS_IE_NUM, 203 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 204 }; 205 206 enum rtw89_phy_status_bitmap { 207 RTW89_TD_SEARCH_FAIL = 0, 208 RTW89_BRK_BY_TX_PKT = 1, 209 RTW89_CCA_SPOOF = 2, 210 RTW89_OFDM_BRK = 3, 211 RTW89_CCK_BRK = 4, 212 RTW89_DL_MU_SPOOFING = 5, 213 RTW89_HE_MU = 6, 214 RTW89_VHT_MU = 7, 215 RTW89_UL_TB_SPOOFING = 8, 216 RTW89_RSVD_9 = 9, 217 RTW89_TRIG_BASE_PPDU = 10, 218 RTW89_CCK_PKT = 11, 219 RTW89_LEGACY_OFDM_PKT = 12, 220 RTW89_HT_PKT = 13, 221 RTW89_VHT_PKT = 14, 222 RTW89_HE_PKT = 15, 223 224 RTW89_PHYSTS_BITMAP_NUM 225 }; 226 227 enum rtw89_dig_gain_type { 228 RTW89_DIG_GAIN_LNA_G = 0, 229 RTW89_DIG_GAIN_TIA_G = 1, 230 RTW89_DIG_GAIN_LNA_A = 2, 231 RTW89_DIG_GAIN_TIA_A = 3, 232 RTW89_DIG_GAIN_MAX = 4 233 }; 234 235 enum rtw89_dig_gain_lna_idx { 236 RTW89_DIG_GAIN_LNA_IDX1 = 1, 237 RTW89_DIG_GAIN_LNA_IDX2 = 2, 238 RTW89_DIG_GAIN_LNA_IDX3 = 3, 239 RTW89_DIG_GAIN_LNA_IDX4 = 4, 240 RTW89_DIG_GAIN_LNA_IDX5 = 5, 241 RTW89_DIG_GAIN_LNA_IDX6 = 6 242 }; 243 244 enum rtw89_dig_gain_tia_idx { 245 RTW89_DIG_GAIN_TIA_IDX0 = 0, 246 RTW89_DIG_GAIN_TIA_IDX1 = 1 247 }; 248 249 enum rtw89_tssi_bandedge_cfg { 250 RTW89_TSSI_BANDEDGE_FLAT, 251 RTW89_TSSI_BANDEDGE_LOW, 252 RTW89_TSSI_BANDEDGE_MID, 253 RTW89_TSSI_BANDEDGE_HIGH, 254 255 RTW89_TSSI_CFG_NUM, 256 }; 257 258 enum rtw89_tssi_sbw_idx { 259 RTW89_TSSI_SBW20, 260 RTW89_TSSI_SBW40_0, 261 RTW89_TSSI_SBW40_1, 262 RTW89_TSSI_SBW80_0, 263 RTW89_TSSI_SBW80_1, 264 RTW89_TSSI_SBW80_2, 265 RTW89_TSSI_SBW80_3, 266 RTW89_TSSI_SBW160_0, 267 RTW89_TSSI_SBW160_1, 268 RTW89_TSSI_SBW160_2, 269 RTW89_TSSI_SBW160_3, 270 RTW89_TSSI_SBW160_4, 271 RTW89_TSSI_SBW160_5, 272 RTW89_TSSI_SBW160_6, 273 RTW89_TSSI_SBW160_7, 274 275 RTW89_TSSI_SBW_NUM, 276 }; 277 278 struct rtw89_txpwr_byrate_cfg { 279 enum rtw89_band band; 280 enum rtw89_nss nss; 281 enum rtw89_rate_section rs; 282 u8 shf; 283 u8 len; 284 u32 data; 285 }; 286 287 #define DELTA_SWINGIDX_SIZE 30 288 289 struct rtw89_txpwr_track_cfg { 290 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 291 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 292 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 293 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 294 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 295 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 296 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 297 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 298 const s8 *delta_swingidx_2gb_n; 299 const s8 *delta_swingidx_2gb_p; 300 const s8 *delta_swingidx_2ga_n; 301 const s8 *delta_swingidx_2ga_p; 302 const s8 *delta_swingidx_2g_cck_b_n; 303 const s8 *delta_swingidx_2g_cck_b_p; 304 const s8 *delta_swingidx_2g_cck_a_n; 305 const s8 *delta_swingidx_2g_cck_a_p; 306 }; 307 308 struct rtw89_phy_dig_gain_cfg { 309 const struct rtw89_reg_def *table; 310 u8 size; 311 }; 312 313 struct rtw89_phy_dig_gain_table { 314 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 315 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 316 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 317 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 318 }; 319 320 struct rtw89_phy_tssi_dbw_table { 321 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 322 }; 323 324 struct rtw89_phy_reg3_tbl { 325 const struct rtw89_reg3_def *reg3; 326 int size; 327 }; 328 329 #define DECLARE_PHY_REG3_TBL(_name) \ 330 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 331 .reg3 = _name, \ 332 .size = ARRAY_SIZE(_name), \ 333 } 334 335 struct rtw89_nbi_reg_def { 336 struct rtw89_reg_def notch1_idx; 337 struct rtw89_reg_def notch1_frac_idx; 338 struct rtw89_reg_def notch1_en; 339 struct rtw89_reg_def notch2_idx; 340 struct rtw89_reg_def notch2_frac_idx; 341 struct rtw89_reg_def notch2_en; 342 }; 343 344 struct rtw89_ccx_regs { 345 u32 setting_addr; 346 u32 edcca_opt_mask; 347 u32 measurement_trig_mask; 348 u32 trig_opt_mask; 349 u32 en_mask; 350 u32 ifs_cnt_addr; 351 u32 ifs_clm_period_mask; 352 u32 ifs_clm_cnt_unit_mask; 353 u32 ifs_clm_cnt_clear_mask; 354 u32 ifs_collect_en_mask; 355 u32 ifs_t1_addr; 356 u32 ifs_t1_th_h_mask; 357 u32 ifs_t1_en_mask; 358 u32 ifs_t1_th_l_mask; 359 u32 ifs_t2_addr; 360 u32 ifs_t2_th_h_mask; 361 u32 ifs_t2_en_mask; 362 u32 ifs_t2_th_l_mask; 363 u32 ifs_t3_addr; 364 u32 ifs_t3_th_h_mask; 365 u32 ifs_t3_en_mask; 366 u32 ifs_t3_th_l_mask; 367 u32 ifs_t4_addr; 368 u32 ifs_t4_th_h_mask; 369 u32 ifs_t4_en_mask; 370 u32 ifs_t4_th_l_mask; 371 u32 ifs_clm_tx_cnt_addr; 372 u32 ifs_clm_edcca_excl_cca_fa_mask; 373 u32 ifs_clm_tx_cnt_msk; 374 u32 ifs_clm_cca_addr; 375 u32 ifs_clm_ofdmcca_excl_fa_mask; 376 u32 ifs_clm_cckcca_excl_fa_mask; 377 u32 ifs_clm_fa_addr; 378 u32 ifs_clm_ofdm_fa_mask; 379 u32 ifs_clm_cck_fa_mask; 380 u32 ifs_his_addr; 381 u32 ifs_t4_his_mask; 382 u32 ifs_t3_his_mask; 383 u32 ifs_t2_his_mask; 384 u32 ifs_t1_his_mask; 385 u32 ifs_avg_l_addr; 386 u32 ifs_t2_avg_mask; 387 u32 ifs_t1_avg_mask; 388 u32 ifs_avg_h_addr; 389 u32 ifs_t4_avg_mask; 390 u32 ifs_t3_avg_mask; 391 u32 ifs_cca_l_addr; 392 u32 ifs_t2_cca_mask; 393 u32 ifs_t1_cca_mask; 394 u32 ifs_cca_h_addr; 395 u32 ifs_t4_cca_mask; 396 u32 ifs_t3_cca_mask; 397 u32 ifs_total_addr; 398 u32 ifs_cnt_done_mask; 399 u32 ifs_total_mask; 400 }; 401 402 struct rtw89_physts_regs { 403 u32 setting_addr; 404 u32 dis_trigger_fail_mask; 405 u32 dis_trigger_brk_mask; 406 }; 407 408 struct rtw89_cfo_regs { 409 u32 comp; 410 u32 weighting_mask; 411 u32 comp_seg0; 412 u32 valid_0_mask; 413 }; 414 415 enum rtw89_bandwidth_section_num_ax { 416 RTW89_BW20_SEC_NUM_AX = 8, 417 RTW89_BW40_SEC_NUM_AX = 4, 418 RTW89_BW80_SEC_NUM_AX = 2, 419 }; 420 421 enum rtw89_bandwidth_section_num_be { 422 RTW89_BW20_SEC_NUM_BE = 16, 423 RTW89_BW40_SEC_NUM_BE = 8, 424 RTW89_BW80_SEC_NUM_BE = 4, 425 RTW89_BW160_SEC_NUM_BE = 2, 426 }; 427 428 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 429 430 struct rtw89_txpwr_limit_ax { 431 s8 cck_20m[RTW89_BF_NUM]; 432 s8 cck_40m[RTW89_BF_NUM]; 433 s8 ofdm[RTW89_BF_NUM]; 434 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; 435 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; 436 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; 437 s8 mcs_160m[RTW89_BF_NUM]; 438 s8 mcs_40m_0p5[RTW89_BF_NUM]; 439 s8 mcs_40m_2p5[RTW89_BF_NUM]; 440 }; 441 442 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 443 444 struct rtw89_txpwr_limit_be { 445 s8 cck_20m[RTW89_BF_NUM]; 446 s8 cck_40m[RTW89_BF_NUM]; 447 s8 ofdm[RTW89_BF_NUM]; 448 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; 449 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; 450 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; 451 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; 452 s8 mcs_320m[RTW89_BF_NUM]; 453 s8 mcs_40m_0p5[RTW89_BF_NUM]; 454 s8 mcs_40m_2p5[RTW89_BF_NUM]; 455 s8 mcs_40m_4p5[RTW89_BF_NUM]; 456 s8 mcs_40m_6p5[RTW89_BF_NUM]; 457 }; 458 459 #define RTW89_RU_SEC_NUM_AX 8 460 461 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 462 463 struct rtw89_txpwr_limit_ru_ax { 464 s8 ru26[RTW89_RU_SEC_NUM_AX]; 465 s8 ru52[RTW89_RU_SEC_NUM_AX]; 466 s8 ru106[RTW89_RU_SEC_NUM_AX]; 467 }; 468 469 #define RTW89_RU_SEC_NUM_BE 16 470 471 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 472 473 struct rtw89_txpwr_limit_ru_be { 474 s8 ru26[RTW89_RU_SEC_NUM_BE]; 475 s8 ru52[RTW89_RU_SEC_NUM_BE]; 476 s8 ru106[RTW89_RU_SEC_NUM_BE]; 477 s8 ru52_26[RTW89_RU_SEC_NUM_BE]; 478 s8 ru106_26[RTW89_RU_SEC_NUM_BE]; 479 }; 480 481 struct rtw89_phy_gen_def { 482 u32 cr_base; 483 const struct rtw89_ccx_regs *ccx; 484 const struct rtw89_physts_regs *physts; 485 const struct rtw89_cfo_regs *cfo; 486 487 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, 488 const struct rtw89_chan *chan, 489 enum rtw89_phy_idx phy_idx); 490 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, 491 const struct rtw89_chan *chan, 492 enum rtw89_phy_idx phy_idx); 493 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, 494 const struct rtw89_chan *chan, 495 enum rtw89_phy_idx phy_idx); 496 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, 497 const struct rtw89_chan *chan, 498 enum rtw89_phy_idx phy_idx); 499 }; 500 501 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 502 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 503 504 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 505 u32 addr, u8 data) 506 { 507 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 508 509 rtw89_write8(rtwdev, addr + phy->cr_base, data); 510 } 511 512 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 513 u32 addr, u16 data) 514 { 515 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 516 517 rtw89_write16(rtwdev, addr + phy->cr_base, data); 518 } 519 520 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 521 u32 addr, u32 data) 522 { 523 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 524 525 rtw89_write32(rtwdev, addr + phy->cr_base, data); 526 } 527 528 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 529 u32 addr, u32 bits) 530 { 531 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 532 533 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 534 } 535 536 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 537 u32 addr, u32 bits) 538 { 539 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 540 541 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 542 } 543 544 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 545 u32 addr, u32 mask, u32 data) 546 { 547 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 548 549 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 550 } 551 552 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 553 { 554 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 555 556 return rtw89_read8(rtwdev, addr + phy->cr_base); 557 } 558 559 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 560 { 561 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 562 563 return rtw89_read16(rtwdev, addr + phy->cr_base); 564 } 565 566 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 567 { 568 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 569 570 return rtw89_read32(rtwdev, addr + phy->cr_base); 571 } 572 573 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 574 u32 addr, u32 mask) 575 { 576 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 577 578 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 579 } 580 581 static inline 582 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 583 { 584 switch (subband) { 585 default: 586 case RTW89_CH_2G: 587 return RTW89_GAIN_OFFSET_2G_OFDM; 588 case RTW89_CH_5G_BAND_1: 589 return RTW89_GAIN_OFFSET_5G_LOW; 590 case RTW89_CH_5G_BAND_3: 591 return RTW89_GAIN_OFFSET_5G_MID; 592 case RTW89_CH_5G_BAND_4: 593 return RTW89_GAIN_OFFSET_5G_HIGH; 594 } 595 } 596 597 static inline 598 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 599 { 600 switch (subband) { 601 default: 602 case RTW89_CH_2G: 603 return RTW89_BB_GAIN_BAND_2G; 604 case RTW89_CH_5G_BAND_1: 605 return RTW89_BB_GAIN_BAND_5G_L; 606 case RTW89_CH_5G_BAND_3: 607 return RTW89_BB_GAIN_BAND_5G_M; 608 case RTW89_CH_5G_BAND_4: 609 return RTW89_BB_GAIN_BAND_5G_H; 610 case RTW89_CH_6G_BAND_IDX0: 611 case RTW89_CH_6G_BAND_IDX1: 612 return RTW89_BB_GAIN_BAND_6G_L; 613 case RTW89_CH_6G_BAND_IDX2: 614 case RTW89_CH_6G_BAND_IDX3: 615 return RTW89_BB_GAIN_BAND_6G_M; 616 case RTW89_CH_6G_BAND_IDX4: 617 case RTW89_CH_6G_BAND_IDX5: 618 return RTW89_BB_GAIN_BAND_6G_H; 619 case RTW89_CH_6G_BAND_IDX6: 620 case RTW89_CH_6G_BAND_IDX7: 621 return RTW89_BB_GAIN_BAND_6G_UH; 622 } 623 } 624 625 enum rtw89_rfk_flag { 626 RTW89_RFK_F_WRF = 0, 627 RTW89_RFK_F_WM = 1, 628 RTW89_RFK_F_WS = 2, 629 RTW89_RFK_F_WC = 3, 630 RTW89_RFK_F_DELAY = 4, 631 RTW89_RFK_F_NUM, 632 }; 633 634 struct rtw89_rfk_tbl { 635 const struct rtw89_reg5_def *defs; 636 u32 size; 637 }; 638 639 #define RTW89_DECLARE_RFK_TBL(_name) \ 640 const struct rtw89_rfk_tbl _name ## _tbl = { \ 641 .defs = _name, \ 642 .size = ARRAY_SIZE(_name), \ 643 } 644 645 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 646 {.flag = RTW89_RFK_F_WRF, \ 647 .path = _path, \ 648 .addr = _addr, \ 649 .mask = _mask, \ 650 .data = _data,} 651 652 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 653 {.flag = RTW89_RFK_F_WM, \ 654 .addr = _addr, \ 655 .mask = _mask, \ 656 .data = _data,} 657 658 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 659 {.flag = RTW89_RFK_F_WS, \ 660 .addr = _addr, \ 661 .mask = _mask,} 662 663 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 664 {.flag = RTW89_RFK_F_WC, \ 665 .addr = _addr, \ 666 .mask = _mask,} 667 668 #define RTW89_DECL_RFK_DELAY(_data) \ 669 {.flag = RTW89_RFK_F_DELAY, \ 670 .data = _data,} 671 672 void 673 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 674 675 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 676 do { \ 677 typeof(dev) __dev = (dev); \ 678 if (cond) \ 679 rtw89_rfk_parser(__dev, (tbl_t)); \ 680 else \ 681 rtw89_rfk_parser(__dev, (tbl_f)); \ 682 } while (0) 683 684 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 685 const struct rtw89_phy_reg3_tbl *tbl); 686 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 687 const struct rtw89_chan *chan, 688 enum rtw89_bandwidth dbw); 689 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 690 u32 addr, u32 mask); 691 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 692 u32 addr, u32 mask); 693 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 694 u32 addr, u32 mask, u32 data); 695 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 696 u32 addr, u32 mask, u32 data); 697 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 698 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 699 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 700 const struct rtw89_reg2_def *reg, 701 enum rtw89_rf_path rf_path, 702 void *extra_data); 703 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 704 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 705 u32 data, enum rtw89_phy_idx phy_idx); 706 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 707 enum rtw89_phy_idx phy_idx); 708 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 709 struct rtw89_txpwr_byrate *head, 710 const struct rtw89_rate_desc *desc); 711 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 712 const struct rtw89_rate_desc *rate_desc); 713 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 714 const struct rtw89_txpwr_table *tbl); 715 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 716 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 717 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 718 u8 ru, u8 ntx, u8 ch); 719 720 static inline 721 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 722 const struct rtw89_chan *chan, 723 enum rtw89_phy_idx phy_idx) 724 { 725 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 726 727 phy->set_txpwr_byrate(rtwdev, chan, phy_idx); 728 } 729 730 static inline 731 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 732 const struct rtw89_chan *chan, 733 enum rtw89_phy_idx phy_idx) 734 { 735 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 736 737 phy->set_txpwr_offset(rtwdev, chan, phy_idx); 738 } 739 740 static inline 741 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 742 const struct rtw89_chan *chan, 743 enum rtw89_phy_idx phy_idx) 744 { 745 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 746 747 phy->set_txpwr_limit(rtwdev, chan, phy_idx); 748 } 749 750 static inline 751 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 752 const struct rtw89_chan *chan, 753 enum rtw89_phy_idx phy_idx) 754 { 755 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 756 757 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); 758 } 759 760 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 761 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 762 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 763 u32 changed); 764 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 765 struct ieee80211_vif *vif, 766 const struct cfg80211_bitrate_mask *mask); 767 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 768 u32 len, u8 class, u8 func); 769 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 770 void rtw89_phy_cfo_track_work(struct work_struct *work); 771 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 772 struct rtw89_rx_phy_ppdu *phy_ppdu); 773 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 774 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 775 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 776 u32 val); 777 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 778 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 779 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 780 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 781 struct rtw89_rx_phy_ppdu *phy_ppdu); 782 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 783 void rtw89_phy_antdiv_work(struct work_struct *work); 784 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 785 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 786 enum rtw89_mac_idx mac_idx, 787 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 788 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 789 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 790 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 791 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 792 u8 *ch, enum nl80211_band *band); 793 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); 794 795 #endif 796