1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_BBMCU_ADDR_OFFSET 0x30000 11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 12 13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 14 #define PHY_HEADLINE_VALID 0xf 15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 17 FIELD_PREP(GENMASK(7, 0), cv)) 18 19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 24 #define PHY_COND_BRANCH_IF 0x8 25 #define PHY_COND_BRANCH_ELIF 0x9 26 #define PHY_COND_BRANCH_ELSE 0xa 27 #define PHY_COND_BRANCH_END 0xb 28 #define PHY_COND_CHECK 0x4 29 #define PHY_COND_DONT_CARE 0xff 30 31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 33 #define RA_MASK_SUBCCK_RATES 0x5ULL 34 #define RA_MASK_SUBOFDM_RATES 0x10ULL 35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 50 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12) 51 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28) 52 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44) 53 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60) 54 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12) 55 56 #define CFO_TRK_ENABLE_TH (2 << 2) 57 #define CFO_TRK_STOP_TH_4 (30 << 2) 58 #define CFO_TRK_STOP_TH_3 (20 << 2) 59 #define CFO_TRK_STOP_TH_2 (10 << 2) 60 #define CFO_TRK_STOP_TH_1 (03 << 2) 61 #define CFO_TRK_STOP_TH (2 << 2) 62 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 63 #define CFO_PERIOD_CNT 15 64 #define CFO_BOUND 64 65 #define CFO_TP_UPPER 100 66 #define CFO_TP_LOWER 50 67 #define CFO_COMP_PERIOD 250 68 #define CFO_COMP_WEIGHT 8 69 #define MAX_CFO_TOLERANCE 30 70 #define CFO_TF_CNT_TH 300 71 72 #define UL_TB_TF_CNT_L2H_TH 100 73 #define UL_TB_TF_CNT_H2L_TH 70 74 75 #define ANTDIV_TRAINNING_CNT 2 76 #define ANTDIV_TRAINNING_INTVL 30 77 #define ANTDIV_DELAY 110 78 #define ANTDIV_TP_DIFF_TH_HIGH 100 79 #define ANTDIV_TP_DIFF_TH_LOW 5 80 #define ANTDIV_EVM_DIFF_TH 8 81 #define ANTDIV_RSSI_DIFF_TH 3 82 83 #define CCX_MAX_PERIOD 2097 84 #define CCX_MAX_PERIOD_UNIT 32 85 #define MS_TO_4US_RATIO 250 86 #define ENV_MNTR_FAIL_DWORD 0xffffffff 87 #define ENV_MNTR_IFSCLM_HIS_MAX 127 88 #define PERMIL 1000 89 #define PERCENT 100 90 #define IFS_CLM_TH0_UPPER 64 91 #define IFS_CLM_TH_MUL 4 92 #define IFS_CLM_TH_START_IDX 0 93 94 #define TIA0_GAIN_A 12 95 #define TIA0_GAIN_G 16 96 #define LNA0_GAIN (-24) 97 #define U4_MAX_BIT 3 98 #define U8_MAX_BIT 7 99 #define DIG_GAIN_SHIFT 2 100 #define DIG_GAIN 8 101 102 #define LNA_IDX_MAX 6 103 #define LNA_IDX_MIN 0 104 #define TIA_IDX_MAX 1 105 #define TIA_IDX_MIN 0 106 #define RXB_IDX_MAX 31 107 #define RXB_IDX_MIN 0 108 109 #define IGI_RSSI_MAX 110 110 #define PD_TH_MAX_RSSI 70 111 #define PD_TH_MIN_RSSI 8 112 #define CCKPD_TH_MIN_RSSI (-18) 113 #define PD_TH_BW160_CMP_VAL 9 114 #define PD_TH_BW80_CMP_VAL 6 115 #define PD_TH_BW40_CMP_VAL 3 116 #define PD_TH_BW20_CMP_VAL 0 117 #define PD_TH_CMP_VAL 3 118 #define PD_TH_SB_FLTR_CMP_VAL 7 119 120 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 121 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 122 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 123 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 124 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 125 126 #define EDCCA_MAX 249 127 #define EDCCA_TH_L2H_LB 66 128 #define EDCCA_TH_REF 3 129 #define EDCCA_HL_DIFF_NORMAL 8 130 #define RSSI_UNIT_CONVER 110 131 #define EDCCA_UNIT_CONVER 128 132 #define EDCCA_PWROFST_DEFAULT 18 133 134 enum rtw89_phy_c2h_ra_func { 135 RTW89_PHY_C2H_FUNC_STS_RPT, 136 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 137 RTW89_PHY_C2H_FUNC_TXSTS, 138 RTW89_PHY_C2H_FUNC_RA_MAX, 139 }; 140 141 enum rtw89_phy_c2h_rfk_log_func { 142 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0, 143 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1, 144 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2, 145 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3, 146 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, 147 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, 148 149 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, 150 }; 151 152 enum rtw89_phy_c2h_rfk_report_func { 153 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0, 154 RTW89_PHY_C2H_RFK_LOG_TAS_PWR = 6, 155 }; 156 157 enum rtw89_phy_c2h_dm_func { 158 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 159 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 160 RTW89_PHY_C2H_DM_FUNC_SIGB, 161 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 162 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 163 RTW89_PHY_C2H_DM_FUNC_NUM, 164 }; 165 166 enum rtw89_phy_c2h_class { 167 RTW89_PHY_C2H_CLASS_RUA, 168 RTW89_PHY_C2H_CLASS_RA, 169 RTW89_PHY_C2H_CLASS_DM, 170 RTW89_PHY_C2H_RFK_LOG = 0x8, 171 RTW89_PHY_C2H_RFK_REPORT = 0x9, 172 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 173 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 174 RTW89_PHY_C2H_CLASS_MAX, 175 }; 176 177 enum rtw89_env_monitor_result_level { 178 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 179 RTW89_PHY_ENV_MON_NHM = BIT(0), 180 RTW89_PHY_ENV_MON_CLM = BIT(1), 181 RTW89_PHY_ENV_MON_FAHM = BIT(2), 182 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 183 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 184 }; 185 186 #define CCX_US_BASE_RATIO 4 187 enum rtw89_ccx_unit { 188 RTW89_CCX_4_US = 0, 189 RTW89_CCX_8_US = 1, 190 RTW89_CCX_16_US = 2, 191 RTW89_CCX_32_US = 3 192 }; 193 194 enum rtw89_phy_status_ie_type { 195 RTW89_PHYSTS_IE00_CMN_CCK = 0, 196 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 197 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 198 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 199 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 200 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 201 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 202 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 203 RTW89_PHYSTS_IE08_FTR_CH = 8, 204 RTW89_PHYSTS_IE09_FTR_0 = 9, 205 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 206 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 207 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 208 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 209 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 210 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 211 RTW89_PHYSTS_IE16_RSVD16 = 16, 212 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 213 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 214 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 215 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 216 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 217 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 218 RTW89_PHYSTS_IE23_RSVD23 = 23, 219 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 220 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 221 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 222 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 223 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 224 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 225 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 226 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 227 228 /* keep last */ 229 RTW89_PHYSTS_IE_NUM, 230 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 231 }; 232 233 enum rtw89_phy_status_bitmap { 234 RTW89_TD_SEARCH_FAIL = 0, 235 RTW89_BRK_BY_TX_PKT = 1, 236 RTW89_CCA_SPOOF = 2, 237 RTW89_OFDM_BRK = 3, 238 RTW89_CCK_BRK = 4, 239 RTW89_DL_MU_SPOOFING = 5, 240 RTW89_HE_MU = 6, 241 RTW89_VHT_MU = 7, 242 RTW89_UL_TB_SPOOFING = 8, 243 RTW89_RSVD_9 = 9, 244 RTW89_TRIG_BASE_PPDU = 10, 245 RTW89_CCK_PKT = 11, 246 RTW89_LEGACY_OFDM_PKT = 12, 247 RTW89_HT_PKT = 13, 248 RTW89_VHT_PKT = 14, 249 RTW89_HE_PKT = 15, 250 251 RTW89_PHYSTS_BITMAP_NUM 252 }; 253 254 enum rtw89_dig_gain_type { 255 RTW89_DIG_GAIN_LNA_G = 0, 256 RTW89_DIG_GAIN_TIA_G = 1, 257 RTW89_DIG_GAIN_LNA_A = 2, 258 RTW89_DIG_GAIN_TIA_A = 3, 259 RTW89_DIG_GAIN_MAX = 4 260 }; 261 262 enum rtw89_dig_gain_lna_idx { 263 RTW89_DIG_GAIN_LNA_IDX1 = 1, 264 RTW89_DIG_GAIN_LNA_IDX2 = 2, 265 RTW89_DIG_GAIN_LNA_IDX3 = 3, 266 RTW89_DIG_GAIN_LNA_IDX4 = 4, 267 RTW89_DIG_GAIN_LNA_IDX5 = 5, 268 RTW89_DIG_GAIN_LNA_IDX6 = 6 269 }; 270 271 enum rtw89_dig_gain_tia_idx { 272 RTW89_DIG_GAIN_TIA_IDX0 = 0, 273 RTW89_DIG_GAIN_TIA_IDX1 = 1 274 }; 275 276 enum rtw89_tssi_bandedge_cfg { 277 RTW89_TSSI_BANDEDGE_FLAT, 278 RTW89_TSSI_BANDEDGE_LOW, 279 RTW89_TSSI_BANDEDGE_MID, 280 RTW89_TSSI_BANDEDGE_HIGH, 281 282 RTW89_TSSI_CFG_NUM, 283 }; 284 285 enum rtw89_tssi_sbw_idx { 286 RTW89_TSSI_SBW20, 287 RTW89_TSSI_SBW40_0, 288 RTW89_TSSI_SBW40_1, 289 RTW89_TSSI_SBW80_0, 290 RTW89_TSSI_SBW80_1, 291 RTW89_TSSI_SBW80_2, 292 RTW89_TSSI_SBW80_3, 293 RTW89_TSSI_SBW160_0, 294 RTW89_TSSI_SBW160_1, 295 RTW89_TSSI_SBW160_2, 296 RTW89_TSSI_SBW160_3, 297 RTW89_TSSI_SBW160_4, 298 RTW89_TSSI_SBW160_5, 299 RTW89_TSSI_SBW160_6, 300 RTW89_TSSI_SBW160_7, 301 302 RTW89_TSSI_SBW_NUM, 303 }; 304 305 struct rtw89_txpwr_byrate_cfg { 306 enum rtw89_band band; 307 enum rtw89_nss nss; 308 enum rtw89_rate_section rs; 309 u8 shf; 310 u8 len; 311 u32 data; 312 }; 313 314 struct rtw89_txpwr_track_cfg { 315 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 316 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 317 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 318 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 319 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 320 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 321 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 322 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 323 const s8 *delta_swingidx_2gb_n; 324 const s8 *delta_swingidx_2gb_p; 325 const s8 *delta_swingidx_2ga_n; 326 const s8 *delta_swingidx_2ga_p; 327 const s8 *delta_swingidx_2g_cck_b_n; 328 const s8 *delta_swingidx_2g_cck_b_p; 329 const s8 *delta_swingidx_2g_cck_a_n; 330 const s8 *delta_swingidx_2g_cck_a_p; 331 }; 332 333 struct rtw89_phy_dig_gain_cfg { 334 const struct rtw89_reg_def *table; 335 u8 size; 336 }; 337 338 struct rtw89_phy_dig_gain_table { 339 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 340 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 341 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 342 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 343 }; 344 345 struct rtw89_phy_tssi_dbw_table { 346 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 347 }; 348 349 struct rtw89_phy_reg3_tbl { 350 const struct rtw89_reg3_def *reg3; 351 int size; 352 }; 353 354 #define DECLARE_PHY_REG3_TBL(_name) \ 355 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 356 .reg3 = _name, \ 357 .size = ARRAY_SIZE(_name), \ 358 } 359 360 struct rtw89_nbi_reg_def { 361 struct rtw89_reg_def notch1_idx; 362 struct rtw89_reg_def notch1_frac_idx; 363 struct rtw89_reg_def notch1_en; 364 struct rtw89_reg_def notch2_idx; 365 struct rtw89_reg_def notch2_frac_idx; 366 struct rtw89_reg_def notch2_en; 367 }; 368 369 struct rtw89_ccx_regs { 370 u32 setting_addr; 371 u32 edcca_opt_mask; 372 u32 measurement_trig_mask; 373 u32 trig_opt_mask; 374 u32 en_mask; 375 u32 ifs_cnt_addr; 376 u32 ifs_clm_period_mask; 377 u32 ifs_clm_cnt_unit_mask; 378 u32 ifs_clm_cnt_clear_mask; 379 u32 ifs_collect_en_mask; 380 u32 ifs_t1_addr; 381 u32 ifs_t1_th_h_mask; 382 u32 ifs_t1_en_mask; 383 u32 ifs_t1_th_l_mask; 384 u32 ifs_t2_addr; 385 u32 ifs_t2_th_h_mask; 386 u32 ifs_t2_en_mask; 387 u32 ifs_t2_th_l_mask; 388 u32 ifs_t3_addr; 389 u32 ifs_t3_th_h_mask; 390 u32 ifs_t3_en_mask; 391 u32 ifs_t3_th_l_mask; 392 u32 ifs_t4_addr; 393 u32 ifs_t4_th_h_mask; 394 u32 ifs_t4_en_mask; 395 u32 ifs_t4_th_l_mask; 396 u32 ifs_clm_tx_cnt_addr; 397 u32 ifs_clm_edcca_excl_cca_fa_mask; 398 u32 ifs_clm_tx_cnt_msk; 399 u32 ifs_clm_cca_addr; 400 u32 ifs_clm_ofdmcca_excl_fa_mask; 401 u32 ifs_clm_cckcca_excl_fa_mask; 402 u32 ifs_clm_fa_addr; 403 u32 ifs_clm_ofdm_fa_mask; 404 u32 ifs_clm_cck_fa_mask; 405 u32 ifs_his_addr; 406 u32 ifs_t4_his_mask; 407 u32 ifs_t3_his_mask; 408 u32 ifs_t2_his_mask; 409 u32 ifs_t1_his_mask; 410 u32 ifs_avg_l_addr; 411 u32 ifs_t2_avg_mask; 412 u32 ifs_t1_avg_mask; 413 u32 ifs_avg_h_addr; 414 u32 ifs_t4_avg_mask; 415 u32 ifs_t3_avg_mask; 416 u32 ifs_cca_l_addr; 417 u32 ifs_t2_cca_mask; 418 u32 ifs_t1_cca_mask; 419 u32 ifs_cca_h_addr; 420 u32 ifs_t4_cca_mask; 421 u32 ifs_t3_cca_mask; 422 u32 ifs_total_addr; 423 u32 ifs_cnt_done_mask; 424 u32 ifs_total_mask; 425 }; 426 427 struct rtw89_physts_regs { 428 u32 setting_addr; 429 u32 dis_trigger_fail_mask; 430 u32 dis_trigger_brk_mask; 431 }; 432 433 struct rtw89_cfo_regs { 434 u32 comp; 435 u32 weighting_mask; 436 u32 comp_seg0; 437 u32 valid_0_mask; 438 }; 439 440 enum rtw89_bandwidth_section_num_ax { 441 RTW89_BW20_SEC_NUM_AX = 8, 442 RTW89_BW40_SEC_NUM_AX = 4, 443 RTW89_BW80_SEC_NUM_AX = 2, 444 }; 445 446 enum rtw89_bandwidth_section_num_be { 447 RTW89_BW20_SEC_NUM_BE = 16, 448 RTW89_BW40_SEC_NUM_BE = 8, 449 RTW89_BW80_SEC_NUM_BE = 4, 450 RTW89_BW160_SEC_NUM_BE = 2, 451 }; 452 453 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 454 455 struct rtw89_txpwr_limit_ax { 456 s8 cck_20m[RTW89_BF_NUM]; 457 s8 cck_40m[RTW89_BF_NUM]; 458 s8 ofdm[RTW89_BF_NUM]; 459 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; 460 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; 461 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; 462 s8 mcs_160m[RTW89_BF_NUM]; 463 s8 mcs_40m_0p5[RTW89_BF_NUM]; 464 s8 mcs_40m_2p5[RTW89_BF_NUM]; 465 }; 466 467 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 468 469 struct rtw89_txpwr_limit_be { 470 s8 cck_20m[RTW89_BF_NUM]; 471 s8 cck_40m[RTW89_BF_NUM]; 472 s8 ofdm[RTW89_BF_NUM]; 473 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; 474 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; 475 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; 476 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; 477 s8 mcs_320m[RTW89_BF_NUM]; 478 s8 mcs_40m_0p5[RTW89_BF_NUM]; 479 s8 mcs_40m_2p5[RTW89_BF_NUM]; 480 s8 mcs_40m_4p5[RTW89_BF_NUM]; 481 s8 mcs_40m_6p5[RTW89_BF_NUM]; 482 }; 483 484 #define RTW89_RU_SEC_NUM_AX 8 485 486 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 487 488 struct rtw89_txpwr_limit_ru_ax { 489 s8 ru26[RTW89_RU_SEC_NUM_AX]; 490 s8 ru52[RTW89_RU_SEC_NUM_AX]; 491 s8 ru106[RTW89_RU_SEC_NUM_AX]; 492 }; 493 494 #define RTW89_RU_SEC_NUM_BE 16 495 496 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 497 498 struct rtw89_txpwr_limit_ru_be { 499 s8 ru26[RTW89_RU_SEC_NUM_BE]; 500 s8 ru52[RTW89_RU_SEC_NUM_BE]; 501 s8 ru106[RTW89_RU_SEC_NUM_BE]; 502 s8 ru52_26[RTW89_RU_SEC_NUM_BE]; 503 s8 ru106_26[RTW89_RU_SEC_NUM_BE]; 504 }; 505 506 struct rtw89_phy_rfk_log_fmt { 507 const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM]; 508 }; 509 510 struct rtw89_phy_gen_def { 511 u32 cr_base; 512 const struct rtw89_ccx_regs *ccx; 513 const struct rtw89_physts_regs *physts; 514 const struct rtw89_cfo_regs *cfo; 515 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr); 516 void (*config_bb_gain)(struct rtw89_dev *rtwdev, 517 const struct rtw89_reg2_def *reg, 518 enum rtw89_rf_path rf_path, 519 void *extra_data); 520 void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev); 521 void (*bb_wrap_init)(struct rtw89_dev *rtwdev); 522 void (*ch_info_init)(struct rtw89_dev *rtwdev); 523 524 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, 525 const struct rtw89_chan *chan, 526 enum rtw89_phy_idx phy_idx); 527 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, 528 const struct rtw89_chan *chan, 529 enum rtw89_phy_idx phy_idx); 530 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, 531 const struct rtw89_chan *chan, 532 enum rtw89_phy_idx phy_idx); 533 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, 534 const struct rtw89_chan *chan, 535 enum rtw89_phy_idx phy_idx); 536 }; 537 538 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 539 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 540 541 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 542 u32 addr, u8 data) 543 { 544 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 545 546 rtw89_write8(rtwdev, addr + phy->cr_base, data); 547 } 548 549 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 550 u32 addr, u16 data) 551 { 552 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 553 554 rtw89_write16(rtwdev, addr + phy->cr_base, data); 555 } 556 557 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 558 u32 addr, u32 data) 559 { 560 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 561 562 rtw89_write32(rtwdev, addr + phy->cr_base, data); 563 } 564 565 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 566 u32 addr, u32 bits) 567 { 568 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 569 570 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 571 } 572 573 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 574 u32 addr, u32 bits) 575 { 576 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 577 578 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 579 } 580 581 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 582 u32 addr, u32 mask, u32 data) 583 { 584 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 585 586 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 587 } 588 589 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 590 { 591 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 592 593 return rtw89_read8(rtwdev, addr + phy->cr_base); 594 } 595 596 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 597 { 598 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 599 600 return rtw89_read16(rtwdev, addr + phy->cr_base); 601 } 602 603 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 604 { 605 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 606 607 return rtw89_read32(rtwdev, addr + phy->cr_base); 608 } 609 610 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 611 u32 addr, u32 mask) 612 { 613 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 614 615 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 616 } 617 618 static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev, 619 u32 addr, u32 data, enum rtw89_phy_idx phy_idx) 620 { 621 if (phy_idx && addr < 0x10000) 622 addr += 0x20000; 623 624 rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data); 625 } 626 627 static inline 628 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 629 { 630 switch (subband) { 631 default: 632 case RTW89_CH_2G: 633 return RTW89_GAIN_OFFSET_2G_OFDM; 634 case RTW89_CH_5G_BAND_1: 635 return RTW89_GAIN_OFFSET_5G_LOW; 636 case RTW89_CH_5G_BAND_3: 637 return RTW89_GAIN_OFFSET_5G_MID; 638 case RTW89_CH_5G_BAND_4: 639 return RTW89_GAIN_OFFSET_5G_HIGH; 640 case RTW89_CH_6G_BAND_IDX0: 641 return RTW89_GAIN_OFFSET_6G_L0; 642 case RTW89_CH_6G_BAND_IDX1: 643 return RTW89_GAIN_OFFSET_6G_L1; 644 case RTW89_CH_6G_BAND_IDX2: 645 return RTW89_GAIN_OFFSET_6G_M0; 646 case RTW89_CH_6G_BAND_IDX3: 647 return RTW89_GAIN_OFFSET_6G_M1; 648 case RTW89_CH_6G_BAND_IDX4: 649 return RTW89_GAIN_OFFSET_6G_H0; 650 case RTW89_CH_6G_BAND_IDX5: 651 return RTW89_GAIN_OFFSET_6G_H1; 652 case RTW89_CH_6G_BAND_IDX6: 653 return RTW89_GAIN_OFFSET_6G_UH0; 654 case RTW89_CH_6G_BAND_IDX7: 655 return RTW89_GAIN_OFFSET_6G_UH1; 656 } 657 } 658 659 static inline 660 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 661 { 662 switch (subband) { 663 default: 664 case RTW89_CH_2G: 665 return RTW89_BB_GAIN_BAND_2G; 666 case RTW89_CH_5G_BAND_1: 667 return RTW89_BB_GAIN_BAND_5G_L; 668 case RTW89_CH_5G_BAND_3: 669 return RTW89_BB_GAIN_BAND_5G_M; 670 case RTW89_CH_5G_BAND_4: 671 return RTW89_BB_GAIN_BAND_5G_H; 672 case RTW89_CH_6G_BAND_IDX0: 673 case RTW89_CH_6G_BAND_IDX1: 674 return RTW89_BB_GAIN_BAND_6G_L; 675 case RTW89_CH_6G_BAND_IDX2: 676 case RTW89_CH_6G_BAND_IDX3: 677 return RTW89_BB_GAIN_BAND_6G_M; 678 case RTW89_CH_6G_BAND_IDX4: 679 case RTW89_CH_6G_BAND_IDX5: 680 return RTW89_BB_GAIN_BAND_6G_H; 681 case RTW89_CH_6G_BAND_IDX6: 682 case RTW89_CH_6G_BAND_IDX7: 683 return RTW89_BB_GAIN_BAND_6G_UH; 684 } 685 } 686 687 static inline 688 enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband) 689 { 690 switch (subband) { 691 default: 692 case RTW89_CH_2G: 693 return RTW89_BB_GAIN_BAND_2G_BE; 694 case RTW89_CH_5G_BAND_1: 695 return RTW89_BB_GAIN_BAND_5G_L_BE; 696 case RTW89_CH_5G_BAND_3: 697 return RTW89_BB_GAIN_BAND_5G_M_BE; 698 case RTW89_CH_5G_BAND_4: 699 return RTW89_BB_GAIN_BAND_5G_H_BE; 700 case RTW89_CH_6G_BAND_IDX0: 701 return RTW89_BB_GAIN_BAND_6G_L0_BE; 702 case RTW89_CH_6G_BAND_IDX1: 703 return RTW89_BB_GAIN_BAND_6G_L1_BE; 704 case RTW89_CH_6G_BAND_IDX2: 705 return RTW89_BB_GAIN_BAND_6G_M0_BE; 706 case RTW89_CH_6G_BAND_IDX3: 707 return RTW89_BB_GAIN_BAND_6G_M1_BE; 708 case RTW89_CH_6G_BAND_IDX4: 709 return RTW89_BB_GAIN_BAND_6G_H0_BE; 710 case RTW89_CH_6G_BAND_IDX5: 711 return RTW89_BB_GAIN_BAND_6G_H1_BE; 712 case RTW89_CH_6G_BAND_IDX6: 713 return RTW89_BB_GAIN_BAND_6G_UH0_BE; 714 case RTW89_CH_6G_BAND_IDX7: 715 return RTW89_BB_GAIN_BAND_6G_UH1_BE; 716 } 717 } 718 719 struct rtw89_rfk_chan_desc { 720 /* desc is valid iff ch is non-zero */ 721 u8 ch; 722 723 /* To avoid us from extending old chip code every time, each new 724 * field must be defined along with a bool flag in positivte way. 725 */ 726 bool has_band; 727 u8 band; 728 bool has_bw; 729 u8 bw; 730 }; 731 732 enum rtw89_rfk_flag { 733 RTW89_RFK_F_WRF = 0, 734 RTW89_RFK_F_WM = 1, 735 RTW89_RFK_F_WS = 2, 736 RTW89_RFK_F_WC = 3, 737 RTW89_RFK_F_DELAY = 4, 738 RTW89_RFK_F_NUM, 739 }; 740 741 struct rtw89_rfk_tbl { 742 const struct rtw89_reg5_def *defs; 743 u32 size; 744 }; 745 746 #define RTW89_DECLARE_RFK_TBL(_name) \ 747 const struct rtw89_rfk_tbl _name ## _tbl = { \ 748 .defs = _name, \ 749 .size = ARRAY_SIZE(_name), \ 750 } 751 752 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 753 {.flag = RTW89_RFK_F_WRF, \ 754 .path = _path, \ 755 .addr = _addr, \ 756 .mask = _mask, \ 757 .data = _data,} 758 759 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 760 {.flag = RTW89_RFK_F_WM, \ 761 .addr = _addr, \ 762 .mask = _mask, \ 763 .data = _data,} 764 765 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 766 {.flag = RTW89_RFK_F_WS, \ 767 .addr = _addr, \ 768 .mask = _mask,} 769 770 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 771 {.flag = RTW89_RFK_F_WC, \ 772 .addr = _addr, \ 773 .mask = _mask,} 774 775 #define RTW89_DECL_RFK_DELAY(_data) \ 776 {.flag = RTW89_RFK_F_DELAY, \ 777 .data = _data,} 778 779 void 780 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 781 782 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 783 do { \ 784 typeof(dev) __dev = (dev); \ 785 if (cond) \ 786 rtw89_rfk_parser(__dev, (tbl_t)); \ 787 else \ 788 rtw89_rfk_parser(__dev, (tbl_f)); \ 789 } while (0) 790 791 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 792 const struct rtw89_phy_reg3_tbl *tbl); 793 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 794 const struct rtw89_chan *chan, 795 enum rtw89_bandwidth dbw); 796 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 797 enum rtw89_bandwidth dbw); 798 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 799 u32 addr, u32 mask); 800 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 801 u32 addr, u32 mask); 802 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 803 u32 addr, u32 mask); 804 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 805 u32 addr, u32 mask, u32 data); 806 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 807 u32 addr, u32 mask, u32 data); 808 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 809 u32 addr, u32 mask, u32 data); 810 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 811 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 812 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 813 const struct rtw89_reg2_def *reg, 814 enum rtw89_rf_path rf_path, 815 void *extra_data); 816 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 817 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev); 818 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 819 u32 data, enum rtw89_phy_idx phy_idx); 820 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 821 enum rtw89_phy_idx phy_idx); 822 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 823 enum rtw89_phy_idx phy_idx); 824 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 825 enum rtw89_phy_idx phy_idx); 826 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 827 struct rtw89_txpwr_byrate *head, 828 const struct rtw89_rate_desc *desc); 829 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 830 const struct rtw89_rate_desc *rate_desc); 831 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev); 832 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev, 833 const struct rtw89_chan *chan); 834 void rtw89_print_ant_gain(struct seq_file *m, struct rtw89_dev *rtwdev, 835 const struct rtw89_chan *chan); 836 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 837 const struct rtw89_txpwr_table *tbl); 838 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 839 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 840 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 841 u8 ru, u8 ntx, u8 ch); 842 843 static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev) 844 { 845 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 846 847 phy->preinit_rf_nctl(rtwdev); 848 } 849 850 static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev) 851 { 852 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 853 854 if (phy->bb_wrap_init) 855 phy->bb_wrap_init(rtwdev); 856 } 857 858 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) 859 { 860 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 861 862 if (phy->ch_info_init) 863 phy->ch_info_init(rtwdev); 864 } 865 866 static inline 867 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 868 const struct rtw89_chan *chan, 869 enum rtw89_phy_idx phy_idx) 870 { 871 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 872 873 phy->set_txpwr_byrate(rtwdev, chan, phy_idx); 874 } 875 876 static inline 877 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 878 const struct rtw89_chan *chan, 879 enum rtw89_phy_idx phy_idx) 880 { 881 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 882 883 phy->set_txpwr_offset(rtwdev, chan, phy_idx); 884 } 885 886 static inline 887 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 888 const struct rtw89_chan *chan, 889 enum rtw89_phy_idx phy_idx) 890 { 891 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 892 893 phy->set_txpwr_limit(rtwdev, chan, phy_idx); 894 } 895 896 static inline 897 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 898 const struct rtw89_chan *chan, 899 enum rtw89_phy_idx phy_idx) 900 { 901 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 902 903 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); 904 } 905 906 static inline s8 rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_rf) 907 { 908 const struct rtw89_chip_info *chip = rtwdev->chip; 909 910 return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf); 911 } 912 913 static inline s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 914 { 915 const struct rtw89_chip_info *chip = rtwdev->chip; 916 917 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 918 } 919 920 static inline s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm) 921 { 922 const struct rtw89_chip_info *chip = rtwdev->chip; 923 924 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63); 925 } 926 927 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link); 928 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 929 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 930 u32 changed); 931 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev, 932 struct rtw89_sta_link *rtwsta_link, 933 u32 changed); 934 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 935 struct ieee80211_vif *vif, 936 const struct cfg80211_bitrate_mask *mask); 937 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); 938 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 939 u32 len, u8 class, u8 func); 940 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 941 enum rtw89_phy_idx phy_idx, 942 unsigned int ms); 943 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 944 enum rtw89_phy_idx phy_idx, 945 const struct rtw89_chan *chan, 946 enum rtw89_tssi_mode tssi_mode, 947 unsigned int ms); 948 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 949 enum rtw89_phy_idx phy_idx, 950 const struct rtw89_chan *chan, 951 unsigned int ms); 952 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 953 enum rtw89_phy_idx phy_idx, 954 const struct rtw89_chan *chan, 955 unsigned int ms); 956 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 957 enum rtw89_phy_idx phy_idx, 958 const struct rtw89_chan *chan, 959 unsigned int ms); 960 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 961 enum rtw89_phy_idx phy_idx, 962 const struct rtw89_chan *chan, 963 unsigned int ms); 964 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 965 enum rtw89_phy_idx phy_idx, 966 const struct rtw89_chan *chan, 967 bool is_chl_k, unsigned int ms); 968 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 969 enum rtw89_phy_idx phy, 970 const struct rtw89_chan *chan, 971 struct rtw89_h2c_rf_tssi *h2c); 972 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 973 enum rtw89_phy_idx phy, 974 const struct rtw89_chan *chan, 975 struct rtw89_h2c_rf_tssi *h2c); 976 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 977 void rtw89_phy_cfo_track_work(struct work_struct *work); 978 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 979 struct rtw89_rx_phy_ppdu *phy_ppdu); 980 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 981 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 982 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 983 u32 val); 984 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 985 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 986 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 987 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 988 struct rtw89_rx_phy_ppdu *phy_ppdu); 989 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 990 void rtw89_phy_antdiv_work(struct work_struct *work); 991 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, 992 struct rtw89_vif_link *rtwvif_link); 993 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 994 enum rtw89_mac_idx mac_idx, 995 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 996 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 997 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 998 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 999 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 1000 u8 *ch, enum nl80211_band *band); 1001 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); 1002 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev); 1003 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev); 1004 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 1005 enum rtw89_phy_idx phy_idx); 1006 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 1007 enum rtw89_phy_idx phy_idx); 1008 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 1009 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 1010 const struct rtw89_chan *target_chan); 1011 1012 #endif 1013