1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 11 12 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 13 #define PHY_HEADLINE_VALID 0xf 14 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 15 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 16 FIELD_PREP(GENMASK(7, 0), cv)) 17 18 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 19 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 20 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 21 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 22 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 23 #define PHY_COND_BRANCH_IF 0x8 24 #define PHY_COND_BRANCH_ELIF 0x9 25 #define PHY_COND_BRANCH_ELSE 0xa 26 #define PHY_COND_BRANCH_END 0xb 27 #define PHY_COND_CHECK 0x4 28 #define PHY_COND_DONT_CARE 0xff 29 30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 32 #define RA_MASK_SUBCCK_RATES 0x5ULL 33 #define RA_MASK_SUBOFDM_RATES 0x10ULL 34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 39 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 40 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 41 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 42 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 46 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 47 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 48 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 49 50 #define CFO_TRK_ENABLE_TH (2 << 2) 51 #define CFO_TRK_STOP_TH_4 (30 << 2) 52 #define CFO_TRK_STOP_TH_3 (20 << 2) 53 #define CFO_TRK_STOP_TH_2 (10 << 2) 54 #define CFO_TRK_STOP_TH_1 (00 << 2) 55 #define CFO_TRK_STOP_TH (2 << 2) 56 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 57 #define CFO_PERIOD_CNT 15 58 #define CFO_BOUND 64 59 #define CFO_TP_UPPER 100 60 #define CFO_TP_LOWER 50 61 #define CFO_COMP_PERIOD 250 62 #define CFO_COMP_WEIGHT 8 63 #define MAX_CFO_TOLERANCE 30 64 #define CFO_TF_CNT_TH 300 65 66 #define UL_TB_TF_CNT_L2H_TH 100 67 #define UL_TB_TF_CNT_H2L_TH 70 68 69 #define ANTDIV_TRAINNING_CNT 2 70 #define ANTDIV_TRAINNING_INTVL 30 71 #define ANTDIV_DELAY 110 72 #define ANTDIV_TP_DIFF_TH_HIGH 100 73 #define ANTDIV_TP_DIFF_TH_LOW 5 74 #define ANTDIV_EVM_DIFF_TH 8 75 #define ANTDIV_RSSI_DIFF_TH 3 76 77 #define CCX_MAX_PERIOD 2097 78 #define CCX_MAX_PERIOD_UNIT 32 79 #define MS_TO_4US_RATIO 250 80 #define ENV_MNTR_FAIL_DWORD 0xffffffff 81 #define ENV_MNTR_IFSCLM_HIS_MAX 127 82 #define PERMIL 1000 83 #define PERCENT 100 84 #define IFS_CLM_TH0_UPPER 64 85 #define IFS_CLM_TH_MUL 4 86 #define IFS_CLM_TH_START_IDX 0 87 88 #define TIA0_GAIN_A 12 89 #define TIA0_GAIN_G 16 90 #define LNA0_GAIN (-24) 91 #define U4_MAX_BIT 3 92 #define U8_MAX_BIT 7 93 #define DIG_GAIN_SHIFT 2 94 #define DIG_GAIN 8 95 96 #define LNA_IDX_MAX 6 97 #define LNA_IDX_MIN 0 98 #define TIA_IDX_MAX 1 99 #define TIA_IDX_MIN 0 100 #define RXB_IDX_MAX 31 101 #define RXB_IDX_MIN 0 102 103 #define IGI_RSSI_MAX 110 104 #define PD_TH_MAX_RSSI 70 105 #define PD_TH_MIN_RSSI 8 106 #define CCKPD_TH_MIN_RSSI (-18) 107 #define PD_TH_BW160_CMP_VAL 9 108 #define PD_TH_BW80_CMP_VAL 6 109 #define PD_TH_BW40_CMP_VAL 3 110 #define PD_TH_BW20_CMP_VAL 0 111 #define PD_TH_CMP_VAL 3 112 #define PD_TH_SB_FLTR_CMP_VAL 7 113 114 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 115 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 116 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 117 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 118 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 119 120 enum rtw89_phy_c2h_ra_func { 121 RTW89_PHY_C2H_FUNC_STS_RPT, 122 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 123 RTW89_PHY_C2H_FUNC_TXSTS, 124 RTW89_PHY_C2H_FUNC_RA_MAX, 125 }; 126 127 enum rtw89_phy_c2h_dm_func { 128 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 129 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 130 RTW89_PHY_C2H_DM_FUNC_SIGB, 131 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 132 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 133 RTW89_PHY_C2H_DM_FUNC_NUM, 134 }; 135 136 enum rtw89_phy_c2h_class { 137 RTW89_PHY_C2H_CLASS_RUA, 138 RTW89_PHY_C2H_CLASS_RA, 139 RTW89_PHY_C2H_CLASS_DM, 140 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 141 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 142 RTW89_PHY_C2H_CLASS_MAX, 143 }; 144 145 enum rtw89_env_monitor_result_level { 146 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 147 RTW89_PHY_ENV_MON_NHM = BIT(0), 148 RTW89_PHY_ENV_MON_CLM = BIT(1), 149 RTW89_PHY_ENV_MON_FAHM = BIT(2), 150 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 151 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 152 }; 153 154 #define CCX_US_BASE_RATIO 4 155 enum rtw89_ccx_unit { 156 RTW89_CCX_4_US = 0, 157 RTW89_CCX_8_US = 1, 158 RTW89_CCX_16_US = 2, 159 RTW89_CCX_32_US = 3 160 }; 161 162 enum rtw89_phy_status_ie_type { 163 RTW89_PHYSTS_IE00_CMN_CCK = 0, 164 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 165 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 166 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 167 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 168 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 169 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 170 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 171 RTW89_PHYSTS_IE08_FTR_CH = 8, 172 RTW89_PHYSTS_IE09_FTR_0 = 9, 173 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 174 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 175 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 176 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 177 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 178 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 179 RTW89_PHYSTS_IE16_RSVD16 = 16, 180 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 181 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 182 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 183 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 184 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 185 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 186 RTW89_PHYSTS_IE23_RSVD23 = 23, 187 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 188 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 189 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 190 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 191 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 192 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 193 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 194 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 195 196 /* keep last */ 197 RTW89_PHYSTS_IE_NUM, 198 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 199 }; 200 201 enum rtw89_phy_status_bitmap { 202 RTW89_TD_SEARCH_FAIL = 0, 203 RTW89_BRK_BY_TX_PKT = 1, 204 RTW89_CCA_SPOOF = 2, 205 RTW89_OFDM_BRK = 3, 206 RTW89_CCK_BRK = 4, 207 RTW89_DL_MU_SPOOFING = 5, 208 RTW89_HE_MU = 6, 209 RTW89_VHT_MU = 7, 210 RTW89_UL_TB_SPOOFING = 8, 211 RTW89_RSVD_9 = 9, 212 RTW89_TRIG_BASE_PPDU = 10, 213 RTW89_CCK_PKT = 11, 214 RTW89_LEGACY_OFDM_PKT = 12, 215 RTW89_HT_PKT = 13, 216 RTW89_VHT_PKT = 14, 217 RTW89_HE_PKT = 15, 218 219 RTW89_PHYSTS_BITMAP_NUM 220 }; 221 222 enum rtw89_dig_gain_type { 223 RTW89_DIG_GAIN_LNA_G = 0, 224 RTW89_DIG_GAIN_TIA_G = 1, 225 RTW89_DIG_GAIN_LNA_A = 2, 226 RTW89_DIG_GAIN_TIA_A = 3, 227 RTW89_DIG_GAIN_MAX = 4 228 }; 229 230 enum rtw89_dig_gain_lna_idx { 231 RTW89_DIG_GAIN_LNA_IDX1 = 1, 232 RTW89_DIG_GAIN_LNA_IDX2 = 2, 233 RTW89_DIG_GAIN_LNA_IDX3 = 3, 234 RTW89_DIG_GAIN_LNA_IDX4 = 4, 235 RTW89_DIG_GAIN_LNA_IDX5 = 5, 236 RTW89_DIG_GAIN_LNA_IDX6 = 6 237 }; 238 239 enum rtw89_dig_gain_tia_idx { 240 RTW89_DIG_GAIN_TIA_IDX0 = 0, 241 RTW89_DIG_GAIN_TIA_IDX1 = 1 242 }; 243 244 enum rtw89_tssi_bandedge_cfg { 245 RTW89_TSSI_BANDEDGE_FLAT, 246 RTW89_TSSI_BANDEDGE_LOW, 247 RTW89_TSSI_BANDEDGE_MID, 248 RTW89_TSSI_BANDEDGE_HIGH, 249 250 RTW89_TSSI_CFG_NUM, 251 }; 252 253 enum rtw89_tssi_sbw_idx { 254 RTW89_TSSI_SBW20, 255 RTW89_TSSI_SBW40_0, 256 RTW89_TSSI_SBW40_1, 257 RTW89_TSSI_SBW80_0, 258 RTW89_TSSI_SBW80_1, 259 RTW89_TSSI_SBW80_2, 260 RTW89_TSSI_SBW80_3, 261 RTW89_TSSI_SBW160_0, 262 RTW89_TSSI_SBW160_1, 263 RTW89_TSSI_SBW160_2, 264 RTW89_TSSI_SBW160_3, 265 RTW89_TSSI_SBW160_4, 266 RTW89_TSSI_SBW160_5, 267 RTW89_TSSI_SBW160_6, 268 RTW89_TSSI_SBW160_7, 269 270 RTW89_TSSI_SBW_NUM, 271 }; 272 273 struct rtw89_txpwr_byrate_cfg { 274 enum rtw89_band band; 275 enum rtw89_nss nss; 276 enum rtw89_rate_section rs; 277 u8 shf; 278 u8 len; 279 u32 data; 280 }; 281 282 #define DELTA_SWINGIDX_SIZE 30 283 284 struct rtw89_txpwr_track_cfg { 285 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 286 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 287 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 288 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 289 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 290 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 291 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 292 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 293 const s8 *delta_swingidx_2gb_n; 294 const s8 *delta_swingidx_2gb_p; 295 const s8 *delta_swingidx_2ga_n; 296 const s8 *delta_swingidx_2ga_p; 297 const s8 *delta_swingidx_2g_cck_b_n; 298 const s8 *delta_swingidx_2g_cck_b_p; 299 const s8 *delta_swingidx_2g_cck_a_n; 300 const s8 *delta_swingidx_2g_cck_a_p; 301 }; 302 303 struct rtw89_phy_dig_gain_cfg { 304 const struct rtw89_reg_def *table; 305 u8 size; 306 }; 307 308 struct rtw89_phy_dig_gain_table { 309 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 310 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 311 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 312 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 313 }; 314 315 struct rtw89_phy_tssi_dbw_table { 316 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 317 }; 318 319 struct rtw89_phy_reg3_tbl { 320 const struct rtw89_reg3_def *reg3; 321 int size; 322 }; 323 324 #define DECLARE_PHY_REG3_TBL(_name) \ 325 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 326 .reg3 = _name, \ 327 .size = ARRAY_SIZE(_name), \ 328 } 329 330 struct rtw89_nbi_reg_def { 331 struct rtw89_reg_def notch1_idx; 332 struct rtw89_reg_def notch1_frac_idx; 333 struct rtw89_reg_def notch1_en; 334 struct rtw89_reg_def notch2_idx; 335 struct rtw89_reg_def notch2_frac_idx; 336 struct rtw89_reg_def notch2_en; 337 }; 338 339 struct rtw89_ccx_regs { 340 u32 setting_addr; 341 u32 edcca_opt_mask; 342 u32 measurement_trig_mask; 343 u32 trig_opt_mask; 344 u32 en_mask; 345 u32 ifs_cnt_addr; 346 u32 ifs_clm_period_mask; 347 u32 ifs_clm_cnt_unit_mask; 348 u32 ifs_clm_cnt_clear_mask; 349 u32 ifs_collect_en_mask; 350 u32 ifs_t1_addr; 351 u32 ifs_t1_th_h_mask; 352 u32 ifs_t1_en_mask; 353 u32 ifs_t1_th_l_mask; 354 u32 ifs_t2_addr; 355 u32 ifs_t2_th_h_mask; 356 u32 ifs_t2_en_mask; 357 u32 ifs_t2_th_l_mask; 358 u32 ifs_t3_addr; 359 u32 ifs_t3_th_h_mask; 360 u32 ifs_t3_en_mask; 361 u32 ifs_t3_th_l_mask; 362 u32 ifs_t4_addr; 363 u32 ifs_t4_th_h_mask; 364 u32 ifs_t4_en_mask; 365 u32 ifs_t4_th_l_mask; 366 u32 ifs_clm_tx_cnt_addr; 367 u32 ifs_clm_edcca_excl_cca_fa_mask; 368 u32 ifs_clm_tx_cnt_msk; 369 u32 ifs_clm_cca_addr; 370 u32 ifs_clm_ofdmcca_excl_fa_mask; 371 u32 ifs_clm_cckcca_excl_fa_mask; 372 u32 ifs_clm_fa_addr; 373 u32 ifs_clm_ofdm_fa_mask; 374 u32 ifs_clm_cck_fa_mask; 375 u32 ifs_his_addr; 376 u32 ifs_t4_his_mask; 377 u32 ifs_t3_his_mask; 378 u32 ifs_t2_his_mask; 379 u32 ifs_t1_his_mask; 380 u32 ifs_avg_l_addr; 381 u32 ifs_t2_avg_mask; 382 u32 ifs_t1_avg_mask; 383 u32 ifs_avg_h_addr; 384 u32 ifs_t4_avg_mask; 385 u32 ifs_t3_avg_mask; 386 u32 ifs_cca_l_addr; 387 u32 ifs_t2_cca_mask; 388 u32 ifs_t1_cca_mask; 389 u32 ifs_cca_h_addr; 390 u32 ifs_t4_cca_mask; 391 u32 ifs_t3_cca_mask; 392 u32 ifs_total_addr; 393 u32 ifs_cnt_done_mask; 394 u32 ifs_total_mask; 395 }; 396 397 struct rtw89_physts_regs { 398 u32 setting_addr; 399 u32 dis_trigger_fail_mask; 400 u32 dis_trigger_brk_mask; 401 }; 402 403 enum rtw89_bandwidth_section_num_ax { 404 RTW89_BW20_SEC_NUM_AX = 8, 405 RTW89_BW40_SEC_NUM_AX = 4, 406 RTW89_BW80_SEC_NUM_AX = 2, 407 }; 408 409 enum rtw89_bandwidth_section_num_be { 410 RTW89_BW20_SEC_NUM_BE = 16, 411 RTW89_BW40_SEC_NUM_BE = 8, 412 RTW89_BW80_SEC_NUM_BE = 4, 413 RTW89_BW160_SEC_NUM_BE = 2, 414 }; 415 416 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 417 418 struct rtw89_txpwr_limit_ax { 419 s8 cck_20m[RTW89_BF_NUM]; 420 s8 cck_40m[RTW89_BF_NUM]; 421 s8 ofdm[RTW89_BF_NUM]; 422 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; 423 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; 424 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; 425 s8 mcs_160m[RTW89_BF_NUM]; 426 s8 mcs_40m_0p5[RTW89_BF_NUM]; 427 s8 mcs_40m_2p5[RTW89_BF_NUM]; 428 }; 429 430 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 431 432 struct rtw89_txpwr_limit_be { 433 s8 cck_20m[RTW89_BF_NUM]; 434 s8 cck_40m[RTW89_BF_NUM]; 435 s8 ofdm[RTW89_BF_NUM]; 436 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; 437 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; 438 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; 439 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; 440 s8 mcs_320m[RTW89_BF_NUM]; 441 s8 mcs_40m_0p5[RTW89_BF_NUM]; 442 s8 mcs_40m_2p5[RTW89_BF_NUM]; 443 s8 mcs_40m_4p5[RTW89_BF_NUM]; 444 s8 mcs_40m_6p5[RTW89_BF_NUM]; 445 }; 446 447 #define RTW89_RU_SEC_NUM_AX 8 448 449 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 450 451 struct rtw89_txpwr_limit_ru_ax { 452 s8 ru26[RTW89_RU_SEC_NUM_AX]; 453 s8 ru52[RTW89_RU_SEC_NUM_AX]; 454 s8 ru106[RTW89_RU_SEC_NUM_AX]; 455 }; 456 457 #define RTW89_RU_SEC_NUM_BE 16 458 459 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 460 461 struct rtw89_txpwr_limit_ru_be { 462 s8 ru26[RTW89_RU_SEC_NUM_BE]; 463 s8 ru52[RTW89_RU_SEC_NUM_BE]; 464 s8 ru106[RTW89_RU_SEC_NUM_BE]; 465 s8 ru52_26[RTW89_RU_SEC_NUM_BE]; 466 s8 ru106_26[RTW89_RU_SEC_NUM_BE]; 467 }; 468 469 struct rtw89_phy_gen_def { 470 u32 cr_base; 471 const struct rtw89_ccx_regs *ccx; 472 const struct rtw89_physts_regs *physts; 473 474 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, 475 const struct rtw89_chan *chan, 476 enum rtw89_phy_idx phy_idx); 477 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, 478 const struct rtw89_chan *chan, 479 enum rtw89_phy_idx phy_idx); 480 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, 481 const struct rtw89_chan *chan, 482 enum rtw89_phy_idx phy_idx); 483 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, 484 const struct rtw89_chan *chan, 485 enum rtw89_phy_idx phy_idx); 486 }; 487 488 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 489 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 490 491 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 492 u32 addr, u8 data) 493 { 494 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 495 496 rtw89_write8(rtwdev, addr + phy->cr_base, data); 497 } 498 499 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 500 u32 addr, u16 data) 501 { 502 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 503 504 rtw89_write16(rtwdev, addr + phy->cr_base, data); 505 } 506 507 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 508 u32 addr, u32 data) 509 { 510 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 511 512 rtw89_write32(rtwdev, addr + phy->cr_base, data); 513 } 514 515 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 516 u32 addr, u32 bits) 517 { 518 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 519 520 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits); 521 } 522 523 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 524 u32 addr, u32 bits) 525 { 526 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 527 528 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits); 529 } 530 531 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 532 u32 addr, u32 mask, u32 data) 533 { 534 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 535 536 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); 537 } 538 539 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 540 { 541 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 542 543 return rtw89_read8(rtwdev, addr + phy->cr_base); 544 } 545 546 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 547 { 548 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 549 550 return rtw89_read16(rtwdev, addr + phy->cr_base); 551 } 552 553 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 554 { 555 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 556 557 return rtw89_read32(rtwdev, addr + phy->cr_base); 558 } 559 560 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 561 u32 addr, u32 mask) 562 { 563 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 564 565 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask); 566 } 567 568 static inline 569 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 570 { 571 switch (subband) { 572 default: 573 case RTW89_CH_2G: 574 return RTW89_GAIN_OFFSET_2G_OFDM; 575 case RTW89_CH_5G_BAND_1: 576 return RTW89_GAIN_OFFSET_5G_LOW; 577 case RTW89_CH_5G_BAND_3: 578 return RTW89_GAIN_OFFSET_5G_MID; 579 case RTW89_CH_5G_BAND_4: 580 return RTW89_GAIN_OFFSET_5G_HIGH; 581 } 582 } 583 584 static inline 585 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 586 { 587 switch (subband) { 588 default: 589 case RTW89_CH_2G: 590 return RTW89_BB_GAIN_BAND_2G; 591 case RTW89_CH_5G_BAND_1: 592 return RTW89_BB_GAIN_BAND_5G_L; 593 case RTW89_CH_5G_BAND_3: 594 return RTW89_BB_GAIN_BAND_5G_M; 595 case RTW89_CH_5G_BAND_4: 596 return RTW89_BB_GAIN_BAND_5G_H; 597 case RTW89_CH_6G_BAND_IDX0: 598 case RTW89_CH_6G_BAND_IDX1: 599 return RTW89_BB_GAIN_BAND_6G_L; 600 case RTW89_CH_6G_BAND_IDX2: 601 case RTW89_CH_6G_BAND_IDX3: 602 return RTW89_BB_GAIN_BAND_6G_M; 603 case RTW89_CH_6G_BAND_IDX4: 604 case RTW89_CH_6G_BAND_IDX5: 605 return RTW89_BB_GAIN_BAND_6G_H; 606 case RTW89_CH_6G_BAND_IDX6: 607 case RTW89_CH_6G_BAND_IDX7: 608 return RTW89_BB_GAIN_BAND_6G_UH; 609 } 610 } 611 612 enum rtw89_rfk_flag { 613 RTW89_RFK_F_WRF = 0, 614 RTW89_RFK_F_WM = 1, 615 RTW89_RFK_F_WS = 2, 616 RTW89_RFK_F_WC = 3, 617 RTW89_RFK_F_DELAY = 4, 618 RTW89_RFK_F_NUM, 619 }; 620 621 struct rtw89_rfk_tbl { 622 const struct rtw89_reg5_def *defs; 623 u32 size; 624 }; 625 626 #define RTW89_DECLARE_RFK_TBL(_name) \ 627 const struct rtw89_rfk_tbl _name ## _tbl = { \ 628 .defs = _name, \ 629 .size = ARRAY_SIZE(_name), \ 630 } 631 632 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 633 {.flag = RTW89_RFK_F_WRF, \ 634 .path = _path, \ 635 .addr = _addr, \ 636 .mask = _mask, \ 637 .data = _data,} 638 639 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 640 {.flag = RTW89_RFK_F_WM, \ 641 .addr = _addr, \ 642 .mask = _mask, \ 643 .data = _data,} 644 645 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 646 {.flag = RTW89_RFK_F_WS, \ 647 .addr = _addr, \ 648 .mask = _mask,} 649 650 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 651 {.flag = RTW89_RFK_F_WC, \ 652 .addr = _addr, \ 653 .mask = _mask,} 654 655 #define RTW89_DECL_RFK_DELAY(_data) \ 656 {.flag = RTW89_RFK_F_DELAY, \ 657 .data = _data,} 658 659 void 660 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 661 662 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 663 do { \ 664 typeof(dev) __dev = (dev); \ 665 if (cond) \ 666 rtw89_rfk_parser(__dev, (tbl_t)); \ 667 else \ 668 rtw89_rfk_parser(__dev, (tbl_f)); \ 669 } while (0) 670 671 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 672 const struct rtw89_phy_reg3_tbl *tbl); 673 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 674 const struct rtw89_chan *chan, 675 enum rtw89_bandwidth dbw); 676 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 677 u32 addr, u32 mask); 678 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 679 u32 addr, u32 mask); 680 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 681 u32 addr, u32 mask, u32 data); 682 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 683 u32 addr, u32 mask, u32 data); 684 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 685 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 686 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 687 const struct rtw89_reg2_def *reg, 688 enum rtw89_rf_path rf_path, 689 void *extra_data); 690 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 691 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 692 u32 data, enum rtw89_phy_idx phy_idx); 693 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 694 enum rtw89_phy_idx phy_idx); 695 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 696 struct rtw89_txpwr_byrate *head, 697 const struct rtw89_rate_desc *desc); 698 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 699 const struct rtw89_rate_desc *rate_desc); 700 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 701 const struct rtw89_txpwr_table *tbl); 702 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 703 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 704 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 705 u8 ru, u8 ntx, u8 ch); 706 707 static inline 708 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 709 const struct rtw89_chan *chan, 710 enum rtw89_phy_idx phy_idx) 711 { 712 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 713 714 phy->set_txpwr_byrate(rtwdev, chan, phy_idx); 715 } 716 717 static inline 718 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 719 const struct rtw89_chan *chan, 720 enum rtw89_phy_idx phy_idx) 721 { 722 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 723 724 phy->set_txpwr_offset(rtwdev, chan, phy_idx); 725 } 726 727 static inline 728 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 729 const struct rtw89_chan *chan, 730 enum rtw89_phy_idx phy_idx) 731 { 732 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 733 734 phy->set_txpwr_limit(rtwdev, chan, phy_idx); 735 } 736 737 static inline 738 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 739 const struct rtw89_chan *chan, 740 enum rtw89_phy_idx phy_idx) 741 { 742 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 743 744 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); 745 } 746 747 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 748 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 749 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 750 u32 changed); 751 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 752 struct ieee80211_vif *vif, 753 const struct cfg80211_bitrate_mask *mask); 754 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 755 u32 len, u8 class, u8 func); 756 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 757 void rtw89_phy_cfo_track_work(struct work_struct *work); 758 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 759 struct rtw89_rx_phy_ppdu *phy_ppdu); 760 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 761 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 762 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 763 u32 val); 764 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 765 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 766 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 767 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 768 struct rtw89_rx_phy_ppdu *phy_ppdu); 769 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 770 void rtw89_phy_antdiv_work(struct work_struct *work); 771 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 772 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 773 enum rtw89_mac_idx mac_idx, 774 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 775 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 776 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 777 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 778 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 779 u8 *ch, enum nl80211_band *band); 780 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); 781 782 #endif 783